LC66665308A [SANYO]
Four-Bit Single-Chip Microcontrollers with 4, 6, and 8 KB of On-Chip ROM; 四位单片微控制器有4个，6个和8 KB的片上ROM
| 型号： | LC66665308A |
| 厂家： | 
SANYO SEMICON DEVICE |
| 描述： | Four-Bit Single-Chip Microcontrollers with 4, 6, and 8 KB of On-Chip ROM |
| 文件： | 总21页 (文件大小：142K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CMOS LSI
LC66354C, 66356C, 66358C
No. 5484
Four-Bit Single-Chip Microcontrollers
with 4, 6, and 8 KB of On-Chip ROM
Preliminary
Overview
The LC66354C, LC66356C, and LC66358C are 4-bit
CMOS microcontrollers that integrate on a single chip all
the functions required in a system controller, including
ROM, RAM, I/O ports, a serial interface, comparator
inputs, three-value inputs, timers, and interrupt functions.
These three microcontrollers are available in a 42-pin
package.
• Evaluation LSIs
— LC66599 (evaluation chip) + EVA85/800-TB6630X
— LC66E308 (on-chip EPROM microcontroller)
used together.
Package Dimensions
unit: mm
3025B-DIP42S
These products differ from the earlier LC66358A Series
and LC66358B Series in the power-supply voltage range,
the operating speed, and other points.
[LC66354C/66356C/66358C]
42
22
Features and Functions
• On-chip ROM capacities of 4, 6, and 8 kilobytes, and an
on-chip RAM capacity of 512 × 4 bits.
• Fully supports the LC66000 Series common instruction
set (128 instructions).
• I/O ports: 36 pins
• 8-bit serial interface: two circuits (can be connected in
cascade to form a 16-bit interface)
1
21
37.9
0.95
• Instruction cycle time: 0.92 to 10 µs (at 2.5 to 5.5 V)
— For the earlier LC66358A Series: 1.96 to 10 µs (at
3.0 to 5.5 V) and 3.92 to 10 µs (at 2.2 to 5.5 V)
— For the earlier LC66358B Series: 0.92 to 10 µs (at
3.0 to 5.5 V)
• Powerful timer functions and prescalers
— Time limit timer, event counter, pulse width
measurement, and square wave output using a 12-bit
timer.
— Time limit timer, event counter, PWM output, and
square wave output using an 8-bit timer.
— Time base function using a 12-bit prescaler.
• Powerful interrupt system with 8 interrupt factors and 8
interrupt vector locations.
0.48
1.15
1.78
SANYO: DIP42S
unit: mm
3156-QFP48E
[LC66354C/66356C/66358C]
17.2
1.6
1.5
14.0
0.15
1.5 1.0
36
25
24
37
— External interrupts: 3 factors/3 vector locations
— Internal interrupts: 5 factors/5 vector locations
• Flexible I/O functions
Comparator inputs, three-value inputs, 20-mA drive
outputs, 15-V high-voltage pins, and pull-up/open-drain
options.
48
13
12
1
0.35
0.1
2.70
(STAND OFF)
0.8
15.6
• Optional runaway detection function (watchdog timer)
• 8-bit I/O functions
SANYO: QFP48E
• Power saving functions using halt and hold modes.
• Packages: DIP42S, QIP48E (QFP48E)
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110 JAPAN
22897HA (OT) No. 5484-1/21
LC66354C, 66356C, 66358C
Series Organization
No. of
pins
RAM
capacity
Type No.
ROM capacity
Package
Features
LC66304A/306A/308A
LC66404A/406A/408A
LC66506B/508B/512B/516B
LC66354A/356A/358A
LC66354S/356S/358S
LC66556A/558A/562A/566A
LC66354B/356B/358B
LC66556B/558B
42
42
64
42
42
64
42
64
64
42
42
42
48
48
4 K/6 K/8 KB
4 K/6 K/8 KB
512 W
DIP42S
DIP42S
DIP64S
DIP42S
QFP48E
QFP48E
QFP64A
QFP48E
QFP44M
QFP64E
QFP48E
QFP64E
QFP64E
QFP48E
QFP48E
QFP48E
QFP48E
QFP48E
Normal versions
4.0 to 6.0 V/0.92 µs
512 W
6 K/8 K/12 K/16 KB 512 W
4 K/6 K/8 KB
4 K/6 K/8 KB
512 W
512 W
Low-voltage versions
2.2 to 5.5 V/3.92 µs
6 K/8 K/12 K/16 KB 512 W
DIP64S
DIP42S
DIP64S
DIP64S
DIP42S
DIP42S
DIP42S
DIP48S
DIP48S
4 K/6 K/8 KB
6 K/8 KB
512 W
512 W
512 W
512 W
512 W
512 W
512 W
512 W
Low-voltage high-speed versions
3.0 to 5.5 V/0.92 µs
LC66562B/566B
12 K/16 KB
4 K/6 K/8 KB
4 K/6 K/8 KB
12 K/16 KB
4 K/6 K/8 KB
12 K/16 KB
LC66354C/356C/358C
LC662304A/2306A/2308A
LC662312A/2316A
2.5 to 5.5 V/0.92 µs
On-chip DTMF generator versions
3.0 to 5.5 V/0.95 µs
LC665304A/665306A/665308A
LC665312A/5316A
Dual oscillator support
3.0 to 5.5 V/0.95 µs
DIC42S
with window
QFC48
with window
LC66E308
LC66P308
LC66E408
LC66P408
LC66E516
LC66P516
LC66E2316
42
42
42
42
64
64
42
EPROM 8 KB
OTPROM 8 KB
EPROM 8 KB
OTPROM 8 KB
EPROM 16 KB
OTPROM 16 KB
EPROM 16 KB
512 W
512 W
512 W
512 W
512 W
512 W
512 W
DIP42S
QFP48E
DIC42S
with window
QFC48
with window
Window and OTP evaluation versions
4.5 to 5.5 V/0.92 µs
DIP42S
QFP48E
DIC64S
with window
QFC64
with window
DIP64S
QFP64E
DIC42S
with window
QFC48
with window
4.5 to 5.5 V/0.95 µs
4.0 to 5.5 V/0.95 µs
DIC52S
with window
QFC48
with window
LC66E5316
52/48
EPROM 16 KB
512 W
LC66P2316*
42
48
OTPROM 16 KB
OTPROM 16 KB
512 W
512 W
DIP42S
DIP48S
QFP48E
QFP48E
LC66P5316
Note: * Under development
No. 5484-2/21
LC66354C, 66356C, 66358C
Pin Assignments
DIP42S
PE1/TRB
42
PE0/TRA
41
P00
P01
1
2
V
P02
3
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
DD
PD3/CMP3
P03
4
PD2/CMP2
PD1/CMP1
PD0/CMP0
PC3/VREF1
PC2/VREF0
P63/PIN1
P62/SCK1
P61/SO1
P60/SI1
P53/INT2
P52
P10
5
P11
6
P12
7
P13
8
LC66354C
356C
SI0/P20
SO0/P21
SCK0/P22
INT0/P23
INT1/P30
POUT0/P31
POUT1/P32
HOLD/P33
P40
9
358C
10
11
12
13
14
15
16
17
18
19
20
21
P51
P50
P43
P41
P42
TEST
RES
V
SS
OSC2
OSC1
QFP48E
36 35 34 33 32 31 30 29 28 27 26 25
CMP2/PD2 37
CMP3/PD3 38
24 P50
23 P43
22 P42
21 RES
20 OSC2
19 NC
V
39
DD
LC66354C
356C
TRA/PE0 40
TRB/PE1 41
NC 42
358C
NC 43
18 NC
P00 44
17 OSC1
P01 45
16
V
SS
P02 46
15 TEST
14 P41
13 P40
P03 47
P10 48
1
2 3 4 5 6 7 8 9 10 11 12
Top view
We recommend the use of reflow-soldering techniques to solder-mount QFP packages.
Please consult with your Sanyo representative for details on process conditions if the package itself is to be directly
immersed in a dip-soldering bath (dip-soldering techniques).
No. 5484-3/21
LC66354C, 66356C, 66358C
System Block Diagram
RAM STACK
(512W)
ROM
(4K/6K/8K)
RES
C
Z
TEST
FLAG
SYSTEM
OSC1
OSC2
HOLD
CONTROL
D D D D
P P P P
H L Y X
E
M
R
ALU
PC
SP
E
A
POUT0
SI0
TRA
TRB
CMP0
CMP1
CMP2
CMP3
MPX
TIMER0
SERIAL I/O 0
PRESCALER
MPX
SO0
PE
PD
PC
SCK0
INT0
INT1. INT2
SI1
SO1
INTERRUPT
CONTROL
MPX
P3
TIMER1
SERIAL I/O 1
SCK1
PIN1. POUT1
P0
P1
P2
P4
P5
P6
Differences between the LC66354C, LC66356C, and LC66358C and the LC6630X Series
LC6630X Series
(Including the LC66599 evaluation chip)
Item
System differences
Hardware wait time (number of cycles)
when hold mode is cleared
LC6635XC Series
65536 cycles
16384 cycles
About 64 ms at 4 MHz (Tcyc = 1 µs)
Set to FF0.
About 16 ms at 4 MHz (Tcyc = 1 µs)
Value of timer 0 after a reset
(Including the value after hold mode is
cleared)
Set to FFC.
2.5 to 5.5 V/0.92 to 10 µs
• LC6635XA
2.2 to 5.5 V/3.92 to 10 µs
3.0 to 5.5 V/1.96 to 10 µs
• LC6635XB
• LC66304A/306A/308A
4.0 to 6.0 V/0.92 to 10 µs
• LC66E308/P308
Difference in major features
Operating power-supply voltage and
operating speed (cycle time)
4.5 to 5.5 V/0.92 to 10 µs
3.0 to 5.5 V/0.92 to 10 µs
Note: 1. An RC oscillator cannot be used with the LC66354C, LC66356C, and LC66358C.
2. There are other differences, including differences in output currents and port input voltages.
For details, see the data sheets for the LC66308A, LC66E308, and LC66P308.
3. Pay close attention to the differences listed here when using the LC66E308 and LC66P308 for evaluation.
No. 5484-4/21
LC66354C, 66356C, 66358C
Pin Function Overview
Pin
I/O
Overview
Output driver type
Options
State after a reset
P00
P01
P02
P03
I/O ports P00 to P03
• Pch: Pull-up MOS type
• Nch: Intermediate sink current
type
• Pull-up MOS or Nch
OD output
• Output level on reset
• Input or output in 4-bit or 1-bit units
• P00 to P03 support the halt mode control
function
High or low
(option)
I/O
P10
P11
P12
P13
• Pch: Pull-up MOS type
• Nch: Intermediate sink current
type
• Pull-up MOS or Nch
OD output
• Output level on reset
I/O ports P10 to P13
Input or output in 4-bit or 1-bit units
High or low
(option)
I/O
I/O ports P20 to P23
• Input or output in 4-bit or 1-bit units
• P20 is also used as the serial input SI0
pin.
• P21 is also used as the serial output
SO0 pin.
• P22 is also used as the serial clock
SCK0 pin.
• P23 is also used as the INT0 interrupt
request pin, and also as the timer 0
event counting and pulse width
measurement input.
• Pch: CMOS type
• Nch: Intermediate sink current
type
• Nch: +15-V handling when OD
option selected
P20/SI0
P21/SO0
P22/SCK0
P23/INT0
CMOS or Nch OD
output
I/O
H
I/O ports P30 to P32
• Input or output in 3-bit or 1-bit units
• P30 is also used as the INT1 interrupt
request.
• P31 is also used for the square wave
output from timer 0.
• Pch: CMOS type
• Nch: Intermediate sink current
type
• Nch: +15-V handling when OD
option selected
P30/INT1
P31/POUT0
P32/POUT1
CMOS or Nch OD
output
I/O
H
• P32 is also used for the square wave
output from timer 1.
Hold mode control input
• Hold mode is set up by the HOLD
instruction when HOLD is low.
• In hold mode, the CPU is restarted by
setting HOLD to the high level.
• This pin can be used as input port P33
along with P30 to P32.
P33/HOLD
I
• When the P33/HOLD pin is at the low
level, the CPU will not be reset by a low
level on the RES pin. Therefore,
applications must not set P33/HOLD low
when power is first applied.
I/O ports P40 to P43
• Input or output in 4-bit or 1-bit units
• Input or output in 8-bit units when used
in conjunction with P50 to P53.
• Can be used for output of 8-bit ROM
data when used in conjunction with P50
to P53.
• Pch: Pull-up MOS type
• Nch: Intermediate sink current
type
• Nch: +15-V handling when OD
option selected
P40
P41
P42
P43
Pull-up MOS or Nch OD
output
I/O
H
I/O ports P50 to P53
• Input or output in 4-bit or 1-bit units
• Input or output in 8-bit units when used
in conjunction with P40 to P43.
• Can be used for output of 8-bit ROM
data when used in conjunction with P40
to P43.
• Pch: Pull-up MOS type
• Nch: Intermediate sink current
type
• Nch: +15-V handling when OD
option selected
P50
P51
P52
Pull-up MOS or Nch OD
output
I/O
H
P53/INT2
• P53 is also used as the INT2 interrupt
request.
Continued on next page.
No. 5484-5/21
LC66354C, 66356C, 66358C
Continued from preceding page.
Pin
I/O
Overview
Output driver type
Options
State after a reset
I/O ports P60 to P63
• Input or output in 4-bit or 1-bit units
• P60 is also used as the serial input SI1
pin.
• P61 is also used as the serial output
SO1 pin.
• Pch: CMOS type
• Nch: Intermediate sink current
type
• Nch: +15-V handling when OD
option selected
P60/SI0
P61/SO1
P62/SCK1
P63/PIN1
CMOS or Nch OD
output
I/O
H
• P62 is also used as the serial clock
SCK1 pin.
• P63 is also used for the event count
input to timer 1.
I/O ports PC2 and PC3
• Input or output in 2-bit or 1-bit units
• PC2 is also used as the VREF0
comparator comparison voltage pin.
• PC3 is also used as the VREF1
comparator comparison voltage pin.
• Pch: CMOS type
• Nch: Intermediate sink current
type
CMOS or Nch OD
output
PC2/VREF0
PC3/VREF1
I/O
H
Dedicated input ports PD0 to PD3
• These pins can be switched in software
to function as comparator inputs.
• The comparison voltage for PD0 is
provided by VREF0.
• The comparison voltage for PD1 to PD3
is provided by VREF1.
• Pins PD0 and PD1 can be set to the
comparator function individually, but pins
PD2 and PD3 are set together.
PD0/CMP0
PD1/CMP1
PD2/CMP2
PD3/CMP3
I
I
Normal input
Dedicated input ports
These pins can be switched in software to
function as three-value inputs.
PE0/TRA
PE1/TRB
Normal input
System clock oscillator connections
When an external clock is used, leave
OSC2 open and connect the clock signal
to OSC1.
Use of either a ceramic
oscillator or an external
clock can be selected.
OSC1
OSC2
I
O
System reset input
When the P33/HOLD pin is at the high
level, a low level input to the RES pin will
initialize the CPU.
RES
I
I
CPU test pin
This pin must be connected to VSS during
normal operation.
TEST
VDD
VSS
Power supply pins
Note: Pull-up MOS type: The output circuit includes a MOS transistor that pulls the pin up to VDD
.
CMOS output: Complementary output.
OD output: Open-drain output.
No. 5484-6/21
LC66354C, 66356C, 66358C
User Options
1. Port 0 and 1 output level at reset option
The output levels at reset for I/O ports 0 and 1, in independent 4-bit groups, can be selected from the following two
options.
Option
Conditions and notes
1. Output high at reset
2. Output low at reset
The four bits of ports 0 or 1 are set in a group
The four bits of ports 0 or 1 are set in a group
2. Oscillator circuit options
Option
Circuit
Conditions and notes
OSC1
1. External clock
The input has Schmitt characteristics
C1
OSC1
OSC2
Ceramic oscillator
C2
2. Ceramic oscillator
Note: There is no RC oscillator option.
3. Watchdog timer option
A runaway detection function (watchdog timer) can be selected as an option.
4. Port output type options
• The output type of each bit (pin) in ports P0, P1, P2, P3 (except for the P33/HOLD pin), P4, P5, P6, and PC can be
selected individually from the following two options.
Option
Circuit
Conditions and notes
Output data
Input data
The port P2, P3, P5, and P6 inputs have Schmitt
characteristics.
1. Open-drain output
DSB
Output data
Input data
The port P2, P3, P5, and P6 inputs have Schmitt
characteristics.
2. Output with built-in pull-up
resistor
The CMOS outputs (ports P2, P3, P6, and PC)
and the pull-up MOS outputs (P0, P1, P4, and
P5) are distinguished by the drive capacity of the
p-channel transistor.
DSB
• The port PD comparator input and the port PE three-value input are selected in software.
No. 5484-7/21
LC66354C, 66356C, 66358C
Specifications
Absolute Maximum Ratings at Ta = 25°C, VSS = 0 V
Parameter
Maximum supply voltage
Symbol
DD max
Conditions
Ratings
Unit
V
Note
V
VDD
–0.3 to +7.0
P2, P3 (except for the P33/HOLD pin), P4, P5,
and P6
VIN
IN2
VOUT
OUT2
ION
1
–0.3 to +15.0
–0.3 to VDD + 0.3
–0.3 to +15.0
–0.3 to VDD + 0.3
20
V
V
1
2
1
2
3
Input voltage
V
All other inputs
P2, P3 (except for the P33/HOLD pin), P4, P5,
and P6
1
V
Output voltage
V
All other inputs
V
P0, P1, P2, P3 (except for the P33/HOLD pin),
P4, P5, P6, and PC
mA
Output current per pin
–IOP1
–IOP2
P0, P1, P4, P5
2
4
mA
mA
4
4
P2, P3 (except for the P33/HOLD pin), P6, and PC
P0, P1, P2, P3 (except for the P33/HOLD pin),
P40, and P41
Σ ION
1
75
75
25
mA
mA
mA
3
3
4
4
Σ ION2
P5, P6, P42, P43, PC
Total pin current
P0, P1, P2, P3 (except for the P33/HOLD pin),
P40, and P41
Σ IOP
1
Σ IOP2
P5, P6, P42, P43, PC
25
600
mA
mW
mW
°C
DIP42S
Ta = –30 to +70°C
Allowable power dissipation
Pd max
QFP48E
430
5
Operating temperature
Storage temperature
Topr
Tstg
–30 to +70
–55 to +125
°C
Note: 1. Applies to pins with open-drain output specifications. For pins with other than open-drain output specifications, the ratings in the pin column for that
pin apply.
2. For the oscillator input and output pins, levels up to the free-running oscillation level are allowed.
3. Sink current
4. Source current (Applies to pins with pull-up output and CMOS output specifications.)
5. We recommend the use of reflow soldering techniques to solder mount QFP packages.
Please consult with your Sanyo representative for details on process conditions if the package itself is to be directly immersed in a dip-soldering
bath (dip-soldering techniques).
No. 5484-8/21
LC66354C, 66356C, 66358C
Allowable Operating Ranges at Ta = –30 to +70°C, VSS = 0 V, VDD = 2.5 to 5.5 V, unless otherwise specified.
Parameter
Symbol
VDD
Conditions
VDD: 0.92 Tcyc 10 µs
min
2.5
1.8
typ
max
5.5
5.5
Unit
V
Note
Operating supply voltage
Memory retention supply voltage
VDDH
VDD: During hold mode
V
P2, P3 (except for the P33/HOLD pin), P4, P5,
and P6: N-channel output transistor off
VIH
VIH
VIH
1
2
3
0.8 VDD
0.8 VDD
0.8 VDD
+13.5
VDD
V
V
V
1
2
3
P33/HOLD, RES, OSC1:
N-channel output transistor off
Input high-level voltage
Mid-level input voltage
P0, P1, PC, PD, PE:
N-channel output transistor off
VDD
V
IH4
PE: With 3-value input used, VDD = 3.0 to 5.5 V
PE: With 3-value input used, VDD = 3.0 to 5.5 V
0.8 VDD
0.4 VDD
VDD
V
V
VIM
0.6 VDD
PD0, PC2: When the comparator input is used,
VDD = 3.0 to 5.5 V
VCMM
1
1.5
VDD
V
V
Common-mode input
voltage range
PD1, PD2, PD3, PC3: When the comparator
input is used, VDD = 3.0 to 5.5 V
VCMM
2
VSS
VDD – 1.5
P2, P3 (except for the P33/HOLD pin), P5, P6,
RES, and OSC1: N-channel output transistor off
VIL1
VIL2
VIL3
0.2 VDD
0.2 VDD
0.2 VDD
0.2 VDD
V
V
V
V
2
3
P33/HOLD: VDD = 1.8 to 5.5 V
Input low-level voltage
P0, P1, P4, PC, PD, PE, TEST:
N-channel output transistor off
VSS
VSS
VIL4
fop
PE: With 3-value input used, VDD = 3.0 to 5.5 V
Operating frequency
(instruction cycle time)
0.4
(10)
4.35
(0.92)
MHz
(µs)
(Tcyc)
[External clock input conditions]
OSC1: Defined by Figure 1. Input the clock
signal to OSC1 and leave OSC2 open.
(External clock input must be selected as the
oscillator circuit option.)
Frequency
fext
0.4
4.35
MHz
ns
OSC1: Defined by Figure 1. Input the clock
signal to OSC1 and leave OSC2 open.
(External clock input must be selected as the
oscillator circuit option.)
Pulse width
t
extH, textL
100
OSC1: Defined by Figure 1. Input the clock
signal to OSC1 and leave OSC2 open.
(External clock input must be selected as the
oscillator circuit option.)
Rise and fall times
textR, textF
30
ns
Note: 1. Applies to pins with open-drain specifications. However, VIH2 applies to the P33/HOLD pin.
When ports P2, P3, and P6 have CMOS output specifications they cannot be used as input pins.
2. Applies to pins with open-drain specifications.
3. When RE is used as a three-value input, VIH4, VIM, and VIL4 apply. When the ports PC pins have CMOS output specifications they cannot be used
as input pins.
No. 5484-9/21
LC66354C, 66356C, 66358C
Electrical Characteristics at Ta = –30 to +70°C, VSS = 0 V, VDD = 2.5 to 5.5 V unless otherwise specified.
Parameter
Symbol
IIH
Conditions
min
typ
max
5.0
Unit
µA
Note
1
P2, P3 (except for the P33/HOLD pin),
P4, P5, and P6: VIN = 13.5 V, with the output
Nch transistor off
1
Input high-level current
P0, P1, PC, OSC1, RES, P33/HOLD:
I
IH2
1.0
1.0
µA
µA
µA
µA
1
1
2
2
V
IN = VDD, with the output Nch transistor off
PD, PE, PC2, PC3: VIN = VDD
,
IIH
3
with the output Nch transistor off
Input ports other than PD, PE, PC2, and PC3:
VIN = VSS, with the output Nch transistor off
IIL1
IIL2
–1.0
Input low-level current
PC2, PC3, PD, PE: VIN = VSS
,
–1.0
DD – 1.0
DD – 0.5
with the output Nch transistor off
P2, P3 (except for the P33/HOLD pin),
P6, and PC: IOH = –1 mA
V
V
VOH
1
V
3
P2, P3 (except for the P33/HOLD pin),
P6, and PC: IOH = –0.1 mA
Output high-level voltage
P0, P1, P4, P5: IOH = –50 µA
VDD – 1.0
VDD – 0.5
–1.6
V
OH2
V
mA
V
4
4
5
P0, P1, P4, P5: IOH = –30 µA
Output pull-up current
IPO
P0, P1, P4, P5: VIN = VSS, VDD = 5.5 V
P0, P1, P2, P3, P4, P5, P6, and PC
(except for the P33/HOLD pin): IOL = 1.6 mA
VOL
1
2
0.4
1.5
Output low-level voltage
P0, P1, P2, P3, P4, P5, P6, and PC
(except for the P33/HOLD pin): IOL = 8 mA
VOL
V
I
I
OFF1
OFF2
P2, P3, P4, P5, P6: VIN = 13.5 V
P0, P1, PC: VIN = VDD
5.0
1.0
µA
µA
5
5
Output off leakage current
Comparator offset voltage
PD1 to PD3: VIN = VSS to VDD – 1.5 V,
VOFF
1
±50
±300
±300
mV
mV
VDD = 3.0 to 5.5 V
V
OFF2
PD0: VIN = 1.5 to VDD, VDD = 3.0 to 5.5 V
±50
[Schmitt characteristics]
Hysteresis voltage
VHIS
Vt H
Vt L
0.1 VDD
High-level threshold voltage
Low-level threshold voltage
[Ceramic oscillator]
P2, P3, P5, P6, OSC1 (EXT), RES
0.5 VDD
0.2 VDD
0.8 VDD
0.5 VDD
V
V
Oscillator frequency
fCF
OSC1, OSC2: Figure 2, 4 MHz
Figure 3, 4 MHz
4.0
MHz
ms
Oscillator stabilization time
[Serial clock]
fCFS
10
Input
0.9
2.0
0.4
1.0
µs
Tcyc
µs
Cycle time
tCKCY
Output
Input
SCK0, SCK1: With the timing of Figure 4 and
the test load of Figure 5.
tCKL
tCKH
Low-level and high-level
pulse widths
Output
Output
Tcyc
µs
Rise an fall times
[Serial input]
t
CKR, tCKF
0.1
Data setup time
tICK
tCKI
0.3
0.3
µs
µs
SI0, SI1: With the timing of Figure 4.
Stipulated with respect to the rising edge (↑) of
SCK0 or SCK1.
Data hold time
[Serial output]
SO0, SO1: With the timing of Figure 4 and
the test load of Figure 5. Stipulated with respect
to the falling edge (↓) of SCK0 or SCK1.
Output delay time
tCKO
0.3
Continued on next page.
No. 5484-10/21
LC66354C, 66356C, 66358C
Continued from preceding page.
Parameter
Symbol
Conditions
min
2
typ
max
Unit
Note
[Pulse conditions]
INT0: Figure 6, conditions under which the INT0
interrupt can be accepted, conditions under
which the timer 0 event counter or pulse width
measurement input can be accepted
INT0 high and low-level
tIOH, tIOL
Tcyc
High and low-level pulse widths
for interrupt inputs other than INT0
INT1, INT2: Figure 6, conditions under which
the corresponding interrupt can be accepted
t
IIH, tIIL
2
2
3
Tcyc
Tcyc
Tcyc
PIN1 high and low-level
pulse widths
PIN1: Figure 6, conditions under which the
timer 1 event counter input can be accepted
t
PINH, tPINL
RES high and low-level
pulse widths
RES: Figure 6, conditions under which reset
can be applied.
t
RSH, tRSL
Comparator response speed
Operating current drain
TRS
PD: Figure 7, VDD = 3.0 to 5.5 V
VDD: 4-MHz ceramic oscillator
20
5.0
5.0
2.0
2.0
10
ms
mA
mA
mA
mA
µA
3.0
3.0
IDD OP
6
V
DD: 4-MHz external clock
VDD: 4-MHz ceramic oscillator
DD: 4-MHz external clock
VDD: VDD = 1.8 to 5.5 V
1.0
Halt mode current drain
Hold mode current drain
IDDHALT
IDDHOLD
V
1.0
0.01
Note: 1. With the output Nch transistor off in shared I/O ports with the open-drain output specifications. These pins cannot be used as input pins if the
CMOS output specifications are selected.
2. With the output Nch transistor off in shared I/O ports with the open-drain output specifications. The rating for the pull-up output specification pins is
stipulated in terms of the output pull-up current IPO. These pins cannot be used as input pins if the CMOS output specifications are selected.
3. With the output Nch transistor off for CMOS output specification pins.
4. With the output Nch transistor off for pull-up output specification pins.
5. With the output Nch transistor off for open-drain output specification pins.
6. Reset state
V
DD
0.8V
DD
0.2V
DD
OSC1
(OSC2)
OPEN
V
SS
t
t
extH
extL
External clock
t
t
extF
extR
1/fext
Figure 1 External Clock Input Waveform
V
DD
Operating VDD
minimum value
OSC1
OSC2
Rd
0V
OSC
Stable oscillation
Ceramic
oscillator
Oscillator
unstable period
tCFS
C1
C2
Figure 2 Ceramic Oscillator Circuit
Figure 3 Oscillator Stabilization Period
Table 1 Guaranteed Ceramic Oscillator Constants
C1 = 33 pF ± 10%
C1 = 33 pF ± 10%
4 MHz
4 MHz
(Murata Mfg. Co., Ltd.)
CSA4.00MG
C2 = 33 pF ± 10%
Rd = 0
(Kyocera Corporation)
KBR4.0MS
C2 = 33 pF ± 10%
Rd = 0
No. 5484-11/21
LC66354C, 66356C, 66358C
t
CKCY
t
CKR
t
t
t
CKH
CKF
CKL
SCK0
SCK1
0.8V
V
DD (input)
-1V (output)
DD
0.2V
DD (input)
0.4V
DD (output)
t
t
ICK CKI
SI0
SI1
0.8V
0.2V
DD
DD
R=1kΩ
t
CK0
TEST
point
C=50pF
SO0
SO1
V
DD
0.4V
-1
DD
Figure 4 Serial I/O Timing
Figure 5 Timing Load
t
t
I0H
I1H
t
t
PINH
RSH
0.8V
DD
0.2V
DD
t
t
I0L
I1L
t
t
PINL
RSL
Figure 6 Input Timing for the INT0, INT1, INT2, PIN1, and RES pins
VIN
VREF
VIN
VOFF
VOFF
Comparator output data
Trs
Figure 7 Comparator Response Speed Trs Timing
No. 5484-12/21
LC66354C, 66356C, 66358C
LC66XXX Series Instruction Table (by function)
Abbreviations:
AC:
E:
Accumulator
E register
CF:
ZF:
HL:
XY:
M:
Carry flag
Zero flag
Data pointer DPH, DPL
Data pointer DPX, DPY
Data memory
M (HL): Data memory pointed to by the DPH, DPL data pointer
M (XY): Data memory pointed to by the DPX, DPY auxiliary data pointer
M2 (HL): Two words of data memory (starting on an even address) pointed to by the DPH, DPL data pointer
SP:
Stack pointer
M2 (SP): Two words of data memory pointed to by the stack pointer
M4 (SP): Four words of data memory pointed to by the stack pointer
in:
t2:
n bits of immediate data
Bit specification
t2
11
10
01
00
3
2
2
2
1
2
0
2
Bit
PCh:
PCm:
PCl:
Fn:
Bits 8 to 11 in the PC
Bits 4 to 7 in the PC
Bits 0 to 3 in the PC
User flag, n = 0 to 15
TIMER0: Timer 0
TIMER1: Timer 1
SIO:
P:
Serial register
Port
P (i4):
INT:
Port indicated by 4 bits of immediate data
Interrupt enable flag
( ), [ ]: Indicates the contents of a location
←:
:
Transfer direction, result
Exclusive or
:
Logical and
:
Logical or
+:
–:
—:
Addition
Subtraction
Taking the one's complement
No. 5484-13/21
LC66354C, 66356C, 66358C
Instruction code
D7 D6 D5 D4 D3 D2 D1 D0
[Accumulator manipulation instructions]
Affected
status
bits
Mnemonic
Operation
Description
Note
AC ← 0
(Equivalent to LAI 0.)
Has a vertical
skip function.
CLA
DAA
Clear AC
1
0
0
0
0
0
0
0
1
2
1
2
Clear AC to 0.
ZF
ZF
Decimal adjust AC
in addition
1
0
1
0
0
1
0
0
1
0
1
1
1
1
1
0
AC ← (AC) + 6
(Equivalent to ADI 6.)
Add six to AC.
Add 10 to AC.
AC ← (AC) + 10
(Equivalent to
ADI 0AH.)
Decimal adjust AC
in subtraction
1
0
1
0
0
1
0
0
1
1
1
0
1
1
1
0
DAS
2
2
ZF
CLC
STC
Clear CF
Set CF
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
1
1
1
1
1
CF ← 0
CF ← 1
Clear CF to 0.
Set CF to 1.
CF
CF
Take the one’s complement
of AC.
CMA
Complement AC
0
0
0
1
1
0
0
0
1
1
AC ← (AC)
ZF
IA
Increment AC
Decrement AC
0
0
0
0
0
1
1
0
0
0
1
1
0
0
0
0
1
1
1
1
AC ← (AC) + 1
AC ← (AC) – 1
Increment AC.
Decrement AC.
ZF, CF
ZF, CF
DA
AC3 ← (CF),
ACn ← (ACn + 1),
CF ← (AC0)
Rotate AC right
through CF
RAR
RAL
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
1
1
1
1
Shift AC (including CF) right. CF
AC0 ← (CF),
ACn + 1 ← (ACn),
CF ← (AC3)
Rotate AC left
through CF
Shift AC (including CF) left.
CF, ZF
TAE
TEA
Transfer AC to E
Transfer E to AC
0
0
1
1
0
0
0
0
0
0
1
1
0
1
1
0
1
1
1
1
E ← (AC)
AC ← (E)
Transfer the contents of AC to E.
Transfer the contents of E to AC. ZF
Exchange the contents of
AC and E.
XAE
Exchange AC with E
0
1
0
0
0
1
0
0
1
1
(AC) ↔ (E)
[Memory manipulation instructions]
M (HL) ←
[M (HL)] + 1
IM
Increment M
Decrement M
0
0
0
1
0
0
1
0
1
1
2
2
1
1
1
1
2
2
1
1
Increment M (HL).
Decrement M (HL).
ZF, CF
M (HL) ←
[M (HL)] – 1
DM
0
1
0
1
1
0
0
0
0
0
0
1
1
1
0
1
ZF, CF
ZF, CF
ZF, CF
IMDR i8 Increment M direct
DMDR i8 Decrement M direct
SMB t2 Set M data bit
M (i8) ← [M (i8)] + 1 Increment M (i8).
M (i8) ← [M (i8)] – 1 Decrement M (i8).
I7 I6 I5 I4 I3 I2 I1 I0
1
1
0
0
0 0 1 1
I7 I6 I5 I4 I3 I2 I1 I0
Set the bit in M (HL) specified
by t0 and t1 to 1.
0
0
0
0
0
1
0
0
1
1
1
1
t1 t0
t1 t0
[M (HL), t2] ← 1
[M (HL), t2] ← 0
Clear the bit in M (HL)
specified by t0 and t1 to 0.
RMB t2 Reset M data bit
ZF
[Arithmetic, logic and comparison instructions]
Add the contents of AC and
M (HL) as two’s complement
values and store the result
in AC.
AC ← (AC) +
[M (HL)]
AD
Add M to AC
0
0
0
0
0
1
1
0
1
0
0
1
1
2
1
2
1
1
2
1
2
1
ZF, CF
ZF, CF
ZF, CF
ZF
Add the contents of AC and
M (i8) as two’s complement
values and store the result
in AC.
1
1
0
0
ADDR i8 Add M direct to AC
AC ← (AC) + [M (i8)]
I7 I6 I5 I4 I3 I2 I1 I0
Add the contents of AC,
M (HL) and C as two’s
complement values and
store the result in AC.
AC ← (AC) +
[M (HL)] + (CF)
ADC
Add M to AC with CF
0
0
0
0
0
1
0
1
1
1
0
1
Add the contents of AC and
the immediate data as two’s
complement values and store
the result in AC.
Add immediate data
to AC
1
0
1
0
0
1
0
0
AC ← (AC) +
I3, I2, I1, I0
ADI i4
SUBC
I3 I2 I1 I0
Subtract the contents of AC
and CF from M (HL) as two’s
complement values and store
the result in AC.
CF will be zero if
there was a
borrow and one
otherwise.
Subtract AC from M
with CF
AC ← [M (HL)] –
(AC) – (CF)
0
0
0
1
0
1
1
1
ZF, CF
Take the logical and of AC
and M (HL) and store the
result in AC.
And M with AC then
store AC
AC ← (AC)
[M (HL)]
ANDA
ORA
0
0
0
0
0
0
0
0
0
0
1
1
1
0
1
1
1
1
1
1
ZF
ZF
Take the logical or of AC and
M (HL) and store the result
in AC.
Or M with AC then
store AC
AC ← (AC)
[M (HL)]
Continued on next page.
No. 5484-14/21
LC66354C, 66356C, 66358C
Continued from preceding page.
Instruction code
D7 D6 D5 D4 D3 D2 D1 D0
Affected
status
bits
Mnemonic
Operation
Description
Note
[Arithmetic, logic and comparison instructions]
Take the logical exclusive or
of AC and M (HL) and store
the result in AC.
Exclusive or M with
AC then store AC
AC ← (AC)
[M (HL)]
EXL
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
1
0
1
0
1
0
1
1
0
1
1
1
1
1
1
ZF
ZF
ZF
Take the logical and of AC
and M (HL) and store the
result in M (HL).
And M with AC then
store M
M (HL) ← (AC)
[M (HL)]
ANDM
ORM
Take the logical or of AC and
M (HL) and store the result
in M (HL).
Or M with AC then
store M
M (HL) ← (AC)
[M (HL)]
Compare the contents of AC
and M (HL) and set or clear CF
and ZF according to the result.
Magnitude
CF ZF
CM
Compare AC with M
0
0
0
1
0
1
1
0
1
1
[M (HL)] + (AC) + 1
ZF, CF
comparison
[M (HL)] > (AC)
[M (HL)] = (AC)
[M (HL)] < (AC)
0
1
1
0
1
0
Compare the contents of AC
and the immediate data
I3 I2 I1 I0 and set or clear CF
and ZF according to the result.
Magnitude
CF ZF
Compare AC with
immediate data
1
1
1
0
0
1
0
0
1
1 1 1
CI i4
2
2
I3 I2 I1 I0 + (AC) + 1
ZF, CF
comparison
I3 I2 I1 I0
I3 I2 I1 I0 > AC
I3 I2 I1 I0 = AC
I3 I2 I1 I0 < AC
0
1
1
0
1
0
ZF ← 1
if (DPL) = I3 I2 I1 I0
ZF ← 0
Compare the contents of DPL
with the immediate data.
Set ZF if identical and clear
ZF if not.
Compare DPL with
immediate data
1
1
1
0
0
1
0
1
1
1
1
1
CLI i4
2
2
2
2
ZF
ZF
I3 I2 I1 I0
if (DPL) - I 3 I2 I1 I0
ZF ← 1
if (AC, t2) = [M (HL), Compare the corresponding
t2]
ZF← 0
Compare AC bit with
M data bit
1
1
1
1
0
0
0
1
1
0
1
0
1
t1 t0
1
bits specified by t0 and t1 in
AC and M (HL). Set ZF if
CMB t2
if (AC, t2) - [M (HL), identical and clear ZF if not.
t2]
[Load and store instructions]
Load AC and E from
M2 (HL)
AC ← M (HL),
E ← M (HL + 1)
Load the contents of M2 (HL)
into AC, E.
LAE
0
1
0
1
1
1
0
0
1
1
2
1
1
1
1
2
1
1
Load AC with
LAI i4
Load the immediate data
into AC.
Has a vertical
skip function
1
1
0
1
0
0
0
0
I3 I2 I1 I0
AC ← I3 I2 I1 I0
AC ← [M (i8)]
M (HL) ← (AC)
ZF
ZF
immediate data
Load AC from M
0
0
0
1
Load the contents of M (i8)
into AC.
LADR i8
direct
I7 I6 I5 I4 I3 I2 I1 I0
Store the contents of AC into
M (HL).
S
Store AC to M
0
0
1
1
0
0
0
1
0
1
1
1
1
1
1
0
Store AC and E to
M2 (HL)
M (HL) ← (AC)
M (HL + 1) ← (E)
Store the contents of AC, E
into M2 (HL).
SAE
Load the contents of M (reg)
into AC.
The reg is either HL or XY
depending on t0.
Load AC from
M (reg)
LA reg
0
1
0
0
1
0
t0
0
1
1
AC ← [M (reg)]
ZF
reg
T0
HL
XY
0
1
Continued on next page.
No. 5484-15/21
LC66354C, 66356C, 66358C
Continued from preceding page.
Instruction code
D7 D6 D5 D4 D3 D2 D1 D0
Affected
status
bits
Mnemonic
Operation
Description
Note
[Load and store instructions]
Load the contents of M (reg)
into AC. (The reg is either HL
or XY.) Then increment the
ZF is set
according to the
result of
incrementing
DPL or DPY.
AC ← [M (reg)]
DPL ← (DPL) + 1
Load AC from M (reg)
LA reg, I
0
0
1
1
0
0
0
1
1
1
0
0
t0
1
1
1
1
2
2
contents of either DPL or DPY. ZF
then increment reg
or DPY ← (DPY) + 1 The relationship between t0
and reg is the same as that
for the LA reg instruction.
Load the contents of M (reg)
into AC. (The reg is either HL
or XY.) Then decrement the
ZF is set
according to the
result of
decrementing
DPL or DPY.
AC ← [M (reg)]
DPL ← (DPL) – 1
Load AC from M (reg)
LA reg, D
t0
contents of either DPL or DPY. ZF
then decrement reg
or DPY ← (DPY) – 1 The relationship between t0
and reg is the same as that
for the LA reg instruction.
Exchange the contents of
M (reg) and AC.
The reg is either HL or XY
depending on t0.
Exchange AC with
XA reg
M (reg)
0
1
0
0
1
1
t0
0
1
1
(AC) ↔ [M (reg)]
reg
T0
HL
XY
0
1
Exchange the contents of
M (reg) and AC. (The reg is
either HL or XY.) Then
increment the contents of
either DPL or DPY. The
relationship between t0 and
reg is the same as that for
the XA reg instruction.
ZF is set
according to the
result of
incrementing
DPL or DPY.
Exchange AC with
XA reg, I M (reg) then
increment reg
(AC) ↔ [M (reg)]
DPL ← (DPL) + 1
or DPY ← (DPY) + 1
0
1
0
0
1
1
t0
1
1
2
ZF
Exchange the contents of
M (reg) and AC. (The reg is
either HL or XY.) Then
decrement the contents of
either DPL or DPY. The
relationship between t0 and
reg is the same as that for
the XA reg instruction.
ZF is set
according to the
result of
decrementing
DPL or DPY.
Exchange AC with
XA reg, D M (reg) then
decrement reg
(AC) ↔ [M (reg)]
DPL ← (DPL) – 1
or DPY ← (DPY) – 1
0
1
1
1
0
0
1
0
1
1
1
0
t0
1
0
1
2
ZF
Exchange AC with
XADR i8
0
Exchange the contents of AC
and M (i8).
2
2
2
2
(AC) ↔ [M (i8)]
M direct
I7 I6 I5 I4 I3 I2 I1 I0
Load E & AC with
LEAI i8
1
1
0
0
0
1
1
0
E ← I7 I6 I5 I4
AC ← I3 I2 I1 I0
Load the immediate data i8
into E, AC.
immediate data
I7 I6 I5 I4 I3 I2 I1 I0
Load into E, AC the ROM data
at the location determined by
[ROM (PCh, E, AC)] replacing the lower 8 bits of
the PC with E, AC.
Read table data from
RTBL
E, AC ←
0
0
1
1
0
0
1
1
1
1
0
0
1
0
0
0
1
1
2
2
program ROM
Output from ports 4 and 5 the
ROM data at the location
Read table data from
RTBLP program ROM then
output to P4, 5
Port 4, 5 ←
determined by replacing the
[ROM (PCh, E, AC)]
lower 8 bits of the PC with
E, AC.
[Data pointer manipulation instructions]
Load DPH with zero
and DPL with
immediate data
respectively
DPH ← 0
DPL ← I3 I2 I1 I0
Load zero into DPH and the
immediate data i4 into DPL.
LDZ i4
0
1
1
0
I3 I2 I1 I0
1
1
Load DPH with
immediate data
1
0
1
0
0
0
0
0
1
1
1
1
Load the immediate data i4
into DPH.
LHI i4
LLI i4
2
2
2
2
2
2
2
2
DPH ← I3 I2 I1 I0
DPL ← I3 I2 I1 I0
I3 I2 I1 I0
Load DPL with
immediate data
1
0
1
0
0
0
0
1
1
1
1
1
Load the immediate data i4
into DPL.
I3 I2 I1 I0
Load DPH, DPL with
immediate data
1
1
0
0
0
0
0
0
DPH ← I7 I6 I5 I4
DPL ← I3 I2 I1 I0
Load the immediate data into
DLH, DPL.
LHLI i8
LXYI i8
I7 I6 I5 I4 I3 I2 I1 I0
Load DPX, DPY with
immediate data
1
1
0
0
0
0
0
0
DPX ← I7 I6 I5 I4
DPY ← I3 I2 I1 I0
Load the immediate data into
DLX, DPY.
I7 I6 I5 I4 I3 I2 I1 I0
Continued on next page.
No. 5484-16/21
LC66354C, 66356C, 66358C
Continued from preceding page.
Instruction code
D7 D6 D5 D4 D3 D2 D1 D0
[Data pointer manipulation instructions]
Affected
status
bits
Mnemonic
Operation
Description
Note
Increment the contents
of DPL.
IL
Increment DPL
0
0
0
0
0
0
0
0
0
1
0
1
1
0
1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
2
2
1
2
2
1
2
2
1
2
2
1
1
1
1
1
2
2
1
2
2
1
2
2
1
2
2
1
DPL ← (DPL) + 1
DPL ← (DPL) – 1
DPY ← (DPY) + 1
DPY ← (DPY) – 1
DPH ← (AC)
ZF
ZF
ZF
ZF
Decrement the contents
of DPL.
DL
Decrement DPL
Increment DPY
Increment the contents
of DPY.
IY
Decrement the contents
of DPY.
DY
Decrement DPY
Transfer AC to DPH
Transfer DPH to AC
1
1
1
1
0
1
0
1
1
0
1
0
1
0
1
0
Transfer the contents of AC
to DPH.
TAH
THA
XAH
TAL
TLA
XAL
TAX
TXA
XAX
TAY
TYA
XAY
1
1
1
1
0
1
0
0
1
0
1
0
1
0
1
0
Transfer the contents of DPH
to AC.
AC ← (DPH)
ZF
ZF
ZF
ZF
Exchange AC
with DPH
Exchange the contents of AC
and DPH.
0
1
0
0
0
0
0
0
(AC) ↔ (DPH)
DPL ← (AC)
1
1
1
1
0
1
0
1
1
0
1
0
1
0
1
1
Transfer the contents of AC
to DPL.
Transfer AC to DPL
Transfer DPL to AC
1
1
1
1
0
1
0
0
1
0
1
0
1
0
1
1
Transfer the contents of DPL
to AC.
AC ← (DPL)
Exchange AC
with DPL
Exchange the contents of AC
and DPL.
0
1
0
0
0
0
0
1
(AC) ↔ (DPL)
DPX ← (AC)
1
1
1
1
0
1
0
1
1
0
1
0
1
1
1
0
Transfer the contents of AC
to DPX.
Transfer AC to DPX
Transfer DPX to AC
1
1
1
1
0
1
0
0
1
0
1
0
1
1
1
0
Transfer the contents of DPX
to AC.
AC ← (DPX)
Exchange AC
with DPX
Exchange the contents of AC
and DPX.
0
1
0
0
0
0
1
0
(AC) ↔ (DPX)
DPY ← (AC)
1
1
1
1
0
1
0
1
1
0
1
0
1
1
1
1
Transfer the contents of AC
to DPY.
Transfer AC to DPY
Transfer DPY to AC
1
1
1
1
0
1
0
0
1
0
1
0
1
1
1
1
Transfer the contents of DPY
to AC.
AC ← (DPY)
Exchange AC
with DPY
Exchange the contents of AC
and DPY.
0
1
0
0
0
0
1
1
(AC) ↔ (DPY)
[Flag manipulation instructions]
SFB n4 Set flag bit
Set the flag specified
by n4 to 1.
0
0
1
0
1
1
1
1
n3 n2 n1 n0
n3 n2 n1 n0
1
1
1
1
Fn ← 1
Fn ← 0
Reset the flag specified
by n4 to 0.
RFB n4 Reset flag bit
ZF
[Jump and subroutine instructions]
This becomes
PC12 + (PC12)
immediately
following a BANK
instruction.
PC13, 12 ←
PC13, 12
PC11 to 0 ←
P11 to P8
Jump to the location in the
same bank specified by the
immediate data P12.
JMP
addr
Jump in the current
bank
1
1
1
0
P11P10P9 P8
2
1
2
1
P7 P6 P5 P4 P3 P2 P1 P0
PC13 to 8 ←
PC13 to 8,
PC7 to 4 ← (E),
PC3 to 0 ← (AC)
Jump to the location
determined by replacing the
lower 8 bits of the PC
by E, AC.
Jump to the address
stored at E and AC
in the current page
JPEA
0
0
1
0
0 1 1 1
PC13 to 11 ← 0,
PC10 to 0 ←
P10 to P0,
CAL
addr
0
1
0
1
0 P10P9 P8
Call subroutine
2
2
Call a subroutine.
P7 P6 P5 P4 P3 P2 P1 P0
M4 (SP) ←
(CF, ZF, PC13 to 0),
SP ← (SP)-4
PC13 to 6,
PC10 ← 0,
CZP
addr
Call subroutine in the
zero page
PC5 to 2 ← P3 to P0, Call a subroutine on page 0
1
0
0
1
0
0
1
P3 P2 P1 P0
1
1
2
1
M4 (SP) ←
in bank 0.
(CF, ZF, PC12 to 0),
SP ← SP-4
Change the memory bank
and register bank.
BANK
Change bank
0
1 0 1 1
Continued on next page.
No. 5484-17/21
LC66354C, 66356C, 66358C
Continued from preceding page.
Instruction code
D7 D6 D5 D4 D3 D2 D1 D0
Affected
status
bits
Mnemonic
Operation
Description
Note
[Jump and subroutine instructions]
Store the contents of reg in
M2 (SP). Subtract 2 from SP
after the store.
reg
i1 i0
PUSH
reg
1
1
1
1
0
1
0
1
1
1
1
i1 i0
1
1
0
M2 (SP) ← (reg)
SP ← (SP) – 2
Push reg on M2 (SP)
2
2
2
2
HL
XY
AE
0
0
1
1
0
1
0
1
Illegal value
Add 2 to SP and then load the
contents of M2(SP) into reg.
The relation between i1i0 and
reg is the same as that for the
PUSH reg instruction.
POP
reg
1
1
1
1
0
1
0
0
1
1
1
i1 i0
1
1
0
SP ← (SP) + 2
reg ← [M2 (SP)]
Pop reg off M2 (SP)
Return from a subroutine or
interrupt handling routine. ZF
and CF are not restored.
Return from
subroutine
SP ← (SP) + 4
PC ← [M4 (SP)]
RT
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
1
1
1
2
2
SP ← (SP) + 4
PC ← [M4 (SP)]
Return from a subroutine or
interrupt handling routine. ZF ZF, CF
CF, ZF ← [M4 (SP)] and CF are restored.
Return from interrupt
routine
RTI
[Branch instructions]
PC7 to 0 ←
P7 P6 P5 P4
Branch to the location in the
BAt2
addr
1
1
0
1
0
0
t1 t0
same page specified by P7 to
P0 if the bit in AC specified by
the immediate data t1 t0 is one.
Branch on AC bit
2
2
2
2
P7 P6 P5 P4 P3 P2 P1 P0
P3 P2 P1 P0
if (AC, t2) = 1
PC7 to 0 ←
Branch to the location in the
same page specified by P7 to
P0 if the bit in AC specified by
the immediate data t1 t0 is zero.
BNAt2
addr
1
0
0
1
0
0
t1 t0
P7 P6 P5 P4
P3 P2 P1 P0
if (AC, t2) = 0
Branch on no AC bit
Branch on M bit
P7 P6 P5 P4 P3 P2 P1 P0
PC7 to 0 ←
Branch to the location in the
same page specified by P7 to
P0 if the bit in M (HL) specified
by the immediate data t1 t0
is one.
P7 P6 P5 P4
P3 P2 P1 P0
if [M (HL),t2]
= 1
BMt2
addr
1
1
0
1
0
1
t1 t0
2
2
2
2
P7 P6 P5 P4 P3 P2 P1 P0
PC7 to 0 ←
Branch to the location in the
same page specified by P7 to
P0 if the bit in M (HL) specified
by the immediate data t1 t0
is zero.
P7 P6 P5 P4
P3 P2 P1 P0
if [M (HL),t2]
= 0
BNMt2
addr
1
0
0
1
0
1
t1 t0
Branch on no M bit
P7 P6 P5 P4 P3 P2 P1 P0
Internal control
registers can also
be tested by
executing this
instruction
immediately after
a BANK
instruction.
PC7 to 0 ←
Branch to the location in the
same page specified by P7 to
P0 if the bit in port (DPL)
specified by the immediate
data t1 t0 is one.
P7 P6 P5 P4
P3 P2 P1 P0
if [P (DPL), t2]
= 1
BPt2
addr
1
1
0
1
1
0
t1 t0
Branch on Port bit
2
2
P7 P6 P5 P4 P3 P2 P1 P0
However, this is
limited to
registers that can
be read out.
Internal control
registers can also
be tested by
executing this
instruction
immediately after
a BANK
instruction.
PC7 to 0 ←
Branch to the location in the
same page specified by P7 to
P0 if the bit in port (DPL)
specified by the immediate
data t1 t0 is zero.
P7 P6 P5 P4
P3 P2 P1 P0
if [P (DPL), t2]
= 0
BNPt2
addr
1
0
0
1
1
0
t1 t0
Branch on no Port bit
2
2
P7 P6 P5 P4 P3 P2 P1 P0
However, this is
limited to
registers that can
be read out.
Continued on next page.
No. 5484-18/21
LC66354C, 66356C, 66358C
Continued from preceding page.
Instruction code
D7 D6 D5 D4 D3 D2 D1 D0
Affected
status
bits
Mnemonic
Operation
Description
Note
[Branch instructions]
PC7 to 0 ←
P7 P6 P5 P4
Branch to the location in the
same page specified by P7 to
P0 if CF is one.
1
1
0
1
1 1 0 0
BC addr Branch on CF
2
2
2
2
2
2
2
2
P
7 P6 P5 P4 P3 P2 P1 P0
P3 P2 P1 P0
if (CF) = 1
PC7 to 0 ←
7 P6 P5 P4
Branch to the location in the
same page specified by P7 to
P0 if CF is zero.
BNC
1
0
0
1
1
1
0
0
P
Branch on no CF
addr
P7 P6 P5 P4 P3 P2 P1 P0
P3 P2 P1 P0
if (CF) = 0
PC7 to 0 ←
7 P6 P5 P4
Branch to the location in the
same page specified by P7 to
P0 if ZF is one.
1
1
0
1
1
1
0
1
P
BZ addr Branch on ZF
P
7 P6 P5 P4 P3 P2 P1 P0
P3 P2 P1 P0
if (ZF) = 1
PC7 to 0 ←
7 P6 P5 P4
Branch to the location in the
same page specified by P7 to
P0 if ZF is zero.
BNZ
1
0
0
1
1
1
0
1
P
Branch on no ZF
addr
P7 P6 P5 P4 P3 P2 P1 P0
P3 P2 P1 P0
if (ZF) = 0
Branch to the location in the
same page specified by P0 to
P7 if the flag (of the 16 user
flags) specified by n3 n2 n1 n0
is one.
PC7 to 0 ←
P7 P6 P5 P4
3 P2 P1 P0
if (Fn) = 1
BFn4
1
1
1
1
n3 n2 n1 n0
Branch on flag bit
addr
2
2
2
2
P7 P6 P5 P4 P3 P2 P1 P0
P
Branch to the location in the
same page specified by P0 to
P7 if the flag (of the 16 user
flags) specified by n3 n2 n1 n0
is zero.
PC7 to 0 ←
P7 P6 P5 P4
3 P2 P1 P0
if (Fn) = 0
BNFn4
1
0
1
1
n3 n2 n1 n0
Branch on no flag bit
addr
P7 P6 P5 P4 P3 P2 P1 P0
P
[I/O instructions]
Input the contents of port
0 to AC.
IP0
IP
Input port 0 to AC
Input port to AC
Input port to M
0
0
0
0
0
0
1
1
0
0
0
1
0
0
0
1
0
1
0
0
1
1
1
1
AC ← (P0)
ZF
ZF
Input the contents of port
P (DPL) to AC.
AC ← [P (DPL)]
Input the contents of port
P (DPL) to M (HL).
IPM
1
1
0
1
0
1
1
1
1
2
1
2
M (HL) ← [P (DPL)]
AC ← [P (i4)]
Input port to
AC direct
1
0
1
1
0
1
0
0
Input the contents of
P (i4) to AC.
IPDR i4
ZF
I3 I2 I1 I0
Input the contents of ports
P (4) and P (5) to E and AC
respectively.
Input port 4, 5 to
E, AC respectively
1
1
1
1
0
0
0
1
1
0
1
1
1
0
1
0
E ← [P (4)]
AC ← [P (5)]
IP45
2
2
Output the contents of AC to
port P (DPL).
OP
Output AC to port
Output M to port
0
0
0
0
1
0
0
1
0
1
0
1
1
1
2
1
1
2
P (DPL) ← (AC)
P (DPL) ← [M (HL)]
P (i4) ← (AC)
Output the contents of M (HL)
to port P (DPL).
OPM
1
1
0
1
1
1
0
1
Output AC to
port direct
1
0
1
1
0
1
0
1
Output the contents of AC
to P (i4).
OPDR i4
I3 I2 I1 I0
Output the contents of E and
AC to ports P (4) and P (5)
respectively.
Output E, AC to port
4, 5 respectively
1
1
1
1
0
0
0
1
1
0
1
1
1
0
1
1
P (4) ← (E)
P (5) ← (AC)
OP45
2
1
1
2
1
1
Set to one the bit in port
P (DPL) specified by the
immediate data t1 t0.
SPB t2
RPB t2
Set port bit
0
0
1
0
0
1
0
1
0
0
0
0
1
1
0
0
0
1
t1 t0
[P (DPL), t2] ← 1
[P (DPL), t2] ← 0
Clear to zero the bit in port
P (DPL) specified by the
immediate data t1 t0.
Reset port bit
t1 t0
ZF
ZF
Take the logical AND of P (P3
to P0) and the immediate data
I3 I2 I1 I0 and output the result
to P (P3 to P0).
And port with
immediate data then
output
P (P3 to P0) ←
[P (P3 to P0)]
I3 to I0
ANDPDR
i4, p4
0 1
2
2
2
2
I3 I2 I1 I0 P3 P2 P1 P0
Take the logical OR of P (P3
Or port with
immediate data then
output
P (P3 to P0) ←
[P (P3 to P0)]
I3 to I0
ORPDR
i4, p4
1
1
0
0
0
1
0
0
to P0) and the immediate data ZF
I3 I2 I1 I0 and output the result
to P (P3 to P0).
I3 I2 I1 I0 P3 P2 P1 P0
Continued on next page.
No. 5484-19/21
LC66354C, 66356C, 66358C
Continued from preceding page.
Instruction code
D7 D6 D5 D4 D3 D2 D1 D0
Affected
status
bits
Mnemonic
Operation
Description
Note
[Timer control instructions]
WTTM0 Write timer 0
Write the contents of M2 (HL),
AC into the timer 0 reload
register.
TIMER0 ← [M2 (HL)],
(AC)
1
1
0
0
1
0
1
0
1
2
1
2
2
2
Write the contents of E, AC
TIMER1 ← (E), (AC) into the timer 1 reload
1
1
1
1
0
1
0
1
1
0
1
1
1
0
1
0
WTTM1 Write timer 1
register A.
Read out the contents of the
timer 0 counter into M2 (HL),
AC.
M2 (HL),
AC ← (TIMER0)
RTIM0
RTIM1
Read timer 0
Read timer 1
1
1
0
0
1
0
1
1
1
1
1
1
0
1
0
1
1
0
1
1
1
0
1
1
Read out the contents of the
E, AC ← (TIMER1)
2
2
2
2
2
2
2
2
2
2
timer 1 counter into E, AC.
1
1
1
1
0
1
0
0
1
0
1
1
1
1
1
0
START0 Start timer 0
START1 Start timer 1
STOP0 Stop timer 0
Start timer 0 counter Start the timer 0 counter.
Start timer 1 counter Start the timer 1 counter.
Stop timer 0 counter Stop the timer 0 counter.
Stop timer 1 counter Stop the timer 1 counter.
1
1
1
1
0
1
0
0
1
0
1
1
1
1
1
1
1
1
1
1
0
1
0
1
1
0
1
1
1
1
1
0
1
1
1
1
0
1
0
1
1
0
1
1
1
1
1
1
STOP1 Stop timer 1
[Interrupt control instructions]
Set interrupt master
enable flag
1
0
1
1
0
0
0
1
1
0
1
0
0
0
1
0
Set the interrupt master
MSE ← 1
MSET
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
enable flag to one.
Reset interrupt
MRESET
1
1
1
0
0
0
0
1
1
0
1
0
0
0
1
0
Clear the interrupt master
MSE ← 0
master enable flag
enable flag to zero.
1
0
1
1
0
0
0
1
1
1
0
1
Set the interrupt enable flag
to one.
EIH i4
EIL i4
DIH i4
DIL i4
WTSP
RSP
Enable interrupt high
Enable interrupt low
Disable interrupt high
Disable interrupt low
Write SP
EDIH ← (EDIH) i4
I3 I2 I1 I0
1
0
1
1
0
0
0
0
1
1
0
1
Set the interrupt enable flag
to one.
EDIL ← (EDIL) i4
I3 I2 I1 I0
1
1
1
0
0
0
0
1
1
1
0
1
Clear the interrupt enable
EDIH ← (EDIH) i4
ZF
ZF
I3 I2 I1 I0
flag to zero.
1
1
1
0
0
0
0
0
1
1
0
1
Clear the interrupt enable
EDIL ← (EDIL) i4
I3 I2 I1 I0
flag to zero.
1
1
1
1
0
0
0
1
1
1
1
0
1
1
1
0
Transfer the contents of E,
AC to SP.
SP ← (E), (AC)
1
1
1
1
0
0
0
1
1
1
1
0
1
1
1
1
Transfer the contents of SP
to E, AC.
Read SP
E, AC ← (SP)
[Standby control instructions]
1
1
1
1
0
0
0
1
1
1
1
1
1
1
1
0
HALT
HOLD
HALT
HOLD
2
2
2
2
HALT
HOLD
Enter halt mode.
Enter hold mode.
1
1
1
1
0
0
0
1
1
1
1
1
1
1
1
1
[Serial I/O control instructions]
STARTS Start serial I O
1
1
1
1
0
1
0
0
1
1
1
1
1
1
1
0
2
2
2
2
2
2
START SI O
Start SIO operation.
1
1
1
1
0
1
0
0
1
1
1
1
1
1
1
1
Write the contents of E,
AC to SIO.
WTSIO Write serial I O
SIO ← (E), (AC)
E, AC ← (SIO)
1
1
1
1
0
1
0
1
1
1
1
1
1
1
1
1
Read out the contents of SIO
into E, AC.
RSIO
Read serial I O
[Other instructions]
Consume one machine cycle
without performing any
operation.
NOP
No operation
0
0
0
0
0
0
0
1
0
1
1
2
1
2
No operation
1
1
1
1
0
0
0
0
1
0
1
0
SB i2
Select bank
PC12 ← I1 I0
Specify the memory bank.
I1 I0
Note: The range of for i2 in SB instruction varies according to device. Refer to User’s Manual for that.
No. 5484-20/21
LC66354C, 66356C, 66358C
■ No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace
equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of
which may directly or indirectly cause injury, death or property loss.
■ Anyone purchasing any products described or contained herein for an above-mentioned use shall:
➀ Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and
distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all
damages, cost and expenses associated with such use:
➁ Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on
SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees
jointly or severally.
■ Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for
volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied
regarding its use or any infringements of intellectual property rights or other rights of third parties.
This catalog provides information as of February, 1997. Specifications and information herein are subject to
change without notice.
No. 5484-21/21
相关型号：
LC66F408
4K/6K/8K-BYTE ROM-CONTAINED SINGLE-CHIP 4-BIT MICROCOMPUTER FOR CONTROL-ORIENTED APPLICATIONS
SANYO
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