LC72321 [SANYO]
Single-Chip Microcontroller with PLL and LCD Driver; 单芯片微控制器，带有PLL和LCD驱动器
| 型号： | LC72321 |
| 厂家： | 
SANYO SEMICON DEVICE |
| 描述： | Single-Chip Microcontroller with PLL and LCD Driver |
| 文件： | 总13页 (文件大小：235K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Ordering number : EN4796A
CMOS LSI
LC72321
Single-Chip Microcontroller with PLL
and LCD Driver
Preliminaly
Overview
The LC72321 is a single-chip microcontroller for use in
electronic tuning applications. It includes on chip both
LCD drivers and a PLL circuit that can operate at up to
150 MHz. It features a large-capacity ROM, a highly
efficient instruction set, and powerful hardware.
• Voltage detection type reset circuit
• One 6-bit A/D converter
• Two 8-bit D/A converters (PWM)
• One external interrupt (The LC72321 provides an
external interrupt, and internal interrupt and a serial I/O
interrupt, one of which can be selected under program
control.)
• Hold mode for RAM backup
• Sense FF for hot/cold startup determination
• PLL: 4.5 to 5.5 V
Functions
• Serial I/O
• Built-in timer interrupts: 80 µs, 1 ms, 2 ms and 5 ms
• Stack: Eight levels
• Beep control: Six beep tones (2.08, 2.25, 2.5, 3.0, 3.75,
and 4.17 kHz)
• CPU: 3.5 to 5.5 V
• RAM: 1.3 to 5.5 V
• Fast programmable divider
• General-purpose counters: HCTR for frequency
measurement and LCTR for frequency or period
measurement
• LCD driver for displays with up to 56 segments
(1/2 duty, 1/2 bias)
Package Dimensions
unit: mm
3174-QIP80E
[LC72321]
• Program memory (ROM): 16 bits × 4095
• Data memory (RAM): 4 bits × 256
• All instructions are single-word instructions
• Cycle time: 2.67 µs, 13.33 µs, or 40.00 µs (option)
• Unlock FF: 0.55 µs detection, 1.1 µs detection
• Timer FF:
1 ms, 5ms, 25ms, 125ms
• Input ports*: One dedicated key input port and one
high breakdown voltage port
• Output ports*: Two dedicated key output ports, one high
breakdown voltage open drain port
Two CMOS output ports (of which one
can be switched to be used as LCD driver
outputs)
Seven CMOS output ports (mask option
switchable to use as LCD ports)
SANYO: QIP80E
• I/O ports*:
One switchable between input and output
in four-bit units and one switchable
between input and output in one-bit units
Note: * Each port consists of four bits
• Program runaway can be detected and a special address
set. (Programmable watchdog timer)
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110 JAPAN
83194TH (OT) No. 4796-1/13
LC72321
Pin Assignment
No. 4796-2/13
LC72321
Block Diagram
No. 4796-3/13
LC72321
Specifications
Absolute Maximum Ratings at Ta = 25°C, VSS = 0 V
Parameter
Maximum supply voltage
Symbol
DD max
Conditions
Ratings
–0.3 to +6.5
–0.3 to +13
–0.3 to VDD + 0.3
–0.3 to +15
–0.3 to VDD + 0.3
0 to 5
Unit
V
V
V
IN1
IN2
HOLD, INT, RES, SNS, and the G port
V
Input voltage
V
Inputs other than VIN
1
V
V
OUT1
OUT2
H port
V
Output voltage
V
Outputs other than VOUT
All D and H port pins
All E and F port pins
All B and C port pins
1
V
I
I
I
I
OUT1
OUT2
OUT3
OUT4
mA
mA
mA
mA
mW
°C
°C
0 to 3
Output current
0 to 1
S1 to S28 and all I port pins
Ta = –40 to +85°C
0 to 1
Allowable power dissipation
Operating temperature range
Storage temperature range
Pd max
Topg
300*
–40 to +85
–45 to +125
Tstg
Note: * Reference value
Allowable Operating Ranges at Ta = –40 to +85°C, V = 3.5 to 5.5 V
DD
Ratings
typ
Parameter
Symbol
Conditions
Unit
min
4.5
max
5.5
VDD1
VDD2
VDD3
CPU and PLL operating
CPU operating
Memory retention voltage
G port
V
V
V
V
V
V
V
V
Supply voltage
3.5
1.3
5.5
5.5
V
IH1
IH2
IH3
IH4
IH5
0.7 VDD
0.8 VDD
2.5
8.0
V
RES, INT, HOLD
SNS
8.0
V
V
V
8.0
Input high level voltage
A port
0.6 VDD
0.7 VDD
VDD
VDD
PE0, PE2, F port
LCTR (period measurement),
VIH6
0.8 VDD
VDD
V
VDD1, PE1, PE3
V
V
V
V
V
V
V
IL1
IL2
IL3
IL4
IL5
IL6
IL7
G port
0
0
0.3 VDD
0.2 VDD
1.3
V
V
RES, INT, PE1, PE3
SNS
0
V
Input low level voltage
A port
0
0.2 VDD
0.3 VDD
0.2 VDD
0.4 VDD
5.0
V
PE0, PE2, F port
0
V
LCTR (period measurement), VDD
1
0
V
HOLD
XIN
0
V
fIN1
fIN2
fIN3
fIN4
fIN5
fIN6
fIN7
fIN8
4.0
10
10
0.5
2.0
0.4
100
1
4.5
MHz
MHz
MHz
MHz
MHz
MHz
kHz
Hz
FMIN, VIN2, VDD
1
1
130
FMIN, VIN3, VDD
150
AMIN (L), VIN4, VDD
AMIN (H), VIN5, VDD
HCTR, VIN6, VDD
LCTR (frequency), VIN7, VDD
1
10
Input frequency
1
40
1
12
1
500
3
LCTR (period), VIH6, VIL6, VDD
1
20 × 10
V
V
V
IN1
IN2
IN3
XIN
0.50
0.10
0.15
0.10
0.10
0
1.5
1.5
Vrms
Vrms
Vrms
Vrms
Vrms
V
FMIN
Input amplitude
FMIN
1.5
V
V
IN4, 5
IN6, 7
AMIN
1.5
LCTR, HCTR
ADI
1.5
Input voltage range
V
IN8
VDD
No. 4796-4/13
LC72321
Electrical Characteristics for the Allowable Operating Ranges
Ratings
typ
Parameter
Symbol
Conditions
Unit
min
max
Hysteresis
VH
LCTR (period), RES, INT, PE1, PE3
SNS
0.1 VDD
V
µs
V
Rejected pulse width
PREJ
VDET
50
Power-down detection voltage
2.7
3.0
3.3
INT, HOLD, RES, ADI, SNS,
and the G port: VI = 5.5 V
IIH1
3.0
µA
A, E, and F ports: E and F ports with
outputs off, A port with no RPD, VI = VDD
IIH
IIH
IIH
2
3
4
3.0
15
30
µA
µA
µA
µA
µA
Input high level current
XIN: VI = VDD = 5.0 V
2.0
4.0
5.0
10
50
FMIN, AMIN, HCTR, LCTR:
VI = VDD = 5.0 V
I
IH5
IIL
IL2
A port: With an RPD, VI = VDD = 5.0 V
INT, HOLD, RES, ADI, SNS,
and the G port: VI = VSS
1
3.0
3.0
A, E, and F ports: E and F ports with
outputs off, A port with no RPD, VI = VSS
I
µA
Input low level current
IIL
3
XIN: VIN = VSS
2.0
4.0
5.0
10
15
30
µA
µA
V
I
IL4
FMIN, AMIN, HCTR, LCTR: VI = VSS
A port: With an RPD
Input floating voltage
Pull-down resistance
VIF
0.05 VDD
200
RPD
A port: With an RPD, VDD = 5.0 V
EO1, EO2: VO = VDD
75
100
kΩ
nA
µA
µA
nA
µA
V
I
I
I
OFFH1
OFFH2
OFFH3
0.01
10
Output high level off leakage current
Output low level off leakage current
B, C, D, E, F, and I ports: VO = VDD
H port: VO = 13 V
3.0
5.0
I
I
OFFL1
OFFL2
EO1, EO2: VO = VSS
0.01
10
B, C, D, E, F, and I ports: VO = VSS
B and C ports: IO = 1 mA
E and F ports: IO = 1 mA
EO1, EO2: IO = 500 µA
XOUT: IO = 200 µA
3.0
V
OH1
OH2
OH3
OH4
OH5
OH6
OH7
VDD – 2.0
VDD – 1.0
VDD – 1.0
VDD – 1.0
VDD – 1.0
VDD – 1.0
VDD – 0.75
0.5
VDD – 1.0
VDD – 0.5
V
V
V
V
V
V
V
V
Output high level voltage
V
S1 to S28 and the I port: IO = –0.1 mA
D port: IO = 5 mA
V
V
COM1, COM2: IO = 25 µA
B and C ports: IO = 50 µA
E and F ports: IO = 1 mA
EO1, EO2: IO = 500 µA
XOUT: IO = 200 µA
VDD – 0.5
1.0
VDD – 0.3
V
VOL1
VOL2
VOL3
VOL4
VOL5
VOL6
VOL7
VOL8
2.0
V
1.0
V
1.0
V
1.0
V
Output low level voltage
S1 to S28 and the I port: IO = 0.1 mA
D port: IO = 5 mA
1.0
V
1.0
0.75
V
COM1, COM2: IO = 25 µA
H port: IO = 5 mA
0.3
(150 Ω) 0.75
2.0
0.5
2.5
V
(400 Ω) 2.0
3.0
V
Output middle level voltage
A/D conversion error
VM1
COM1, COM2: VDD = 5.0 V, IO = 25 µA
ADI: VDD1
V
–1/2
1/2
LSB
mA
IDD1
VDD1, fIN2 = 130 MHz
15
20
VDD1, PLL stopped, CT = 2.67 µs
(HOLD mode, Figure 1)
IDD
2
1.5
mA
mA
mA
µA
VDD1, PLL stopped, CT = 13.33 µs
(HOLD mode, Figure 1)
I
DD3
DD4
1.0
0.7
Current drain
VDD1, PLL stopped, CT = 40.00 µs
(HOLD mode, Figure 1)
I
V
DD = 5.5 V, oscillator stopped, Ta = 25°C
(BACKUP mode, Figure 2)
DD = 2.5 V, oscillator stopped, Ta = 25°C
(BACKUP mode, Figure 2)
5
1
IDD5
V
µA
No. 4796-5/13
LC72321
Test Circuits
Note: PB to PF, PH, and PI are all open. However, PE and PF are output selected.
Figure 1 I 2 to I 4 in HOLD Mode
DD
DD
Note: PA to PI, S1 to S4, COM1, and COM2 are all open.
Figure 2 I 5 in BACK UP Mode
DD
No. 4796-6/13
LC72321
Pin Functions
Pin
Pin No.
Function
I/O
I/O circuit type
Low threshold type dedicated input port
PA0
PA1
PA2
PA3
35
34
33
32
These pins can be used, for example, for key data acquisition.
Built-in pull-down resistors can be specified as an option. This
option is in 4-pin units, and cannot be specified for individual
pins.
Input
Input through these pins is disabled in BACKUP mode.
PB0
PB1
PB2
PB3
PC0
PC1
PC2
PC3
30
29
28
27
26
25
24
23
Dedicated output ports
Since the output transistor impedances are unbalanced
CMOS, these pins can be effectively used for functions such
as key scan timing. These pins go to the output high
impedance state in BACKUP mode.
These pins go to the low level during a reset, i.e., when the
RES pin is low.
Output
Dedicated output ports
PD0
PD1
PD2
PD3
22
21
20
19
These are normal CMOS outputs. These pins go to the output
high impedance state in BACKUP mode.
These pins go to the low level during a reset, i.e., when the
RES pin is low.
I/O port
These pins are switched between input and output as follows.
Once an input instruction (IN, TPT, or TPF) is executed, these
pins latch in the input mode. Once an output instruction (OUT,
SPB, or RPB) is executed, they latch in the output mode.
PE0
18
17
16
15
PE1/SCK
PE2/SO
PE3/SI
Note that PE1, PE2 and PE3 are also used as the serial I/O
port. These pins go to the input mode during a reset, i.e.,
when the RES pin is low.
In BACKUP mode these pins go to the input mode with input
disabled.
I/O
I/O port
These pins are switched between input and output by the
FPC instruction.
PF0
PF1
PF2
PF3
14
13
12
11
The I/O states of this port can be specified for individual pins.
These pins go to the input mode during a reset, i.e., when the
RES pin is low.
In BACKUP mode these pins go to the input mode with input
disabled.
PG0
PG1
PG2
PG3
6
5
4
3
Dedicated input port
Input
Input through these pins is disabled in BACKUP mode.
Continued on next page.
No. 4796-7/13
LC72321
Continued from preceding page.
Pin
Pin No.
Function
I/O
I/O circuit type
Dedicated output port
Since these pins are high breakdown voltage n-channel
transistor open-drain outputs, they can be effectively used for
functions such as band power supply switching.
PH0
10
9
PH1/BEEP
PH2/DAC1
PH3/DAC2
Output
8
Note that PH1 is also used as the BEEP output and that PH2
and PH3 are also used as the DAC1 and DAC2 outputs.
7
These ports go to the high impedance state during a reset,
i.e., when the RES pin is low, and in BACKUP mode.
Dedicated output port
While these pins have a CMOS output circuit structure, they
can be switched to function as LCD drivers. Their function is
switched by the SS and RS instructions. These pins cannot
be switched individually.
PI0/S25
PI1/S26
PI2/S27
PI3/S28
39
38
37
36
The LCD driver function is selected and a segment off signal
is output when power is first applied or when RES is low.
Output
These pins are held at the low level in BACKUP mode.
Note that when the general-purpose port use option is
specified, these pins output the contents of IPORT when LPC
is 1, and the contents of the general-purpose output port
LATCH when LPC is 0.
LCD driver segment outputs
A frame frequency of 100 Hz and a 1/2 duty, 1/2 bias drive
type are used.
A segment off signal is output when power is first applied or
when RES is low.
S1 to S24 63 to 40
Output
These pins are held at the low level in BACKUP mode.
The use of these pins as general-purpose output ports can be
specified as an option.
LCD driver common outputs
A 1/2 duty, 1/2 bias drive type is used.
COM1
COM2
65
64
Output
The output when power is first applied or when RES is low is
identical to the normal operating mode output.
These pins are held at the low level in BACKUP mode.
FM VCO (local oscillator) input
FMIN
AMIN
74
75
The input must be capacitor-coupled.
The input frequency range is from 10 to 130 MHz.
AM VCO (local oscillator) input
Input
The band supported by this pin can be selected using the PLL
instruction.
High (2 to 40 MHz) → SW
Low (0.5 to 10 MHz) → LW and MW
Continued on next page.
No. 4796-8/13
LC72321
Continued from preceding page.
Pin
Pin No.
Function
I/O
I/O circuit type
Universal counter input
The input should be capacitor-coupled.
HCTR
70
The input frequency range is from 0.4 to 12 MHz.
This input can be effectively used for FM IF or AM IF counting.
Universal counter input
Input
The input should be capacitor-coupled for input frequencies in
the range 100 to 150 kHz.
LCTR
71
Capacitor coupling is not required for input frequencies from
1 Hz to 20 kHz.
This input can be effectively used for AM IF counting.
This pin can also be used as a normal input port.
A/D converter input
A 1.28 ms period is required for a 6-bit sequential comparison
conversion. The full scale input is ((63/96) · VDD) for a data
value of 3FH.
ADI
69
66
Input
External interrupt request input
An interrupt is generated when the INTEN flag is set (by an
SS instruction) and a falling edge is input.
INT
Input
This pin can also be used as a normal input port.
Reference frequency and programmable divisor phase
comparison error outputs
EO1
EO2
77
78
Output
Charge pump circuits are built in.
EO1 and EO2 are the same.
Input pin used to determine if a power outage has occurred in
BACKUP mode
SNS
72
67
Input
Input
This pin can also be used as a normal input port.
Input pin used to force the LC72322 to HOLD mode
The LC72322 goes to HOLD mode when the HOLDEN flag is
set (by an SS instruction) and the HOLD input goes low.
HOLD
A high breakdown voltage circuit is used so that this input can
be used in conjunction with the normal power switch.
System reset input
This signal should be held low for 75 ms after power is first
applied to effect a power-up reset.
RES
68
Input
The reset starts when a low level has been input for at least
six reference clock cycles.
Crystal oscillator connections
(4.5 MHz)
XIN
1
Input
XOUT
80
Output
A feedback resistor is built in.
TEST1
TEST2
2
LSI test pins. These pins must be connected to VSS
.
—
—
79
VDD
VSS
31, 73
76
Power supply
No. 4796-9/13
LC72321
Mask Options
No.
Description
Selections
WDT included
No WDT
1
2
WDT (watchdog timer) inclusion selection
Port A pull-down resistor inclusion selection
Pull-down resistors included
No pull-down resistors
2.67 µs
3
4
Cycle time selection
13.33 µs
40.00 µs
LCD ports
LCD port/general-purpose port selection
General-purpose output ports
Development Environment
• The LC72P321 is used for OTP.
• The LC72EV321 is used as the evaluation chip.
• A total debugging system is available in which the TB-72EV32 evaluation chip board and the RE32 multifunction
emulator are controlled by a personal computer.
No. 4796-10/13
LC72321
LC72321 Instruction Table
Abbreviations:
ADDR: Program memory address [12 bits]
b:
Borrow
B:
C:
Bank number [2 bits]
Carry
DH:
DL:
I:
Data memory address high (row address) [2 bits]
Data memory address low (column address) [4 bits]
Immediate data [4 bits]
M:
N:
Data memory address
Bit position [4 bits]
Pn:
r:
Rn:
( ):
Port number [4 bits]
General register (one of the locations 00 to 0FH in bank 0)
Register number [4 bits]
Contents of register or memory
( )N: Contents of bit N of register or memory
Operand
Machine code
D15 14 13 12 11 10
Mnemonic
Function
Operation
1st 2nd
9
8
7
6
5
4
3
2
1
D0
AD
r
r
M
M
M
M
I
Add M to r
Add M to r,
r ← (r) + (M)
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
0
0
0
1
1
1
1
1
0
0
0
0
1
0
0
0
1
1
0
0
0
1
0
0
0
1
0
1
0
1
DH
DL
Rn
r ← (r) + (M)
skip if carry
ADS
AC
DH
DH
DH
DH
DH
DH
DH
DH
DH
DL
DL
DL
DL
DL
DL
DL
DL
DL
Rn
Rn
Rn
I
then skip if carry
r
Add M to r with carry
r ← (r) + (M) + C
Add M to r with carry,
then skip if carry
r ← (r) + (M) + C
skip if carry
ACS
AI
r
M
M
M
M
r
Add I to M
M ← (M) + I
Add I to M,
then skip if carry
M ← (M) + I
skip if carry
AIS
AIC
AICS
SU
I
I
I
Add I to M with carry
M ← (M) + I + C
I
Add I to M with carry,
then skip if carry
M ← (M) + I + C
skip if carry
I
I
M
M
Subtract M from r
r ← (r) – (M)
Rn
Rn
Subtract M from r,
then skip if borrow
r ← (r) – (M)
skip if borrow
SUS
r
Subtract M from r with
borrow
SB
r
r
M
M
r ← (r) – (M) – b
0
0
1
1
1
1
0
0
1
0
0
0
DH
DH
DL
DL
Rn
Rn
Subtract M from r with
borrow,
then skip if borrow
r ← (r) – (M) – b
skip if borrow
SBS
SI
M
M
I
I
Subtract I from M
M ← (M) – I
0
0
1
1
1
1
1
1
0
0
0
1
DH
DH
DL
DL
I
I
Subtract I from M,
then skip if borrow
M ← (M) – I
skip if borrow
SIS
Subtract I from M with
borrow
SIB
M
M
r
I
I
M ← (M) – I – b
0
0
0
0
0
0
1
1
0
0
0
0
1
0
0
0
1
1
1
1
0
0
1
1
1
1
0
1
0
1
0
1
1
1
1
1
DH
DH
DH
DH
DH
DH
DL
DL
DL
DL
DL
DL
I
I
Subtract I from M with
borrow,
then skip if borrow
M ← (M) – I – b
skip if borrow
SIBS
SEQ
SGE
SEQI
SGEI
r – M
skip if zero
M
M
I
Skip if r equals M
Rn
Rn
I
r – M
skip if not borrow
(r) ≥ (M)
Skip if r is greater
than or equal to M
r
M – I
skip if zero
M
M
Skip if M equal to I
M – I
skip if not borrow
(M) ≥ I
Skip if M is greater
than or equal to I
I
I
Continued on next page.
No. 4796-11/13
LC72321
Continued from preceding page.
Operand
Machine code
D15 14 13 12 11 10
Mnemonic
1st 2nd
Function
Operation
9
8
7
6
5
4
3
2
1
D0
AND
OR
M
M
r
I
I
AND I with M
M ← (M)
M ← (M)
I
I
0
0
0
0
0
0
1
1
1
1
1
0
0
1
0
0
0
0
DH
DL
I
I
OR I with M
DH
DH
DL
DL
EXL
M
Exclusive OR M with r
r ← (r) (M)
Rn
LD
ST
r
M
r
Load M to r
Store r to M
r ← (M)
M ← (r)
1
1
0
0
0
0
0
0
0
0
0
1
DH
DH
DL
DL
Rn
Rn
M
Move M to destination
M referring to r in
the same row
MVRD
MVRS
r
M
r
[DH, Rn] ← (M)
M ← [DH, Rn]
1
1
0
0
0
0
0
0
1
1
0
1
DH
DH
DL
DL
Rn
Rn
Move source M
referring to r to M in
the same row
M
Move M to M in
the same row
MVSR
MVI
M1
M
M2
[DH, DL1] ← [DH, DL2]
M ← I
1
1
1
0
0
0
0
0
0
1
1
1
0
0
1
0
1
0
DH
DH
DH
DL1
DL
DL2
I
I
Move I to M
Load M to PLL
registers
PLL
M
r
PLL r ← PLL DATA
DL
Rn
Test M bits, then skip
if all bits specified
are true
if M (N) = all 1s,
then skip
TMT
TMF
M
M
N
N
1
1
0
0
1
1
0
0
0
1
1
1
DH
DH
DL
DL
N
N
Test M bits, then skip
if all bits specified
are false
if M (N) = all 0s,
then skip
JMP
CAL
RT
ADDR
ADDR
Jump to the address
Call subroutine
PC ← ADDR
Stack ← (PC) + 1
PC ← Stack
1
1
1
1
0
1
1
1
1
0
0
0
1
0
1
1
ADDR (12 bits)
ADDR (12 bits)
Return from subroutine
Return from interrupt
0
0
1
1
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RTI
PC ← Stack
0
1
0
Test timer F/F
then skip if it has
not been set
if timer F/F = 0,
then skip
TTM
TUL
N
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
0
0
0
0
0
0
0
N
Test unlock F/F
then skip if it has
not been set
if UL F/F = 0,
then skip
N
1
N
(Status register 1)
N ← 1
SS
N
N
N
N
Set status register
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
N
N
N
N
(Status register 1)
N ← 0
RS
Reset status register
Test status register true
Test status register false
if (Status register 2) N =
all 1s, then skip
TST
TSF
if (Status register 2) N =
all 0s, then skip
BANK
B
Select bank
BANK ← B
1
1
0
1
0
0
B
0
0
0
0
0
0
0
0
Continued on next page.
No. 4796-12/13
LC72321
Continued from preceding page.
Operand
Machine code
Mnemonic
1st 2nd
Function
Operation
D15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
D0
Output segment pattern
to LCD digit direct
LCD
LCP
M
M
I
I
LCD (DIGIT) ← M
1
1
1
1
1
1
0
0
0
0
0
1
DH
DL
DIGIT
DIGIT
Output segment pattern
to LCD digit through PLA
LCD (DIGIT) ← PLA ← M
DH
DL
IN
M
M
P
P
P
N
N
Input port data to M
Output contents of M to port
Set port bits
M ← (Port (P))
(Port (P)) ← M
(Port (P)) N ← 1
(Port (P)) N ← 0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
1
1
0
0
0
1
0
1
DH
DH
DL
DL
P
P
P
N
N
OUT
SPB
RPB
0
0
1
P
Reset port bits
0
P
Test port bits,
then skip if all bits
specified are true
if (Port (P)) N = all 1s,
then skip
TPT
TPF
UCS
UCC
P
P
I
N
N
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
1
0
0
1
0
1
1
1
P
P
N
N
I
Test port bits,
then skip if all bits
specified are false
if (Port (P)) N = all 0s,
then skip
1
0
1
Set I to UCCW1
Set I to UCCW2
UCCW1 ← I
UCCW2 ← I
0
0
0
0
0
0
0
I
0
I
FPC
N
F port I/O control
Clock stop
FPC latch ← N
Stop clock if HOLD = 0
DAreg ← DAC DATA
SIOCW ← I1, I2
M ← SIOreg
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
1
1
1
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
0
0
0
0
1
1
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
N
CKSTP
DAC
0
0
0
0
I
Load M to D/A registers
I
SIO
I1
M
M
I
I2 Serial I/O control
I1
I2
I
SIOL
SIOS
BEEP
NOP
I
I
Load SIOreg to M
Store M to SIOreg
Beep control
DH
DH
DL
DL
SIOreg ← M
I
BEEPreg ← I
1
0
0
0
0
0
0
0
0
0
I
No operation
0
0
0
0
0
0
■ No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace
equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of
which may directly or indirectly cause injury, death or property loss.
■ Anyone purchasing any products described or contained herein for an above-mentioned use shall:
➀ Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and
distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all
damages, cost and expenses associated with such use:
➁ Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on
SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees
jointly or severally.
■ Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for
volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied
regarding its use or any infringements of intellectual property rights or other rights of third parties.
This catalog provides information as of December, 1997. Specifications and information herein are subject to
change without notice.
No. 4796-13/13
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