LC74723M [SANYO]
On-Screen Display Controller; 屏幕显示控制器
| 型号： | LC74723M |
| 厂家： | 
SANYO SEMICON DEVICE |
| 描述： | On-Screen Display Controller |
| 文件： | 总12页 (文件大小：145K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Ordering number : EN4841C
CMOS LSI
LC74723, 74723M
On-Screen Display Controller
Overview
Package Dimensions
unit: mm
The LC74723 and LC74723M are on-screen display
controller CMOS LSIs that display characters and patterns
on a TV screen under microprocessor control. Characters
are 8 × 8 dots, and a dot interpolation function is provided.
The LC74723 can display 24 characters × 10 lines of text.
3067-DIP24S
[LC74723]
Features
• Screen structure: 24 characters × 10 lines (up to 240
characters)
• Character structure: 8 (horizontal) × 8 (vertical)
(interpolation function supported)
• Character sizes: Two horizontal and two vertical sizes
• Number of characters: 64
• Display start position: 64 horizontal and 64 vertical
positions
• Blinking: In character units
SANYO: DIP24S
• Blinking types: Two, with periods of 0.5 and 1.0 seconds
• Blue background screen display: (in internal synchro-
nization mode)
unit: mm
• External control inputs: 8-bit serial input interface
• Built-in sync separator circuit
3045B-MFP24
• Video output: Compound NTSC and PAL-M output
• Packages: 24-pin plastic MFP (375 mil)
24-pin plastic DIP (300 mil)
[LC74723M]
SANYO: MFP24
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110 JAPAN
63097HA (OT)/41596TH (OT)/83194TH (OT) No. 4841-1/12
LC74723, 74723M
Pin Assignment
Pin Functions
Pin No.
Symbol
Function
Description
1
2
3
V
1
Ground
Ground (digital system ground)
SS
Xtal
Used either for connecting the external crystal and capacitor that are used for internal
synchronization signal generation, or to input an external clock signal (2f or 4f ).
IN
Crystal oscillator connection
Xtal
sc
sc
OUT
Switches the LC74723 between external clock input mode and crystal oscillator mode.
Low = crystal oscillator mode, high = external clock mode
4
5
CTRL1
CSYN
Crystal oscillator input switching
Composite synchronization
signal output
Outputs a composite synchronization signal. Outputs the crystal oscillator clock on
reset, i.e., when RST is low.
OUT
6
7
OSC
OSC
Connections for the coil and capacitor that form the oscillator used to generate the
character output dot clock.
IN
LC oscillator
OUT
Outputs the result of judging whether or not there is an external synchronization
signal. Outputs a high level when an external synchronization signal is present.
Outputs the dot clock (LC oscillator) on reset, i.e., when RST is low. (The LC74723
can be set not to output this signal on reset using control data.)
External synchronization signal
judgment output
8
9
SYNC
JDG
Enables serial data input. Serial data input is enabled when this input is low. There is
a built-in pull-up resistor on this input (hysteresis input).
CS
Enable input
Inputs the clock signal used for serial data input.
There is a built-in pull-up resistor on this input (hysteresis input).
10
11
12
SCLK
SIN
Clock input
Data input
Serial data input. There is a built-in pull-up resistor on this input (hysteresis input).
Power supply (analog system power supply) for composite video signal level
adjustment.
V
2
Power supply
Video signal output
DD
13
14
15
16
CV
Composite video signal output
OUT
NC
Must be either connected to ground or left open.
Composite video signal input
CV
Video signal input
Power supply
IN
1
V
Power supply (+5 V: digital system power supply)
DD
Video signal input for the built-in sync separator circuit (When the built-in sync
separator circuit is not used, input either the horizontal synchronization signal or the
composite synchronization signal.)
17
SYN
Sync separator circuit input
IN
18
19
SEP
Sync separator circuit bias voltage Built-in sync separator circuit bias voltage monitor
C
Composite synchronization
signal output
Outputs the built-in sync separator circuit's composite synchronization signal.
(Outputs the SYN input signal when the built-in sync separator circuit is not used.)
IN
SEP
OUT
Inputs the vertical synchronization signal by integrating the output signal from the
SEP
pin.
OUT
20
SEP
Vertical synchronization signal input
IN
An integration circuit must be connected between the SEP
pin and this pin. Hold
OUT
at V 1 if this input is unused.
DD
Continued on next page.
No. 4841-2/12
LC74723, 74723M
Continued from preceding page.
Pin No.
21
Symbol
CTRL2
Function
Description
Switches the synchronization signal generation between NTSC and PAL-M.
Low = NTSC, high = PAL-M
NTSC/PAL-M switch input
Controls whether the VSYNC signal is input to SEP
Low = Input VSYNC, high = do not input.
.
IN
22
CTRL3
RST
SEP input control
IN
System reset input
There is a built-in pull-up resistor on this input (hysteresis input).
23
24
Reset input
V
1
Power supply (+5 V)
Power supply (+5 V: digital system power supply)
DD
Note: * Both the V 1 pins (pins 16 and 24) must be connected.
DD
Specifications
Absolute Maximum Ratings at Ta = 25°C
Parameter
Maximum supply voltage
Symbol
Conditions
Ratings
– 0.3 to V + 7.0
Unit
V
V
max
max
V
1, V
2
V
V
DD
DD
DD
SS
SS
Maximum input voltage
Maximum output voltage
Allowable power dissipation
Operating temperature
Storage temperature
V
All input pins
– 0.3 to V
– 0.3 to V
+ 0.3
+ 0.3
350
V
IN
SS
SS
DD
V
max CSYN
, SYNC , SEP
JDG OUT
V
V
OUT
OUT
DD
Pd max
Topr
Ta = 25°C
mW
°C
°C
–30 to +70
Tstg
–40 to +125
Allowable Operating Ranges at Ta = –30 to +70°C
Parameter
Supply voltage
Symbol
Conditions
min
typ
5.0
5.0
max
5.5
Unit
V
V
V
1
2
V
V
1
2
4.5
4.5
1
DD
DD
DD
1.27 V
1
V
DD
DD
V
1
RST, CS, SIN, SCLK
0.8 V
V
V
1 + 0.3
1 + 0.3
V
IH
DD
DD
DD
Input high level voltage
V
2
CTRL1, CTRL2, CTRL3, SEP
RST, CS, SIN, SCLK
0.7 V
1
V
IH
IN
DD
V
V
1
2
V
V
– 0.3
– 0.3
0.2 V
0.3 V
1
1
V
IL
SS
SS
DD
Input low level voltage
Pull-up resistance
CTRL1, CTRL2, CTRL3, SEP
V
IL
IN
DD
Applies to the RST, CS, SIN, and SCLK pins and to
the pins specified by options.
R
V
25
50
90
kΩ
PU
1
CV ; V 1 = 5 V
IN DD
2.0
2.0
Vp-p
Vp-p
IN
IN
Composite video input voltage
Input voltage
V
V
f
2
3
1
SYN ; V 1 = 5 V
IN DD
2.5
5.0
Xtal (when external clock input is used)
IN
= 2f or 4f ; V 1 = 5 V
0.1
Vp-p
IN
f
in
sc sc DD
Xtal and Xtal
IN
oscillator pins (2f : NTSC)
sc
7.159
MHz
MHz
MHz
MHz
MHz
osc
osc
osc
osc
osc
OUT
OUT
OUT
OUT
f
f
f
f
1
1
1
2
Xtal and Xtal
IN
oscillator pins (4f : NTSC)
sc
14.318
7.151
Oscillator frequency
Xtal and Xtal
IN
oscillator pins (2f : PAL-M)
sc
Xtal and Xtal
IN
oscillator pins (4f : PAL-M)
sc
14.302
OSC and OSC
oscillator pins (LC oscillator)
5
12
IN
OUT
Note: When the Xtal pin is used in clock input mode, be extremely careful of input noise.
IN
Electrical Characteristics at Ta = –30 to +70°C, V 1 = 5 V unless otherwise specified
DD
Parameter
Input off leakage current
Output off leakage current
Symbol
Conditions
min
typ
max
1
Unit
µA
I
I
1
2
CV
CV
leak
IN
1
µA
leak
OUT
CSYN
, SYNC
, SEP
OUT
= –1.0 mA
, SEP
OUT
;
;
OUT
JDG
Output high level voltage
Output low level voltage
V
1
3.5
V
V
OH
V
1 = 4.5 V, I
DD
OH
CSYN
, SYNC
OUT
JDG
V
1
1.0
1
OL
V
1 = 4.5 V, I = 1.0 mA
DD
OL
RST, CS, SIN, SCLK, CTRL1, CTRL2, CTRL3, SEP
;
IN
I
µA
IH
V
= V
1
Input current
IN
DD
I
CTRL1, CTRL2, CTRL3, OSC ; V = V 1
SS
–1
µA
mA
mA
IL
IN IN
I
I
1
V
V
1; All outputs open, Xtal: 7.159 MHz, LC: 8 MHz
15
20
DD
DD
DD
Current drain (operating)
2
2; V 2 = 5 V
DD
DD
Continued on next page.
No. 4841-3/12
LC74723, 74723M
Continued from preceding page.
Parameter
Sync level
Symbol
Conditions
min
0.69
0.89
1.28
1.47
0.97
1.16
1.60
1.79
1.44
1.63
1.96
2.16
1.43
1.61
2.01
2.18
2.57
2.76
typ
max
0.93
1.13
1.52
1.71
1.21
1.40
1.84
2.03
1.68
1.87
2.20
2.40
1.67
1.85
2.25
2.42
2.81
3.00
Unit
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
When the sync level is 0.8 V, CV
: V 1, V 2 = 5 V
0.81
1.01
1.40
1.59
1.09
1.28
1.72
1.91
1.56
1.75
2.08
2.28
1.55
1.73
2.13
2.30
2.69
2.88
OUT DD
DD
V
SN
When the sync level is 1.0 V, CV
When the sync level is 0.8 V, CV
When the sync level is 1.0 V, CV
When the sync level is 0.8 V, CV
When the sync level is 1.0 V, CV
When the sync level is 0.8 V, CV
When the sync level is 1.0 V, CV
When the sync level is 0.8 V, CV
When the sync level is 1.0 V, CV
When the sync level is 0.8 V, CV
When the sync level is 1.0 V, CV
When the sync level is 0.8 V, CV
When the sync level is 1.0 V, CV
When the sync level is 0.8 V, CV
When the sync level is 1.0 V, CV
When the sync level is 0.8 V, CV
When the sync level is 1.0 V, CV
: V 1, V 2 = 5 V
DD
OUT DD
: V 1, V 2 = 5 V
OUT DD
DD
Pedestal level
V
PD
: V 1, V 2 = 5 V
OUT DD
DD
: V 1, V 2 = 5 V
OUT DD
DD
Color burst low level
Color burst high level
Background color low level
Background color high level
Trimming level 0
V
CBL
: V 1, V 2 = 5 V
OUT DD
DD
: V 1, V 2 = 5 V
OUT DD
DD
V
CBH
: V 1, V 2 = 5 V
OUT DD
DD
: V 1, V 2 = 5 V
OUT DD
DD
V
RSL
: V 1, V 2 = 5 V
OUT DD
DD
: V 1, V 2 = 5 V
OUT DD
DD
V
RSH
: V 1, V 2 = 5 V
OUT DD
DD
: V 1, V 2 = 5 V
OUT DD
DD
V
BK0
: V 1, V 2 = 5 V
OUT DD
DD
: V 1, V 2 = 5 V
OUT DD
DD
Trimming level 1
V
BK1
: V 1, V 2 = 5 V
OUT DD
DD
: V 1, V 2 = 5 V
OUT DD
DD
Character level
V
CHA
: V 1, V 2 = 5 V
OUT DD
DD
Timing Characteristics at Ta = –30 to +70°C, V 1 = 5 ± 0.5 V
DD
Parameter
Symbol
Conditions
min
200
1
typ
max
Unit
ns
µs
ns
ns
µs
ns
µs
µs
t
SCLK
W (SCLK)
Minimum input pulse width
t
CS (the period while CS is high)
W (CS)
t
CS
200
200
2
SU (CS)
Data setup time
Data hold time
t
SIN
SU (SIN)
t
CS
h (CS)
t
SIN
200
4.2
1
h (SIN)
t
The time to write 8 bits of data
The RAM data write time
word
One word write time
t
wt
Serial Data Input Timing
No. 4841-4/12
LC74723, 74723M
System Block Diagram
D e c o d e r
No. 4841-5/12
LC74723, 74723M
Display Control Commands
Display control commands are input as serial data in 8-bit units. Commands consist of a first byte that includes the
command identifier code and data in the following second byte. The LC74723 supports the following six commands.
1. COMMAND0: Set display memory (VRAM) write address
2. COMMAND1: Set up display character data write
3. COMMAND2: Set vertical display start position and vertical character size
4. COMMAND3: Set horizontal display start position and horizontal character size
5. COMMAND4: Display control
6. COMMAND5: Display control
Display Control Command Table
First byte
Command identifier code
Second byte
Data
Command
Data
7
6
5
4
3
2
1
0
7
0
6
0
5
0
4
3
2
1
0
COMMAND0
(Set write address)
1
0
0
0
V3
V2
0
V1
V0
H4
H3
H2
H1
H0
COMMAND1
(Write character)
1
1
1
1
1
0
0
0
1
1
0
1
1
0
0
1
0
1
0
1
0
0
0
0
0
0
at
0
0
c5
c4
c3
c2
c1
c0
COMMAND 2 (Vertical display start
position and vertical character size)
VS
20
VS
10
VP
5
VP
4
VP
3
VP
2
VP
1
VP
0
FS
LC
COMMAND3 (Horizontal display start
position and horizontal character size)
HS
20
HS
10
HP
5
HP
4
HP
3
HP
2
HP
1
HP
0
EGP
0
COMMAND4
(Display control)
TST RAM OSC SYS
MOD ERS STP RST
BK
1
BK
0
DSP
ON
0
EGL NON EG
RV
—
COMMAND5
(Synchronization signal control)
0
PH RSN INT
—
—
—
—
—
—
—
Once written, the command identifier code in the first byte is stored until the next first byte is written. However, when
the display character data write command (COMMAND1) is written, the LC74723 locks into the display character data
write mode, and another first byte cannot be written.
When a high level is input to the CS pin, the LC74723 is set to COMMAND0 (display memory write address setting
mode).
1. COMMAND0 (Display memory write address setting command)
• First byte
Contents
Function
DA
0 to 7
Register
name
Remarks
State
7
6
5
4
—
—
—
—
1
0
0
0
0
1
0
1
0
1
0
1
Command 0 identification code
Set display memory write address.
3
2
1
0
V3
V2
V1
V0
Display memory address (0 to 9 hexadecimal)
No. 4841-6/12
LC74723, 74723M
• Second byte
Contents
Function
DA
0 to 7
Register
name
Remarks
State
7
6
5
—
—
—
0
0
0
0
1
0
1
0
1
0
1
0
1
Second byte identification code
4
3
2
1
0
H4
H3
H2
H1
H0
Display memory address (0 to 17 hexadecimal)
Note: The register states are all set to zero when the LC74723 is reset with the RST pin.
2. COMMAND1 (Display character data write setup command)
• First byte
Contents
Function
DA
0 to 7
Register
name
Remarks
State
7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
—
1
0
0
1
0
0
0
0
When this command is input, the LC74723
locks into the display character data write
mode until the CS pin goes high.
Command 1 identification code
Set up display character data write.
• Second byte
Contents
Function
DA
0 to 7
Register
name
Remarks
State
0
Character attribute off
Character attribute on
7
6
5
at
—
c5
1
0
0
1
0
4
3
2
1
0
c4
c3
c2
c1
c0
1
0
1
Character code (00 to 3F hexadecimal)
0
1
0
1
0
1
Note: The register states are all set to zero when the LC74723 is reset with the RST pin.
No. 4841-7/12
LC74723, 74723M
3. COMMAND2 (Vertical display start position and vertical character size setting command)
• First byte
Contents
Function
DA
0 to 7
Register
name
Remarks
State
7
6
5
4
3
—
—
—
—
—
1
0
1
0
0
0
1
0
0
1
Command 2 identification code
Set vertical display start position and vertical character size.
1H per dot
2H per dot
2
1
0
VS20
—
Second line vertical character size
First line vertical character size
1H per dot
2H per dot
VS10
• Second byte
Contents
Function
DA
0 to 7
Register
name
Remarks
State
0
7
6
—
Second byte identification code
0
Crystal oscillator frequency: 2f
sc
FS
1
Crystal oscillator frequency: 4f
sc
0
If VS is the vertical display start position then:
VP5
(MSB)
5
4
3
2
1
0
5
1
n
VS = H × (2Σ 2 VP )
n
n = 0
0
VP4
VP3
VP2
VP1
H: the horizontal synchronization pulse period
1
0
The vertical display start position is set by the
6 bits VP0 to VP5.
The weight of the low-order bit is 2H.
1
0
1
0
1
0
VP0
(LSB)
1
Note: The register states are all set to zero when the LC74723 is reset with the RST pin.
4. COMMAND3 (Horizontal display start position and horizontal character size setting command)
• First byte
Contents
Function
DA
0 to 7
Register
name
Remarks
State
7
6
5
4
—
—
—
—
1
0
1
1
0
1
0
1
0
0
1
Command 3 identification code
Set horizontal display start position and horizontal character size.
Correction: on
Correction: off
1Tc per dot
Trimming specifications when the horizontal
character size is doubled
3
EGP
2
1
0
HS20
—
Second line horizontal character size
2Tc per dot
1Tc per dot
2Tc per dot
HS10
First line horizontal character size
No. 4841-8/12
LC74723, 74723M
• Second byte
Contents
Function
DA
0 to 7
Register
name
Remarks
State
0
7
6
—
Second byte identification code
Selects the dot clock used for horizontal
direction character display.
0
An LC oscillator is used for the dot clock
A crystal oscillator is used for the dot clock
LC
1
If HS is the horizontal display start position then:
0
5
4
3
2
1
0
HP5
5
1
(MSB)
n
HS = Tc × (2Σ 2 HP )
n
n = 0
0
HP4
HP3
HP2
HP1
Tc: The oscillator period of the OSCIN and
OUT pin oscillator in operating mode
1
0
The horizontal display start position is set by
the 6 bits HP0 to HP5.
1
The weight of the low-order bit is 2Tc.
0
1
0
1
HP0
(LSB)
0
1
Note: The register states are all set to zero when the LC74723 is reset with the RST pin.
5. COMMAND4 (Display control command)
• First byte
Contents
Function
DA
0 to 7
Register
name
Remarks
State
7
6
5
4
—
—
—
—
1
1
0
0
0
1
0
1
0
1
0
1
Command 4 identification code
Set display control.
Normal operating mode
Test mode
3
2
1
0
TSTMOD
RAMERS
OSCSTP
SYSRST
This bit must be zero.
The RAM erase operation requires about
500 µs (It is executed in the DSPOFF state.)
Erase display RAM (set to 3F hexadecimal)
Do not stop the crystal oscillator or LC oscillator circuits.
Stop the crystal oscillator or LC oscillator circuits.
Valid when character display is off in external
synchronization mode.
Reset occurs when the CS pin is low, and
the reset is cleared when CS is high.
Reset all registers and turn the display off.
• Second byte
Contents
Function
DA
0 to 7
Register
name
Remarks
State
7
6
—
0
0
1
0
1
0
1
0
1
Second byte identification code
Trimming level 0 (V
Trimming level 1 (V
)
)
BK0
EGL
Trimming level switching
BK1
Interlace (256.5 H per field)
Non-interlace (263 H per field)
Trimming off
5
4
3
NON
EG
Interlace/non-interlace switching
Trimming on
Blinking period: about 0.5 s
Blinking period: about 1.0 s
BK1
Blinking state switching
When blinking is specified for reversed
characters, the blinking will be between normal
character and reversed character display.
0
Blinking off
2
BK0
1
0
1
0
1
Blinking on
Reverse (character reversing) off
Reverse (character reversing) on
Character display off
1
0
RV
DSPON
Character display on
Note: The register states are all set to zero when the LC74723 is reset with the RST pin.
No. 4841-9/12
LC74723, 74723M
6. COMMAND5 (Display control command)
• First byte
Contents
Function
DA
0 to 7
Register
name
Note
State
7
6
5
4
3
—
—
—
—
—
1
1
0
1
0
Command 5 identification code
Synchronization signal control setup
Background color switching (Only valid in
NTSC mode, only a blue background color is
supported in PAL-M mode.)
0
1
Green background
Blue background
2
PH
External synchronization signal detection
control Judges whether the signal has gone
from present to absent or from absent to
present.
0
1
External synchronization signal detection control: Disabled
External synchronization signal detection control: Enabled
1
0
RSN
INT
0
1
External synchronization
Internal synchronization
External/internal synchronization switching
Note: The register states are all set to zero when the LC74723 is reset with the RST pin.
Display Screen Structure
The display consists of 24 characters × 10 rows for a maximum of 240 characters. The maximum number of characters is
reduced when the character size is enlarged.
Display memory addresses are specified as row (0 to 9 decimal) and column (0 to 23 decimal) addresses.
Display Screen Structure (display memory addresses)
No. 4841-10/12
LC74723, 74723M
Composite Video Signal Output Level (internally generated level)
CV
output level waveform (V 2 = 5.00 V)
DD
OUT
Output level
Output voltage ➀ [V]
Output voltage [V]
➁
V
: Character
2.69
2.08
1.72
1.56
2.13
1.55
1.40
1.09
0.81
2.88
2.28
1.91
1.75
2.30
1.73
1.59
1.28
1.01
CHA
V
V
V
V
V
V
V
V
: Background color high
: Color burst high
RSH
CBH
: Background color low
: Trimming
RSL
BK1
BK0
: Trimming
: Pedestal
PD
: Color burst low
CBL
: Sync
SN
Note: V 2 = 5.00 V
DD
No. 4841-11/12
LC74723, 74723M
■ No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace
equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of
which may directly or indirectly cause injury, death or property loss.
■ Anyone purchasing any products described or contained herein for an above-mentioned use shall:
➀ Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and
distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all
damages, cost and expenses associated with such use:
➁ Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on
SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees
jointly or severally.
■ Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for
volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied
regarding its use or any infringements of intellectual property rights or other rights of third parties.
This catalog provides information as of June, 1997. Specifications and information herein are subject to change
without notice.
No. 4841-12/12
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