LC7573 [SANYO]
Electronic Volume Control System for Audio Equipment; 音频设备电子音量控制系统
| 型号： | LC7573 |
| 厂家： | 
SANYO SEMICON DEVICE |
| 描述： | Electronic Volume Control System for Audio Equipment |
| 文件： | 总11页 (文件大小：284K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Ordering number : EN2169C
CMOS LSI
LC7537, 7537AN, 7537NE
Electronic Volume Control System for
Audio Equipment
Overview
Package Dimensions
The LC7537N is an electronic control LSI capable of
electronically controlling the volume, balance, loudness,
fader, bass, and treble functions individually with fewer
externally connected component parts.
unit : mm
3025B-DIP42S
[LC7573N]
Features
• Enables controlling the below-listed functions with 3-
line serial data, including CE, DI, and CLK. Also, due
to 0 V to 5 V swing of the serial data input voltage,
permits the use of a general purpose microcomputer.
SANYO: DIP42S
Volume :
Separately controls the Lch and Rch
volume levels across 81 positions over
the 0 dB to –79 dB (in 1 dB steps) range
and –∞, and consequently also serves
balance control purposes.
unit : mm
3156-QFP48E
[LC7537NE]
Loudness : By virtue of a center tap provided at the
–20 dB position of the volume
controlling ladder resistors, permits
loudness to be controlled with
externally connected CR components.
Fader :
By varying only the rear or front output
level across 16 positions, provides fader
functions (in 2 dB steps over the 0 dB to
–20 dB range, and 5 dB steps over the
–20 dB to –45 dB range, and at –∞, for
a total of 16 positions).
SANYO: QIP48E
Bass/Treble : With CR components externally
connected, forms an NF type tone
control circuit (Baxandall type) to
exercise control across 15 positions
over both the bass and treble functions
in 2 dB steps.
unit : mm
3052A-QFP48A
[LC7537AN]
• By virtue of its CMOS structure, the LSI operates under
a broad power supply voltage range from +4.5 V to +15
V, permitting the use of either a single or a dual ± power
supply, whichever is preferred.
SANYO: QIP48A
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110 JAPAN
81096HA(OT)/31293JN/7018YT/6186KI,TS No. 2169-1/11
LC7537N, 7537AN, 7537NE
Pin Assignments
Equivalent Circuit Block Diagram
Specifications
Absolute Maximum Ratings at Ta = 25°C, V = 0 V, V = ≥ V > V ≥ V
SS
DD
CC
SS
EE
Item
Symbol
Condition
Rating
Unit
V
V
V
V
V
– V max
EE
V
, V : V ≥ –8 V
16
V
DD
CC
I1
DD EE
EE
Maximum supply voltage
max
V
: V
≥ V
– 0.3 to V + 7
SS
V
CC
DD
CC
SS
DI, CLK, CE
INIT
V
V
– 0.3 to V + 0.3
DD
V
SS
SS
Input supply voltage
– 0.3 to V + 0.3
DD
V
I2
Ta ≤ 85˚C, (LC7537N, 7537AN)
Ta ≤ 85˚C, (LC7537NE)
200
300
mW
mW
˚C
˚C
Allowable power dissipation
Pd max
Operating temperature
Storage temperature
Topr
–40 to +85
Tstg *3
–50 to +125
Allowable Operating Conditions at Ta = 25°C, V = 0 V, V = ≥ V > V ≥ V
EE
SS
DD
CC
SS
Item
Symbol
EE
Condition
Rating
Unit
V
V
V
V
V
V
V
V
– V
*2
V
≥ –7.5 V
EE
4.5 to 15
4.5 to 5.5
DD
CC
IH1
IH2
IL1
IL2
IN
Supply voltage *1
V
DI, CLK, CE
INIT
0.8 V
to V
V
CC
CC
Input high–level voltage
Input low–level voltage
0.8 (V – V ) + V to V
V
DD
EE
EE
DD
*2
DI, CLK, CE
INIT
V
V
V
to 0.2 V
V
SS
EE
EE
CC
to 0.2 (V – V ) + V
V
DD
EE
EE
Input signal amplitude
Input pulse width
setup time
to V
V
DD
P-P
tø
t
1 min
1 min
1 min
µs
µs
W
set up
hold
Hold time
t
f
µs
Operating frequency
up to 330
kHz
opg
Note: 1. A1000 pF or larger capacitor should be added on between each individual power supply terminal and V
.
SS
2. When the microcomputer side control signals rise faster than V
the DI, CLK, and CE lines.
for the LC7537, a 2 kΩ or higher resistor should be inserted midway on each of
DD
3. When mounting the QIP package on the board, do not dip the entire package in solder. Only the LC7537NE may be dipped directly in solder during
mounting.
No. 2169-2/11
LC7537N, 7537AN, 7537NE
Electrical Characteristics at Ta = 25°C, V =+7.5 V, V =–7.5 V, V =+5 V
DD
EE
CC
Rating
Item
Total harmonic
Symbol
THD(1)
Condition
min
typ
max
0.01
%
Unit
%
V
V
V
V
= 1 V, f = 1kHz, all flat overall
= 1 V, f = 20 kHZ, all flat overall
= 1 V, f = 1 kHz, all flat, Rg = 1 kΩ
0.005
0.02
95
IN
IN
IN
IN
Distortion
THD(2)
CT
0.006
60
dB
Crosstalk
V
V
(1)
= 1 V, f = 1 kHz, MAIN, VR = ∞, FADER VR = ∞
80
90
dB
omin
(2)
V
V
= 1 V, f = 1 kHz, MAIN, VR = ∞, V = 8 V, FADER VR = ∞,
omin
IN
DD
Maximum attenuation output
VR resistance voltage
70
80
dB
= V = 0 V, C between V and GND of L/R = 1000 µF
EE
SS
SS
R
R
R
R
R
(1)
(2)
5 dB-step
1 dB-step
12
12
12
12
12
20
20
20
20
20
2
28
28
28
28
28
10
10
1
kΩ
kΩ
kΩ
kΩ
kΩ
µV
µV
mA
mA
VOL
VOL
BASS
TREBLE
FADER
V (1)
N
All flat overall (I
) Rg = 1 kΩ
HF-A
Output noise
Current drain
V (2)
N
Rg = 1 kΩ, V
= 8 V, V = V = 0 V
2
DD
EE
SS
I
V
V
– V = 15 V
EE
DD
DD
CC
I
= 5 V
1
CC
Pin Description ( ) : LC7537AN, 7537NE
Pin No.
12(8)
Symbol
L.IN
Description of Functions
Remarks
Main volume control block 5 dB-step attenuator input terminals. These pins should be
driven at a low impedance.
31(29)
9(4)
R.IN
L.C1
Main volume control block 5 dB-step attenuator output terminals. Having been designed
to be open, the step positions will develop errors if at low acceptor impedances, so that as
high load impedances as possible should be provided.
VR resistance : 20 kΩ
VR resistance : 20 kΩ
34(33)
R.C1
10(5)
L.C2
R.C2
Main volume control block 1 dB-step attenuator input terminals. Theses pins should be
driven at alow impedance.
33(32)
Main volume control block 1 dB-step attenuator output terminals. Due to the step
positions designed to be open, load impedances as high as possible should be provided to
them, similar to those for the LC1 and RC1.
11(6)
L.OUT
32(31)
5(47)
R.OUT
L.FIN
R.FIN
L.FOUT
L.ROUT
R.ROUT
R.ROUT
L.B1
Fader functions employing mode input terminals. These pins should be driven at a low
impedance.
38(38)
4(46)
Fader block output terminals. These pins permit the front and rear sides to be faded out
independently of each other. Attenuations exercised on Lch will be the same as on Rch.
Due to the step positions designed to be open, acceptor impedances as high as possible
should be provided to them.
3(45)
VR resistance : 20 kΩ
VR resistance : 20 kΩ
39(39)
40(40)
15(11)
16(9)
L.B2
Bass tone control block terminals. A total of 15 positions have been provided in 2 dB
steps
14(10)
28(26)
27(28)
29(27)
17(13)
16(12)
18(14)
26(24)
27(25)
25(23)
7(1)
L.B3
R.B1
R.B2
R.B3
L.T1
L.T2
L.T3
Treble tone control block terminals. A total of 15 positions have been provided in 2 dB
steps. The VR resistance value is 20 kΩ.
VR resistance : 20 kΩ
R.T1
R.T2
R.T3
LCT1
LCT2
RCT1
RCT2
Loudness dedicated terminals. A high-frequency-range correcting C should be put
between CT1 and IN, and low-frequency-range correcting C between CT2 and L–V
6(48)
SS
36(36)
37(37)
(R–V ).
SS
Continued on next page.
No. 5190-3/10
LC7537N, 7537AN, 7537NE
Continued from preceding page.
Pin No.
Symbol
Description of Functions
Remarks
8(2)
L-V
Main volume control block fader control common terminals. The impedance of pattern
SS
connected to these pins should be as low as possible. Since L–V
(R–V ) and V
SS
SS SS
have not been connected inside the LSI, they should be connected together on the outside
in conformance with their individual specifications. Particular attenuation should be paid to
the capacitance assigned to the capacitors put between L–V
(R–V ) and V , which
SS
SS SS
will emerge as a residual resistive component when control is turned down for maximum
attenuation.
35(35)
R-V
SS
Intra-IC latch resetting terminal
42(42)
INIT
Control-setting data at the internal latch will be indeterminate when power has just been
switched on, so that by engaging the “L” level of this pin at power-on, the fader control
may be set at its –∞ position and muting behaviour is engaged (Note: V
to V Level).
EE
DD
Chip enable terminal. When this pin is made “H” to “L”, data is written in the internal latch,
activating the various analog switches. When the “H” level is then restored, transfer of the
data will be enabled.
22(20)
CE
20(16)
21(17)
DI
Input terminals for serial data and clock that serve control purposes.
CLK
1(43)
V
DD
23(21)
19(15)
24(22)
2(3, 7)
V
These pins are connected to the relevant power supplies. Exercise caution against V
CC
CC
rising earlier than V
.
DD
V
SS
V
EE
41(18, 30, NC
34, 41, 44)
No connect pins. Absolutely nothing should be connected here.
LC7537AN and
LC7537NE only
V
subterminal. Connected to V
or left open.
(19)
V
(NC)
DD
DD
DD
No. 2169-4/11
LC7537N, 7537AN, 7537NE
Control Timing
Data Format
No. 2169-5/11
LC7537N, 7537AN, 7537NE
Main Volume Control Block Equivalent Circuit
Fader Volume Control Block
Equivalent Circuit
Tone Control Block Equivalent Circuit
No. 2169-6/11
LC7537N, 7537AN, 7537NE
Sample Application Circuits
Single Power Supply
Unit (resistance: Ω, capacitance: F)
Note: Bipolar electrolytic capacitors should preferably be employed where no polarity has been indicated.
No. 2169-7/11
LC7537N, 7537AN, 7537NE
Dual ± Power Supply
Unit (resistance: Ω, capacitance: F)
Note: Bipolar electrolytic capacitors should preferably be employed where no polarity has been indicated.
No. 2169-8/11
LC7537N, 7537AN, 7537NE
Single Power Supply
Unit (resistance: Ω, capacitance: F)
Note: Bipolar electrolytic capacitors should preferably be employed where no polarity has been indicated.
No. 2169-9/11
LC7537N, 7537AN, 7537NE
Caution for Pattern Designing
• Space the patterns between L.IN and L.OUT and those
between R.IN and R.OUT as far apart as possible.
When forced to design them close together, provide
shielding patterns between as illustrated. They will be
effective at the maximum attenuated level (with 10 kHz
and higher frequencies). (DIP42S)
• Make the L–V and R–V as broad as possible.
SS
SS
Unit (resistance: Ω, capacitance: F)
No. 2169-10/11
LC7537N, 7537AN, 7537NE
■ No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace
equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of
which may directly or indirectly cause injury, death or property loss.
■ Anyone purchasing any products described or contained herein for an above-mentioned use shall:
Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and
distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all
damages, cost and expenses associated with such use:
Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on
SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees
jointly or severally.
➀
➁
■ Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for
volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied
regarding its use or any infringements of intellectual property rights or other rights of third parties.
This catalog provides information as of November, 1997. Specifications and information herein are subject to
change without notice.
No. 2169-11/11
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