LC7574NW [SANYO]
1/2 Duty VFD Driver for Frequency Display; 1/2占空比VFD驱动器的频率显示
| 型号： | LC7574NW |
| 厂家： | 
SANYO SEMICON DEVICE |
| 描述： | 1/2 Duty VFD Driver for Frequency Display |
| 文件： | 总10页 (文件大小：191K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Ordering number : EN3586A
CMOS LSI
LC7574NE, 7574NW
1/2 Duty VFD Driver for Frequency Display
Overview
Package Dimensions
The LC7574NE and LC7574NW are 1/2 duty VFD
drivers that can be used for electronic tuning frequency
display and other applications under the control of a
controller. These products can directly drive VFDs with
up to 74 segments.
unit: mm
3156-QFP48E
[LC7574NE]
Features
• 74 segment outputs
• Noise reduction circuits are built into the output drivers.
• Serial data input supports CCB* format
communications with the system controller.
• Switching between digital and analog dimmers under
serial data control
• High generality since display data is displayed without
the intervention of a decoder
• All segments can be turned off with the BLK pin
SANYO: QFP48E
•
•
CCB is a trademark of SANYO ELECTRIC CO., LTD.
CCB is SANYO’s original bus format and all the bus
addresses are controlled by SANYO.
unit: mm
3163A-SQFP48
[LC7574NW]
SANYO: SQFP48
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
O2095HA (OT)/4032JN No. 3586-1/10
LC7574NE, 7574NW
Specifications
Absolute Maximum Ratings at Ta = 25°C, V = 0 V
SS
Parameter
Maximum supply voltage
Symbol
Conditions
Ratings
Unit
V
V
max
max
1
V
V
–0.3 to +6.5
–0.3 to +21.0
–0.3 to +6.5
DD
DD
FL
V
V
FL
V
DI, CL, CE, BLK, DIM
OSC
V
IN
Input voltage
V
2
–0.3 to V
+ 0.3
V
IN
DD
V
V
I
1
S1 to S37, G1, G2
OSC
–0.3 to V + 0.3
V
OUT
OUT
FL
Output voltage
2
–0.3 to V
+ 0.3
5
V
DD
1
S1 to S37
mA
mA
mW
mW
°C
°C
OUT
OUT
Output current
I
2
G1, G2
67
Ta = 85°C (LC7574NE)
250
150
Allowable power dissipation
Pd max
Ta = 85°C (LC7574NW)
Operating temperature
Storage temperature
Topr
Tstg
–40 to +85
–50 to +125
Allowable Operating Ranges at Ta = –40 to +85°C, V = 4.5 to 5.5 V, V = 0 V
DD
SS
Parameter
Supply voltage
Symbol
Conditions
min
4.5
typ
5.0
12
max
Unit
V
V
V
V
5.5
DD
DD
FL
V
8
18
V
FL
Input high level voltage
Input low level voltage
Guaranteed oscillator range
V
DI, CL, CE, BLK
DI, CL, CE, BLK
OSC
0.8 V
5.5
V
IH
DD
0
V
IL
0.2 V
V
DD
f
0.4
1.6
12
3.0
MHz
OSC
Recommended external
resistance
R
OSC
OSC
kΩ
OSC
Recommended external
capacitance
C
50
pF
OSC
Low level clock pulse width
High level clock pulse width
Data setup time
t
CL: Figure 1
0.5
0.5
0.5
0.5
0.5
0.5
0.5
10
µs
µs
µs
µs
µs
µs
µs
µs
V
øL
t
CL: Figure 1
øH
t
DI, CL: Figure 1
DI, CL: Figure 1
CE, CL: Figure 1
CE, CL: Figure 1
CE, CL: Figure 1
BLK, CE: Figure 3
DIM
ds
Data hold time
t
dh
CE wait time
t
cp
CE setup time
t
cs
CE hold time
t
ch
BLK switching time
Input voltage range
t
c
V
0
+5.5
IN
Electrical Characteristics in the Allowable Operating Ranges
Parameter
Input high level current
Input low level current
Symbol
Conditions
min
typ
max
Unit
µA
µA
V
I
DI, CL, CE, BLK, DIM: V = 5.5 V
I
5
IH
I
DI, CL, CE, BLK, DIM: V = 0 V
I
–5
IL
V
V
V
1
2
3
S1 to S37: I = 2 mA
O
V
V
V
– 0.6
– 0.6
– 1.3
0.125
OH
OH
OH
FL
FL
FL
Output high level voltage
G1, G2: I = 25 mA
O
V
G1, G2: I = 50 mA
O
V
Output low level voltage
Oscillator frequency
Hysteresis voltage
V
S1 to S37, G1, G2: I = –5 µA, Ta = 25°C
O
0.25
1.6
0.5
V
OL
f
R
= 12 kΩ, C = 50 pF
OSC
MHz
V
OSC
OSC
V
H
DI, CL, CE, BLK
DIM
0.5
A/D converter linearity error
Current drain
Err
–1/2
+1/2
10
LSB
mA
I
Outputs open: f
= 1.6 MHz
DD
OSC
No. 3586-2/10
LC7574NE, 7574NW
Pin Assignment
1. When CL is stopped at the low level
2. When CL is stopped at the high level
Figure 1
No. 3586-3/10
LC7574NE, 7574NW
Block Diagram
Pin Functions
Handling
when unused
Pin No.
Pin
I/O
Function
4
1
V
—
—
—
Driver block power supply. A voltage of between 8.0 and 18.0 V must be supplied.
Logic block power supply. A voltage of between 4.5 and 5.5 V must be supplied.
Ground. Must be connected to the system ground.
—
—
—
FL
V
DD
46
V
SS
Oscillator connection. An oscillator circuit is formed by connecting an external resistor and capacitor
V
48
47
OSC
BLK
I/O
DD
to this pin
.
Display off control input
BLK = low (V ): Display off (G1 and G2 = low)
SS
I
GND
GND
BLK = high (V ): Display on
DD
Note that serial data can be transferred while the display is turned off.
44
43
42
CL
DI
CL: synchronization clock
Serial data transfer inputs. These pins must be
DI: transfer data
I
I
connected to the system controller.
CE: chip enable
CE
When the analog dimmer is selected, the analog voltage applied to this pin controls the duty of the G1
and G2 digit output pins. Since a 6-bit A/D converter is applied to this analog voltage and that result is
input to a decoder that provides a built-in dimmer curve, the relationship between the analog voltage
45
DIM
GND
and the duty can be specified as a mask program. Note that 63/96 · V
6-bit A/D converter.
is the full-scale level for the
DD
2, 3
G1, G2
O
O
Digit outputs. The frame frequency f is (f
/4096) Hz
Open
Open
O
OSC
41 to 5
S1 to S37
Segment outputs for displaying the display data transferred by serial data input.
No. 3586-4/10
LC7574NE, 7574NW
Serial Data Transfer Format
1. When CL is stopped at the low level
2. When CL is stopped at the high level
Figure 2
CCB address: Transfer 1010 , as shown in Figure 2.
B
M0:
Digital/analog dimmer selection data
M0 = 0 ....................................Digital dimmer
M0 = 1 ....................................Analog dimmer
DM0 to DM9: Dimmer data
This data controls the duty of the G1 and G2 digit output pins when the digital dimmer is selected.
This data consists of 10 bits, of which DM0 is the LSB. Note that display intensity can be adjusted by
controlling the duty of the G1 and G2 digit output pins. (The DM0 to DM9 dimmer data is ignored
when the analog dimmer is selected.)
SD1 to SD74: Display data
SD1 to SD37...........................Display data for the G1 digit output pin
SD38 to SD74.........................Display data for the G2 digit output pin
SDn (n = 1 to 74) = 1..............Display on
SDn (n = 1 to 74) = 0..............Display off
Test data
T0:
The T0 bit must be set to 0.
No. 3586-5/10
LC7574NE, 7574NW
Serial Data Format
Correspondence between Display Data (SD1 to SD74) and Segment Output Pins
Segment output pin
G1
G2
Segment output pin
G1
G2
S1
S2
SD1
SD38
SD39
SD40
SD41
SD42
SD43
SD44
SD45
SD46
SD47
SD48
SD49
SD50
SD51
SD52
SD53
SD54
SD55
SD56
S20
S21
S22
S23
S24
S25
S26
S27
S28
S29
S30
S31
S32
S33
S34
S35
S36
S37
SD20
SD21
SD22
SD23
SD24
SD25
SD26
SD27
SD28
SD29
SD30
SD31
SD32
SD33
SD34
SD35
SD36
SD37
SD57
SD58
SD59
SD60
SD61
SD62
SD63
SD64
SD65
SD66
SD67
SD68
SD69
SD70
SD71
SD72
SD73
SD74
SD2
S3
SD3
S4
SD4
S5
SD5
S6
SD6
S7
SD7
S8
SD8
S9
SD9
S10
S11
S12
S13
S14
S15
S16
S17
S18
S19
SD10
SD11
SD12
SD13
SD14
SD15
SD16
SD17
SD18
SD19
Example: Segment output pin S11 is controlled as follows:
Display data
Segment output pin S11 state
SD11
SD48
0
0
1
1
0
1
0
1
The segments corresponding to both the G1 and G2 digit output pins are off.
The segment corresponding to the G2 digit output pin is on.
The segment corresponding to the G1 digit output pin is on.
The segments corresponding to both the G1 and G2 digit output pins are on.
No. 3586-6/10
LC7574NE, 7574NW
BLK and the Display Control
Since the LSI internal data (SD1 to SD74 and the control data) is undefined when power is first applied, the display is
off (G1 and G2 = low) by setting the BLK pin low at the same time as power is applied. Then, meaningless display at
power on can be prevented by transferring all 92 bits of serial data from the controller while the display is off and setting
BLK pin high after the transfer completes. (See Figure 3.)
Power Supply Sequence
The following sequences must be observed when power is turned on and off. (See Figure 3)
• Power on: Logic block power supply (V ) on → Driver block power supply (V ) on
DD
FL
• Power off: Driver block power supply (V ) off → Logic block power supply (V ) off
FL
DD
Figure 3
Output Waveforms (S1 to S37)
No. 3586-7/10
LC7574NE, 7574NW
Relation between Segment and Digit Outputs
Figure 4
Descriptions
1. Consider the examples shown in Figure 4, where data is set up so that the segment outputs S1 to S37 output a low
level on the G1 digit output timing and a high level on the G2 digit output timing. (Here, the G2 side being lighted)
2. The digit output G1 and G2 waveforms in Example 1 are output when the 10 bits of dimmer data (DM0 to DM9) are
set to 3FE . The relation between t1 and the oscillator frequency f
is:
H
OSC
t1 = 2/f
.
OSC
For example, if f
= 1.6 [MHz], then
OSC
t1 = 2/1.6 [MHz] = 1.25 [µs].
Note that t1 and t2 are the same period in Example 1.
3. The digit output G1 and G2 waveforms in Example 2 are those when the dimmer data (DM0 to DM9) are set to a
smaller value. Although the time t1, which is from the point where digit output falls to segment output changes, does
not change, the time t2, which is from the point where segment output changes to the time the digit output rises,
becomes longer. When the dimmer data (DM0 to DM9) are set to 0FF and f
is 1.6 [MHz], then the frame
H
OSC
frequency f is:
O
f
= 1/(t3 × 2)
O
= f
/4096
OSC
= 391 [Hz],
and,
t3 = 1.28 [ms].
Therefore,
t2 =
(1.28 [ms] – 1.25 [µs] × 2) × (3FF – 0FF )
H
H
= 0.96 [ms].
1023
4. When the dimmer data (DM0 to DM9) are set to an even smaller value, the time t2, which is from the point where
segment output changes to the time the digit output rises, becomes even longer, as in Example 3. Note that t1 does
not change here, either.
No. 3586-8/10
LC7574NE, 7574NW
Sample Application Circuit
Usage Notes
1. Notes on the segment and digit waveforms
Figure 5
No. 3586-9/10
LC7574NE, 7574NW
The segment waveform is distorted by the VFD panel used and the wiring, and furthermore, in the case of being used
with essentially no dimming as in the digit waveform 1, as shown in Figure 5, the VFD panel glow dimly. By
carefully considering the segment waveform, it can be seen that this problem can be resolved by applying an
adequate amount of dimming, as shown in Digit waveform 2. When f
is 1.6 [MHz], we recommend using 10 bits
OSC
of dimmer data in the range 000 to 3E0 .
H
H
■ No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace
equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of
which may directly or indirectly cause injury, death or property loss.
■ Anyone purchasing any products described or contained herein for an above-mentioned use shall:
➀ Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and
distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all
damages, cost and expenses associated with such use:
➁ Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on
SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees
jointly or severally.
■ Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for
volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied
regarding its use or any infringements of intellectual property rights or other rights of third parties.
This catalog provides information as of October, 1995. Specifications and information herein are subject to
change without notice.
PS No. 3586-10/10
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