LC75893M [SANYO]
1/3 Duty LCD Display Driver with Key Input Function; 用按键输入功能1/3占空比LCD显示驱动
| 型号： | LC75893M |
| 厂家： | 
SANYO SEMICON DEVICE |
| 描述： | 1/3 Duty LCD Display Driver with Key Input Function |
| 文件： | 总23页 (文件大小：388K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Ordering number : ENN5971A
CMOS IC
LC75893M
1/3 Duty LCD Display Driver with Key Input Function
Overview
Package Dimensions
The LC75893M is a 1/3 duty LCD display driver that can
directly drive up to 48 segments and can control up to four
general-purpose output ports. This product also
incorporates a key scan circuit that accepts input from up
to 20 keys to reduce printed circuit board wiring.
unit: mm
3204-MFP36S
[LC75893M]
36
19
Features
• Key input function for up to 20 keys (A key scan is
performed only when a key is pressed.)
• 1/3 duty - 1/2 bias and 1/3 duty - 1/3 bias drive schemes
can be controlled from serial data (up to 48 segments).
• Sleep mode and all segments off functions that are
controlled from serial data
1
18
0.15
15.3
• Segment output port/general-purpose output port
function switching that is controlled from serial data
• Serial data I/O supports CCB format communication
with the system controller.
• Direct display of display data without the use of a
decoder provides high generality.
0.35
0.8
0.85
SANYO: MFP36S
• Provision of an on-chip voltage-detection type reset
circuit prevents incorrect displays.
• RC oscillator circuit
•
•
CCB is a trademark of SANYO ELECTRIC CO., LTD.
CCB is SANYO’s original bus format and all the bus
addresses are controlled by SANYO.
Any and all SANYO products described or contained herein do not have specifications that can handle
applications that require extremely high levels of reliability, such as life-support systems, aircraft’s
control systems, or other applications whose failure can be reasonably expected to result in serious
physical and/or material damage. Consult with your SANYO representative nearest you before using
any SANYO products described or contained herein in such applications.
SANYO assumes no responsibility for equipment failures that result from using products at values that
exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other
parameters) listed in products specifications of any and all SANYO products described or contained
herein.
SANYO Electric Co.,Ltd. Semiconductor Company
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
N2999RM (OT) No. 5971-1/23
LC75893M
Specifications
Absolute Maximum Ratings at Ta = 25°C, V = 0V
SS
Parameter
Maximum supply voltage
Symbol
Conditions
Ratings
–0.3 to +7.0
–0.3 to +7.0
–0.3 to VDD +0.3
–0.3 to +7.0
–0.3 to VDD +0.3
300
Unit
V
VDD max
VDD
VIN
VIN
1
CE, CL, DI
V
Input voltage
2
OSC, KI1 to KI5, TEST, VDD1, VDD
2
V
VOUT
OUT2
IOUT
1
DO
V
Output voltage
V
OSC, S1 to S16, COM1 to COM3, KS1 to KS4, P1 to P4
V
1
S1 to S16
µA
mA
mA
mA
mW
°C
°C
IOUT
IOUT
IOUT
2
3
4
COM1 to COM3
KS1 to KS4
P1 to P4
3
Output current
1
5
Allowable power dissipation
Operating temperature
Storage temperature
Pd max
Topr
Ta = 85°C
100
–40 to +85
–55 to +125
Tstg
Allowable Operating Ranges at Ta = –40 to +85°C, V = 0 V
SS
Ratings
Parameter
Supply voltage
Symbol
VDD
Conditions
Unit
min
4.5
typ
max
VDD
VDD
VDD
6.0
VDD
V
V
VDD
1
2
1
2
2/3 VDD
1/3 VDD
Input voltage
VDD
VDD
V
VIH
1
CE, CL, DI
0.8 VDD
0.6 VDD
0
6.0
V
Input high level voltage
VIH2
KI1 to KI5
VDD
V
Input low level voltage
VIL
CE, CL, DI, KI1 to KI5
OSC
0.2 VDD
V
Recommended external resistance
ROSC
68
820
38
kΩ
pF
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
µs
Recommended external capacitance COSC
OSC
Guaranteed oscillation range
Data setup time
Data hold time
fOSC
tds
tdh
tcp
tcs
tch
tøH
tøL
tr
OSC
19
160
160
160
160
160
160
160
76
CL, DI: Figure 2
CL, DI: Figure 2
CE, CL: Figure 2
CE, CL: Figure 2
CE, CL: Figure 2
CL: Figure 2
CL:Figure 2
CE wait time
CE setup time
CE hold time
High level clock pulse width
Low level clock pulse width
Rise time
CE, CL, DI: Figure 2
CE, CL, DI: Figure 2
160
160
Fall time
tf
1
DO output delay time
DO rise time
tdc
tdr
DO: RPU = 4.7 kΩ, CL = 10 pF* : Figure 2
1.5
1.5
1
DO: RPU = 4.7 kΩ, CL = 10 pF* : Figure 2
Note *1: Since DO is an open-drain output, these values depend on the resistance of the pull-up resistor RPU and the load capacitance CL.
No. 5971-2/23
LC75893M
Electrical Characteristics for the Allowable Operating Ranges
Ratings
typ
Parameter
Symbol
Conditions
Unit
min
max
Hysteresis
VH
VDET
IIH
CE, CL, DI, KI1 to KI5
0.1 VDD
3.0
V
V
Power-down detection voltage
Input high level current
Input low level current
Input floating voltage
2.7
3.3
CE, CL, DI: VI = 6.0 V
CE, CL, DI: VI = 0 V
KI1 to KI5
5.0
µA
µA
V
IIL
–5.0
50
VIF
0.05 VDD
250
Pull-down resistance
RPD
IOFFH
KI1 to KI5: VDD = 5.0 V
100
kΩ
µA
V
Output off leakage current
DO: VO = 6.0 V
6.0
VOH
VOH
VOH
VOH
1
2
3
4
KS1 to KS4: IO = –500 µA
VDD – 1.2 VDD – 0.5 VDD – 0.2
P1 to P4: IO = –1 mA
VDD – 1.0
VDD – 1.0
VDD – 1.0
V
Output high level voltage
Output low level voltage
S1 to S16: IO = –20 µA
V
COM1 to COM3: IO = –100 µA
KS1 to KS4: IO = 25 µA
V
VOL
VOL
VOL
VOL
VOL
1
2
3
4
5
0.2
0.5
0.1
1.5
1.0
1.0
1.0
0.5
V
P1 to P4: IO = 1 mA
V
S1 to S16: IO = 20 µA
V
COM1 to COM3: IO = 100 µA
DO: IO = 1 mA
V
V
VMID
VMID
VMID
VMID
VMID
1
2
3
4
5
COM1 to COM3: 1/2 bias, IO = ±100 µA
S1 to S16: 1/3 bias, IO = ±20 µA
S1 to S16: 1/3 bias, IO = ±20 µA
COM1 to COM3: 1/3 bias, IO = ±100 µA
COM1 to COM3: 1/3 bias, IO = ±100 µA
OSC: ROSC = 68 kΩ, COSC = 820 pF
Sleep mode
1
/2 V – 1.0
DD
1/2 V + 1.0
DD
V
2/3 V – 1.0
DD
2/3 V + 1.0
DD
V
2
Output middle level voltage*
1/3 V – 1.0
DD
1/3 V + 1.0
DD
V
2/3 V – 1.0
DD
2/3 V + 1.0
DD
V
1/3 V – 1.0
DD
1/3 V + 1.0
DD
V
Oscillator frequency
Current drain
fOSC
30.4
38
45.6
100
400
340
kHz
µA
µA
µA
IDD
IDD
IDD
1
2
3
VDD = 6.0 V, output open, 1/2 bias, fOSC = 38 kHz
VDD = 6.0 V, output open, 1/3 bias, fOSC = 38 kHz
200
170
Note *2: Excluding the bias voltage generation divider resistor built into VDD1 and VDD2. (See Figure 1.)
No. 5971-3/23
LC75893M
To the common segment driver
Excluding these resistors.
Figure 1
• When CL is stopped at the low level
• When CL is stopped at the high level
Figure 2
No. 5971-4/23
LC75893M
Pin Assignment
Block Diagram
No. 5971-5/23
LC75893M
Pin Functions
Handling
when unused
Pin
Pin No.
Function
Active
—
I/O
O
Segment outputs for displaying the display data transferred by serial data
input.
S1/P1 to S4/P4
S5 to S14
1 to 4
Open
Open
5 to 14
The S1/P1 to S4/P4 pins can be used as general-purpose output ports
under serial data control.
COM1
COM2
COM3
15
16
17
Common driver outputs
—
O
O
The frame frequency fO is given by: fO = (fOSC/384) Hz.
Key scan outputs
18
19
20
21
KS1/S15
KS2/S16
KS3
Although normal key scan timing lines require diodes to be inserted in the
timing lines to prevent shorts, since these outputs are unbalanced CMOS
transistor outputs, these outputs will not be damaged by shorting when
these outputs are used to form a key matrix. The KS1/S15 and KS2/S16
pins can be used as segment outputs when so specified by the control data.
—
Open
KS4
Key scan inputs
These pins have built-in pull-down resistors.
KI1 to KI5
OSC
22 to 26
32
H
I
GND
VDD
Oscillator connection
An oscillator circuit is formed by connecting an external resistor and
capacitor at this pin.
—
H
I/O
CE
CL
I
I
34
35
36
33
27
Serial data interface connections to the controller. Note that DO, being an
open-drain output, requires a pull-up resistor.
GND
CE: Chip enable
CL: Synchronization clock
DI: Transfer data
DI
—
—
—
I
DO: Output data
DO
O
I
Open
—
TEST
This pin must be connected to ground.
Used for applying the LCD drive 2/3 bias voltage externally. Must be
connected to VDD2 when a 1/2 bias drive scheme is used.
VDD
1
—
—
I
I
Open
Open
29
30
Used for applying the LCD drive 1/3 bias voltage externally. Must be
connected to VDD1 when a 1/2 bias drive scheme is used.
V
DD2
VDD
VSS
28
31
Power supply connection. Provide a voltage of between 4.5 and 6.0 V.
Power supply connection. Connect to ground.
—
—
—
—
—
—
No. 5971-6/23
LC75893M
Serial Data Input
1. When CL is stopped at the low level
Display data
Control data
Display data
Fixed data
Note: B0 to B3 and A0 to A3 ··········· CCB address
DD ········································· Direction data
2. When CL is stopped at the high level
Display data
Control data
Display data
Fixed data
Note: B0 to B3 and A0 to A3 ···········CCB address
DD ·········································Direction data
• CCB address ····42H
• D1 to D48··········Display data
• S0, S1···············Sleep control data
• K0, K1···············Key scan output/segment output selection data
• P0 to P2············Segment output port/general-purpose output port selection data
• SC·····················Segment on/off control data
• DR·····················1/2 bias or 1/3 bias drive selection data
No. 5971-7/23
LC75893M
Control Data Functions
1. S0, S1: Sleep control data
These control data bits switch between normal mode and sleep mode and set the states of the KS1 to KS4 key scan
outputs during key scan standby.
Control data
S0 S1
Segment outputs
Output pin states during key scan standby
Mode
OSC oscillator
Common outputs
KS1
H
KS2
H
KS3
H
KS4
H
0
0
Normal
Sleep
Sleep
Sleep
Operating
Stopped
Stopped
Stopped
Operating
0
1
1
1
0
1
L
L
L
L
L
L
H
L
L
H
H
H
H
H
H
Note: This assumes that the KS1/S15 and KS2/S16 output pins are selected for key scan output.
2. K0, K1: Key scan output/segment output selection data
These control data bits switch the functions of the KS1/S15 and KS2/S16 output pins between key scan output and
segment output.
Control data
K0 K1
Output pin state
Maximum number
KS1/S15 KS2/S16
of input keys
Note: KSn (n = 1, 2): Key scan output
Sn (n = 15, 16): Segment output
0
0
KS1
S15
S15
KS2
KS2
S16
20
15
10
0
1
1
X
X: don’t care
3. P0 to P2: Segment output port/general-purpose output port selection data
These control data bits switch the functions of the S1/P1 to S4/P4 output pins between the segment output port and
the general-purpose output port.
Control data
Output pin state
P0
0
P1
0
P2
0
S1/P1
S1
S2/P2
S2
S3/P3
S3
S4/P4
S4
Note: Sn (n = 1 to 4): Segment output port
Pn (n = 1 to 4): General-purpose output port
0
0
1
P1
S2
S3
S4
0
1
0
P1
P2
S3
S4
0
1
1
P1
P2
P3
S4
1
0
0
P1
P2
P3
P4
The table below lists the correspondence between the display data and the output pins when these pins are selected to be
general-purpose output ports.
Output pin
S1/P1
Corresponding display data
D1
D4
S2/P2
S3/P3
D7
S4/P4
D10
For example, if the S4/P4 output pin is selected to be a general-purpose output port, the S4/P4 output pin will output a
high level (VDD) when the display data D10 is 1, and will output a low level (VSS) when D10 is 0.
4. SC: Segment on/off control data
This control data bit controls the on/off state of the segments.
SC
0
Display state
On
Off
1
However, note that when the segments are turned off by setting SC to 1, the segments are turned off by outputting segment
off waveforms from the segment output pins.
No. 5971-8/23
LC75893M
5. DR: 1/2 bias or 1/3 bias drive selection data
This control data bit switches between LCD 1/2 bias or 1/3 bias drive.
DR
0
Drive scheme
1/3 bias drive
1/2 bias drive
1
Display Data and Output Pin Correspondence
Output pin
S1/P1
S2/P2
S3/P3
S4/P4
S5
COM1
D1
COM2
D2
COM3
D3
D4
D5
D6
D7
D8
D9
D10
D13
D16
D19
D22
D25
D28
D31
D34
D37
D40
D43
D46
D11
D14
D17
D20
D23
D26
D29
D32
D35
D38
D41
D44
D47
D12
D15
D18
D21
D24
D27
D30
D33
D36
D39
D42
D45
D48
S6
S7
S8
S9
S10
S11
S12
S13
S14
KS1/S15
KS2/S16
Note: This is for the case where the output pins S1/P1 to S4/P4, KS1/S15 and KS2/S16 are selected for use as segment outputs.
For example, the table below lists the segment output states for the S11 output pin.
Display data
Output pin state (S11)
D31
0
D32
0
D33
0
The LCD segments for COM1, COM2, and COM3 are off
The LCD segment for COM3 is on
0
0
1
0
1
0
The LCD segment for COM2 is on
0
1
1
The LCD segments for COM2 and COM3 are on
The LCD segment for COM1 is on
1
0
0
1
0
1
The LCD segments for COM1 and COM3 are on
The LCD segments for COM1 and COM2 are on
The LCD segments for COM1, COM2, and COM3 are on
1
1
0
1
1
1
No. 5971-9/23
LC75893M
Serial Data Output
1. When CL is stopped at the low level
Output data
Note: B0 to B3 and A0 to A3 ············ CCB address
2. When CL is stopped at the high level
Output data
Note: B0 to B3 and A0 to A3 ··········· CCB address
• CCB address·········· 43H
• KD1 to KD20 ·········· Key data
• SA ·························· Sleep acknowledge data
Note: If a key data read operation is executed when DO is high, the read key data (KD1 to KD20) and sleep
acknowledge data (SA) will be invalid.
Output Data
1.KD1 to KD20 : Key data
When a key matrix of up to 20 keys is formed from the KS1 to KS4 output pins and the KI1 to KI5 input pins and one
of those keys is pressed, the key output data corresponding to that key will be set to 1. The table shows the relationship
between those pins and the key data bits.
KI1
KD1
KI2
KD2
KI3
KD3
KI4
KD4
KI5
KS1/S15
KS2/S16
KS3
KD5
KD6
KD7
KD8
KD9
KD10
KD15
KD20
KD11
KD16
KD12
KD17
KD13
KD18
KD14
KD19
KS4
When the KS1/S15 and KS2/S16 output pins are selected to be segment outputs by control data bits K0 and K1 and a
key matrix of up to 10 keys is formed using the KS3 and KS4 output pins and the KI1 to KI5 input pins, the KD1 to
KD10 key data bits will be set to 0.
2.SA: Sleep acknowledge data
This output data bit is set to the state when the key was pressed. Also, while DO will be low in this case, if serial data is
input and the mode is set (to normal or sleep mode) during this period, that mode will be set. SA will be 1 in sleep
mode and 0 in normal mode.
Sleep Mode Functions
Sleep mode is set up by setting S0 or S1 in the control data to 1. The segment outputs will all go low and the common
outputs will also go low, and the oscillator on the OSC pin will stop (it will be started by a key press). This reduces
power dissipation. This mode is cleared by sending control data with both S0 and S1 set to 0. However, note that the
S1/P1 to S4/P4 outputs can be used as general-purpose output ports according to the state of the P0 to P2 control data
bits, even in sleep mode. (See the control data description for details.)
No. 5971-10/23
LC75893M
Key Scan Operation Functions
1. Key scan timing
The key scan period is 192 T (s). To reliably determine the on/off state of the keys, the LC75893M scans the keys
twice and determines that a key has been pressed when the key data agrees. It outputs a key data read request (a low
level on DO) 420 T (s) after starting a key scan. If the key data does not agree and a key was pressed at that point, it
scans the keys again. Thus the LC75893M cannot detect a key press shorter than 420 T (s).
Note: *3. In sleep mode the high/low state of these pins is determined by the S0 and S1 bits in the control data. Key scan output signals are not output
from pins that are set low.
2. In normal mode
• The pins KS1 to KS4 are set high.
• When a key is pressed a key scan is started and the keys are scanned until all keys are released. Multiple key
presses are recognized by determining whether multiple key data bits are set.
1
• If a key is pressed for longer than 420 T (s) (where T =
) the LC75893M output a key data read
fOSC
request (a low level on DO) to the controller. The controller acknowledges this request and reads the key data.
However, if CE is high during a serial data transfer, DO will be set high.
• After the controller reads the key data, the key data read request is cleared (DO is set high) and the LC75893M
performs another key scan. Also note that DO, being an open-drain output, requires a pull-up resistor (between 1
and 10 kΩ).
No. 5971-11/23
LC75893M
3. In sleep mode
• The pins KS1 to KS4 are set to high or low by the S0 and S1 bits in the control data. (See the control data
description for details.)
• If a key on one of the lines corresponding to a KS1 to KS4 pin which is set high is pressed, the oscillator on the
OSC pin is started and a key scan is performed. Keys are scanned until all keys are released. Multiple key presses
are recognized by determining whether multiple key data bits are set.
1
• If a key is pressed for longer than 420 T (s) (where T =
) the LC75893M outputs a key data read
fOSC
request (a low level on DO) to the controller. The controller acknowledges this request and reads the key data.
However, if CE is high during a serial data transfer, DO will be set high.
• After the controller reads the key data, the key data read request is cleared (DO is set high) and the LC75893M
performs another key scan. However, this does not clear sleep mode. Also note that DO, being an open-drain
output, requires a pull-up resistor (between 1 and 10 kΩ).
• Sleep mode key scan example
Example: When S0 = 0, S1 = 1 (Sleep with only KS4 high)
When any one of these keys is pressed,
the oscillator on the OSC pin is started
and the keys are scanned.
Note: *4. These diodes are required to reliable recognize multiple key presses on the KS4 line when sleep mode state with only KS4 high, as in the
above example. That is, these diodes prevent incorrect operations due to sneak currents in the KS4 key scan output signal when keys on
the KS1 to KS3 lines are pressed at the same time.
Multiple Key Presses
Although the LC75893M is capable of key scanning without inserting diodes for dual key presses, triple key presses on
the KI1 to KI5 input pin lines, or multiple key presses on the KS1 to KS4 output pin lines, multiple presses other than
these cases may result in keys that were not pressed recognized as having been pressed. Therefore, a diode must be
inserted in series with each key. Applications that do not recognize multiple key presses of three or more keys should
check the key data for three or more 1 bits and ignore such data.
No. 5971-12/23
LC75893M
1/3 Duty, 1/2 Bias Drive Technique
COM1
COM2
COM3
LCD drive output when all LCD
segments corresponding to COM1,
COM2, and COM3 are turned off.
LCD drive output when only LCD
segments corresponding to
COM1 are on.
LCD drive output when only LCD
segments corresponding to
COM2 are on.
LCD drive output when LCD
segments corresponding to
COM1 and COM2 are on.
LCD drive output when only LCD
segments corresponding to
COM3 are on.
LCD drive output when LCD
segments corresponding to
COM1 and COM3 are on.
LCD drive output when LCD
segments corresponding to
COM2 and COM3 are on.
LCD drive output when all LCD
segments corresponding to COM1,
COM2, and COM3 are on.
1/3 Duty, 1/2 Bias Waveforms
No. 5971-13/23
LC75893M
1/3 Duty, 1/3 Bias Drive Technique
COM1
COM2
COM3
LCD drive output when all LCD
segments corresponding to COM1,
COM2, and COM3 are turned off.
LCD drive output when only LCD
segments corresponding to
COM1 are on.
LCD drive output when only LCD
segments corresponding to
COM2 are on.
LCD drive output when LCD
segments corresponding to
COM1 and COM2 are on.
LCD drive output when only LCD
segments corresponding to
COM3 are on.
LCD drive output when LCD
segments corresponding to
COM1 and COM3 are on.
LCD drive output when LCD
segments corresponding to
COM2 and COM3 are on.
LCD drive output when all LCD
segments corresponding to COM1,
COM2, and COM3 are on.
1/3 Duty, 1/3 Bias Waveforms
No. 5971-14/23
LC75893M
Voltage Detection Type Reset Circuit (VDET)
This circuit generates an output signal and resets the system when power is first applied and when the voltage drops, i.e.,
when the power supply voltage is less than or equal to the power down detection voltage VDET, which is 3.0 V, typical.
To assure that this function operates reliably, a capacitor must be added to the power supply line so that the power supply
voltage VDD rise time when power is first applied and the power supply voltage VDD fall time when the voltage drops are
both at least 1 ms. (See Figure 3.)
System Reset
The LC75893M supports the reset method described below. When a system reset is applied, display is turned off, key
scanning is stopped, and all the key data is reset to low. When the reset is cleared, display is turned on and key scanning
become possible.
1. Reset method
If at least 1 ms is assured as the supply voltage VDD rise time when power is applied, a system reset will be applied by
the VDET output signal when the supply voltage is brought up. If at least 1 ms is assured as the supply voltage VDD
fall time when power drops, a system reset will be applied in the same manner by the VDET output signal when the
supply voltage is lowered. Note that the reset is cleared at the point when all the serial data (the display data D1 to
D48 and the control data) has been transferred, i.e., on the fall of the CE signal on the transfer of the last direction
data, after all the direction data has been transferred. (See Figure 3.)
Figure 3
2. LC75893M internal block states during the reset period
• CLOCK GENERATOR
Reset is applied and the base clock is stopped. However the OSC pin state (normal or sleep mode) is determined
after the S0 and S1 control data bits are transferred.
• COMMON DRIVER, SEGMENT DRIVER & LATCH
Reset is applied and the display is turned off. However, display data can be input to the latch circuit in this state.
• KEY SCAN
Reset is applied, the circuit is set to the initial state, and at the same time the key scan operation is disabled.
• KEY BUFFER
Reset is applied and all the key data is set to low.
• CCB INTERFACE, CONTROL REGISTER, SHIFT REGISTER
Since serial data transfer is possible, these circuits are not reset.
No. 5971-15/23
LC75893M
Blocks that are reset
3. Output pin states during the reset period
Output pin
S1/P1 to S4/P4
S5 to S14
State during reset
5
L *
L
L
COM1 to COM3
KS1/S15, KS2/S16
KS3
5
L *
6
X *
KS4
H
7
DO
H *
X: Don’t care
Note: *5. These output pins are forcibly set to the segment output function and held low.
*6. When power is first applied, these output pins are undefined until the S0 and S1 control data bits have been transferred.
*7. Since this output pin is an-open drain output, a pull-up resistor of between 1 and 10 kΩ is required. This pin remains high during the reset period
even if a key data read operation is performed.
No. 5971-16/23
LC75893M
Sample Application Circuit 1
1/2 bias (for use with normal panels)
Note: *8.Add a capacitor to the power supply line so that the power supply voltage VDD rise time when power is applied and the power supply voltage VDD fall
time when power drops are both at least 1 ms, as the LC75893M is reset by the VDET.
*9.The DO pin, being an open-drain output, requires a pull-up resistor. Select a resistance (between 1 to 10 kΩ) appropriate for the capacitance of the
external wiring so that signal waveforms are not degraded.
No. 5971-17/23
LC75893M
Sample Application Circuit 2
1/2 bias (for use with large panels)
Note: *8.Add a capacitor to the power supply line so that the power supply voltage VDD rise time when power is applied and the power supply voltage VDD fall
time when power drops are both at least 1 ms, as the LC75893M is reset by the VDET.
*9.The DO pin, being an open-drain output, requires a pull-up resistor. Select a resistance (between 1 to 10 kΩ) appropriate for the capacitance of the
external wiring so that signal waveforms are not degraded.
No. 5971-18/23
LC75893M
Sample Application Circuit 3
1/3 bias (for use with normal panels)
Note: *8.Add a capacitor to the power supply line so that the power supply voltage VDD rise time when power is applied and the power supply voltage VDD fall
time when power drops are both at least 1 ms, as the LC75893M is reset by the VDET.
*9.The DO pin, being an open-drain output, requires a pull-up resistor. Select a resistance (between 1 to 10 kΩ) appropriate for the capacitance of the
external wiring so that signal waveforms are not degraded.
No. 5971-19/23
LC75893M
Sample Application Circuit 4
1/3 bias (for use with large panels)
Note: *8.Add a capacitor to the power supply line so that the power supply voltage VDD rise time when power is applied and the power supply voltage VDD fall
time when power drops are both at least 1 ms, as the LC75893M is reset by the VDET.
*9.The DO pin, being an open-drain output, requires a pull-up resistor. Select a resistance (between 1 to 10 kΩ) appropriate for the capacitance of the
external wiring so that signal waveforms are not degraded.
Notes on transferring display data from the controller
The display data (D1 to D48) is transferred to the LC75893M in two operations. All of the display data should be
transferred within 30 ms to maintain the quality of the displayed image.
No. 5971-20/23
LC75893M
Notes on the controller key data read techniques
1. Timer based key data acquisition
• Flowchart
CE = [L]
DO = [L]
• Timing chart
t3·······Key scan execution time when the key data agreed for two key scans (420T[s]).
t4·······Key scan execution time when the key data did not agree for two key scans and the key scan was executed again (840T[s]).
t5·······Key address (43H) transfer time
t6·······Key data read time
1
T = ——
fosc
• Explanation
In this technique, the controller uses a timer to determine key on/off states and read the key data. The controller must
check the DO state when CE is low every t7 period without fail. If DO is low, the controller recognizes that a key
has been pressed and executes the key data read operation.
The period t7 in this technique must satisfy the following condition.
t7 > (t5 + t6 + t4)
If a key data read operation is executed when DO is high, the read key data (KD1 to KD20) and sleep acknowledge
data (SA) will be invalid.
No. 5971-21/23
LC75893M
2. Interrupt based key data acquisition
• Flowchart
CE = [L]
DO = [L]
CE = [L]
DO = [H]
• Timing chart
t3·······Key scan execution time when the key data agreed for two key scans (420T[s]).
t4·······Key scan execution time when the key data did not agree for two key scans and the key scan was executed again (840T[s]).
t5·······Key address (43H) transfer time
t6·······Key data read time
1
T = ——
fosc
• Explanation
In this technique, the controller uses interrupts to determine key on/off states and read the key data. The controller
must check the DO state when CE is low. If DO is low, the controller recognizes that a key has been pressed and
executes the key data read operation. After that the next key on/off determination is performed after the time t8 has
elapsed by checking the DO state when CE is low and reading the key data. The period t8 in this technique must
satisfy the following condition.
t8 > t4
If a key data read operation is executed when DO is high, the read key data (KD1 to KD20) and sleep acknowledge
data (SA) will be invalid.
No. 5971-22/23
LC75893M
Specifications of any and all SANYO products described or contained herein stipulate the performance,
characteristics, and functions of the described products in the independent state, and are not guarantees
of the performance, characteristics, and functions of the described products as mounted in the customer’s
products or equipment. To verify symptoms and states that cannot be evaluated in an independent device,
the customer should always evaluate and test devices mounted in the customer’s products or equipment.
SANYO Electric Co., Ltd. strives to supply high-quality high-reliability products. However, any and all
semiconductor products fail with some probability. It is possible that these probabilistic failures could
give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire,
or that could cause damage to other property. When designing equipment, adopt safety measures so
that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective
circuits and error prevention circuits for safe design, redundant design, and structural design.
In the event that any or all SANYO products (including technical data, services) described or contained
herein are controlled under any of applicable local export control laws and regulations, such products must
not be exported without obtaining the export license from the authorities concerned in accordance with the
above law.
No part of this publication may be reproduced or transmitted in any form or by any means, electronic or
mechanical, including photocopying and recording, or any information storage or retrieval system,
or otherwise, without the prior written permission of SANYO Electric Co., Ltd.
Any and all information described or contained herein are subject to change without notice due to
product/technology improvement, etc. When designing equipment, refer to the “Delivery Specification”
for the SANYO product that you intend to use.
Information (including circuit diagrams and circuit parameters) herein is for example only; it is not
guaranteed for volume production. SANYO believes information herein is accurate and reliable, but
no guarantees are made or implied regarding its use or any infringements of intellectual property rights
or other rights of third parties.
This catalog provides information as of November, 1999. Specifications and information herein are
subject to change without notice.
PS No. 5971-23/23
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