LC7940YC_技术文档

Ordering number: EN 6157

CMOS IC

LC7940YC,7941YC

Dot-matrix LCD Drivers

Overview

The LC7940YC and LC7941YC are segment driver ICs

for driving large, dot

bit parallel or serial input, display data from a controller

into an 80 bit latch, and then generate LCD drive signals

–matrix LCD displays. They read 4–

–

corresponding to that data.

The LC7940YC and LC7941YC feature mirror–image pin

assignments, allowing them to be used together to increase

component density. They are designed to be used with the

LC7942YC common driver to drive large LCD panels.

Features

• 80 built

• 1/8 to l/128 display duty cycle

• Serial or 4 bit parallel data input

–in LCD display drive circuits

–

• Chip disable for low power dissipation for large

–sized

panels

• Bias supply voltags can be supplied externally

• Operating supply voltage and ambient temperature

- 2.7 to 5.5 V logic supply ( V ) at Ta = 20 to +85°C

) at Ta = 20 to

–

DD

- 8 to 20V LCD supply (V

+85 °C

–

V

–

DD

EE

• CMOS process

Speciﬁcations

The following electrical characteristics apply when sealed in a Sanyo standard QIC-100 package.

Absolute Maximum Ratings at Ta = 25 ± 2°C, V = 0 V

SS

Parameter

Symbol

V max

DD

Ratings

–0.3 to +7.0

0 to 22

Unit

V

Logic supply voltge

LCD supply voltage, See Note below.

Input voltage

V

– V max

V

DD

EE

V max

–0.3 to V + 03

°C

I

DD

■

Any and all SANYO products described or contained herein do not have speciﬁcations that can handle

applications that require extremely high levels of reliability, such as life-support systems, aircraft’s

control systems, or other applications whose failure can be reasonably expected to result in serious

physical and/or material damage. Consult with your SANYO representative nearest you before using

any SANYO products described or contained herein in such applications.

SANYO assumes no responsibility for equipment failures that result from using products at values that

exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other

parameters) listed in products speciﬁcations of any and all SANYO products described or contained

herein.

SANYO Electric Co., Ltd. Semiconductor Company

TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN

63099RM (ID) No. 6157—1/13

LC7940YC, LC7941YC

Parameter

Operating temperature range

Symbol

Ratings

–20 to +85

–40 to +125

Unit

°C

T

opr

Storage temperature range

T

°C

stg

Note

V

≥ V > V > V > V

1 3 4 EE

DD

Recommended Operating Condltions at Ta = –20 to + 85°C, V = 0V

SS

Ratings

typ

Parameter

Symbol

Conditions

Unit

min

max

Logic supply voltage

V

2.7

8

–

5.5

20

V

DD

LCD supply voltage

V

– V

See Notes 1 and 2.

–

DD

EE

CP, CDl, DI1 to DI3, M,

SDl, P/S, DISPOFF and

LOAD

HIGH–level input voltage

V

0.8V

–

V

IH

DD

–

CP, CDI, Dl1 to DI3, M,

SDl, P/S,DISPOFF and

LOAD

LOW–level inpvt voltage

V

–

0.2V

DD

IL

CP shift clock frequency

CP pulsewidth

f

–

3.3

–

MHz

ns

CP

t

100

80

0

WC

LOAD pulsewidth

t

–

WL

DIn and SDI to CP setup time

DIn and SDI to CP hold time

t

–

SETUP

t

–

HOLD

t

–

CL1

CL2

CP to LOAD time

100

–

LOAD to CP time

CP rise time

t

–

LC

t

50

R

CP fall time

t

–

F

LOAD rise time

LOAD fall time

t

–

RL

t

–

FL

Notes

1.

V

≥ V > V > V > V

DD l 3 4 EE

2. At turn ON, the LCD supply should be energized after or simultaneously with the logic supply. At turn OFF, the logic supply

should be cut after or simultaneously with the LCD supply.

Electrlcai Characterfstlcs at Ta = 25 ± 2°C,V = 0V, V = 2.7 to 5.5 V

SS

DD

Ratings

typ

Parameter

Symbol

Conditions

Unit

min

max

V

=V ; LOAD, CP, CDI,

DD

IN

HIGH–level input current

I

P/S, DI1 to DI3, SDl, M,

and DISPOFF

–

1

µA

IH

VIN = VSS; LOAD, CP,

CDl, P/S, DI1 to DI3, SDI,

M, and DISPOFF

LOW–level input current

I

–

–1

µA

IL

CDO HIGH–level output voltage

CDO LOW–levef output voltage

V

I

= –400 µA

= 400 µA

V

DD

– 0.4

–

V

OH

OL

V

0.4

OL

V

– V = 18 V,

EE

DD

O1 to O80 driver ON resistance

R

|V – V = 0.25 V.

–

2

4

kΩ

ON

DE

O|

See note

No. 6157—2/13

LC7940YC, LC7941YC

Ratings

typ

Parameter

Symbol

Conditions

Unit

min

max

CDI = V

,

DD

V

– V = 18 V,

= 3.3 MHz,

DD

EE

V

to V standby supply current

I

–

200

µA

DD

SS

ST

SS

EE

f

CP

no output load ; V

SS

V

– V = 18 V,

EE

= 3.3 MHz,

= 5.156 kHz,

= 52 Hz ;VSS

DD

f

I

f

CP

to V operating supply current

I

–

1.0

mA

ss

LOAD

M

V

– V = 18V,

EE

= 3.3 MHz,

= 5,156 kHz,

DD

f

CP

to V operating supply current

–

5

0.1

–

mA

pF

EE

LOAD

= 52 Hz ; V

M

EE

CP input capacitance

C

f

= 3.3 MHz ; CP

–

I

CP

Note

V

= V or V , or V or V , V = V , V = 9/11 × (V

–

V

), V = 2/11 × (V

–

V

)

DE

1

3

4

EE

1

DD

3

DD

EE

4

DD

EE

Switching Characteristics at Ta = 25 ± 2°C,V = 0V, V = 2.7 to 5.5 V

SS

DD

Ratings

typ

Parameter

Symbol

Conditions

Unit

min

max

200

CDO output delay time

t

C

= 30 pF

–

ns

D

L

Switching Characteristics Waveform

t

WC

t

R

F

0.8V^DD

CP

0.2VDD

t

SET

UP

t

HOLD

SDI

DI1 to 3

t

FL

RL

t

CL (2)

CL (1)

t

LC

LOAD

CDO

t

WL

t

D

No. 6157—3/13

LC7940YC, LC7941YC

Pad Layout (Top view)

O1

O2

O3

O4

O5

O6

O7

O8

O9

O10

O11

O12

O13

O14

O15

O16

O17

O18

O19

O20

O21

O22

O23

O24

O25

O26

O27

O28

O29

O30

O80

O79

O78

O77

O76

O75

O74

O73

O72

O71

O70

O69

O68

O67

O66

O65

O64

O63

O62

O61

O60

O59

O58

O57

O56

O55

O54

O53

O52

O51

LC7940YC

O80

O1

O2

O3

O4

O5

O6

O7

O8

O9

O79

O78

O77

O76

O75

O74

O73

O72

O71

O70

O69

O68

O67

O66

O65

O64

O63

O62

O61

O60

O59

O58

O57

O56

O55

O54

O53

O52

O51

O10

O11

O12

O13

O14

O15

O16

O17

O18

O19

O20

O21

O22

O23

O24

O25

O26

O27

O28

O29

O30

LC7941YC

No. 6157—4/13

LC7940YC, LC7941YC

LC7940YC Pad Location

chip size : 4.830 mm x 3.550 mm

Pin_No.

1

Name

O1

X

Y

Pin_No.

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

100

Name

O51

O52

O53

O54

O55

O56

O57

O58

O59

O60

O61

O62

O63

O64

O65

O66

O67

O68

O69

O70

071

X

Y

-1600

-1420

-1262

-1106

-952

2240

2072

1906

1742

1580

1420

1262

1106

952

1600

---

-2240

-2072

-1906

-1742

-1580

-1420

-1262

-1106

-952

-800

-650

-502

-356

-212

-70

2

O2

3

O3

4

O4

5

O5

6

O6

7

O7

8

O8

9

O9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

O10

O11

O12

O13

O14

O15

O16

O17

O18

O19

O20

O21

O22

O23

O24

O25

O26

O27

O28

O29

O30

O31

O32

O33

O34

O35

O36

O37

O38

O39

O40

O41

O42

O43

O44

O45

O46

O47

O48

O49

O50

800

650

502

356

212

70

-70

70

-212

212

-356

356

-502

502

-650

650

-800

800

-952

O72

O73

O74

O75

O76

O77

O78

O79

O80

---

952

-1106

-1262

-1420

-1580

-1742

-1906

-2072

-2240

1106

1262

1420

1580

1742

1906

2072

2240

---

CDO

---

1415

---

2240

---

DISPOFF

P/S

1252

1091

825

2240

2179

---

-800

-650

V

SS

EE

-502

629

-356

V

464

4

3

-212

V

299

-70

---

70

V

123

2179

2240

DD

212

V

-42

1

356

M

DI1

-316

-467

-620

-775

-932

-1091

-1252

-1415

502

650

DI2

800

DI3

952

SDI

LOAD

CDI

CP

1106

1262

1420

No. 6157—5/13

LC7940YC, LC7941YC

LC7941C Pad Location

chip size : 4.830 mm x 3.550 mm

Pin No.

1

Name

O80

O79

O78

O77

O76

O75

O74

O73

O72

O71

O70

O69

O68

O67

O66

O65

O64

O63

O62

O61

O60

O59

O58

O57

O56

O55

O54

O53

O52

O51

O50

O49

O48

O47

O46

O45

O44

O43

O42

O41

O40

O39

O38

O37

O36

O35

O34

O33

O32

O31

X

Y

Pin No.

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

100

Name

O30

O29

O28

O27

O26

O25

O24

O23

O22

O21

O20

O19

O18

O17

O16

O15

O14

O13

O12

O11

O10

O9

X

Y

-1600

-1420

-1262

-1106

-952

2240

2072

1906

1742

1580

1420

1262

1106

952

1600

1415

1252

1091

932

-2240

-2072

-1906

-1742

-1580

-1420

-1262

-1106

-952

-800

-650

-502

-356

-212

-70

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

800

650

502

356

212

70

-70

70

-212

212

-356

356

-502

502

-650

650

-800

800

-952

952

-1106

-1262

-1420

-1580

-1742

-1906

-2072

-2240

O8

1106

1262

1420

1580

1742

1906

2072

2240

2179

---

O7

O6

O5

O4

O3

O2

O1

CP

CDI

LOAD

SDI

DI3

-800

775

-650

DI2

620

-502

DI1

467

-356

M

316

-212

V

42

1

-70

V

-123

---

DD

70

---

212

V

-299

-464

-629

-825

-1091

-1252

---

2179

2240

---

3

4

356

502

V

EE

SS

650

800

P/S

DISPOFF

---

952

1106

1262

1420

CDO

---

-1415

---

2240

---

No. 6157—6/13

LC7940YC, LC7941YC

Block Diagram

01 02 03

079 080

V1

V3

V4

V^EE

VDD

4 Level LCD Drive Circuit

(80 bits)

V^SS

80

Level Shifter (80 bits)

M

DISP OFF

80

2nd Latch (80 bits)

80

1st Latch (80 bits)

4

20

SDI

DI3

DI2

DI1

Address Decoder

CLK

4 bits

Data Bus

Interface

Address Counter

(7 bits)

Chip Disable &

Latch Control

SER/PAR

Control

P/S

CDI

CDO

CP

LOAD

Pin Functions

Pin No.

Symbol

I/O

Function

LC7940YC

LC7941YC

91

86

87

92

89

88

l00

90

95

94

89

92

93

81

V

DD

V

– V is the logic supply.

SS

DD

V

Supply

SS

EE

– V is the LCD supply.

EE

V

1

3

4

LCD panel drive voltage supplies

V

Supply

and V are selected levels.

1

3

EE

and V are not–selected levels.

4

V

CP

I

Display data Input clock (falling–edge trigger).

Chip disable.

99

98

82

83

CDI

Data is read in when LOW, and not road in when HIGH.

Display data latch clock (falling–edge trigger).

On the falling edge, the LCD drive signals set by the display data are output.

LOAD

I

97

96

95

84

85

86

SDI

DI3

DI2

Serial data input.

4–bit parallel data input pins.

Data input

SDI

LCD driver outputs

O4

O3

O2

O1

O8

O7

O6

O5

O80

O79

O78

O77

DI3

I

DI2

94

87

D11

DI1

In serial data input mode, DI1 to DI3 should all be tied HIGH or LOW.

No. 6157—7/13

LC7940YC, LC7941YC

Pin No.

Symbol

I/O

Function

LC7940YC

LC7941YC

93

85

88

96

M

I

LCD panel drive voltage output alternation control signal.

P/S

Data input mode select. 4–bit parallel input when HIGH, and serial input when LOW

Cascade connection pin for extension segment drivers. Data is read out when HIGH.

Goes LOW after data is read out. Connected to the CDI input of the next chip.

82

1 to 80

84

99

80 to 1

97

CDO

O

LCD drive outputs.

The output drive level is determined by the display data, M signal and DISP OFF

input as shown below.

M

Q

DISP OFF

HIGH

Output

LOW

HIGH

×

LOW

HIGH

LOW

HIGH

×

V

3

1

4

HIGH

Ol to O80

O

HIGH

V

EE

LOW

V

1

Note

x = don’t care (tied HIGH or LOW)

O1 to O80 output control input pin.

DISPOFF

I

When LOW, V1 is output on the O1 to 080 outputs, See the truth table.

No connection.

81

83

90

91

98

NC

–

100

No. 6157—8/13

LC7940YC, LC7941YC

Application Notes

LCD Panel 1

1

2

6 4 1

6 4 2

1 5 9

1 6 0

7 9 9

8 0 0

1 6 1

1 6 2

8 0 1

8 0 2

3 1 9

3 2 0

9 5 9

9 6 0

3 2 1

3 2 2

9 6 1

9 6 2

4 7 9

4 8 0

1 1 1 9

1 1 2 0

4 8 1

4 8 2

1 1 2 1

1 1 2 2

6 3 9

6 4 0

1 2 7 9

1 2 8 0

No. 6157—9/13

LC7940YC, LC7941YC

LCD Panel 2

No. 6157—10/13

LC7940YC, LC7941YC

100 x 240-pixel LCD Panel Application

A 100 × 240–pixel LCD panel requires the following

drivers.

• 3 x LC7940YC (or LC7941YC) drivers

• 2 x LC7942YC drivers

An example using l/l00 duty cycle is shown below.

(m,n) : pixel address

1,79

Segment line (n)

Common line (m)

Frame Signal

1,1

2,1

1,2

2,2

1,79

1,80

1,81

1,82

1,160

1,161

1,240

2,240

DI01

01

---

RS/LS 02

LC7942YC

#1

LCD Panel (100 × 240 pixels)

CP

M

063

63,1

64,1

65,1

66,1

63,2

64,2

65,2

66,2

---

DI064 064

64,80 64,81

64,160 64,161

65,160 65,161

64,240

65,240

65,80 65,81

---

DI01

01

RS/LS 02

LC7942YC

#2

CP

M

---

100,1 100,2

100,79 100,80 100,81 100,82

100,160 100,161

100,240

080

036

DI064

O37 to O64

are open.

01

02

079

080

01

02

080

01

LC7940YC

#1

#2

CDO

CDI

CDO

CDI

CDO

CDI

(LC7941YC)

1. The LC7942YC chips are cascaded by connecting

DIO64 on chip I to DIO1 on chip 2. For a 100

–bit shift

register, O37 to O64 on chip 2 are left open.

2. The LC7940YC (or LC7941YC) chips are cascaded by

connecting CDO on chip I to CDI on chip 2, and CDO

on chip 2 to CDI on chip 3. CDI on chip I is tied to

GND, and CDO on chip 3 is not used. This

conﬁguration allows the input of 240–bit serial data.

No. 6157—11/13

LC7940YC, LC7941YC

100 x 240-pixel LCD Panel Timing Diagram

M

LOAD

CP

1,1

1,2

---

1,79

1,80

1,81

---

1,160

1,161

---

1,240

SDI

#1

SDO

#2

#3

Chip 1 data read

1 frame (240 bits)

Chip 2 data read

Chip 3 data read

M

LOAD

CP

1,1

1,2

---

1,239

1,240

2,1

---

2,240

3,1

---

100,240

SDI

1st line data read

2nd line data read

1frame (100 × 240 bits)

M

#1 DIO1

LOAD

---

98,1

98,2

99,1

100,1

100,2

1,1

1,2

---

99,1

99,2

100,1

100,2

01

1,1

1,2

2,1

2,2

99,2

99,80

99,81

02

#1

---

98,80

98,81

100,80

100,81

1,80

1,81

---

99,80

99,81

100,80

100,81

1,80

2,80

080

01

#2

---

1,81

2,81

98,160 99,160 100,160 1,160

99,160 100,160

1,160

2,160

080

01

#3

---

98,161 99,161 100,161 1,161

98,240 99,240 100,240 1,240

---

99,161 100,161

99,240 100,240

1,161

1,240

2,161

2,240

080

No. 6157—12/13

LC7940YC, LC7941YC

Segment Data Not Multiples of 4

Example.

LCD panel (100 × 230 pixels)

---

01

080

01

080

01

070

LC7940YC

#1

LC7940YC

#2

LC7940YC

#3

LOAD

SDI

m,1

m,2

---

,228

m,229

m,230

m+1,1

m+1,2

,228 m+1,229 m+1,230

If this timing data is sent, data elements (m, 229), (m, in 4–bit units, which also decreases power dissipation . For

230), (m+1, 229), (m+1. 230)... will not appear in the data that is not a multiple of 4, like 230, the following

output (O69 and O70 on chip 3). This is because the scheme is used.

LC7940YC (or LC7941YC) converts serial/parallel data

LOAD

m,1

m,2

---

Valid display data

Multiple of 4

,228

m,229

m,230

m,231

m,232

SDI

Dummy data

In this case, (m, 231) is output on O71 on chip 3, and (m,

232) on O72 on chip 3. However, these outputs are not

connected to the panel and are, therefore, invalid.

■

Speciﬁcations of any and all SANYO products described or contained herein stipulate the performance,

characteristics, and functions of the described products in the independent state, and are not guarantees

of the performance, characteristics, and functions of the described products as mounted in the customer’s

products or equipment. To verify symptoms and states that cannot be evaluated in an independent device,

the customer should always evaluate and test devices mounted in the customer’s products or equipment.

■

SANYO Electric Co., Ltd. strives to supply high-quality high-reliability products. However, any and all

semiconductor products fail with some probability. It is possible that these probabilistic failures could give

rise to accidents or events that could endanger human lives, that could give rise to smoke or ﬁre, or that

could cause damage to other property. When designing equipment, adopt safety measures so that these

kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits

and error prevention circuits for safe design, redundant design, and structural design.

■

In the event that any or all SANYO products(including technical data,services) described or contained

herein are controlled under any of applicable local export control laws and regulations, such products

must not be exported without obtaining the export license from the authorities concerned in accordance

with the above law.

■

No part of this publication may be reproduced or transmitted in any form or by any means, electronic or

mechanical, including photocopying and recording, or any information storage or retrieval system, or

otherwise, without the prior written permission of SANYO Electric Co. , Ltd.

Any and all information described or contained herein are subject to change without notice due to

product/technology improvement, etc. When designing equipment, refer to the "Delivery Speciﬁcation" for

the SANYO product that you intend to use.

Information (including circuit diagrams and circuit parameters) herein is for example only ; it is not

guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no

guarantees are made or implied regarding its use or any infringements of intellectual property rights or

other rights of third parties.

This catalog provides information as of June, 1999. Speciﬁcations and information herein are subject to

change without notice.

No. 6157—13/13


型号：	LC7940YC
厂家：	SANYO SEMICON DEVICE
描述：	Dot-matrix LCD Drivers 点阵LCD驱动器驱动器接口集成电路 CD
文件：	总13页 (文件大小：250K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LC7940YC [SANYO]

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