LC863548B [SANYO]
8-bit 1-chip Microcontroller; 8位单芯片微控制器
| 型号： | LC863548B |
| 厂家： | 
SANYO SEMICON DEVICE |
| 描述： | 8-bit 1-chip Microcontroller |
| 文件： | 总17页 (文件大小：528K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Ordering number : ENN7936
LC863548B, LC863540B
LC863532B, LC863528B
LC863524B, LC863520B
LC863516B
CMOS IC
FROM 48K/40K/32K/28K/24K/20K/16K-byte,
RAM 640/512-byte on-chip and 176
×
9-bit OSD RAM
8-bit 1-chip Microcontroller
Overview
The LC863548/40/32/28/24/20/16B are 8-bit single chip microcontrollers with the following on-chip functional blocks :
• CPU : Operable at a minimum bus cycle time of 0.424µs
• On-chip ROM capacity
Program ROM : 48K/40K/32K/28K/24K/20K/16K-bytes
CGROM
: 16K-bytes
• On-chip RAM capacity : 640/512-bytes
• OSD RAM : 176 × 9-bits
• On-screen display controller
• Four channels × 6-bit AD Converter
• Three channels × 7-bit PWM
• Two channels × 16-bit timer/counter, 14-bit base timer
• IIC-bus compliant serial interface circuit (Multi-master type)
• ROM correction function
• 13-source 8-vectored interrupt system
• Integrated system clock generator and display clock generator
Only one X’tal oscillator (32.768kHz) for PLL reference is used for both generators.
All of the above functions are fabricated on a single chip.
Ver.0.92
62102
73004 JO IM No.7936-1/17
LC863548B/40B/32B/28B/24B/20B/16B
Features
■Read-Only Memory (ROM)
: 49152 × 8-bits/40960 × 8-bits/32768 × 8-bits/
28672 × 8-bits/24576 × 8-bits/20480 × 8-bits/
16384 × 8-bits for program
16128 × 8-bits for CGROM
■Random Access Memory (RAM) : 512 × 8-bits (working area) : LC863548B/40B
384 × 8-bits (working area) : LC863532B/28B/24B/20B/16B
128 × 8-bits (working or ROM correction function)
176 × 9-bits (for CRT display)
■OSD functions
• Screen display : 36 characters × 8 lines (by software)
• RAM
: 176 words (9-bits per word)
Display area : 36 words × 4 lines
Control area : 8 words × 4 lines
• Characters
Up to 252 kinds of 16 × 32 dot character fonts (4 characters including 1 test character are not programmable)
Each font can be divided into two parts and used as two fonts (Ex. 16 × 16 dot character font × 2)
• Various character attributes
Character colors
: 16 colors (analog mode : l Vp-p output) /8 colors (digital mode)
Character background colors : 16 colors (analog mode : l Vp-p output) /8 colors (digital mode)
Fringe/shadow colors
Full screen colors
Rounding
: 16 colors (analog mode : l Vp-p output) /8 colors (digital mode)
: 16 colors (analog mode : l Vp-p output) /8 colors (digital mode)
Underline
Italic character (slanting)
• Attribute can be changed without spacing
• Vertical display start line number can be set for each row independently (Rows can be overlapped)
• Horizontal display start position can be set for each row independently
• Horizontal pitch (bit 9 to 16) *1 and vertical pitch (bit 1 to 32) can be set for each row independently
• Different display modes can be set for each row independently
Caption • Text mode/OSD mode 1/OSD mode 2 (Quarter size) /Simplified graphic mode
• Ten character sizes *1
Horez. × Vert. = (1 × 1), (1 × 2), (2 × 2), (2 × 4), (0.5 × 0.5)
(1.5 × 1), (1.5 × 2), (3 × 2), (3 × 4), (0.75 × 0.5)
• Shuttering and scrolling on each row
• Simplified Graphic Display
*1 Note : range depends on display mode : refer to the manual for details.
■Bus Cycle Time/Instruction-Cycle Time
Bus cycle time
Instruction cycle time
Clock divider
System clock oscillation
Internal VCO
(Ref : X'tal 32.768kHz)
Internal RC
Oscillation frequency
14.156MHz
Voltage
0.424µs
0.848µs
1/2
4.5V to 5.5V
7.5µs
91.55µs
183.1µs
15.0µs
183.1µs
366.2µs
1/2
1/1
1/2
800kHz
32.768kHz
32.768kHz
4.5V to 5.5V
4.5V to 5.5V
4.5V to 5.5V
Crystal
Crystal
■Ports
• Input/Output Ports
Data direction programmable in nibble units
: 4 ports (24 terminals)
: 1 port (8 terminals)
(If the N-ch open drain output is selected by option, the corresponding port data can be read in output mode.)
Data direction programmable for each bit individually : 3 ports (16 terminals)
■AD converter
• 4-channels × 6-bit AD converters
No.7936-2/17
LC863548B/40B/32B/28B/24B/20B/16B
■Serial interfaces
• IIC-bus compliant serial interface (Multi-master type)
Consists of a single built-in circuit with two I/O channels. The two data lines and two clock lines can be connected
internally.
■PWM output
• 3-channels × 7-bit PWM
■Timer
• Timer 0 : 16-bit timer/counter
With 2-bit prescaler + 8-bit programmable prescaler
Mode 0 : Two 8-bit timers with a programmable prescaler
Mode 1 : 8-bit timer with a programmable prescaler + 8-bit counter
Mode 2 : 16-bit timer with a programmable prescaler
Mode 3 : 16-bit counter
The resolution of timer is 1 tCYC.
• Timer 1 : 16-bit timer/ PWM
Mode 0 : Two 8-bit timers
Mode 1 : 8-bit timer + 8-bit PWM
Mode 2 : 16-bit timer
Mode 3 : A variable-bit PWM (9 to 16 bits)
In mode 0/1, the resolution of timer/PWM is 1 tCYC
In mode 2/3, the resolution of timer/PWM is selectable by program ; tCYC or 1/2 tCYC
• Base timer
Generate every 500ms overflow for a clock application
(using 32.768kHz crystal oscillation for the base timer clock)
Generate every 976µs, 3.9ms, 15.6ms, 62.5ms overflow
(using 32.768kHz crystal oscillation for the base timer clock)
Clock for the base timer is selectable from 32.768kHz crystal oscillation, system clock or programmable prescaler
output of Timer 0
■Remote control receiver circuit (connected to the P73/INT3/T0IN terminal)
• Noise rejection function
• Polarity switching
■Watchdog timer
External RC circuit is required
Interrupt or system reset is activated when the timer overflows
■ROM correction function
Max 128-bytes/2 addresses
■Interrupts
• 13 sources 8 vectored interrupts
1. External Interrupt INT0
2. External Interrupt INT1
3. External Interrupt INT2, Timer/counter T0L (Lower 8-bits)
4. External Interrupt INT3, base timer
5. Timer/counter T0H (Upper 8-bits)
6. Timer T1H, Timer T1L
7. Vertical synchronous signal interrupt ( ), horizontal line (
VS
)
HS
9. IIC, Software
• Interrupt priority control
Three interrupt priorities are supported (low, high and highest) and multi-level nesting is possible.
Low or high priority can be assigned to the interrupts from 3 to 8 listed above.
For the external interrupt INT0 and INT1, low or highest priority can be set.
No.7936-3/17
LC863548B/40B/32B/28B/24B/20B/16B
■Sub-routine stack level
• A maximum of 128 levels (stack is built in the internal RAM)
■Multiplication/division instruction
• 16-bits × 8-bits (7 instruction cycle times)
• 16-bits ÷ 8-bits (7 instruction cycle times)
■3 oscillation circuits
• Built-in RC oscillation circuit used for the system clock
• Built-in VCO circuit used for the system clock and OSD
• X’tal oscillation circuit used for base timer, system clock and PLL reference
■Standby function
• HALT mode
The HALT mode is used to reduce the power dissipation. In this operation mode, the program execution is stopped.
This mode can be released by the interrupt request or the system reset.
• HOLD mode
The HOLD mode is used to stop the oscillations ; RC (internal), VCO, and X’tal oscillations.
This mode can be released by the following conditions.
1. Pull the reset terminal (
) to low level.
2. Feed the selected level to either P70/INT0 or P71/INT1.
RES
■Package
• MFP36S
• DIP36S
■Development tools
• Flash EEPROM
• Evaluation chip
• Emulator
: LC86F3548A
: LC863096
: EVA86000 (main) + ECB863200A (evaluation chip board)
+ SUB863400A (sub board)
+ POD36-CABLE (cable)
+ POD36-DIP (for DIP36S)
or POD36-MFP (for MFP36S)
No.7936-4/17
LC863548B/40B/32B/28B/24B/20B/16B
Package Dimensions
unit : mm
3204B
Package Dimensions
unit : mm
3170A
No.7936-5/17
LC863548B/40B/32B/28B/24B/20B/16B
Pin Assignment
P10/SDA0
P11/SCLK0
P12/SDA1
P13/SCLK1
P03
1
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
P02
2
P01
3
P00
4
V
P17/PWM
P16/PWM3
P15/PWM2
P14/PWM1
P73/INT3/T0IN
P72/INT2/T0IN
P71/INT1
P70/INT0
P32
5
SS
XT1
6
XT2
7
V
8
DD
P04/AN4
P05/AN5
P06/AN6
P07/AN7
9
10
11
12
13
14
15
16
17
18
RES
FILT
P33
P30
P31
BL
B
G
VS
HS
R
Top view
No.7936-6/17
LC863548B/40B/32B/28B/24B/20B/16B
System Block Diagram
Interrupt Control
Standby Control
IR
PLA
ROM
X’tal
RC
VCO
PC
PLL
IIC
ROM Correct Control
ACC
B Register
C Register
XRAM
Timer 0
Bus Interface
Port 1
Port 3
Timer 1
ALU
Base Timer
ADC
Port 7
PSW
RAR
RAM
INT0 to 3
Noise Rejection Filter
PWM
CGROM
OSD
Control
Circuit
Stack Pointer
Port 0
VRAM
Watch Dog Timer
No.7936-7/17
LC863548B/40B/32B/28B/24B/20B/16B
Pin Description
Pin name
I/O
-
Function
Option
V
Negative power supply
SS
XT1
I
Input terminal for crystal oscillator
Output terminal for crystal oscillator
Positive power supply
XT2
O
-
V
DD
I
Reset terminal
RES
FILT
VS
HS
R
O
I
Filter terminal for PLL
Vertical synchronization signal input terminal
Horizontal synchronization signal input terminal
Red (R) output terminal of RGB image output
Green (G) output terminal of RGB image output
Blue (B) output terminal of RGB image output
I
O
O
O
O
G
B
BL
Fast blanking control signal
Switch TV image signal and caption/OSD image signal
• 8-bit input/output port
Port 0
I/O
Pull-up resistor
Input/output can be specified in nibble unit
(If the N-ch open drain output is selected by option, the corresponding port data can be
read in output mode.)
provided/not provided
Output Format
CMOS/Nch-OD
P00 to P07
• Other functions
AD converter input port (P04 to P07 : 4 channels)
• 8-bit input/output port
Input/output can be specified for each bit
(programmable pull-up resister provided)
• Other functions
Port 1
I/O
Output Format
CMOS/Nch-OD
P10 to P17
P10
P11
P12
P13
P14
P15
P16
P17
IIC0 data I/O
IIC0 clock output
IIC1 data I/O
IIC1 clock output
PWM1 output
PWM2 output
PWM3 output
Timer 1 (PWM) output
Port 3
I/O
I/O
• 4-bit input/output port
Input/output can be specified for each bit
(CMOS output/input with programmable pull-up resister)
• 4-bit input/output port
P30 to P33
Port 7
Input or output can be specified for each bit
P70 : I/O with programmable pull-up resister
P71 to P73 : CMOS output/input with programmable pull-up resister
• Other function
P70
P71 to P73
P70
INT0 input/HOLD release input/
Nch-Tr. Output for watchdog timer
INT1 input/HOLD release input
INT2 input/Timer 0 event input
INT3 input (noise rejection filter connected) /
Timer 0 event input
P71
P72
P73
Interrupt receiver format, vector addresses
rising/
falling
rising
falling
H level
L level
vector
INT0
INT1
INT2
INT3
enable
enable
enable
enable
enable
enable
enable
enable
disable
enable
enable
disable
disable
enable
enable
disable
disable
03H
0BH
13H
1BH
disable
enable
enable
Note : A capacitor of at least 10µF must be inserted between V
DD
and V when using this IC.
SS
Continued on next page.
No.7936-8/17
LC863548B/40B/32B/28B/24B/20B/16B
Continued from preceding page.
• Output form and existence of pull-up resistor for all ports can be specified for each bit.
• Programmable pull-up resistor is always connected regardless of port option, CMOS or N-ch open drain output in port 1.
• Port status in reset
Terminal
Port 0
I/O
Pull-up resistor status at selecting CMOS output option
Pull-up resistor OFF, ON after reset release
Programmable pull-up resistor OFF
I
I
Port 1
Absolute Maximum Ratings / Ta = 25°C, V = 0V
SS
Limits
Parameter
Symbol
Pins
Conditions
V
[V]
min
-0.3
typ
max
+7.0
unit
V
DD
Supply voltage
Input voltage
V
max
V
DD
DD
V (1)
,
,
RES HS VS
-0.3
-0.3
-0.3
V
V
V
+0.3
+0.3
+0.3
I
DD
DD
DD
Output voltage
Input/output voltage
V
V
(1)
R, G, B, BL, FILT
Ports 0, 1, 3, 7
Ports 0, 1, 3, 7
O
IO
High
Peak
IOPH(1)
• CMOS output
• For each pin.
• CMOS output
• For each pin.
The total of all pins.
-4
-5
level
output
current
output
current
IOPH(2)
R, G, B, BL
Total
output
current
ΣIOAH(1)
ΣIOAH(2)
ΣIOAH(3)
IOPL(1)
Ports 0, 1
Ports 3, 7
R, G, B, BL
Ports 0, 1, 3
Port 7
-20
-10
-12
The total of all pins.
The total of all pins.
For each pin.
mA
Low
level
output
current
Peak
output
current
20
15
IOPL(2)
For each pin.
IOPL(3)
R, G, B, BL
Ports 0, 1
Ports 3, 7
R, G, B, BL
MFP36S
For each pin.
5
Total
output
current
ΣIOAL(1)
ΣIOAL(2)
ΣIOAL(3)
Pd max
The total of all pins.
The total of all pins.
The total of all pins.
Ta = -10 to +70°C
40
20
12
Maximum power
dissipation
340
500
mW
°C
DIP36S
Operating
temperature range
Storage
Topr
Tstg
-10
-55
+70
+125
temperature range
Recommended Operating Range / Ta = -10°C to +70°C, V = 0V
SS
Limits
Parameter
Symbol
Pins
Conditions
V
[V]
min
typ
max
unit
DD
Operating supply
voltage range
V
V
V
(1)
V
0.844µs ≤ tCYC ≤ 0.852µs
4µs ≤ tCYC ≤ 400µs
4.5
5.5
DD
DD
DD
(2)
4.5
5.5
DD
Hold voltage
V
RAMs and the registers
data are kept in HOLD
mode.
HD
2.0
5.5
High level input
voltage
V
(1)
IH
(2)
Port 0
Output disable
4.5 to 5.5
4.5 to 5.5
0.6V
V
V
DD
DD
V
V
• Ports 1, 3 (Schumitt)
• Port 7 (Schumitt)
port input/interrupt
Output disable
IH
0.75V
DD
DD
•
,
,
RES HS VS
(Schumitt)
V
(3)
Port 70
Watchdog timer input
Output disable
IH
4.5 to 5.5
V
-0.5
DD
V
DD
Continued on next page.
No.7936-9/17
LC863548B/40B/32B/28B/24B/20B/16B
Continued from preceding page.
Limits
Parameter
Symbol
Pins
Conditions
Output disable
V
[V]
min
V
typ
max
0.2V
unit
V
DD
Low level input
voltage
V
V
(1)
(2)
Port 0
4.5 to 5.5
IL
IL
SS
DD
• Ports 1, 3 (Schumitt)
• Port 7 (Schumitt)
port input/interrupt
Output disable
4.5 to 5.5
V
0.25V
SS
DD
•
,
,
RES HS VS
(Schumitt)
V
(3)
Port 70
Watchdog timer input
Output disable
IL
4.5 to 5.5
V
0.6V
DD
SS
Operation cycle time
tCYC(1)
tCYC(2)
FmRC
• All functions operating
• OSD is not operating
Internal RC oscillation
4.5 to 5.5
4.5 to 5.5
0.844
0.844
0.848
0.8
0.852
400
µs
Oscillation
frequency range
4.5 to 5.5
0.4
3.0
MHz
Electrical Characteristics / Ta = -10°C to +70°C, V = 0V
SS
Limits
typ
Parameter
Symbol
Pins
Conditions
V
[V]
min
max
unit
DD
High level input
current
I
(1)
Ports 0, 1, 3, 7
• Output disable
• Pull-up MOS Tr. OFF
• V = V
IH
4.5 to 5.5
4.5 to 5.5
4.5 to 5.5
1
1
IN DD
(Including the off-leak current of
the output Tr.)
I
I
(2)
•
•
• V = V
RES
IH
IN
DD
,
HS VS
µA
Low level input
current
(1)
(2)
Ports 0, 1, 3, 7
• Output disable
• Pull-up MOS Tr. OFF
IL
• V = V
-1
IN SS
(Including the off- leak current of
the output Tr.)
I
•
•
V
= V
SS
RES
IL
IN
4.5 to 5.5
4.5 to 5.5
4.5 to 5.5
-1
-1
,
HS VS
High level
output voltage
V
(1)
• CMOS output of
ports 0, 1, 3,
71 to 73
I
= -1.0mA
OH
OH
V
DD
V
(2)
R, G, B, BL
I
= -0.1mA
R. G. B : digital mode
OH
OH
V
-0.5
DD
V
Low level
output voltage
V
V
V
(1)
(2)
(3)
Ports 0, 1, 3, 71 to 73
Ports 0, 3, 71 to 73
I
I
I
= 10mA
= 1.6mA
= 3.0mA
4.5 to 5.5
4.5 to 5.5
1.5
0.4
OL
OL
OL
OL
OL
OL
• R, G, B, BL
• Port 1
Port 70
4.5 to 5.5
4.5 to 5.5
4.5 to 5.5
0.4
0.4
80
R. G. B : digital mode
= 1mA
V
(4)
I
OL
OL
Pull-up MOS
Tr. resistance
Bus terminal
short circuit
resistance
Rpu
• Ports 0, 1, 3, 7
V
= 0.9V
OH DD
13
38
kΩ
RBS
• P10 to P12
• P11 to P13
4.5 to 5.5
130
300
Ω
(SCL0 to SCL1,
SDA0 to SDA1)
Hysteresis
VHIS
CP
• Ports 1, 3, 7
Output disable
voltage
•
•
4.5 to 5.5
4.5 to 5.5
0.1V
V
RES
DD
10
,
HS VS
Pin
All pins
• f = 1MHz
capacitance
• Every other terminals are
pF
connected to V
• Ta = 25°C
.
SS
No.7936-10/17
LC863548B/40B/32B/28B/24B/20B/16B
IIC Input/Output Conditions / Ta = -10°C to +70°C, V = 0V
SS
Standard
High speed
Parameter
Symbol
unit
min
0
max
min
0
max
SCL Frequency
fSCL
tBUF
100
400
kHz
µs
µs
µs
µs
µs
µs
ns
ns
ns
µs
BUS free time between stop to start
HOLD time of start, restart condition
L time of SCL
4.7
4.0
4.7
4.0
4.7
0
-
1.3
0.6
1.3
0.6
0.6
0
-
tHD ; STA
tLOW
-
-
-
-
H time of SCL
tHIGH
-
-
-
Set-up time of restart condition
HOLD time of SDA
tSU ; STA
tHD ; DAT
tSU ; DAT
tR
-
-
-
0.9
-
Set-up time of SDA
250
-
100
Rising time of SDA, SCL
Falling time of SDA, SCL
Set-up time of stop condition
1000
300
-
20 + 0.1Cb
20 + 0.1Cb
0.6
300
300
-
tF
-
tSU ; STO
4.0
Refer to figure 7
Note : Cb : Total capacitance of all BUS (unit : pF)
Pulse Input Conditions / Ta = -10°C to +70°C, V = 0V
SS
Limits
Parameter
Symbol
Pins
Conditions
V
[V]
min
typ
max
unit
DD
High/low level pulse
width
tPIH(1)
•INT0, INT1
•INT2/T0IN
INT3/T0IN
• Interrupt acceptable
• Timer 0-countable
• Interrupt acceptable
• Timer 0-countable
4.5 to 5.5
1
2
tPIL(1)
tPIH(2)
tPIL(2)
(1 tCYC is selected for
noise rejection clock.)
INT3/T0IN
(16 tCYC is selected for
noise rejection clock.)
INT3/T0IN
(64 tCYC is selected for
noise rejection clock.)
RES
4.5 to 5.5
tCYC
tPIH(3)
tPIL(3)
• Interrupt acceptable
• Timer 0-countable
4.5 to 5.5
32
tPIH(4)
tPIL(4)
• Interrupt acceptable
• Timer 0-countable
4.5 to 5.5
4.5 to 5.5
128
200
tPIL(5)
Reset acceptable
tPIH(6)
tPIL(6)
,
• Display position
controllable (Note)
HS VS
µs
• The active edge of
HS
must be apart
4.5 to 5.5
4.5 to 5.5
3
and
VS
at least 1 tCYC.
• Refer to figure 4.
Refer to figure 4.
Rising/falling time
tTHL
tTLH
HS
500
ns
AD Converter Characteristics / Ta = -10°C to +70°C, V = 0V
SS
Limits
6
Parameter
Symbol
Pins
Conditions
V
[V]
min
typ
max
unit
bit
DD
Resolution
N
Absolute precision
Conversion time
ET
(Note)
±1
LSB
tCAD
Vref selection
to conversion
finish
1-bit conversion time = 2 × tCYC
1.69
µs
4.5 to 5.5
Analog input
voltage range
Analog port
input current
VAIN
AN4 to AN7
V
V
V
SS
DD
IAINH
IAINL
VAIN = V
DD
VAIN = V
SS
1
µA
-1
Note : Absolute precision does not include quantizing error (1/2LSB).
No.7936-11/17
LC863548B/40B/32B/28B/24B/20B/16B
Analog Mode RGB Characteristics / Ta = -10°C to +70°C, V = 0V
SS
Limits
Parameter
Symbol
Pins
Conditions
V
[V]
min
0.45
typ
max
0.55
unit
V
DD
Analog output
voltage
R. G. B
Low level output
Intensity output
Hi level output
70% 10pf load
0.5
1.0
1.5
Analog output mode
0.90
1.35
1.10
1.65
50
5.0
Time setting
R. G. B
ns
Sample Current Dissipation Characteristics / Ta = -10°C to +70°C, V = 0V
SS
The sample current dissipation characteristics are the measurement result of SANYO provided evaluation board
when the recommended circuit parameters shown in the sample oscillation circuit characteristics are used externally.
The currents through the output transistors and the pull-up MOS transistors are ignored.
Limits
Parameter
Symbol
Pins
Conditions
V
[V]
min
typ
max
unit
DD
Current dissipation
during basic
operation
IDDOP(1)
V
• FmX’tal = 32.768kHz
X’tal oscillation
DD
DD
DD
• System clock : VCO
• VCO for OSD operating
• OSD is Digital mode
• Internal RC oscillation stops
• FmX’tal = 32.768kHz
X’tal oscillation
• System clock : VCO
• VCO for OSD operating
• OSD is Analog mode
• Internal RC oscillation stops
• FmX’tal = 32.768kHz
X’tal oscillation
4.5 to 5.5
4.5 to 5.5
13
21
25
37
(Note 3)
mA
IDDOP(2)
IDDOP(3)
V
V
• System clock : X’tal
(Instruction cycle time : 366.2µs)
• VCO for system VCO for OSD,
internal RC oscillation stop
• Data slicer, AD converters stop
• HALT mode
• FmX’tal = 32.768kHz
X’tal oscillation
• System clock : VCO
• VCO for OSD stops
• Internal RC oscillation stops
• HALT mode
• FmX’tal = 32.768kHz
X’tal oscillation
• VCO for system stops
• VCO for OSD stops
• System clock : Internal RC
• HALT mode
4.5 to 5.5
50
300
µA
Current dissipation
in HALT mode
(Note 3)
IDDHALT(1)
IDDHALT(2)
IDDHALT(3)
V
V
V
DD
DD
DD
4.5 to 5.5
4.5 to 5.5
4
10
mA
300
1000
µA
• FmX’tal = 32.768kHz
X’tal oscillation
• VCO for system stops
• VCO for OSD stops
• System clock : X’tal
(Instruction cycle time : 366.2µs)
• HOLD mode
4.5 to 5.5
4.5 to 5.5
35
200
20
Current dissipation
in HOLD mode
(Note 3)
IDDHOLD
V
DD
• All oscillation stops.
0.05
µA
Note 3 : The currents through the output transistors and the pull-up MOS transistors are ignored.
No.7936-12/17
LC863548B/40B/32B/28B/24B/20B/16B
Recommended Oscillation Circuit and Sample Characteristics
The sample oscillation circuit characteristics in the table below is based on the following conditions :
• Recommended circuit parameters are verified by an oscillator manufacturer using a SANYO provided oscillation
evaluation board.
• Sample characteristics are the result of the evaluation with the recommended circuit parameters connected
externally.
Recommended oscillation circuit and sample characteristics (Ta = -10 to +70°C)
Oscillation
stabilizing time
Recommended circuit parameters
Operating supply
voltage range
Frequency
Manufacturer
Oscillator
Notes
C1
C2
Rf
Rd
typ
max
32.768kHz
Seiko Epson
C-002RX
18pF
18pF
OPEN
390kΩ
4.5 to 5.5V
1.00S
1.50S
Notes : The oscillation stabilizing time period is the time until the VCO oscillation for the internal system becomes
stable after the following conditions. (Refer to Figure 2.)
1. The V
becomes higher than the minimum operating voltage after the power is supplied.
DD
2. The HOLD mode is released.
The sample oscillation circuit characteristics may differ applications.
For further assistance, please contact with oscillator manufacturer with the following notes in your mind.
• Since the oscillation frequency precision is affected by wiring capacity of the application board, etc., adjust the
oscillation frequency on the production board.
• The above oscillation frequency and the operating supply voltage range are based on the operating temperature of
-10°C to +70°C. For the use with the temperature outside of the range herein, or in the applications requiring high
reliability such as car products, please consult with oscillator manufacturer.
• When using the oscillator which is not shown in the sample oscillation circuit characteristics, please consult with
SANYO sales personnel.
Since the oscillation circuit characteristics are affected by the noise or wiring capacity because the circuit is designed
with low gain in order to reduce the power dissipation, refer to the following notices.
• The distance between the clock I/O terminal (XT1 terminal XT2 terminal) and external parts should be as short as
possible.
• The capacitors’ V should be allocated close to the microcontroller’s GND terminal and be away from other GND.
SS
• The signal lines with rapid state changes or with large current should be allocated away from the oscillation circuit.
XT1
XT2
Rf
Rd
C1
C2
X’tal
Figure 1 Recommended oscillation circuit
No.7936-13/17
LC863548B/40B/32B/28B/24B/20B/16B
V
V
DD
DD
Power supply
limit
0V
Reset time
RES
Internal RC
resonator
oscillation
XT1, XT2
VCO for system
Operation mode
tmsVCO
Reset
stable
Unfixed
Instruction execution mode
<Reset time and oscillation stabilizing time>
HOLD release
Valid
Internal RC
resonator
oscillation
XT1, XT2
VCO for system
Operation mode
tmsVCO
stable
HOLD
Instruction execution mode
<HOLD release signal and oscillation stabilizing time>
Figure 2 Oscillation stabilizing time
No.7936-14/17
LC863548B/40B/32B/28B/24B/20B/16B
tPIL (1) to (5)
tPIH (1) to (4)
Figure 3 Pulse input timing condition - 1
tPIL(6)
HS
0.75V
DD
0.25V
DD
tTLH
VS
tPIL(6)
more than ±1tCYC
Figure 4 Pulse input timing condition - 2
LC863548A
10kΩ
HS
HS
C536
Figure 5 Recommended Interface circuit
No.7936-15/17
LC863548B/40B/32B/28B/24B/20B/16B
100Ω
FILT
+
-
2.2µF
33000pF
1MΩ
Figure 6 FILT recommended circuit
Note : Place FILT parts on board as close to the microcontroller as possible.
S
Sr
P
P
SDA
SCL
tBUF
tF
tsp
tR
tHD ; STA
tHD ; STA
tLOW
tHIGH
tHD ; DAT
tSU ; DAT
tSU ; STA
tSU ; STO
S : start condition
P : stop condition
Sr : restart condition
tsp : Spike suppression
Figure 7 IIC timing
Standard mode : not exist
High speed mode : less than 50ns
I≈1mA
↓
I ↓
I ↓
PAD
R≈500Ω
Figure 8 R. G. B. analog output equivalent circuit
No.7936-16/17
LC863548B/40B/32B/28B/24B/20B/16B
No.7936-17/17
PS
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