LC87F7LC8A(100TQFP) [ONSEMI]
Microcontroller, 8-Bit, FLASH, 12MHz, CMOS, PQFP100,;型号: | LC87F7LC8A(100TQFP) |
厂家: | ONSEMI |
描述: | Microcontroller, 8-Bit, FLASH, 12MHz, CMOS, PQFP100, 微控制器 |
文件: | 总25页 (文件大小:190K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Ordering number : ENA0835
CMOS IC
FROM 128K byte, RAM 4096 byte on-chip
LC87F7LC8A
8-bit 1-chip Microcontroller
Overview
The SANYO LC87F7LC8A is an 8-bit microcomputer that, centered around a CPU running at a minimum bus cycle
time of 83.3ns, integrates on a single chip a number of hardware features such as 128K-byte flash ROM (onboard
programmable), 4096-byte RAM, an on-chip debugger, a LCD controller/driver, sophisticated 16-bit timer/counter
(may be divided into 8-bit timers), a 16-bit timer/counter (may be divided into 8-bit timers/counters or 8-bit PWMs),
four 8-bit timers with a prescaler, a 16-bit timer with a prescaler (may be divided into 8-bit timers), a base timer serving
as a time-of-day clock, a day and time counter, a synchronous SIO interface (with automatic block transmission/
reception capabilities), an asynchronous/synchronous SIO interface, a UART interface (full duplex), an 8-bit 15-channel
AD converter, two 12-bit PWM channels, a high-speed clock counter, a system clock frequency divider, a small signal
detector, ROM correction function, remote control receive function, and a 28-source 10-vector interrupt feature.
Features
Flash ROM
• Capable of on-board-programming with wide range, 3.0 to 5.5V, of voltage source
• Block-erasable in 128byte units
• 131072 × 8 bits (LC87F7LC8A)
RAM
• 4096 × 9 bits (LC87F7LC8A)
Minimum Bus Cycle Time
• 83.3ns (12MHz)
• 125ns (8MHz)
• 250ns (4MHz)
V
DD
V
DD
V
DD
=3.0 to 5.5V
=2.5 to 3.0V
=2.2 to 2.5V
Note: The bus cycle time here refers to the ROM read speed.
* This product is licensed from Silicon Storage Technology, Inc. (USA), and manufactured and sold by
SANYO Semiconductor Co., Ltd.
Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to
"standard application", intended for the use as general electronics equipment (home appliances, AV equipment,
communication device, office equipment, industrial equipment etc.). The products mentioned herein shall not be
intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace
instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety
equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case
of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee
thereof. If you should intend to use our products for applications outside the standard applications of our
customer who is considering such use and/or outside the scope of our intended standard applications, please
consult with us prior to the intended use. If there is no consultation or inquiry before the intended use, our
customer shall be solely responsible for the use.
Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate
the performance, characteristics, and functions of the described products in the independent state, and are not
guarantees of the performance, characteristics, and functions of the described products as mounted in the
customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent
device, the customer should always evaluate and test devices mounted in the customer
's products or
equipment.
Ver.0.92
82907HKIM 20070330-S00001 No.A0835-1/25
LC87F7LC8A
Minimum Instruction Cycle Time (tCYC)
• 250ns (12MHz)
• 375ns (8MHz)
• 750ns (4MHz)
V
V
V
=3.0 to 5.5V
=2.5 to 3.0V
=2.2 to 2.5V
DD
DD
DD
Ports
• Normal withstand voltage I/O ports
Ports whose I/O direction can be designated in 1 bit units 27(P1n, P30 to P35, P70 to P73, P8n, XT2)
Ports whose I/O direction can be designated in 4 bit units 8(P0n)
• Normal withstand voltage input port
• LCD ports
1(XT1)
Segment output
Common output
Bias terminals for LCD driver
Other functions
48(S00 to S47)
4(COM0 to COM3)
3(V1 to V3)
Input/output ports
Input ports
48(PAn, PBn, PCn, PDn, PEn, PFn)
7(PLn)
• Dedicated oscillator ports
• Reset pin
2(CF1, CF2)
1(
RES
)
• Power supply
6(V 1 to V 3,V 1 to V 3)
SS SS DD DD
LCD Controller
1) Seven display modes are available (static, 1/2, 1/3, 1/4 duty ×1/2, 1/3 bias)
2) Segment output and common output can be switched to general purpose input/output ports
Small Signal Detection (MIC signals etc)
1) Counts pulses with the level which is greater than a preset value
2) 2-bit counter
Timers
• Timer 0: 16-bit timer/counter with two capture registers.
Mode 0: 8-bit timer with an 8-bit programmable prescaler (with two 8-bit capture registers) × 2 channels
Mode 1: 8-bit timer with an 8-bit programmable prescaler (with two 8-bit capture registers) + 8-bit counter
(with two 8-bit capture registers)
Mode 2: 16-bit timer with an 8-bit programmable prescaler (with two 16-bit capture registers)
Mode 3: 16-bit counter (with two 16-bit capture registers)
• Timer1: 16-bit timer/counter that supports PWM/toggle outputs
Mode 0: 8-bit timer with an 8-bit prescaler (with toggle outputs) + 8-bit timer/counter with an 8-bit prescaler
(with toggle outputs)
Mode 1: 8-bit PWM with an 8-bit prescaler × 2 channels
Mode 2: 16-bit timer/counter with an 8-bit prescaler (with toggle outputs)
(toggle outputs also possible from the lower-order 8 bits)
Mode 3: 16-bit timer with an 8-bit prescaler (with toggle outputs) (The lower-order 8 bits can be used as PWM.)
• Timer4: 8-bit timer with 6-bit prescaler
• Timer5: 8-bit timer with 6-bit prescaler
• Timer6: 8-bit timer with 6-bit prescaler (with toggle output)
• Timer7: 8-bit timer with 6-bit prescaler (with toggle output)
• Timer8: 16-bit timer
Mode 0: 8-bit timer with an 8-bit prescaler ×2 channels (with toggle output)
Mode 1: 16-bit timer with an 8-bit prescaler (with toggle output)
• Base Timer
1) The clock is selectable from the subclock (32.768kHz crystal oscillation), system clock, and timer 0 prescaler
output.
2) Interrupts programmable in 5 different time schemes
• Day and time counter
1) Using with a base timer, it can be used as 65000 day + minute + second counter.
No.A0835-2/25
LC87F7LC8A
High-speed Clock Counter
1) Can count clocks with a maximum clock rate of 20MHz (at a main clock of 10MHz).
2) Can generate output real-time.
SIO
• SIO0: 8-bit synchronous serial interface
1) LSB first/MSB first is selectable
2) Built-in 8-bit baudrate generator (maximum transfer clock cycle=4/3tCYC)
3) Automatic continuous data transmission (1 to 256 bits specifiable in 1 bit units, suspension and resumption of
data transmission possible in 1 byte units)
• SIO1: 8-bit asynchronous/synchronous serial interface
Mode 0: Synchronous 8-bit serial I/O (2- or 3-wire configuration, 2 to 512 tCYC transfer clocks)
Mode 1: Asynchronous serial I/O (half-duplex, 8 data bits, 1 stop bit, 8 to 2048 tCYC baudrates)
Mode 2: Bus mode 1 (start bit, 8 data bits, 2 to 512 tCYC transfer clocks)
Mode 3: Bus mode 2 (start detect, 8 data bits, stop detect)
UART
1) Full duplex
2) 7/8/9 bit data bits selectable
3) 1 stop bit (2-bit in continuous data transmission)
4) Built-in baudrate generator
AD Converter
• 8 bits × 15 channels
PWM
• Multi frequency 12-bit PWM × 2 channels
Remote Control Receiver Circuit
1) Noise rejection function (Units of noise rejection filter: about 120μs, when selecting a 32.768kHz
crystal oscillator as a clock)
2) Supporting reception formats with a guide-pulse of half-clock/clock/none.
3) Determines a end of reception by detecting a no-signal periods (No carrier).
(Supports same reception format with a different bit length.)
4) X’tal HOLD mode release function
Watchdog Timer
1) External RC watchdog timer
2) Interrupt and reset signals selectable
Clock Output Function
1) Able to output selected oscillation clock 1/1, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64 as system clock.
2) Able to output oscillation clock of sub clock.
No.A0835-3/25
LC87F7LC8A
Interrupts
• 28 sources, 10 vector addresses
1) Provides three levels (low (L), high (H), and highest (X)) of multiplex interrupt control. Any interrupt requests
of the level equal to or lower than the current interrupt are not accepted.
2) When interrupt requests to two or more vector addresses occur at the same time, the interrupt of the highest
level takes precedence over the other interrupts. For interrupts of the same level, the interrupt into the smallest
vector address takes precedence.
No.
1
Vector Address
00003H
Level
X or L
X or L
H or L
H or L
H or L
H or L
H or L
H or L
H or L
H or L
Interrupt Source
INT0
INT1
2
0000BH
00013H
3
INT2/T0L/INT4/remote control receiver
INT3/base timer/INT5
T0H/INT6
4
0001BH
00023H
5
6
0002BH
00033H
T1L/T1H/INT7
7
SIO0/UART1 receive/T8L/T8H
SIO1/UART1 transmit
ADC/MIC/T6/T7/PWM4,5
Port 0/T4/T5
8
0003BH
00043H
9
10
0004BH
• Priority levels X > H > L
• Of interrupts of the same level, the one with the smallest vector address takes precedence.
• IFLG (List of interrupt source flag function)
1) Shows a list of interrupt source flags that caused a branching to a particular vector address (shown in the
diagram above).
Subroutine Stack Levels
• 2048 levels (the stack is allocated in RAM)
High-speed Multiplication/Division Instructions
• 16-bits × 8-bits
• 24-bits × 16-bits
• 16-bits ÷ 8-bits
• 24-bits ÷ 16-bits
(5 tCYC execution time)
(12 tCYC execution time)
(8 tCYC execution time)
(12 tCYC execution time)
Oscillation Circuits
• RC oscillation circuit (internal): For system clock
• CF oscillation circuit:
For system clock, with internal Rf, external Rd
• Crystal oscillation circuit:
For low-speed system clock, with internal Rf, external Rd
• Frequency variable RC oscillation circuit (internal): For system clock
1) Adjustable in ±4% (typ.) step from a selected center frequency.
2) Measures oscillation clock using a input signal from XT1 as a reference.
System Clock Divider Function
• Can run on low current.
• The minimum instruction cycle selectable from 300ns, 600ns, 1.2μs, 2.4μs, 4.8μs, 9.6μs, 19.2μs, 38.4μs, and
76.8μs (at a main clock rate of 10MHz).
No.A0835-4/25
LC87F7LC8A
Standby Function
• HALT mode: Halts instruction execution while allowing the peripheral circuits to continue operation.
(Some parts of the serial transfer function stops operation.)
1) Oscillation is not halted automatically.
2) Canceled by a system reset or occurrence of an interrupt
• HOLD mode: Suspends instruction execution and the operation of the peripheral circuits.
1) The CF, RC, X’tal, and frequency variable RC oscillators automatically stop operation.
2) There are three ways of resetting the HOLD mode.
(1) Setting the reset pin to the low level
(2) Setting at least one of the INT0, INT1, INT2, INT4, and INT5 pins to the specified level
(3) Having an interrupt source established at port 0
• X'tal HOLD mode: Suspends instruction execution and the operation of the peripheral circuits except the base timer
and the remote control receiver circuit.
1) The CF, RC, and frequency variable RC oscillators automatically stop operation.
2) The state of crystal oscillation established when the X'tal HOLD mode is entered is retained.
3) There are five ways of resetting the X'tal HOLD mode.
(1) Setting the reset pin to the low level
(2) Setting at least one of the INT0, INT1, INT2, INT4, and INT5 pins to the specified level
(3) Having an interrupt source established at port 0
(4) Having an interrupt source established in the base timer circuit
(5) Having an interrupt source established in the remote control receiver circuit
ROM Correction Function
• Executes the correction program on detection of a match with the program counter value.
• Correction program area size: 128 bytes
On-chip Debugger
• Supports software debugging with the IC mounted on the target board.
Package Form
• QIP100E(14×20):
• ΤQFP100(14×14):
Lead-free type
Lead-free type
Development Tools
• On-chip Debugger: TCB87-TypeA or TCB87-TypeB + LC87F7LC8A
Flash ROM Programming boards
Package
Programming Boards
W87FQ100
QIP100E(14×20)
TQFP100(14×14)
W87FSQ100
Flash ROM Programmer
Maker
Model
Supported version (Note)
After 02.54
Device
AF9708/AF9709/AF9709B
(including product of
Ando Electric Co., Ltd.)
AF9723 (Main body)
(including product of
Ando Electric Co., Ltd.)
AF9833 (Unit)
Flash Support Group, Inc.
(Single)
LC87F75C8A
After 02.03D
After 01.82G
Flash Support Group, Inc.
(Gang)
LC87F5JC8A
LC87F7LC8A
(including product of
Ando Electric Co., Ltd.)
Application Version
1.03
SANYO
SKK (SANYO FWS)
Chip Data Version
2.05
Note: Please check the latest version.
No.A0835-5/25
LC87F7LC8A
Package Dimensions
unit : mm (typ)
3151A
23.2
20.0
80
51
81
50
31
100
1
30
0.65
0.3
0.15
(0.58)
SANYO : QIP100E(14X20)
Pin Assignment
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
S20/PC4
S19/PC3
S18/PC2
S17/PC1
S16/PC0
S15/PB7
S14/PB6
S13/PB5
S12/PB4
S11/PB3
S10/PB2
S9/PB1
S8/PB0
S7/PA7
S6/PA6
S5/PA5
S4/PA4
S3/PA3
S2/PA2
S1/PA1
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
V2/PL5/AN13/DBGP1
V1/PL4/AN12/DBGP0
COM0/PL0
COM1/PL1
COM2/PL2
COM3/PL3
P30/INT4/T1IN/INT6/T0LCP1/PWM4
P31/INT4/T1IN/PWM5
V
V
3
3
SS
DD
LC87F7LC8A
P32/INT4/T1IN UTX1
/
P33/INT4/T1IN/URX1
P34/INT5/T1IN/INT7/T0HCP1
P35/INT5/T1IN
P00
P01
P02/T8LO
P03/T8HO
P04
P05/CKO
Top view
SANYO: QIP100E(14×20) “Lead-free Type”
No.A0835-6/25
LC87F7LC8A
Package Dimensions
unit : mm (typ)
3274
16.0
14.0
75
51
50
76
100
26
1
25
0.125
0.5
0.2
(1.0)
SANYO : TQFP100(14X14)
Pin Assignment
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
S47/PF7
S23/PC7
S22/PC6
S21/PC5
S20/PC4
S19/PC3
S18/PC2
S17/PC1
S16/PC0
S15/PB7
S14/PB6
S13/PB5
S12/PB4
S11/PB3
S10/PB2
S9/PB1
S8/PB0
S7/PA7
S6/PA6
S5/PA5
S4/PA4
S3/PA3
S2/PA2
S1/PA1
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
V3/PL6/AN14/DBGP2
V2/PL5/AN13/DBGP1
V1/PL4/AN12/DBGP0
COM0/PL0
COM1/PL1
COM2/PL2
COM3/PL3
P30/INT4/T1IN/INT6/T0LCP1/PWM4
P31/INT4/T1IN/PWM5
V
V
3
3
SS
DD
LC87F7LC8A
P32/INT4/T1IN/UTX1
P33/INT4/T1IN/URX1
P34/INT5/T1IN/INT7/T0HCP1
P35/INT5/T1IN
P00
P01
P02/T8LO
P03/T8HO
P04
P05/CKO
P06/T6O
P07/T7O
P10/SO0
S0/PA0
P73/INT3/T0IN/RMIN
Top view
SANYO: TQFP100(14×14) “Lead-free Type”
No.A0835-7/25
LC87F7LC8A
System Block Diagram
Interrupt control
IR
PLA
ROM correct
Standby control
Flash ROM
CF
RC
VMRC
PC
X’tal
SIO0
SIO1
Bus interface
Port 0
ACC
B register
Timer 0
(High speed clockcounter)
C register
Port 1
Port 3
Timer 1
ALU
Port 7
Port 8
Base timer
PSW
RAR
LCD controller
INT0 to 7
Noise rejection filter
ADC
Small signal
detector
RAM
Timer 4
Timer 5
Timer 6
Stack pointer
Watchdog timer
On-chip debugger
Timer 7
Timer 8
UART1
PWM4/5
Remote control
receiver circuit
Day and time
counter
No.A0835-8/25
LC87F7LC8A
Pin Description
Pin Name
I/O
Description
Option
No
V
V
V
V
V
V
1
-
- power supply pin
+ power supply pin
SS
2
3
1
SS
SS
-
No
DD
DD
DD
2
3
Port 0
I/O
• 8-bit I/O port
Yes
• I/O specifiable in 4-bit units
P00 to P07
• Pull-up resistors can be turned on and off in 4-bit units.
• Input for HOLD release
• Input for port 0 interrupt
• Shared pins
P02: Timer 8L toggle output
P03: Timer 8H toggle output
P05: Clock output (system clock/can selected from sub clock)
P06: Timer 6 toggle output
P07: Timer 7 toggle output
Port 1
I/O
• 8-bit I/O port
Yes
• I/O specifiable in 1-bit units
P10 to P17
• Pull-up resistors can be turned on and off in 1-bit units.
• Shared pins
P10: SIO0 data output
P11: SIO0 data input/bus I/O
P12: SIO0 clock I/O
P13: SIO1 data output
P14: SIO1 data input/bus I/O
P15: SIO1 clock I/O
P16: Timer 1PWML output
P17: Timer 1PWMH output/beeper output
• 6-bit I/O port
Port 3
I/O
Yes
• I/O specifiable in 1-bit units
P30 to P35
• Pull-up resistors can be turned on and off in 1-bit units.
• Shared pins
P30 to P33: INT4 input/HOLD release input/timer 1 event input/timer 0L capture input/
timer 0H capture input
P34 to P35: INT5 input/HOLD release input/timer 1 event input/timer 0L capture input/
timer 0H capture input
P30: PWM4 output/INT6 input/timer 0L capture 1 input
P31: PWM5 output
P32: UART1 transmit
P33: UART1 receive
P34: INT7 input/timer 0H capture 1 input
Interrupt acknowledge type
Rising &
Rising
Falling
H level
L level
Falling
enable
enable
enable
enable
INT4
INT5
INT6
INT7
enable
enable
enable
enable
enable
enable
enable
enable
disable
disable
disable
disable
disable
disable
disable
disable
Continued on next page.
No.A0835-9/25
LC87F7LC8A
Continued from preceding page.
Pin Name
Port 7
I/O
I/O
Description
Option
No
• 4-bit I/O port
• I/O specifiable in 1-bit units
P70 to P73
• Pull-up resistors can be turned on and off in 1-bit units.
• Shared pins
P70: INT0 input/HOLD release input/timer 0L capture input/watchdog timer output
P71: INT1 input/HOLD release input/timer 0H capture input
P72: INT2 input/HOLD release input/timer 0 event input/timer 0L capture input/
high speed clock counter input
P73: INT3 input (with noise filter)/timer 0 event input/timer 0H capture input/
remote control receiver input
AD converter input ports: AN8 (P70), AN9 (P71)
Interrupt acknowledge type
Rising &
Rising
Falling
H level
L level
Falling
disable
disable
enable
enable
INT0
INT1
INT2
INT3
enable
enable
enable
enable
enable
enable
enable
enable
enable
enable
disable
disable
enable
enable
disable
disable
Port 8
I/O
• 8-bit I/O port
No
• I/O specifiable in 1-bit units
• Shared pins
P80 to P87
AD converter input ports: AN0 (P80) to AN7 (P87)
Small signal detector input port: MICIN (P87)
• Segment output for LCD
S0/PA0 to
S7/PA7
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
No
No
No
No
No
No
No
No
• Can be used as general-purpose I/O port (PA)
• Segment output for LCD
S8/PB0 to
S15/PB7
• Can be used as general-purpose I/O port (PB)
• Segment output for LCD
S16/PC0 to
S23/PC7
• Can be used as general-purpose I/O port (PC)
• Segment output for LCD
S24/PD0 to
S31/PD7
• Can be used as general-purpose I/O port (PD)
• Segment output for LCD
S32/PE0 to
S39/PE7
• Can be used as general-purpose I/O port (PE)
• Segment output for LCD
S40/PF0 to
S47/PF7
• Can be used as general-purpose I/O port (PF)
• Common output for LCD
COM0/PL0 to
COM3/PL3
V1/PL4 to
V3/PL6
• Can be used as general-purpose input port (PL)
• LCD output bias power supply
• Can be used as general-purpose input port (PL)
• Shared pins
AD converter input ports: AN12 (V1) to AN14 (V3)
On-chip debugger pins: DBGP0 (V1) to DBGP2 (V3)
RES
XT1
Input
Input
No
No
Reset pin
• 32.768kHz crystal oscillator input pin
• Shared pins
General-purpose input port
Must be connected to V 1 if not to be used.
DD
AD converter input port: AN10
• 32.768kHz crystal oscillator output pin
• Shared pins
XT2
I/O
No
General-purpose I/O port
Must be set for oscillation and kept open if not to be used.
AD converter input port: AN11
Ceramic resonator input pin
CF1
CF2
Input
No
No
Output
Ceramic resonator output pin
No.A0835-10/25
LC87F7LC8A
Port Output Types
The table below lists the types of port outputs and the presence/absence of a pull-up resistor.
Data can be read into any input port even if it is in the output mode
Option Selected
Port Name
Option Type
Output Type
Pull-up Resistor
in Units of
each bit
P00 to P07
1
2
CMOS
Programmable (Note)
No
Nch-open drain
CMOS
P10 to P17
P30 to P35
each bit
each bit
1
Programmable
Programmable
Programmable
Programmable
Programmable
Programmable
No
2
Nch-open drain
CMOS
1
2
Nch-open drain
Nch-open drain
CMOS
P70
-
-
-
-
-
No
No
No
No
No
P71 to P73
P80 to P87
S0/PA0 to S47/PF7
Nch-open drain
CMOS
Programmable
COM0/PL0 to
COM3/PL3
Input only
No
No
No
V1/PL4 to V3/PL6
-
-
No
No
Input only
XT1
Input for 32.768kHz crystal
oscillator (Input only)
XT2
-
No
Output for 32.768kHz crystal oscillator
(Nch-open drain when in general-purpose
output mode)
No
Note 1: Programmable pull-up resistors for port 0 are controlled in 4 bit units (P00 to 03, P04 to 07).
*1: Connect the IC as shown below to minimize the noise input to the V 1 pin.
DD
Be sure to electrically short the V 1, V 2, and V 3 pins.
SS
SS
SS
LSI
V
1
DD
Power
supply
For backup *2
V
V
2
3
DD
DD
V
1 V
2
SS
V
3
SS
SS
*2: The internal memory is sustained by V 1. If none of V 2 and V 3 are backed up, the high level output at
DD DD DD
the ports are unstable in the HOLD backup mode, allowing through current to flow into the input buffer and thus
shortening the backup time.
Make sure that the port outputs are held at the low level in the HOLD backup mode.
No.A0835-11/25
LC87F7LC8A
Absolute Maximum Ratings at Ta = 25°C, V 1 = V 2 = V 3 = 0V
SS
SS
SS
Specification
typ max
Parameter
Symbol
Pin/Remarks
Conditions
V
[V]
min
-0.3
unit
DD
Maximum supply
voltage
V
max
V
1, V 2, V
3
V
V
1=V 2=V
DD
3
3
DD
DD
DD
DD
DD
DD
DD
+6.5
supply voltage for
LCD
VLCD
V1/PL4, V2/PL5,
V3/PL6
1=V 2=V
DD
DD
-0.3
-0.3
V
DD
V
Input voltage
V (1)
I
Port L
V
V
+0.3
DD
RES
XT1, CF1,
Input/output voltage
V
(1)
IO
Ports 0, 1, 3, 7, 8
Ports A, B, C, D, E, F
XT2
-0.3
+0.3
DD
Peak output
current
IOPH(1)
IOPH(2)
Ports 0, 1, 32 to 35
• CMOS output selected
• Current at each pin
• CMOS output selected
• Current at each pin
Current at each pin
-10
-20
Ports 30, 31
IOPH(3)
IOPH(4)
IOMH(1)
Ports 71 to 73
-5
-5
Ports A, B, C, D, E, F
Ports 0, 1, 32 to 35
Current at each pin
Mean output
current
• CMOS output selected
• Current at each pin
• CMOS output selected
• Current at each pin
Current at each pin
-7.5
-15
(Note 1-1)
IOMH(2)
Ports 30, 31
IOMH(3)
IOMH(4)
ΣIOAH(1)
ΣIOAH(2)
ΣIOAH(3)
ΣIOAH(4)
ΣIOAH(5)
ΣIOAH(6)
ΣIOAH(7)
IOPL(1)
Ports 71 to 73
-3
-3
Ports A, B, C, D, E, F
Ports 0, 1, 32 to 35
Ports 30, 31
Current at each pin
Total of all pins
Total of all pins
Total of all pins
Total of all pins
Total of all pins
Total of all pins
Total of all pins
Current at each pin
Current at each pin
Current at each pin
Total output
current
-25
-25
-45
-5
Ports 0, 1, 3
Ports 71 to 73
Ports A, B, C
-25
-25
-45
Ports D, E, F
Ports A, B, C, D, E, F
Ports 0, 1, 32 to 35
Ports 30, 31
mA
Peak output
current
20
30
IOPL(2)
IOPL(3)
Ports 7, 8
10
XT2
IOPL(4)
IOML(1)
IOML(2)
IOML(3)
Ports A, B, C, D, E, F
Current at each pin
Current at each pin
Current at each pin
Current at each pin
10
15
20
Mean output
current
Ports 0, 1, 32 to 35
Ports 30, 31
(Note 1-1)
Ports 7, 8
7.5
XT2
IOML(4)
ΣOAL(1)
ΣIOAL(2)
ΣIOAL(3)
ΣIOAL(4)
Ports A, B, C, D, E, F
Current at each pin
Total of all pins
Total of all pins
Total of all pins
Total of all pins
7.5
45
45
80
Total output
current
Ports 0,1,32 to 35
Ports 30, 31
Ports 0, 1, 3
Ports 7, 8
XT2
20
ΣIOAL(5)
ΣIOAL(6)
ΣIOAL(7)
Pd max
Ports A, B, C
Total of all pins
Total of all pins
Total of all pins
Ta=-20 to +70°C
Ta=-20 to +70°C
45
45
Ports D, E, F
Ports A, B, C, D, E, F
QIP100E(14×20)
TQFP100(14×14)
80
Power dissipation
461
331
mW
Operating ambient
temperature
Topr
Tstg
-20
-55
+70
°C
Storage ambient
temperature
+125
Note 1-1: The mean output current is a mean value measured over 100ms.
No.A0835-12/25
LC87F7LC8A
Allowable Operating Conditions at Ta = -20°C to +70°C, V 1 = V 2 = V 3 = 0V
SS
SS
SS
Specification
Parameter
Symbol
Pin/Remarks
1=V 2=V 3
DD
Conditions
V
[V]
min
typ
max
unit
DD
Operating
V
V
V
(1)
V
0.237μs≤tCYC≤200μs
0.356μs≤tCYC≤200μs
0.712μs≤tCYC≤200μs
3.0
5.5
5.5
5.5
DD
DD
DD
supply voltage
(Note 2-1)
(2)
2.5
2.2
DD
(3)
DD
Memory
VHD
V
1
RAM and register contents
sustained in HOLD mode.
DD
sustaining
supply voltage
High level input
voltage
2.0
5.5
V
V
(1)
Ports 0, 3, 8
Output disabled
IH
0.3V
V
V
DD
DD
Ports A, B, C, D, E, F
Port L
2.2 to 5.5
2.2 to 5.5
+0.7
(2)
Port 1
• Output disabled
• When INT1VTSL=0
(P71 only)
IH
Ports 71 to 73
P70 port input/
interrupt side
P71 interrupt side
0.3V
DD
DD
+0.7
V
V
V
V
V
(3)
(4)
(5)
(6)
• Output disabled
• When INT1VTSL=1
Output disabled
IH
IH
IH
IH
2.2 to 5.5
2.2 to 5.5
2.2 to 5.5
2.2 to 5.5
0.85V
V
V
DD
DD
DD
P87 small signal
input side
0.75V
0.9V
DD
V
P70 watchdog timer
side
Output disabled
V
V
DD
DD
RES
XT1, XT2, CF1,
DD
0.75V
DD
Low level input
voltage
(1)
Ports 0, 3, 8
Output disabled
0.15V
IL
DD
4.0 to 5.5
2.2 to 4.0
4.0 to 5.5
V
V
V
SS
SS
SS
Ports A, B, C, D, E, F
Port L
+0.4
0.2V
DD
V
(2)
Port 1
• Output disabled
• When INT1VTSL=0
(P71 only)
0.1V
IL
DD
Ports 71 to 73
P70 port input/
interrupt side
P71 interrupt side
+0.4
2.2 to 4.0
2.2 to 5.5
2.2 to 5.5
2.2 to 5.5
V
V
V
0.2V
SS
SS
SS
DD
V
V
V
V
(3)
(4)
(5)
(6)
• Output disabled
• When INT1VTSL=1
Output disabled
IL
IL
IL
IL
0.45V
DD
P87 small signal
input side
0.25V
0.8V
DD
DD
P70 watchdog timer
side
Output disabled
V
V
SS
-1.0
RES
XT1, XT2, CF1,
2.2 to 5.5
3.0 to 5.5
2.5 to 5.5
2.2 to 5.5
3.0 to 5.5
2.5 to 5.5
0.25V
DD
SS
Instruction cycle
time
tCYC
0.237
0.356
0.712
0.1
200
μs
200
200
12
(Note 2-2)
External system
clock frequency
FEXCF(1)
CF1
• CF2 pin open
• System clock frequency
division ratio=1/1
0.1
8
• External system clock
duty=50±5%
2.2 to 5.5
0.1
4
MHz
• CF2 pin open
3.0 to 5.5
2.5 to 5.5
2.2 to 5.5
0.2
0.2
0.2
24.4
16
8
• System clock frequency
division ratio=1/2
Note 2-1: V
DD
must be held greater than or equal to 3.0V in the flash ROM onboard programming mode.
Note 2-2: Relationship between tCYC and oscillation frequency is 3/FmCF at a division ratio of 1/1 and 6/FmCF at a
division ratio of 1/2.
Continued on next page.
No.A0835-13/25
LC87F7LC8A
Continued from preceding page.
Specification
typ max
Parameter
Symbol
Pin/Remarks
CF1, CF2
Conditions
V
[V]
min
unit
DD
Oscillation
FmCF(1)
• 12MHz ceramic oscillation
• See Fig. 1.
3.0 to 5.5
2.5 to 5.5
12
frequency range
(Note 2-3)
FmCF(2)
FmCF(3)
CF1, CF2
CF1, CF2
• 8MHz ceramic oscillation
• See Fig. 1.
8
• 4MHz ceramic oscillation
• See Fig. 1.
2.2 to 5.5
2.2 to 5.5
4
FmRC
Internal RC oscillation
0.3
1.0
2.0
FmVMRC(1)
• Frequency variable RC
source oscillation
• When
MHz
2.2 to 5.5
10
VMRAJ2 to 0=4,
VMFAJ2 to 0=0,
VMSL4M=0
FmVMRC(2)
• Frequency variable RC
source oscillation
• When
2.2 to 5.5
4
VMRAJ2 to 0=4,
VMFAJ2 to 0=0,
VMSL4M=1
FsX’tal
XT1, XT2
• 32.768kHz crystal oscillation
• See Fig. 2.
2.2 to 5.5
2.2 to 5.5
32.768
10
kHz
Frequency
variable RC
oscillation
usable range
Frequency
variable RC
oscillation
adjustment
range
OpVMRC(1)
OpVMRC(2)
When VMSL4M=0
8
12
When VMSL4M=1
MHz
2.2 to 5.5
2.2 to 5.5
2.2 to 5.5
3.5
4
24
4
4.5
VmADJ(1)
VmADJ(2)
Each step of VMRAJn
(Wide range)
8
1
64
8
%
Each step of VMFAJn
(Small range)
Note 2-3: See Tables 1 and 2 for the oscillation constants.
Electrical Characteristics at Ta = -20°C to +70°C, V 1 = V 2= V 3= 0V
SS
SS
SS
Specification
typ max
Parameter
Symbol
Pin/Remarks
Conditions
V
[V]
min
unit
DD
High level input
current
I
(1)
IH
Ports 0, 1, 3, 7, 8
• Output disabled
• Pull-up resistor off
• V =V (Including output Tr's
Ports A, B, C, D, E,
2.2 to 5.5
1
F
IN DD
off leakage current)
Port L
RES
I
I
(2)
IH
V
=V
2.2 to 5.5
2.2 to 5.5
1
1
IN DD
(3)
IH
XT1, XT2
• For input port specification
• V =V
IN DD
I
I
(4)
IH
CF1
V
=V
IN DD
2.2 to 5.5
4.5 to 5.5
2.2 to 4.5
15
15
10
(5)
IH
P87 small signal
input side
V =VBIS+0.5V
IN
4.2
8.5
(VBIS: Bias voltage)
1.5
5.5
μA
Low level input
current
I
(1)
IL
Ports 0, 1, 3, 7, 8
• Output disabled
Ports A, B, C, D, E,
• Pull-up resistor off
2.2 to 5.5
-1
F
• V =V
(Including output Tr's
off leakage current)
IN SS
Port L
RES
I
I
(2)
IL
V
=V
2.2 to 5.5
2.2 to 5.5
-1
-1
IN SS
(3)
IL
XT1, XT2
• For input port specification
• V =V
IN SS
I
I
(4)
IL
CF1
V
=V
IN SS
2.2 to 5.5
4.5 to 5.5
2.2 to 4.5
-15
-15
-10
(5)
IL
P87 small signal
input side
V
=VBIS-0.5V
IN
-8.5
-5.5
-4.2
-1.5
(VBIS: Bias voltage)
Continued on next page.
No.A0835-14/25
LC87F7LC8A
Continued from preceding page.
Specification
typ max
Parameter
Symbol
Pin/Remarks
Conditions
=-1mA
OH
V
[V]
min
unit
DD
High level output
voltage
V
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(10)
(11)
Ports 0, 1, 32 to 35
I
I
I
I
I
4.5 to 5.5
3.0 to 5.5
2.2 to 5.5
4.5 to 5.5
3.0 to 5.5
2.2 to 5.5
3.0 to 5.5
2.2 to 5.5
4.5 to 5.5
3.0 to 5.5
2.2 to 5.5
4.5 to 5.5
3.0 to 5.5
V
-1
OH
OH
OH
OH
OH
OH
OH
OH
OH
OH
OH
DD
V
V
V
V
V
V
V
V
V
V
V
V
V
=-0.4mA
=-0.2mA
=-10mA
=-1.6mA
=-1mA
V
V
V
V
V
V
V
-0.4
-0.4
-1.5
-0.4
-0.4
-0.4
-0.4
-1
OH
OH
OH
OH
DD
DD
DD
DD
DD
DD
Ports 30, 31
IOH
Ports 71 to 73
I
=-0.4mA
=-0.2mA
=-1mA
OH
I
OH
DD
V
Ports A, B, C, D, E,
F
I
OH
DD
I
=-0.4mA
V
V
-0.4
OH
DD
I
=-0.2mA
-0.4
OH
DD
Low level output
voltage
(1)
(2)
(3)
Ports 0, 1, 32 to 35
Ports 30, 31
I
I
I
=10mA
=1.6mA
=1mA
1.5
0.4
OL
OL
OL
OL
OL
OL
(PWM function
output mode)
Port 30, 31
2.2 to 5.5
0.4
V
V
V
V
V
V
V
V
(4)
(5)
(6)
(7)
(8)
(9)
(10)
I
I
I
I
I
I
I
=30mA
=5mA
4.5 to 5.5
3.0 to 5.5
2.2 to 5.5
3.0 to 5.5
2.2 to 5.5
3.0 to 5.5
2.2 to 5.5
1.5
0.4
0.4
0.4
0.4
0.4
0.4
OL
OL
OL
OL
OL
OL
OL
OL
OL
OL
OL
OL
OL
OL
(Port function
output mode)
=2.5mA
=1.6mA
=1mA
Ports 7, 8
XT2
Ports A, B, C, D, E,
F
=1.6mA
=1mA
LCD output voltage
regulation
VODLS
S0 to S47
• I =0mA
O
• VLCD, 2/3VLCD, 1/3VLCD
2.2 to 5.5
2.2 to 5.5
0
0
±0.2
±0.2
level output
• See Fig. 8.
VODLC
COM0 to COM3
• IO=0mA
• VLCD, 2/3VLCD, 1/2VLCD,
1/3VLCD level output
• See Fig. 8.
LCD bias resistor
RLCD(1)
RLCD(2)
Resistance per
one bias resister
Resistance per
one bias resister
1/2R mode
See Fig. 8.
2.2 to 5.5
2.2 to 5.5
60
See Fig. 8.
30
kΩ
Resistance of
Rpu(1)
Rpu(2)
Ports 0, 1, 3, 7
V
=0.9V
4.5 to 5.5
2.2 to 5.5
15
18
35
50
80
OH
DD
pull-up MOS Tr.
Ports A, B, C, D, E,
150
F
Hysterisis voltage
Pin capacitance
Input sensitivity
VHYS(1)
VHYS(2)
CP
Ports 1, 7
RES
2.2 to 5.5
2.2 to 5.5
0.1V
0.1V
DD
DD
V
P87 small signal
input side
All pins
• For pins other than that under test:
=V
V
IN SS
2.2 to 5.5
2.2 to 5.5
10
pF
• f=1MHz
• Ta=25°C
Vsen
P87 small signal
input side
0.12V
Vp-p
DD
No.A0835-15/25
LC87F7LC8A
Serial I/O Characteristics at Ta = -20°C to +70°C, V 1 = V 2= V 3= 0V
SS SS SS
1. SIO0 Serial I/O Characteristics (Note 4-1-1)
Specification
Parameter
Frequency
Symbol
tSCK(1)
Pin/Remarks
SCK0(P12)
Conditions
V
[V]
min
typ
max
unit
DD
See Fig. 6.
2
1
1
Low level
tSCKL(1)
tSCKH(1)
tSCKHA(1)
pulse width
High level
pulse width
2.2 to 5.5
tCYC
• Continuous data
transmission/reception mode
• See Fig. 6.
4
• (Note 4-1-2)
Frequency
tSCK(2)
SCK0(P12)
• CMOS output selected
• See Fig. 6.
4/3
Low level
tSCKL(2)
tSCKH(2)
tSCKHA(2)
1/2
1/2
pulse width
High level
pulse width
tSCK
tCYC
2.2 to 5.5
• Continuous data
transmission/reception mode
• CMOS output selected
• See Fig. 6.
tSCKH(2)
+(10/3)
tCYC
tSCKH(2)
+2tCYC
Data setup time
Data hold time
tsDI(1)
thDI(1)
tdD0(1)
tdD0(2)
tdD0(3)
SB0(P11),
SI0(P11)
• Must be specified with
respect to rising edge of
SIOCLK.
2.2 to 5.5
2.2 to 5.5
2.2 to 5.5
2.2 to 5.5
0.03
0.03
• See Fig. 6.
Output
SO0(P10),
SB0(P11)
• Continuous data
(1/3)tCYC
+0.05
delay time
transmission/reception mode
• (Note 4-1-3)
μs
• Synchronous 8-bit mode
• (Note 4-1-3)
1tCYC
+0.05
(Note 4-1-3)
(1/3)tCYC
+0.05
2.2 to 5.5
Note 4-1-1: These specifications are theoretical values. Add margin depending on its use.
Note 4-1-2: To use serial-clock-input in continuous trans/rec mode, a time from SI0RUN being set when serial clock is
"H" to the first negative edge of the serial clock must be longer than tSCKHA.
Note 4-1-3: Must be specified with respect to falling edge of SIOCLK. Must be specified as the time to the beginning of
output state change in open drain output mode. See Fig. 6.
No.A0835-16/25
LC87F7LC8A
2. SIO1 Serial I/O Characteristics (Note 4-2-1)
Specification
Parameter
Frequency
Symbol
tSCK(3)
Pin/Remarks
SCK1(P15)
Conditions
See Fig. 6.
V
[V]
min
typ
max
unit
DD
2
1
1
2
Low level
tSCKL(3)
tSCKH(3)
tSCK(4)
tSCKL(4)
tSCKH(4)
tsDI(2)
2.2 to 5.5
pulse width
High level
pulse width
Frequency
tCYC
SCK1(P15)
• CMOS output selected
• See Fig. 6.
Low level
pulse width
2.2 to 5.5
1/2
1/2
tSCK
High level
pulse width
Data setup time
SB1(P14),
SI1(P14)
• Must be specified with
respect to rising edge of
SIOCLK.
2.2 to 5.5
2.2 to 5.5
0.03
0.03
• See Fig. 6.
Data hold time
thDI(2)
tdD0(4)
Output delay time
SO1(P13),
SB1(P14)
• Must be specified with
respect to falling edge of
SIOCLK.
μs
• Must be specified as the
time to the beginning of
output state change in
open drain output mode.
• See Fig. 6.
(1/3)tCYC
+0.05
2.2 to 5.5
Note 4-2-1: These specifications are theoretical values. Add margin depending on its use.
No.A0835-17/25
LC87F7LC8A
Pulse Input Conditions at Ta = -20°C to +70°C, V 1 = V 2= V 3= 0V
SS
SS
SS
Specification
typ max
Parameter
Symbol
Pin/Remarks
Conditions
V
[V]
min
unit
DD
High/low
level pulse
width
tPIH(1)
tPIL(1)
INT0(P70),
• Interrupt source flag can be set.
• Event inputs for timer 0 or 1 are
enabled.
INT1(P71),
INT2(P72),
INT4(P30 to P33),
INT5(P34 to P35),
INT6(P30),
2.2 to 5.5
1
INT7(P34)
tPIH(2)
tPIL(2)
tPIH(3)
tPIL(3)
tPIH(4)
tPIL(4)
tPIH(5)
tPIL(5)
tPIH(6)
tPIL(6)
INT3(P73) when noise filter
time constant is 1/1
INT3(P73) when noise filter
time constant is 1/32
INT3(P73) when noise filter
time constant is 1/128
MICIN(P87)
• Interrupt source flag can be set.
tCYC
2.2 to 5.5
2.2 to 5.5
2.2 to 5.5
2.2 to 5.5
2
64
• Event inputs for timer 0 are enabled.
• Interrupt source flag can be set.
• Event inputs for timer 0 are enabled.
• Interrupt source flag can be set.
• Event inputs for timer 0 are enabled.
Condition that signal is accepted to
small signal detection counter.
256
1
RMIN(P73)
Condition that signal is accepted to
remote control receiver circuit.
RMCK
(Note
5-1)
2.2 to 5.5
2.2 to 5.5
4
RES
tPIL(7)
Resetting is enabled.
200
μs
Note 5-1: RMCK is an unit for the base clock (40tCYC/50tCYC/Sub-Clock) of remote control receiver circuit.
AD Converter Characteristics at Ta = -20°C to +70°C, V 1 = V 2= V 3= 0V
SS
SS
SS
Specification
Parameter
Symbol
Pin/Remarks
Conditions
V
[V]
min
typ max
unit
bit
DD
Resolution
N
AN0(P80) to
AN7(P87),
AN8(P70),
AN9(P71),
AN10(XT1),
AN11(XT2),
AN12(V1),
AN13(V2),
AN14(V3)
3.0 to 5.5
3.0 to 5.5
8
Absolute
accuracy
Conversion
time
ET
(Note 6-1)
±1.5
LSB
tCAD
AD conversion time=32×tCYC
15.20
100.80
(tCYC=
3.15µs)
100.80
(tCYC=
3.15µs)
100.80
(tCYC=
1.57µs)
100.80
(tCYC=
1.57µs)
(When ADCR2=0) (Note 6-2)
4.5 to 5.5
3.0 to 5.5
4.5 to 5.5
(tCYC=
0.475µs)
22.78
(tCYC=
0.712µs)
18.24
μs
AD conversion time=64×tCYC
(When ADCR2=1) (Note 6-2)
(tCYC=
0.285µs)
45.56
3.0 to 5.5
3.0 to 5.5
(tCYC=
0.712µs)
Analog input
voltage range
Analog port
input current
VAIN
V
V
V
SS
DD
IAINH
IAINL
VAIN=V
DD
3.0 to 5.5
3.0 to 5.5
1
μA
VAIN=V
SS
-1
Note 6-1: The quantization error (±1/2 LSB) is excluded from the absolute accuracy value.
Note 6-2: The conversion time refers to the interval from the time the instruction for starting the converter is issued till
the complete digital value corresponding to the analog input value is loaded in the required register.
No.A0835-18/25
LC87F7LC8A
Consumption Current Characteristics at Ta = -20°C to +70°C, V 1 = V 2= V 3= 0V
SS
SS
SS
Specification
Pin/
Parameter
Symbol
Conditions
Remarks
V
[V]
min
typ
max
unit
DD
Normal mode
consumption
current
IDDOP(1)
V
1
• FmCF=12MHz ceramic oscillation mode
• FmX’tal=32.768kHz crystal oscillation mode
• System clock set to 12MHz side
DD
=V
2
3
4.5 to 5.5
3.0 to 3.6
8.7
22
DD
DD
=V
(Note 7-1)
• Internal RC oscillation stopped.
IDDOP(2)
• Frequency variable RC oscillation stopped.
• 1/1 frequency division ratio
5
12.5
IDDOP(3)
IDDOP(4)
IDDOP(5)
IDDOP(6)
IDDOP(7)
IDDOP(8)
• FmCF=8MHz ceramic oscillation mode
• FmX’tal=32.768kHz crystal oscillation mode
• System clock set to 8MHz side
4.5 to 5.5
3.0 to 3.6
2.5 to 3.0
4.5 to 5.5
3.0 to 3.6
2.2 to 3.0
6.6
3.8
2.5
2.5
1.4
0.9
16.5
9.6
7.4
6.3
3.5
2.7
• Internal RC oscillation stopped.
• Frequency variable RC oscillation stopped.
• 1/1 frequency division ratio
• FmCF=4MHz ceramic oscillation mode
• FmX’tal=32.768kHz crystal oscillation mode
• System clock set to 4MHz side
• Internal RC oscillation stopped.
• Frequency variable RC oscillation stopped.
• 1/2 frequency division ratio
mA
IDDOP(9)
IDDOP(10)
IDDOP(11)
• FmCF=0Hz (oscillation stopped)
• FmX’tal=32.768kHz crystal oscillation mode
• System clock set to internal RC oscillation
• Frequency variable RC oscillation stopped.
• 1/2 frequency division ratio
4.5 to 5.5
3.0 to 3.6
2.2 to 3.0
0.75
0.4
3.1
1.7
0.28
1.35
IDDOP(12)
• FmCF=0Hz (oscillation stopped)
• FmX’tal=32.768 kHz crystal oscillation mode
• Internal RC oscillation stopped.
• System clock set to 10MHz wifh frequency
variable RC oscillation
4.5 to 5.5
3.0 to 3.6
8
20
12
IDDOP(13)
4.7
• 1/1 frequency division ratio
IDDOP(14)
IDDOP(15)
IDDOP(16)
IDDOP(17)
IDDOP(18)
IDDOP(19)
• FmCF=0Hz (oscillation stopped)
• FmX’tal=32.768kHz crystal oscillation mode
• Internal RC oscillation stopped.
• System clock set to 4MHz wifh frequency
variable RC oscillation
4.5 to 5.5
3.0 to 3.6
2.2 to 3.0
4.5 to 5.5
3.0 to 3.6
2.2 to 3.0
4.5
2.6
1.7
35
11.5
6.6
5
• 1/1 frequency division ratio
• FmCF=0Hz (oscillation stopped)
• FmX’tal=32.768kHz crystal oscillation mode
• System clock set to 32.768kHz side
• Internal RC oscillation stopped.
115
65
μA
18
• Frequency variable RC oscillation stopped.
• 1/2 frequency division ratio
12
46
Note 7-1: The consumption current value includes none of the currents that flow into the output Tr and internal pull-up
resistors.
Continued on next page.
No.A0835-19/25
LC87F7LC8A
Continued from preceding page.
Specification
typ max
Pin/
Parameter
Symbol
Conditions
Remarks
V
[V]
min
unit
DD
HALT mode
consumption
current
IDDHALT(1)
V
1
HALT mode
DD
=V
2
3
• FmCF=12MHz ceramic oscillation mode
• FmX’tal=32.768kHz crystal oscillation mode
• System clock set to 12MHz side
• Internal RC oscillation stopped.
• Frequency variable RC oscillation stopped.
• 1/1 frequency division ratio
DD
DD
4.5 to 5.5
3.0 to 3.6
3.6
8.2
4.6
=V
(Note 7-1)
IDDHALT(2)
2
IDDHALT(3)
IDDHALT(4)
HALT mode
4.5 to 5.5
3.0 to 3.6
2.5 to 3.0
4.5 to 5.5
3.0 to 3.6
2.2 to 3.0
2.6
1.4
1
5.9
3.3
• FmCF=8MHz ceramic oscillation mode
• FmX’tal=32.768kHz crystal oscillation mode
• System clock set to 8 MHz side
• Internal RC oscillation stopped.
• Frequency variable RC oscillation stopped.
• 1/1 frequency division ratio
IDDHALT(5)
IDDHALT(6)
IDDHALT(7)
IDDHALT(8)
2.5
HALT mode
1.15
0.6
0.4
2.65
1.5
• FmCF=4MHz ceramic oscillation mode
• FmX’tal=32.768kHz crystal oscillation mode
• System clock set to 4MHz side
• Internal RC oscillation stopped.
• Frequency variable RC oscillation stopped.
• 1/2 frequency division ratio
1.1
mA
IDDHALT(9)
IDDHALT(10)
IDDHALT(11)
IDDHALT(12)
HALT mode
4.5 to 5.5
3.0 to 3.6
2.2 to 3.0
0.37
0.2
1.3
0.75
0.54
• FmCF=0Hz (oscillation stopped)
• FmX’tal=32.768kHz crystal oscillation mode
• System clock set to internal RC oscillation
• Frequency variable RC oscillation stopped.
• 1/2 frequency division ratio
0.13
HALT mode
• FmCF=0Hz (oscillation stopped)
• FmX’tal=32.768kHz crystal oscillation mode
• Internal RC oscillation stopped.
• System clock set to 10MHz with frequency
variable RC oscillation
4.5 to 5.5
3.0 to 3.6
3.6
2
8.2
4.6
IDDHALT(13)
• 1/1 frequency division ratio
HALT mode
IDDHALT(14)
IDDHALT(15)
IDDHALT(16)
IDDHALT(17)
IDDHALT(18)
IDDHALT(19)
4.5 to 5.5
3.0 to 3.6
2.2 to 3.0
4.5 to 5.5
3.0 to 3.6
2.2 to 3.0
1.7
1
4
2.5
1.8
68
• FmCF=0Hz (oscillation stopped)
• FmX’tal=32.768kHz crystal oscillation mode
• Internal RC oscillation stopped.
• System clock set to 4MHz with frequency
variable RC oscillation
0.7
18.5
10
• 1/1 frequency division ratio
HALT mode
• FmCF=0Hz (oscillation stopped)
• FmX’tal=32.768kHz crystal oscillation mode
• System clock set to 32.768kHz side
• Internal RC oscillation stopped.
• Frequency variable RC oscillation stopped.
• 1/2 frequency division ratio
HOLD mode
38
6.5
26
μA
HOLD mode
consumption
current
IDDHOLD(1)
IDDHOLD(2)
IDDHOLD(3)
IDDHOLD(4)
IDDHOLD(5)
IDDHOLD(6)
V
1
1
4.5 to 5.5
3.0 to 3.6
2.2 to 3.0
4.5 to 5.5
3.0 to 3.6
0.05
0.03
0.02
16
20
12
8
DD
• CF1=V
DD
or open
(External clock mode)
Timer HOLD
mode
V
DD
Timer HOLD mode
58
32
• CF1=V
DD
or open
8.5
consumption
current
(External clock mode)
2.2 to 3.0
5
20
• FmX’tal=32.768kHz crystal oscillation mode
Note 7-1: The consumption current value includes none of the currents that flow into the output Tr and internal pull-up
resistors.
No.A0835-20/25
LC87F7LC8A
F-ROM Programming Characteristics at Ta = +10°C to +55°C, V 1 = V 2= V 3= 0V
SS SS SS
Specification
Parameter
Symbol
Pin/Remarks
Conditions
V
[V]
min
typ max
unit
mA
DD
Onboard
IDDFW(1)
V
1
• 128-byte programming
• Erasing current included
DD
programming
current
3.0 to 5.5
3.0 to 5.5
25
40
45
Programming
time
tFW(1)
• 128-byte programming
• Erasing current included
• Time for setting up 128-byte data is
excluded.
22.5
ms
UART (Full Duplex) Operating Conditions at Ta = +20°C to +70°C, V 1 = V 2= V 3= 0V
SS
SS
Specification
SS
Parameter
Symbol
Pin/Remarks
Conditions
V
[V]
min
16/3
typ
max
8192/3
unit
DD
Transfer rate
UBR
UTX(S32),
URX(S33)
2.2 to 5.5
tCYC
Data length: 7/8/9 bits (LSB first)
Stop bits:
1 bit (2-bit in continuous data transmission)
Parity bits: None
Example of 8-bit Data Transmission Mode Processing (Transmit Data=55H)
Start bit
Stop bit
End of
transmission
Start of
transmission
Transmit data (LSB first)
UBR
Example of 8-bit Data Reception Mode Processing (Receive Data=55H)
Stop bit
Start bit
End of
reception
Start of
reception
Receive data (LSB first)
UBR
No.A0835-21/25
LC87F7LC8A
Characteristics of a Sample Main System Clock Oscillation Circuit
Given below are the characteristics of a sample main system clock oscillation circuit that are measured using a
SANYO-designated oscillation characteristics evaluation board and external components with circuit constant values
with which the oscillator vendor confirmed normal and stable oscillation.
Table 1 Characteristics of a Sample Main System Clock Oscillator Circuit with a Ceramic Oscillator
Operating
Voltage
Range
[V]
Oscillation
Circuit Constant
Nominal
Stabilization Time
Vendor Name
Oscillator Name
Remarks
Frequency
C1
C2
Rf1
Rd1
typ
max
[ms]
[pF]
[pF]
[Ω]
[Ω]
[ms]
Internal
C1, C2
12MHz
8MHz
MURATA
MURATA
CSTCE12M0G52-R0
(10)
(10)
Open
470
3.0 to 5.5
0.05
0.15
CSTCE8M00G52-R0
CSTLS8M00G53-B0
CSTCR4M00G53-R0
CSTLS4M00G53-B0
(10)
(15)
(15)
(15)
(10)
(15)
(15)
(15)
Open
Open
Open
Open
2.2k
680
2.7 to 5.5
2.5 to 5.5
2.2 to 5.5
2.2 to 5.5
0.05
0.05
0.05
0.05
0.15
0.15
0.15
0.15
Internal
C1, C2
3.3k
3.3k
Internal
C1, C2
4MHz
MURATA
The oscillation stabilization time refers to the time interval that is required for the oscillation to get stabilized after V
goes above the operating voltage lower limit (see Fig. 4).
DD
Characteristics of a Sample Subsystem Clock Oscillator Circuit
Given below are the characteristics of a sample subsystem clock oscillation circuit that are measured using a SANYO-
designated oscillation characteristics evaluation board and external components with circuit constant values with
which the oscillator vendor confirmed normal and stable oscillation.
Table 2 Characteristics of a Sample Subsystem Clock Oscillation Circuit with a Crystal Oscillation
Operating
Voltage
Range
[V]
Oscillation
Circuit Constant
Nominal
Oscillator
Name
Stabilization Time
Vendor Name
Remarks
Frequency
C3
C4
Rf2
Rd2
typ
[s]
max
[s]
[pF]
[pF]
[Ω]
[Ω]
Applicable
32.768kHz
SEIKO EPSON
MC-306
18
18
Open
560k
2.2 to 5.5
1.4
3.0
CL value=12.5pF
The oscillation stabilization time refers to the time interval that is required for the oscillation to get stabilized after the
instruction for starting the subclock oscillation circuit is executed and to the time interval that is required for the
oscillation to get stabilized after the HOLD mode is reset (see Fig. 4).
Note: The components that are involved in oscillation should be placed as close to the IC and to one another as possible
because they are vulnerable to the influences of the circuit pattern.
XT1
XT2
CF1
CF2
Rf2
Rf1
CF
Rd2
C4
Rd1
C2
C3
C1
X’tal
Figure 1 CF Oscillator Circuit
Figure 2 XT Oscillator Circuit
0.5V
DD
Figure 3 AC Timing Measurement Point
No.A0835-22/25
LC87F7LC8A
V
DD
Operating V
lower limit
0V
DD
Power supply
Reset time
RES
Internal RC
oscillation
tmsCF
CF1, CF2
tmsX’tal
XT1, XT2
Operating mode
Unpredictable
Reset
Instruction execution
Reset Time and Oscillation Stabilizing Time
HOLD reset signal
absent
HOLD reset signal
HOLD reset signal VALID
Internal RC oscillation
tmsCF
CF1, CF2
tmsX’tal
XT1, XT2
State
HOLD
HALT
HOLD Release Signal and Oscillation Stable Time
Figure 4 Oscillation Stabilizing Times
No.A0835-23/25
LC87F7LC8A
V
DD
R
C
Note:
RES
Determine the value of C
and R so that the reset
RES
RES
signal is present for a period of 200μs after the supply
voltage goes beyond the lower limit of the IC's operating
voltage.
RES
RES
Figure 5 Reset Circuit
SIOCLK:
DATAIN:
DI0
DI1
DI2
DI3
DI4
DI5
DI6
DI7
DI8
DATAOUT:
DO0
DO1
DO2
DO3
DO4
DO5
DO6
DO7
DO8
Data RAM
transfer period
(SIO0 only)
tSCK
tSCKH
thDI
tSCKL
SIOCLK:
DATAIN:
tsDI
tdDO
DATAOUT:
Data RAM
transfer period
(SIO0 only)
tSCKL
tSCKHA
SIOCLK:
DATAIN:
tsDI
thDI
tdDO
DATAOUT:
Figure 6 Serial I/O Waveforms
tPIL
tPIH
Figure 7 Pulse Input Timing Signal Waveform
No.A0835-24/25
LC87F7LC8A
V
DD
SW: ON/OFF (programmable)
RLCD
RLCD
RLCD
RLCD
SW: ON (VLCD=V
)
DD
VLCD
RLCD
RLCD
RLCD
RLCD
RLCD
RLCD
GND
2/3 VLCD
1/2 VLCD
1/3 VLCD
Figure 8 LCD bias resistor
SANYO Semiconductor Co.,Ltd. assumes no responsibility for equipment failures that result from using
products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition
ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor Co.,Ltd.
products described or contained herein.
SANYO Semiconductor Co.,Ltd. strives to supply high-quality high-reliability products, however, any and all
semiconductor products fail or malfunction with some probability. It is possible that these probabilistic failures or
malfunction could give rise to accidents or events that could endanger human lives, trouble that could give rise
to smoke or fire, or accidents that could cause damage to other property. When designing equipment, adopt
safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not
limited to protective circuits and error prevention circuits for safe design, redundant design, and structural
design.
In the event that any or all SANYO Semiconductor Co.,Ltd. products described or contained herein are
controlled under any of applicable local export control laws and regulations, such products may require the
export license from the authorities concerned in accordance with the above law.
No part of this publication may be reproduced or transmitted in any form or by any means, electronic or
mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise,
without the prior written consent of SANYO Semiconductor Co.,Ltd.
Any and all information described or contained herein are subject to change without notice due to
product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the
SANYO Semiconductor Co.,Ltd. product that you intend to use.
Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed
for volume production.
Upon using the technical information or products described herein, neither warranty nor license shall be granted
with regard to intellectual property rights or any other rights of SANYO Semiconductor Co.,Ltd. or any third
party. SANYO Semiconductor Co.,Ltd. shall not be liable for any claim or suits with regard to a third party's
intellctual property rights which has resulted from the use of the technical information and products mentioned
above.
This catalog provides information as of March, 2007. Specifications and information herein are subject
to change without notice.
PS
No.A0835-25/25
相关型号:
LC87F7NC8AVUEJ-2H
8-bit LCD Driver Microcontroller with 128K-byte Flash ROM and 4K-byte RAM, PQFP100 14x20 / QIP100E, 50-FTRAY
ONSEMI
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