LC87FC096AVUEF-3H [ONSEMI]
8-bit Microcontroller with 98K-byte Flash ROM and 4096-byte RAM;
| 型号： | LC87FC096AVUEF-3H |
| 厂家： | 
ONSEMI |
| 描述： | 8-bit Microcontroller with 98K-byte Flash ROM and 4096-byte RAM 时钟 微控制器 外围集成电路 |
| 文件： | 总26页 (文件大小：176K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Ordering number : ENA2150
LC87FC096A
CMOS IC
FROM 98K byte, RAM 4096 byte on-chip
http://onsemi.com
8-bit 1-chip Microcontroller
Overview
The LC87FC096A is an 8-bit microcomputer, integrates a number of hardware features such as 98K-byte flash ROM,
4096-byte RAM, On-chip debugging function, 16-bit timers/counter, four 8-bit timers, a 16-bit timer, a base timer
serving as a time-of-day clock, a high-speed clock counter, a synchronous SIO interface (with automatic block
transmission/reception capabilities), an asynchronous/synchronous SIO port, two UART ports, a single master
I2C/synchronous SIO interface, an 11-channel AD converter, four PWM channels, a system clock frequency divider,
a infrared remote controller receiver function, and interrupt feature.
Package Dimensions
unit : mm (typ)
3159A
Features
Flash ROM
• 100352 × 8 bits
(Address: 00000H to 17FFFH, 1F800H to 1FFFFH)
• Capable of on-board-programing with 2.7 to 3.6V,
of voltage source.
17.2
14.0
48
33
32
49
• Block-erasable in 2K byte units
RAM
• 4096 × 9 bits (LC87FC096A)
Package Form
64
17
• QIP64E (14×14):
Lead-free and halogen-free type
1
16
0.8
0.35
0.15
(1.0)
QIP64E(14X14)
* This product is licensed from Silicon Storage Technology, Inc. (USA).
Semiconductor Components Industries, LLC, 2013
D1912HKIM 20121015-S00005 No.A2150-1/26
May, 2013
Ver.1.0
LC87FC096A
Minimum Bus Cycle
• 83.3ns (12MHz)
• 125ns (8MHz)
V
DD
V
DD
=2.7 to 3.6V
=2.5 to 3.6V
Note: The bus cycle time here refers to the ROM read speed.
Minimum Instruction Cycle Time
• 250ns (12MHz)
• 375ns (8MHz)
V
DD
V
DD
=2.7V to 3.6V
=2.5V to 3.6V
Ports
• Normal withstand voltage I/O ports
Ports whose I/O direction can be designated in 1-bit units 46 (P1n, P2n, P3n, P70 to P73, P80 to P86, PCn,
PWM2, PWM3, XT2)
Ports whose I/O direction can be designated in 4-bit units 8 (P0n)
• Normal withstand voltage input port
• Dedicated oscillator ports
• Reset pins
1 (XT1)
2 (CF1, CF2)
1 (
RES
)
• Power pins
6(V 1 to 3, V 1 to 3)
SS DD
Timers
• Timer 0:16-bit timer/counter with a capture register
Mode 0:8-bit timer with an 8-bit programmable prescaler (with an 8-bit capture register) × 2 channels
Mode 1:8-bit timer with an 8-bit programmable prescaler (with an 8-bit capture register)
+ 8-bit counter (with an 8-bit capture register)
Mode 2:16-bit timer with an 8-bit programmable prescaler (with a 16-bit capture register)
Mode 3:16-bit counter (with a 16-bit capture register)
• Timer 1:16-bit timer/counter that supports PWM/toggle outputs
Mode 0:8-bit timer with an 8-bit prescaler (with toggle outputs) + 8-bit timer/
counter with an 8-bit prescaler (with toggle outputs)
Mode 1:8-bit PWM with an 8-bit prescaler × 2 channels
Mode 2:16-bit timer/counter with an 8-bit prescaler (with toggle outputs)
(toggle outputs also possible from the lower-order 8 bits)
Mode 3:16-bit timer with an 8-bit prescaler (with toggle outputs)
(The lower-order 8 bits can be used as PWM)
• Timer 4:8-bit timer with a 6-bit prescaler
• Timer 5:8-bit timer with a 6-bit prescaler
• Timer 6:8-bit timer with a 6-bit prescaler (with toggle outputs)
• Timer 7:8-bit timer with a 6-bit prescaler (with toggle outputs)
• Timer A:16-bit timer
Mode 0:8-bit timer with an 8-bit programmable prescaler × 2-channels
Mode 1:16-bit timer with an 8-bit programmable prescaler
• Base timer
1) The clock is selectable from the subclock (32.768kHz crystal oscillation), system clock, and timer 0 prescaler
output.
2) Interrupts programmable in 5 different time schemes
High-Speed Clock Counter
• Can count clocks with a maximum clock rate of 24MHz (at a main clock of 12MHz)
• Can generate output real-time
No.A2150-2/26
LC87FC096A
SIO
• SIO0:8-bit Synchronous serial interface
1) LSB first/MSB first mode selectable
2)
transfer clock cycle=4/3tCYC)
Built-in 8-bit baudrate generator (maximum
3) Automatic continuous data transmission (1 to 256 bits, specifiable in 1 bit units, suspension and resumption of
data transmission possible in 1 byte units)
• SIO1:8-bit asynchronous/synchronous serial interface
Mode 0:Synchronous 8-bit serial I/O (2- or 3-wire configuration, 2 to 512 tCYC transfer clocks)
Mode 1:Asynchronous serial I/O (half-duplex, 8 data bits, 1 stop bit, 8 to 2048 tCYC baudrates)
Mode 2:Bus mode 1 (start bit, 8 data bits, 2 to 512 tCYC transfer clocks)
Mode 3:Bus mode 2 (start detect, 8 data bits, stop detect)
• SMIIC0:Single master I2C/8-bit synchronous SIO
Mode 0:Single-master mode communication
Mode 1:Synchronous 8-bit serial I/O (MSB first)
UART: 2 channels
• Full duplex
• 7/8/9 bit data bits selectable
• 1 stop bit (2-bit in continuous data transmission)
• Built-in baudrate generator (with baudrates of 16/3 to 8192/3 tCYC)
AD Converter: 12 bits × 11 channels
PWM: Multifrequency 12-bit PWM × 4-channels
Remote Control Receiver Circuit (sharing pins with P73, INT3, and T0IN)
• Noise filtering function (noise filter time constant selectable from 1 tCYC, 32 tCYC, and 128 tCYC)
• The noise filtering function is available for the INT3, T0IN, or T0HCP signal at P73. When P73 is read with an
instruction, the signal level at that pin is read regardless of the availability of the noise filtering function.
Infrared Remote Controller Receiver Circuit
• Noise rejection function (noise filter time constant: Approx. 120μs when the 32.768kHz crystal oscillator is
selected as the reference clock source)
• Supports data encording systems such as PPM (Pulse Position Modulation) and Manchester encording
• X’tal HOLD mode release function
Watchdog Timer
• External RC watchdog timer
• Interrupt and reset signals selectable
Clock Output Function
• Able to output selected oscillation clock 1/1, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64 as system clock.
• Able to output oscillation clock of sub clock.
No.A2150-3/26
LC87FC096A
Interrupts
• 31 sources, 10 vector addresses
1) Provides three levels (low (L), high (H), and highest (X)) of multiplex interrupt control. Any interrupt requests of
the level equal to or lower than the current interrupt are not accepted.
2) When interrupt requests to two or more vector addresses occur at the same time, the interrupt of the highest level
takes precedence over the other interrupts. For interrupts of the same level, the interrupt into the smallest vector
address takes precedence.
No.
Vector Address
Level
X or L
X or L
H or L
H or L
H or L
H or L
H or L
H or L
H or L
H or L
Interrupt Source
1
00003H
INT0
INT1
2
0000BH
00013H
3
INT2/T0L/INT4/TAL/Infrared remote control receiver
INT3/INT5/base timer0/base timer1
4
0001BH
00023H
5
T0H/INT6/TAH
6
0002BH
00033H
T1L/T1H/INT7/SMIIC0
7
SIO0/UART1 receive/ UART2 receive
SIO1/UART1 transmit/ UART2 transmit
ADC/T6/T7
8
0003BH
00043H
9
10
0004BH
Port 0/T4/T5/PWM2, PWM3/RMPWM
• Priority levels X > H > L
• Of interrupts of the same level, the one with the smallest vector address takes precedence.
Subroutine Stack Levels: 2048 levels (the stack is allocated in RAM)
High-speed Multiplication/Division Instructions
• 16 bits × 8 bits
• 24 bits × 16 bits
• 16 bits ÷ 8 bits
• 24 bits ÷ 16 bits
(5 tCYC execution time)
(12 tCYC execution time)
(8 tCYC execution time)
(12 tCYC execution time)
Oscillation Circuits
• RC oscillation circuit (internal):
• CF oscillation circuit:
• Crystal oscillation circuit:
For system clock
For system clock, with internal Rf
For low-speed system clock
System Clock Divider Function
• Can run on low current.
• The minimum instruction cycle selectable from 250ns, 500ns, 1.0μs, 2.0μs, 4.0μs, 8.0μs, 16.0μs, 32.0μs, and
64.0μs (at a main clock rate of 12MHz).
Standby Function
• HALT mode: Halts instruction execution while allowing the peripheral circuits to continue operation.
1) Oscillation is not halted automatically.
2) Canceled by a system reset or occurrence of an interrupt.
• HOLD mode: Suspends instruction execution and the operation of the peripheral circuits.
1) The CF, RC, and crystal oscillators automatically stop operation.
2) There are three ways of resetting the HOLD mode.
(1) Setting the reset pin to the low level
(2) Setting at least one of the INT0, INT1, INT2, INT4, and INT5 pins to the specified level
(3) Having an interrupt source established at port 0
Continued on next page.
No.A2150-4/26
LC87FC096A
Continued from preceding page.
• X'tal HOLD mode: Suspends instruction execution and the operation of the peripheral circuits except the base
timer and infrared remote controller receiver circuit.
1) The CF and RC oscillators automatically stop operation.
2) The state of crystal oscillation established when the X'tal HOLD mode is entered is retained.
3) There are four ways of resetting the X'tal HOLD mode.
(1) Setting the reset pin to the low level
(2) Setting at least one of the INT0, INT1, INT2, INT4, and INT5 pins to the specified level
(3) Having an interrupt source established at port 0
(4) Having an interrupt source established in the base timer circuit
(5) Having an interrupt source established in the infrared remote controller receiver circuit
On-chip Debugger Function
• Permits software debugging with the test device installed on the target board.
Development Tools
• On-chip debugger: TCB87-TypeC (3wire version) + LC87FC096A
Programming Boards
Package
Programming boards
W87F50256Q
QIP64E
Flash ROM Programmer
Maker
Model
Supported version
Device
Application Version:
After 1.08
SKK/SKK Type-B/SKK DBG Type-B
(SANYO FWS)
Our company
LC87FC096
Chip Data Version:
After 2.42
No.A2150-5/26
LC87FC096A
Pin Assignment
48 47 46 45 44 43 42
40 39 38 37 36 35 34 33
41
P70/INT0/T0LCP/AN8
P71/INT1/T0HCP/AN9
P72/INT2/T0IN/NKIN
P73/INT3/T0IN/RMIN
RES
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
P32/UTX1
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
P33/URX1
P34/UTX2
P35/URX2
P36
XT1/AN10
XT2/AN11
P37
P27/INT5/T1IN
P26/INT5/T1IN
P25/INT5/T1IN
P24/INT5/T1IN/INT7
P23INT4/T1IN
P22/INT4/T1IN
P21/INT4/T1IN
P20/INT4/T1IN/INT6
P07/T7O
V
1
SS
LC87FC096A
CF1
CF2
1
V
DD
P80/AN0
P81/AN1
P82/AN2
P10/SO0
P11/SI0/SB0
P06/T6O
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16
Top view
QIP64E (14×14) “Lead-free and halogen-free type”
No.A2150-6/26
LC87FC096A
System Block Diagram
Interrupt control
Standby control
IR
PLA
Flash ROM
CF
RC
X’tal
PC
SIO0
Bus interface
Port 0
SIO1
ACC
B register
SMIIC0
Port 1
Port 2
Port 7
Port 8
ADC
C register
ALU
Timer 0
Timer 1
Timer 4
Timer 5
Timer 6
PSW
RAR
INT0 to INT7
Noise filter
RAM
Port 3
Port C
Timer 7
Timer A
Stack pointer
UART1
UART2
Watchdog timer
Base timer
PWM2/3
On-chip Debugger
Remote control
receiver circuit
RMPWM
No.A2150-7/26
LC87FC096A
Pin Description
Pin Name
I/O
-
Description
Option
No
V
V
1, V 2, V
3
- Power supply pin
+ Power supply pin
• 8-bit I/O port
SS
SS SS
1, V 2, V
3
-
No
DD
DD DD
Port 0
I/O
Yes
• I/O specifiable in 4-bit units
P00 to P07
• Pull-up resistor can be turned on and off in 4-bit units
• HOLD release input
• Port 0 interrupt input
• Shared Pins
P05 : Clock output (system clock / can selected from sub clock)
P06 : Timer 6 toggle output
P07 : Timer 7 toggle output
Port 1
I/O
• 8-bit I/O port
Yes
• I/O specifiable in 1-bit units
P10 to P17
• Pull-up resistor can be turned on and off in 1-bit units
• Pin functions
P10 : SIO0 data output
P11 : SIO0 data input/bus I/O
P12 : SIO0 clock I/O
P13 : SIO1 data output
P14 : SIO1 data input/bus I/O
P15 : SIO1 clock I/O
P16 : Timer 1 PWML output
P17 : Timer 1 PWMH output/beeper output
• 8-bit I/O port
Port 2
I/O
Yes
• I/O specifiable in 1-bit units
P20 to P27
• Pull-up resistor can be turned on and off in 1-bit units
• Other functions
P20: INT4 input/HOLD reset input/timer 1 event input/timer 0L capture input/
timer 0H capture input/INT6 input/timer 0L capture 1 input
P21 to P23: INT4 input/HOLD reset input/timer 1 event input/timer 0L capture input/
timer 0H capture input
P24: INT5 input/HOLD reset input/timer 1 event input/timer 0L capture input/
timer 0H capture input/INT7 input/timer 0H capture 1 input
P25 to P27: INT5 input/HOLD reset input/timer 1 event input/timer 0L capture input/
timer 0H capture input
• Interrupt acknowledge type
Rising/
Rising
Falling
H level
L level
Falling
enable
enable
enable
enable
INT4
INT5
INT6
INT7
enable
enable
enable
enable
enable
enable
enable
enable
disable
disable
disable
disable
disable
disable
disable
disable
Continued on next page.
No.A2150-8/26
LC87FC096A
Continued from preceding page.
Pin Name
Port 7
I/O
I/O
Description
Option
No
• 4-bit I/O port
• I/O specifiable in 1-bit units
P70 to P73
• Pull-up resistor can be turned on and off in 1-bit units
• Shared pins
P70 : INT0 input/HOLD reset input/timer 0L capture input/watchdog timer output
P71 : INT1 input/HOLD reset input/timer 0H capture input
P72 : INT2 input/HOLD reset input/timer 0 event input/timer 0L capture input/
high speed clock counter input
P73 : INT3 input (with noise filter)/timer 0 event input/timer 0H capture input/
remote control receiver input
AD converter input port: AN8 (P70), AN9 (P71)
• Interrupt acknowledge type
Rising/
Rising
Falling
H level
L level
Falling
disable
disable
enable
enable
INT0
INT1
INT2
INT3
enable
enable
enable
enable
enable
enable
enable
enable
enable
enable
disable
disable
enable
enable
disable
disable
Port 8
I/O
• 7-bit I/O port
No
• I/O specifiable in 1-bit units
• Shared pins
P80 to P86
AD converter input port : AN0 (P80) to AN6 (P86)
• PWM2 and PWM3 output ports
• General-purpose I/O available
• 8-bit I/O port
PWM2
PWM3
Port 3
I/O
I/O
No
Yes
• I/O specifiable in 1-bit units
P30 to P37
• Pull-up resistor can be turned on and off in 1-bit units
• Pin functions
P32: UART1 transmit
P33: UART1 receive
P34: UART2 transmit
P35: UART2 receive
Port C
I/O
• 8-bit I/O port
Yes
• I/O specifiable in 1-bit units
• Pull-up resistor can be turned on and off in 1-bit units
• Pin functions
PC0 to PC7
PC0: SMIIC0 clock input/output
PC1: SMIIC0 bus input/output/data input
PC2: SMIIC0 data output (used in 3-wire SIO mode)
PC3: RMPWM0 output
PC4: RMPWM1 output
PC5: DBGP0
PC6: DBGP1
PC7: DBGP2
DBGP0 to DBGP2: On-chip Debugger
RES
XT1
Input
Input
Reset pin
No
No
• 32.768kHz crystal oscillator input pin
• Shared pins
General-purpose input port
AD converter input port : AN10
Must be connected to VDD1 if not to be used.
XT2
I/O
• 32.768kHz crystal oscillator output pin
• Shared pins
No
General-purpose I/O port
AD converter input port : AN11
Must be set for oscillation and kept open if not to be used.
Ceramic resonator input pin
CF1
CF2
Input
No
No
Output
Ceramic resonator output pin
No.A2150-9/26
LC87FC096A
Port Output Types
The table below lists the types of port outputs and the presence/absence of a pull-up resistor.
Data can be read into any input port even if it is in the output mode.
Option Selected
Port Name
Option Type
Output Type
Pull-up Resistor
in Units of
1 bit
P00 to P07
1
2
CMOS
Programmable (Note 1)
No
Nch-open drain
CMOS
P10 to P17
P20 to P27
1 bit
1 bit
1
Programmable
Programmable
Programmable
Programmable
Programmable
Programmable
No
2
Nch-open drain
CMOS
1
2
Nch-open drain
Nch-open drain
CMOS
P70
-
No
No
No
No
1
P71 to P73
P80 to P86
PWM2, PWM3
P30 to P37
-
-
-
Nch-open drain
CMOS
No
1 bit
CMOS
Programmable
Programmable
Programmable
Programmable
No
2
Nch-open drain
CMOS
PC0 to PC7
1 bit
1
2
Nch-open drain
XT1
XT2
-
-
No
No
Input for 32.768kHz crystal oscillator (Input only)
Output for 32.768kHz crystal oscillator
(Nch-open drain when in general-purpose output
mode)
No
Note 1:Programmable pull-up resistors for port 0 are controlled in 4-bit units (P00 to 03, P04 to 07).
*1: Make the following connection to minimize the noise input to the V 1 pin and prolong the backup time.
DD
Be sure to electrically short the V 1, V 2 and V 3 pins.
SS SS SS
(Example 1) When backup is active in the HOLD mode, the high level of the port outputs is supplied by the
backup capacitors.
Back-up
LSI
capacitor
V
1
DD
Power
Supply
V
2
DD
V
3
DD
1 V 2 V
3
SS
V
SS
SS
(Example 2) The high-level output at the ports is unstable when the HOLD mode backup is in effect.
Back-up
LSI
capacitor
V
V
V
1
2
3
DD
DD
DD
Power
Supply
V
1 V 2 V
SS
3
SS
SS
No.A2150-10/26
LC87FC096A
Absolute Maximum Ratings at Ta = 25°C, V 1 = V 2 = V 3 = 0V
SS SS SS
Specification
typ max
Parameter
Symbol
Pin/Remarks
1, V 2, V 3
DD
Conditions
V
[V]
min
-0.3
unit
V
DD
Maximum supply
voltage
V
max
V
V
1=V 2=V 3
DD
DD
DD
DD DD DD
+4.6
Input voltage
VI(1)
XT1, CF1
-0.3
V
V
+0.3
DD
DD
Input/output voltage
VIO(1)
Ports 0, 1, 2
Ports 7, 8
-0.3
+0.3
Ports 3, C
PWM2, PWM3, XT2
Ports 0, 1, 2
Peak output
current
IOPH(1)
CMOS output select
Per 1 applicable pin
Per 1 applicable pin
-7.5
Ports 3, C
IOPH(2)
IOPH(3)
IOMH(1)
PWM2, PWM3
-12.5
-4.5
P71 to P73
Per 1 applicable pin
Mean output
current
Ports 0, 1, 2
Ports 3, C
CMOS output select
Per 1 applicable pin
Per 1 applicable pin
-5
(Note 1-1)
IOMH(2)
IOMH(3)
ΣIOAH(1)
ΣIOAH(2)
PWM2, PWM3
-10
-3
P71 to P73
P71 to P73
Per 1 applicable pin
Total output
current
Total of all applicable pins
Total of all applicable pins
-10
Port 1
-15
-15
-30
PWM2, PWM3
Ports 0, 2
ΣIOAH(3)
ΣIOAH(4)
Total of all applicable pins
Total of all applicable pins
Ports 0, 1, 2
PWM2, PWM3
Port 3
ΣIOAH(5)
ΣIOAH(6)
ΣIOAH(7)
IOPL(1)
Total of all applicable pins
Total of all applicable pins
Total of all applicable pins
Per 1 applicable pin
-15
-15
-30
Port C
Ports 3, C
Peak output
current
P02 to P07
Ports 1, 2
10
Ports 3, C
PWM2, PWM3
P00, P01
mA
IOPL(2)
IOPL(3)
IOML(1)
Per 1 applicable pin
Per 1 applicable pin
Per 1 applicable pin
15
Ports 7, 8, XT2
7.5
Mean output
current
P02 to P07
Ports 1, 2
7.5
(Note 1-1)
Ports 3, C
PWM2, PWM3
P00, P01
IOML(2)
IOML(3)
ΣIOAL(1)
Per 1 applicable pin
10
5
Ports 7, 8, XT2
Per 1 applicable pin
Total output
current
Port 7
Total of all applicable pins
15
P83 to P86, XT2
P80 to P82
ΣIOAL(2)
ΣIOAL(3)
ΣIOAL(4)
Total of all applicable pins
Total of all applicable pins
Total of all applicable pins
10
25
Ports 7, 8, XT2
Port 1
25
25
50
PWM2, PWM3
Ports 0, 2
ΣIOAL(5)
ΣIOAL(6)
Total of all applicable pins
Total of all applicable pins
Ports 0, 1, 2
PWM2, PWM3
Port 3
ΣIOAL(7)
ΣIOAL(8)
ΣIOAL(9)
Pdmax
Total of all applicable pins
Total of all applicable pins
Total of all applicable pins
Ta=-40 to +85°C
25
25
50
Port C
Ports 3, C
QIP64E(14×14)
Maximum power
dissipation
300
85
mW
Operating ambient
temperature
Topr
Tstg
-40
-55
°C
Storage ambient
temperature
125
Note 1-1: The mean output current is a mean value measured over 100ms.
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating
Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.
No.A2150-11/26
LC87FC096A
Allowable Operating Conditions at Ta = -40°C to +85°C, V 1 = V 2 = V 3 = 0V
SS SS SS
Specification
typ max
Parameter
Symbol
Pin/Remarks
Conditions
VDD[V]
min
unit
Operating
V
V
V
(1)
V
V
1=V 2=V
DD
3
3
0.245μs ≤ tCYC ≤ 200μs
0.367μs ≤ tCYC ≤ 200μs
DD
HD
DD
DD
2.7
2.5
3.6
3.6
supply voltage
(Note 2-1)
Memory
1=V 2=V
DD
RAM and register contents
sustained in HOLD mode.
DD
DD
sustaining
2.0
3.6
supply voltage
High level input
voltage
(1)
Ports 1, 2
IH
P71 to P73
0.3V
DD
+0.7
2.5 to 3.6
2.5 to 3.6
V
V
DD
P70 port input
/interrupt side
Ports 0, 8, 3, C
PWM2, PWM3
V
V
(2)
0.3V
DD
IH
IH
IH
DD
+0.7
(3)
Port 70 watchdog
timer side
V
2.5 to 3.6
2.5 to 3.6
0.9V
V
V
DD
DD
V
V
(4)
XT1, XT2, CF1,
RES
0.75V
DD
DD
Low level input
voltage
(1)
Ports 1, 2
IL
P71 to P73
2.5 to 3.6
V
0.25V
SS
DD
P70 port input/
interrupt side
Ports 0, 8, 3, C
PWM2, PWM3
V
V
V
(2)
(3)
(4)
IL
IL
IL
2.5 to 3.6
2.5 to 3.6
2.5 to 3.6
V
V
V
0.2V
SS
SS
SS
DD
DD
Port 70 watchdog
timer side
0.8V
-1.0
XT1, XT2, CF1,
RES
0.25V
DD
Instruction cycle
time
tCYC
2.7 to 3.6
2.5 to 3.6
0.245
0.367
200
200
μs
(Note 2-2)
External system
clock frequency
FEXCF(1)
CF1
• CF2 pin open
2.7 to 3.6
2.5 to 3.6
0.1
0.1
12
8
• System clock frequency
division rate=1/1
• External system clock
duty=50±5%
MHz
• CF2 pin open
2.7 to 3.6
2.5 to 3.6
0.2
0.2
24
16
• System clock frequency
division rate=1/2
Oscillation
FmCF(1)
FmCF(2)
CF1, CF2
CF1, CF2
12MHz ceramic oscillation
See Fig. 1.
2.7 to 3.6
12
frequency range
(Note 2-3)
8MHz ceramic oscillation
See Fig. 1.
MHz
kHz
2.5 to 3.6
2.5 to 3.6
8
FmRC
FsX’tal
Internal RC oscillation
0.3
1.0
2.0
XT1, XT2
32.768kHz crystal oscillation
See Fig. 2.
2.5 to 2.6
32.768
Note 2-1: V
DD
must be held greater than or equal to 2.7V in the flash ROM onboard programming mode.
Note 2-2: Relationship between tCYC and oscillation frequency is 3/FmCF at a division ratio of 1/1 and 6/FmCF at
a division ratio of 1/2.
Note 2-3: See Tables 1 and 2 for the oscillation constants.
No.A2150-12/26
LC87FC096A
Electrical Characteristics at Ta = -40°C to +85°C, V 1 = V 2 = V 3 = 0V
SS
SS
SS
Specification
typ
Parameter
Symbol
Pins
Conditions
V
[V]
min
max
unit
DD
High level input
current
I
(1)
IH
Ports 0, 1, 2
Ports 7, 8
Ports 3, C
RES
Output disabled
Pull-up resistor off
=V
V
2.5 to 3.6
1
IN DD
(Including output Tr's off leakage
current)
PWM2, PWM3
XT1, XT2
I
(2)
IH
For input port specification
2.5 to 3.6
2.5 to 3.6
1
V
=V
IN DD
I
I
(3)
IH
CF1
V
=V
15
IN DD
μA
Low level input
current
(1)
IL
Ports 0, 1, 2
Ports 7, 8
Ports 3, C
RES
Output disabled
Pull-up resistor off
V
=V
2.5 to 3.6
-1
IN SS
(Including output Tr's off leakage
current)
PWM2, PWM3
XT1, XT2
I
I
(2)
IL
For input port specification
2.5 to 3.6
-1
V
V
I
=V
IN SS
(3)
IL
CF1
=V
2.5 to 3.6
3.0 to 3.6
2.5 to 3.6
3.0 to 3.6
2.5 to 3.6
3.0 to 3.6
2.5 to 3.6
-15
IN SS
High level output
voltage
V
V
(1)
(2)
Ports 0, 1, 2
Ports 3, C
=-0.4mA
V
V
V
V
V
V
-0.4
-0.4
-0.4
-0.4
-0.4
-0.4
OH
OH
OH
DD
DD
DD
DD
DD
DD
I
I
I
=-0.2mA
=-0.4mA
=-0.2mA
OH
OH
OH
V
(3)
P71 to P73
OH
OH
V
(4)
V
V
(5)
(6)
PWM2, PWM3
I
I
=-1.6mA
=-1mA
OH
OH
OH
OH
V
Low level output
voltage
V
(1)
Ports 0, 1, 2
Ports 3, C
PWM2, PWM3
Ports 7, 8
XT2
I
I
=1.6mA
OL
OL
OL
OL
3.0 to 3.6
2.5 to 3.6
0.4
0.4
V
(2)
=1mA
V
V
V
V
(3)
(4)
(5)
(6)
I
I
I
I
=1.6mA
=1mA
3.0 to 3.6
2.5 to 3.6
3.0 to 5.5
2.2 to 5.5
3.0 to 3.6
2.5 to 3.6
0.4
0.4
0.4
0.4
80
OL
OL
OL
OL
OL
OL
OL
OL
P00, P01
=5mA
=2.5mA
=0.9V
Pull-up
Rpu(1)
Rpu(2)
VHYS
Ports 0, 1, 2, 7
Ports 3, C
V
15
15
35
35
OH
DD
kΩ
resistance
100
Hysteresis
voltage
RES
0.1
2.5 to 3.6
V
Ports 1, 2, 7
V
DD
Pin capacitance
CP
All pins
For pins other than that under test:
=V
V
IN SS
2.5 to 3.6
10
pF
f=1MHz
Ta=25°C
No.A2150-13/26
LC87FC096A
Serial I/O Characteristics at Ta = -40°C to +85°C, V 1 = V 2 = V 3 =0V
SS
SS
SS
1. SIO0 Serial I/O Characteristics (Note 4-1-1)
Specification
Pin/
Parameter
Frequency
Symbol
tSCK(1)
Conditions
Remarks
V
[V]
min
typ
max
unit
DD
SCK0(P12)
See Fig. 6.
2
1
1
Low level
tSCKL(1)
tSCKH(1)
tSCKHA(1)
pulse width
High level
pulse width
2.5 to 3.6
tCYC
• Continuous data
transmission/reception mode
• See Fig. 6.
4
• (Note 4-1-2)
Frequency
tSCK(2)
SCK0(P12)
• CMOS output selected
• See Fig. 6.
4/3
Low level
tSCKL(2)
tSCKH(2)
tSCKHA(2)
1/2
1/2
pulse width
High level
pulse width
tSCK
tCYC
2.5 to 3.6
• Continuous data
tSCKH(2)
+(10/3)
tCYC
transmission/reception mode
• CMOS output selected
• See Fig. 6.
tSCKH(2)
+2tCYC
Data setup time
Data hold time
tsDI(1)
thDI(1)
tdD0(1)
tdD0(2)
tdD0(3)
SB0(P11),
SI0(P11)
• Must be specified with respect
to rising edge of SIOCLK.
• See Fig. 6.
2.5 to 3.6
2.5 to 3.6
2.5 to 3.6
2.5 to 3.6
0.03
0.03
Output delay
time
SO0(P10),
SB0(P11)
• Continuous data
(1/3)tCYC
+0.05
transmission/reception mode
• (Note 4-1-3)
μs
• Synchronous 8-bit mode
• (Note 4-1-3)
1tCYC
+0.05
(Note 4-1-3)
(1/3)tCYC
+0.15
2.5 to 3.6
Note 4-1-1: These specifications are theoretical values. Add margin depending on its use.
Note 4-1-2: To use serial-clock-input in continuous trans / rec mode, a time from SI0RUN being set when serial clock is
"H" to the first negative edge of the serial clock must be longer than tSCKHA.
Note 4-1-3: Must be specified with respect to falling edge of SIOCLK. Must be specified as the time to the beginning of
output state change in open drain output mode. See Fig. 6.
No.A2150-14/26
LC87FC096A
2. SIO1 Serial I/O Characteristics (Note 4-2-1)
Specification
Parameter
Frequency
Symbol
tSCK(3)
Pin/Remarks
SCK1(P15)
Conditions
V
[V]
min
typ
max
unit
DD
See Fig. 6.
2
1
1
2
Low level
tSCKL(3)
tSCKH(3)
tSCK(4)
tSCKL(4)
tSCKH(4)
tsDI(2)
2.5 to 3.6
pulse width
High level
pulse width
Frequency
tCYC
SCK1(P15)
• CMOS output selected
• See Fig. 6.
Low level
pulse width
2.5 to 3.6
1/2
1/2
tSCK
High level
pulse width
Data setup time
SB1(P14),
SI1(P14)
• Must be specified with respect
to rising edge of SIOCLK.
• See Fig. 6.
2.5 to 3.6
2.5 to 3.6
0.03
0.03
Data hold time
thDI(2)
tdD0(4)
μs
Output delay time
SO1(P13),
SB1(P14)
• Must be specified with respect
to falling edge of SIOCLK.
• Must be specified as the
time to the beginning of
output state change in
open drain output mode.
• See Fig. 6.
(1/3)tCYC
+0.05
2.5 to 3.6
Note 4-2-1: These specifications are theoretical values. Add margin depending on its use.
No.A2150-15/26
LC87FC096A
3-1. SMIIC0 Simple SIO Mode Input/Output Characteristics
Specification
Applicable
Parameter
Period
Symbol
Conditions
Pin/Remarks
V
[V]
min
4/3
typ
max
unit
DD
tSCK (4)
SM0CK (PC0)
See Fig. 6.
Low level
tSCKL (4)
tSCKH (4)
tSCK (5)
tSCKL (5)
tSCKH (5)
tsDI (3)
2.5 to 3.6
2/3
2/3
4/3
pulse width
High level
pulse width
Period
tCYC
SM0CK (PC0)
• CMOS output selected
• See Fig. 6.
Low level
pulse width
2.5 to 3.6
2.5 to 3.6
2.5 to 3.6
1/2
1/2
tSCK
High level
pulse width
Data setup time
SM0DA (PC1)
• Specified with respect to
rising edge of SIOCLK
• See Fig. 6.
0.03
0.03
Data hold time
thDI (3)
Output delay
time
tdD0 (5)
SM0DO (PC2),
SM0DA (PC1)
• Specified with respect to
falling edge of SIOCLK
• Specified as interval up to
time when output state
starts changing.
μs
1/3tCYC
+0.05
• See Fig. 6.
Note 4-3-1: These specifications are theoretical values. Add margin depending on its use.
No.A2150-16/26
LC87FC096A
3-2. SMIIC0 I2C Mode Input/Output Characteristics
Specification
typ max
Applicable
Parameter
Period
Symbol
tSCL
Conditions
• See Fig. 8.
Pin/Remarks
V
[V]
Min
Unit
Tfilt
DD
SM0CK (PC0)
5
Low level
tSCLL
tSCLH
tSCLx
tSCLLx
tSCLHx
tsp
2.5 to 3.6
2.5
2
pulse width
High level
pulse width
Period
SM0CK (PC0)
• Specified as interval up to
time when output state
starts changing.
10
Low level
pulse width
2.5 to 3.6
2.5 to 3.6
1/2
1/2
tSCL
High level
pulse width
SM0CK and SM0DA
pins input spike
suppression time
Bus release time
between start
and stop
SM0CK (PC0)
SM0DA (PC1)
• See Fig. 8.
• See Fig. 8.
1
Tfilt
Tfilt
tBUF
SM0CK (PC0)
SM0DA (PC1)
2.5
5.5
tBUFx
SM0CK (PC0)
SM0DA (PC1)
• Standard clock mode
• Specified as interval up to
time when output state
starts changing.
2.5 to 3.6
2.5 to 3.6
2.5 to 3.6
μs
• High-speed clock mode
• Specified as interval up to
time when output state
starts changing.
1.6
Start/restart
condition hold
time
tHD;STA
SM0CK (PC0)
SM0DA (PC1)
• When SMIIC register
control bit, SHDS=0
• See Fig. 8.
2.0
2.5
Tfilt
• When SMIIC register
control bit, SHDS=1
• See Fig. 8.
tHD;STAx
SM0CK (PC0)
SM0DA (PC1)
• Standard clock mode
• Specified as interval up to
time when output state
starts changing.
4.1
μs
Tfilt
μs
• High-speed clock mode
• Specified as interval up to
time when output state
starts changing.
1.0
1.0
5.5
Restart
tSU;STA
SM0CK (PC0)
SM0DA (PC1)
• See Fig. 8.
condition setup
time
tSU;STAx
SM0CK (PC0)
SM0DA (PC1)
• Standard clock mode
• Specified as interval up to
time when output state
starts changing.
• High-speed clock mode
• Specified as interval up to
time when output state
starts changing.
1.6
Continued on next page.
No.A2150-17/26
LC87FC096A
Continued from preceding page.
Specification
typ max
Applicable
Parameter
Symbol
Conditions
Pin/Remarks
V
[V]
Min
Unit
Tfilt
DD
Stop condition
setup time
tSU;STO
SM0CK (PC0)
SM0DA (PC1)
• See Fig. 8.
1.0
tSU;STOx
SM0CK (PC0)
SM0DA (PC1)
• Standard clock mode
• Specified as interval up to time
when output state starts
changing.
4.9
1.6
2.5 to 3.6
μs
• High-speed clock mode
• Specified as interval up to time
when output state starts
changing.
Data hold time
tHD;DAT
tHD;DATx
tSU;DAT
tSU;DATx
SM0CK (PC0)
SM0DA (PC1)
• See Fig. 8.
0
1
1
2.5 to 3.6
Tfilt
Tfilt
SM0CK (PC0)
SM0DA (PC1)
• Specified as interval up to time
when output state starts
changing.
1.5
Data setup
time
SM0CK (PC0)
SM0DA (PC1)
• See Fig. 8.
2.5 to 3.6
SM0CK (PC0)
SM0DA (PC1)
• Specified as interval up to time
when output state starts
changing.
1tSCL-
1.5Tfilt
Note 4-3-2: These specifications are theoretical values. Add margin depending on its use.
Note 4-3-3: The value of Tfilt is determined by the values of the register SMIC0BRG, bits 7 and 6 (BRP1, BRP0) and
the system clock frequency.
BRP1
BRP0
Tfilt
0
0
1
1
0
1
0
1
(1/3)tCYC×1
(1/3)tCYC×2
(1/3)tCYC×3
(1/3)tCYC×4
Set bits (BPR1, BPR0) so that the value of Tfilt falls between the following range:
250ns Tfilt > 140ns
Note 4-3-4: The standard clock mode refers to a mode that is entered by configuring SMIC0BRG as follows:
250ns ≥ Tfilt > 140ns
BRDQ (bit5) = 1
SCL frequency setting ≤ 100kHz
The high-speed clock mode refers to a mode that is entered by configuring SMIC0BRG as follows:
250ns ≥ Tfilt > 140ns
BRDQ (bit5) = 0
SCL frequency setting ≤ 400kHz
No.A2150-18/26
LC87FC096A
Pulse Input Conditions at Ta = -40°C to +85°C, V 1 = V 2 = V 3 = 0V
SS
SS
SS
Specification
Parameter
Symbol
Pins/Remarks
Conditions
V
[V]
min
typ
max
unit
tCYC
μs
DD
High/low level
pulse width
tPIH(1)
tPIL(1)
INT0(P70), INT1(P71),
INT2(P72), INT4(P20 to P23),
INT5(P24 to P27)
• Interrupt source flag can be set.
• Event inputs for timer 0 or 1
are enabled.
2.5 to 3.6
1
INT6(P20), INT7(P24)
INT3(P73) when noise
filter time constant is 1/1
tPIH(2)
tPIL(2)
• Interrupt source flag can be set.
• Event inputs for timer 0 are
enabled.
2.5 to 3.6
2.5 to 3.6
2
tPIH(3)
tPIL(3)
INT3(P73) when noise
• Interrupt source flag can be set.
• Event inputs for timer 0 are
enabled.
filter time constant is 1/32
64
tPIH(4)
tPIL(4)
INT3(P73) when noise
• Interrupt source flag can be set.
• Event inputs for timer 0 are
enabled.
filter time constant is 1/128
2.5 to 3.6
2.5 to 3.6
256
200
RES
tPIL(5)
Resetting is enabled.
AD Converter Characteristics at V 1 = V 2 = V 3 = 0V
SS SS SS
<12bits AD Converter Mode at Ta = -40°C to +85°C >
Specification
Parameter
Symbol
Pin/Remarks
Conditions
V
[V]
min
typ
max
unit
bit
DD
Resolution
N
AN0(P80) to
AN6(P86),
AN8(P70),
AN9(P71),
AN10(XT1),
AN11(XT2)
2.5 to 3.6
2.5 to 3.6
12
Absolute
ET
(Note 6-1)
16
LSB
accuracy
Conversion time
TCAD
See Conversion time calculation
formulas. (Note 6-2)
3.0 to 3.6
2.7 to 3.6
2.5 to 3.6
64
115
230
460
128
256
μs
Analog input
voltage range
Analog port
input current
VAIN
2.5 to 3.6
V
V
V
SS
DD
IAINH(1)
IAINL(1)
analog channel
VAIN=V
DD
2.5 to 3.6
2.5 to 3.6
1
μA
VAIN=V
SS
-1
<8bits AD Converter Mode at Ta = -40°C to +85°C >
Specification
Parameter
Symbol
Pin/Remarks
Conditions
V
[V]
min
typ
max
unit
bit
DD
Resolution
N
AN0(P80) to
2.5 to 3.6
2.5 to 3.6
8
AN6(P86),
AN8(P70),
AN9(P71),
AN10(XT1),
AN11(XT2)
Absolute
accuracy
Conversion
time
ET
(Note 6-1)
1.5
LSB
TCAD
See Conversion time calculation
formulas. (Note 6-2)
3.0 to 3.6
2.7 to 3.6
2.5 to 3.6
39
71
140
280
79
μs
157
Analog input
voltage range
Analog port
input current
VAIN
2.5 to 3.6
V
V
V
SS
DD
IAINH(1)
IAINL(1)
analog channel
VAIN=V
DD
2.5 to 3.6
2.5 to 3.6
1
μA
VAIN=V
SS
-1
12bits AD Converter Mode: TCAD(Conversion time)= ((52/(AD division ratio))+2)×(1/3)×tCYC
8bits AD Converter Mode: TCAD(Conversion time)=((32/(AD division ratio))+2)×(1/3)×tCYC
Note 6-1: The quantization error (±1/2LSB) must be excluded from the absolute accuracy. The absolute accuracy must
be measured in the microcontroller's state in which no I/O operations occur at the pins adjacent to the analog
input channel.
Note 6-2: The conversion time refers to the period from the time an instruction for starting a conversion process till the
time the conversion results register(s) are loaded with a complete digital conversion value corresponding to
the analog input value.
The conversion time is 2 times the normal-time conversion time when:
• The first AD conversion is performed in the 12-bit AD conversion mode after a system reset.
• The first AD conversion is performed after the AD conversion mode is switched from 8-bit to 12-bit
conversion mode.
No.A2150-19/26
LC87FC096A
Consumption Current Characteristics at Ta = -40°C to +85°C, V 1 = V 2 = V 3 = 0V
SS
SS
SS
Specification
Typ Max
Pins/Rema
rks
Parameter
Symbol
Conditions
V
[V]
min
unit
DD
Normal mode
consumption
current
IDDOP(1)
V
1
• FmCF=12MHz ceramic oscillation mode
• FmX’tal=32.768kHz by crystal oscillation
mode
DD
=V
2
3
DD
DD
=V
(Note 7-1)
• System clock set to 12MHz side
• Internal RC oscillation stopped
• frequency variable RC oscillation stopped
• 1/1 frequency division ratio.
• FmCF=8MHz ceramic oscillation mode
• FmX’tal=32.768kHz by crystal oscillation
mode
2.7 to 3.6
3.6
9.5
IDDOP(2)
mA
• System clock set to 8MHz side
• Internal RC oscillation stopped
• frequency variable RC oscillation stopped
• 1/1 frequency division ratio.
• FmCF=0Hz (oscillation stopped)
• FmX’tal=32.768kHz by crystal oscillation
mode
2.5 to 3.6
2.5 to 3.6
2.5 to 3.6
2.9
0.186
11.5
7.1
0.96
58
IDDOP(3)
IDDOP(4)
• System clock set to internal RC oscillation
• frequency variable RC oscillation stopped
• 1/2 frequency division ratio.
• FmCF=0Hz (oscillation stopped)
• FmX'al=32.768kHz by crystal oscillation
mode.
• System clock set to 32.768kHz side.
• Internal RC oscillation stopped
• frequency variable RC oscillation stopped
• 1/2 frequency division ratio.
• HALT mode
μA
HALT mode
consumption
current
IDDHALT(1)
IDDHALT(2)
IDDHALT(3)
V
1
DD
=V
=V
2
3
• FmCF=12MHz ceramic oscillation mode
• FmX’tal=32.768kHz by crystal oscillation
mode
DD
DD
(Note 7-1)
2.7 to 3.6
1.5
2.9
• System clock set to 12MHz side
• Internal RC oscillation stopped
• frequency variable RC oscillation stopped
• 1/1 frequency division ratio.
• HALT mode
• FmCF=8MHz ceramic oscillation mode
• FmX’tal=32.768kHz by crystal oscillation
mode
mA
2.5 to 3.6
1
1.8
• System clock set to 8MHz side
• Internal RC oscillation stopped
• frequency variable RC oscillation stopped
• 1/1 frequency division ratio.
• HALT mode
• FmCF=0Hz (oscillation stopped)
• FmX’tal=32.768kHz by crystal oscillation
mode
2.5 to 3.6
0.067
0.28
• System clock set to internal RC oscillation
• frequency variable RC oscillation stopped
• 1/2 frequency division ratio.
Note 7-1: The consumption current value includes none of the currents that flow into the output Tr and internal pull-up
resistors
Continued on next page.
No.A2150-20/26
LC87FC096A
Continued from preceding page.
Specification
typ Max
Parameter
Symbol
Pins/Remarks
Conditions
V
[V]
min
unit
DD
HALT mode
consumption
current
IDDHALT(4)
V
1
• HALT mode
DD
=V
=V
2
3
• FmCF=0Hz (oscillation stopped)
• FmX'al=32.768kHz by crystal oscillation
mode.
DD
DD
(Note 7-1)
2.5 to 3.6
7.4
49
μA
• System clock set to 32.768kHz side.
• Internal RC oscillation stopped
• frequency variable RC oscillation stopped
• 1/2 frequency division ratio.
• HOLD mode
HOLD mode
consumption
current
IDDHOLD(1)
IDDHOLD(2)
V
1
DD
• CF1=V
DD
or open (External clock mode)
2.5 to 3.6
2.5 to 3.6
0.04
5.9
20
35
μA
Timer HOLD
mode
• Timer HOLD mode
• CF1=V or open (External clock mode)
DD
consumption
current
• FmX'tal=32.768kHz by crystal oscillation
mode
Note 7-1: The consumption current value includes none of the currents that flow into the output Tr and internal pull-up
resistors
F-ROM Programming Characteristics at Ta = +10°C to +55°C, V 1 = V 2 = V 3 = 0V
SS SS SS
Specification
Typ Max
Parameter
Symbol
Pins/Remarks
Conditions
V
[V]
Min
unit
mA
DD
Onboard
IDDFW(1)
V
1
• Without CPU curent
DD
programming
current
2.7 to 3.6
7
11
Programming
time
tFW(1)
tFW(2)
• 2k byte Erasing
2.7 to 3.6
2.7 to 3.6
12
35
15
45
ms
µs
• 2 byte Programming
No.A2150-21/26
LC87FC096A
UART (Full Duplex) Operating Conditions at Ta = -40°C to +85°C, V 1 = V 2 = V 3 = 0V
SS SS SS
Specification
Parameter
Symbol
UBR
Pin/Remarks
Conditions
V
[V]
min
typ
max
unit
DD
Transfer rate
P32(UTX1),
P33(URX1),
P34(UTX2),
P35(URX2)
2.5 to 3.6
16/3
8192/3
tCYC
Data length:
Stop bits:
Parity bits:
7, 8, and 9 bits (LSB first)
1 bit (2-bit in continuous data transmission)
None
Example of Continuous 8-bit Data Transmission Mode Processing (first transmit data=55H)
Start bit
Stop bit
End of
transmission
Start of
transmission
Transmit data (LSB first)
UBR
Example of Continuous 8-bit Data Reception Mode Processing (first receive data=55H)
Stop bit
End of
reception
Start bit
Receive data (LSB first)
Start of
reception
UBR
V 1, V 1 Terminal Condition
DD SS
It is necessary to place capacitors between V 1 and V 1 as describe below.
DD SS
• Place capacitors as close to V 1 and VSS1 as possible.
DD
• Place capacitors so that the length of each terminal to the each leg of the capacitor be equal (L1 = L1’, L2 = L2’).
• Place high capacitance capacitor C1 and low capacitance capacitor C2 in parallel.
• Capacitance of C2 must be more than 0.1µF.
• Use thicker pattern for V 1 and V 1.
DD SS
L2
L1
V
V
1
SS
C1
C2
1
DD
L1’
L2’
No.A2150-22/26
LC87FC096A
Characteristics of a Sample Main System Clock Oscillation Circuit
Given below are the characteristics of a sample main system clock oscillation circuit that are measured using a Our
designated oscillation characteristics evaluation board and external components with circuit constant values with
which the oscillator vendor confirmed normal and stable oscillation.
Table 1 Characteristics of a Sample Main System Clock Oscillator Circuit with a Ceramic Oscillator
Oscillation
Circuit Constant
Operating
Voltage Range
[V]
Stabilization Time
Nominal
Vendor Name
Oscillator Name
Remarks
Frequency
C1
C2
Rf1
Rd1
typ
max
[ms]
[pF]
[pF]
[Ω]
[Ω]
[ms]
C1, C2
integrated type
C1, C2
12MHz
8MHz
CSTCE12M0G52-R0
CSTCE8M00G52-R0
CSTLS8M00G53-B0
CSTCR4M00G53-R0
CSTLS4M00G53-B0
(10)
(10)
(15)
(15)
(15)
(10)
(10)
(15)
(15)
(15)
Open
Open
Open
Open
Open
330
680
2.2 to 3.6
2.2 to 3.6
2.2 to 3.6
2.2 to 3.6
2.2 to 3.6
0.02
0.02
0.02
0.02
0.01
0.2
0.2
0.2
0.2
0.1
integrated type
C1, C2
MURATA
680
integrated type
C1, C2
1.5K
1.5K
integrated type
C1, C2
4MHz
integrated type
The oscillation stabilization time refers to the time interval that is required for the oscillation to get stabilized after VDD
goes above the operating voltage lower limit (see Fig. 4).
Characteristics of a Sample Subsystem Clock Oscillator Circuit
Given below are the characteristics of a sample subsystem clock oscillation circuit that are measured using a Our
designated oscillation characteristics evaluation board and external components with circuit constant values with
which the oscillator vendor confirmed normal and stable oscillation.
Table 2 Characteristics of a Sample Subsystem Clock Oscillator Circuit with a Crystal Oscillator
Oscillation
Operating
Voltage
Range
[V]
Circuit Constant
Stabilization Time
Nominal
Vendor
Name
Oscillator Name
Remarks
CL=7pF
Frequency
C3
C4
Rf2
Rd2
typ
[s]
max
[s]
[pF]
[pF]
[Ω]
[Ω]
EPSON
32.768kHz
MC-306
9
9
OPEN
330K
2.2 to 3.6
1.0
3.0
TOYOCOM
The oscillation stabilization time refers to the time interval that is required for the oscillation to get stabilized after the
instruction for starting the subclock oscillation circuit is executed and to the time interval that is required for the
oscillation to get stabilized after the HOLD mode is reset (see Figure 4).
Note: The components that are involved in oscillation should be placed as close to the IC and to one another as possible
because they are vulnerable to the influences of the circuit pattern.
CF1
CF2
XT1
XT2
Rf
Rf
Rd1
C2
Rd2
C4
C1
C3
X’tal
CF
Figure 1 CF Oscillator Circuit
Figure 2 XT Oscillator Circuit
0.5V
DD
Figure 3 AC Timing Measurement Point
No.A2150-23/26
LC87FC096A
V
DD
Power supply
Operating V
0V
lower limit
DD
Reset time
RES
Internal RC oscillation
tmsCF
CF1, CF2
tmsX’tal
XT1, XT2
Operating
Reset
Instruction execution
Unpredictable
mode
Reset Time and Oscillation Stabilization Time
HOLD reset
signal
HOLD reset signal
absent
HOLD reset signal valid
Internal RC oscillation
tmsCF
CF1, CF2
tmsX’tal
XT1, XT2
State
HOLD
HALT
HOLD Reset Signal and Oscillation Stabilization Time
Figure 4 Oscillation Stabilization Times
No.A2150-24/26
LC87FC096A
V
DD
R
C
Note :
RES
Determine the value of C
and R so that the
RES
RES
reset signal is present for a period of 200μs after the
supply voltage goes beyond the lower limit of the IC’s
operating voltage.
RES
RES
Figure 5 Reset Circuit
SIOCLK:
DATAIN:
DI0
DI1
DI2
DI3
DI4
DI5
DI6
DI7
DI8
DATAOUT:
DO0
DO1
DO2
DO3
DO4
DO5
DO6
DO7
DO8
Data RAM
transfer period
(SIO0 only)
tSCK
tSCKL
tSCKH
thDI
SIOCLK:
DATAIN:
tsDI
tdDO
DATAOUT:
Data RAM
transfer period
(SIO0 only)
tSCKL
tSCKHA
SIOCLK:
DATAIN:
tsDI
thDI
tdDO
DATAOUT:
Figure 6 Serial Input/Output Waveforms
tPIL
tPIH
Figure 7 Pulse Input Timing Signal Waveform
No.A2150-25/26
LC87FC096A
P
S
P
Sr
SDA
SCK
tBUF
tHD;STA tR
tF
tHD;STA
tsp
tLOW
tHIGH
tHD;DAT
tSU;DAT
tSU;STA
tSU;STO
S: Start condition
P: Stop condition
Figure 8 I2C Timing
Sir: Restart condition
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application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental
damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual
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No.A2150-26/26
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