LC88F85D0A [SANYO]
FROM 256K byte, RAM 8K byte on-chip 16-bit 1-chip Microcontroller; 从256K字节， RAM 8K字节的片上16位单芯片微控制器
| 型号： | LC88F85D0A |
| 厂家： | 
SANYO SEMICON DEVICE |
| 描述： | FROM 256K byte, RAM 8K byte on-chip 16-bit 1-chip Microcontroller |
| 文件： | 总31页 (文件大小：259K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Ordering number : ENA1954
CMOS IC
FROM 256K byte, RAM 8K byte on-chip
LC88F85D0A
16-bit 1-chip Microcontroller
Overview
The LC88F85D0A is a 16-bit microcomputer that, centered around an Xstormy16 CPU core, integrates on a single chip a
number of hardware features such as 256K bytes of flash ROM (onboard programmable), 8K bytes of RAM, five 16-bit
timers, a time base timer, a synchronous SIO interface with automatic transfer function, a single-master I2C/synchronous
SIO interface, two asynchronous SIO (UART) interfaces, a remote control receiver, LCD dedicated RAM, an LCD dot-
matrix driver, a 12-bit-resolution 8-channel AD converter, a watchdog timer, a system clock frequency divider, and a 35-
source 10-vector interrupt feature.
Features
Xstromy16 CPU
• 4G-byte address space
• General-purpose registers: 16 bits × 16
Flash ROM
• Onboard programmable with a wide range of supply voltages: 3.0 to 5.5V
• Block erasable in 512-byte/1K-byte units
• Data writing in 2-byte units
• 262144 × 8 bits
RAM
• Data: 8192 × 8 bits
• LCD display: 128 × 16 bits
* This product is licensed from Silicon Storage Technology, Inc. (USA), and manufactured and sold by
SANYO Semiconductor Co., Ltd.
Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to
"standard application", intended for the use as general electronics equipment (home appliances, AV equipment,
communication device, office equipment, industrial equipment etc.). The products mentioned herein shall not be
intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace
instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety
equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case
of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee
thereof. If you should intend to use our products for applications outside the standard applications of our
customer who is considering such use and/or outside the scope of our intended standard applications, please
consult with us prior to the intended use. If there is no consultation or inquiry before the intended use, our
customer shall be solely responsible for the use.
Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate
the performance, characteristics, and functions of the described products in the independent state, and are not
guarantees of the performance, characteristics, and functions of the described products as mounted in the
customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent
device, the customer should always evaluate and test devices mounted in the customer
's products or
equipment.
Ver.1.00
51111HKIM 20110412-S00003 No.A1954-1/31
LC88F85D0A
Minimum instruction cycle time (tCYC)
• 100ns (10MHz)
• 125ns (8MHz)
• 500ns (2MHz)
V
V
V
= 4.5 to 5.5V
= 3.0 to 5.5V
= 2.0 to 5.5V
DD
DD
DD
Ports
• Normal withstand voltage I/O ports
Ports whose I/O direction specifiable in 1-bit units:
• LCD (Pins COM16/SEG0 to COM31/SEG15 are multiplexed with COM and SEG.)
20 (P0n, P1n, P20 to P23)
LCD driver bias power supply pins
Step-up capacitor pins
16 common mode
Segment output
4 (V
1 to V
4)
LCD
LCD
2 (CUP00, CUP01)
64 (SEG0 to SEG63)
Common output
16 (COM0 to COM15)
32 common mode
Segment output
Common output
• Oscillation dedicated ports
• Reset pin
48 (SEG16 to SEG63)
32 (COM0 to COM31)
4 (XT1, XT2, CF1, CF2)
1 (RESB)
• TEST pin
1 (TEST)
• LCD port power pins
• Power pins
2 (LCDV 0, LCDV 1)
SS SS
2 (V , V
)
DD SS
LCD
• LCD power supply
• Number of dots
• Contrast
: Capacitor step-up type
: 1024 (64 segments × 16 commons) / 1536 (48 segments × 32 commons)
: Selectable from 16 levels
• LCD frame frequency : Selectable from 4 frequencies
Timers
• Timer 0: 16-bit timer that supports PWM/toggle outputs
<1> With 5-bit prescaler
<2> 8-bit PWM × 2 / 8-bit timer + 8-bit PWM split mode selectable
<3> Clock source selectable from system clock, OSC0, OSC1, and internal RC oscillator
• Timer 1: 16-bit timer with a capture register
<1> With 5-bit prescaler
<2> Can be divided into 8-bit timer × 2 channels
<3> Clock source selectable from system clock, OSC0, OSC1, and internal RC oscillator
• Timer 3: 16-bit timer that supports PWM/toggle outputs
<1> With 8-bit prescaler
<2> 8-bit timer × 2 channels / 8-bit timer + 8-bit PWM split mode selectable
<3> Clock source selectable from system clock, OSC0, OSC1, and external events
• Timer 4: 16-bit timer that supports toggle output
<1> Clock source selectable from system clock and prescaler 0
• Timer 5: 16-bit timer that supports toggle output
<1> Clock source selectable from system clock and prescaler 0
* The prescaler 0 consists of 4 bits and its clock source is selectable from the system clock, OSC0, and OSC1.
• Base timer
<1> The clock can be selected from OSC0 (32.768kHz crystal oscillator) and the frequency-divided output of the
system clock.
<2> Interrupts can be generated in 7 time schemes.
Realtime clock (RTC)
<1> Calendar function from January 1, 2000 to December 31, 2799 (with automatic leap year compensation)
<2> Independent counter configuration for century, year, month, day, hour, minute, and second
<3> Programmable count clock correction function
No.A1954-2/31
LC88F85D0A
Serial interfaces
• SIO0: 8-bit synchronous SIO
<1> LSB first/MSB first selectable
<2> Supports communication of less than 8 bits (1 to 8 bits specifiable).
<3> Built-in 8-bit baudrate generator (transfer clock cycles of 4 tCYC to 512 tCYC)
<4> Automatic continuous data transfer (9 to 32768 bits specifiable in 1-bit units)
<5> Interval function (interval time specifiable in 0 to 64 tSCK units)
<6> Wakeup function
• SMIIC0: Single-master I2C/8-bit synchronous SIO
Mode 0: Single-master master mode communication
Mode 1: 8-bit synchronous serial I/O (MSB first)
• UART0
<1> Data length: 8 bits (LSB first)
<2> Start bits: 1 bit
<3> Stop bits: 1 bit
<4> Parity bits: None/even parity/odd parity
<5> Transfer rate: 4/8 tCYC
<6> Baudrate clock source: The P07 input signal is used as a 1 cycle signal (T0PWMH can be used as the clock
source) or a timer 4 period.
<7> Full duplex communication
• UART2
<1> Data length: 8 bits (LSB first)
<2> Start bits: 1 bit
<3> Stop bits: 1/2 bit
<4> Parity bit: None/even parity/odd parity
<5> Transfer rate: 8 to 4096 tCYC
<6> Baudrate clock source: System clock/OSC0/OSC1/P21 input signal
<7> Wakeup function
<8> Full duplex communication
AD converter
<1> 8/12-bit resolution selectable
<2> Analog inputs: 12 channels
<3> Comparator mode
<4> Automatic reference voltage generation
Watchdog timer
<1> Runs on the base timer + internal watchdog timer dedicated counter.
<2> Interrupt or reset signals selectable
Infrared remote control receiver
<1> Noise rejection function
(Noise filter time constant: Approx. 120μs when the 32.768kHz crystal oscillator is selected as the reference
clock source)
<2> Supports PPM (Pulse Position Modulation), Manchester and other encoding systems.
<3> HOLDX mode release function
Interrupts (peripheral function)
Either "Normal" or "LC888300 Compatible" mode is selectable by user option.
* Note: The "LC888300 Compatible" mode is an option that is available to provide compatibility between this model
and the LC888300. It is to be unavailable in future developed models.
<1> Provides three levels of multiplex interrupt control. Any interrupt request of the level equal to or lower than the
current interrupt is not accepted.
<2> When interrupt requests to two or more vector addresses occur at the same time, the interrupt of the highest level
takes precedence over the other interrupts. For interrupts of the same level, the interrupt into the smallest vector
address takes precedence.
No.A1954-3/31
LC88F85D0A
• Normal mode: 35 sources (15 modules), 10 vectors
No.
Vector
08000H
08004H
08008H
08018H
0801CH
08020H
08024H
08030H
08038H
0803CH
Interrupt Module
1
Watchdog timer (1)
Base timer (2)
Timer 0 (2)
2
3
4
Timer 1 (2)/UART2 (4)
SMIIC0 (1)
5
6
Timer 3 (2)/infrared remote control receiver (4)
Timer 4 (1)
7
8
ADC (1)/timer 5 (1)
9
SIO0 (2)
10
Port 0 (3)/RTC2 (1)/SEGINT (8)
• LC888300 Compatible mode: 35 sources (15 modules), 13 vectors
No.
Vector
08000H
08004H
08008H
08018H
0801CH
08020H
08024H
08028H
0802CH
08030H
08034H
08038H
0803CH
Interrupt Module
1
Watchdog timer (1)
Base timer (2)
Timer 0 (2)
2
3
4
SIO0 (2)
5
Timer 1 (2)
6
UART2 (4)
7
Timer 3 (2)
8
Timer 4 (1)
9
Timer 5 (1)
10
11
12
13
ADC (1)
SMIIC0 (1)
Infrared remote control receiver (4)
Port 0 (3)/RTC2 (1)/SEGINT (8)
• Priority levels X > H > L
• When interrupts of the same level occur at the same time, an interrupt with a smaller vector address is given priority.
• The number in parentheses indicates the number of sources in a module.
Subroutine stack: 8K-byte RAM area
• Subroutine calls that automatically save the PSW, interrupt vector call: 6 bytes
• Subroutine calls that do not automatically save the PSW: 4 bytes
Multiplication/division instructions
• 16 bits × 16 bits
• 16 bits ÷ 16 bits
• 32 bits ÷ 16 bits
(18 tCYC execution time)
(18 to 19 tCYC execution time)
(18 to 19 tCYC execution time)
■Oscillator circuits
• RC oscillator circuit (internal):
• CF oscillator circuit:
• RC oscillator circuit (external R
For system clock
For system clock (OSC1)
): For system clock (OSC1)
CR1
• Crystal oscillator circuit (Rf built-in): For low-speed system clock (OSC0) (option available)
• RC oscillator circuit (external R
• SLRC oscillator circuit (internal):
): For low-speed system clock (OSC0)
CR0
For system clock (used during exception processing)
■System clock frequency divider function
• Can run on low consumption current.
• Supports frequency-dividing of 1/1 to 1/128 of the system clock
Standby function
• HALT mode: Halts instruction execution while allowing the peripheral circuits to continue operation.
1) Oscillation is not halted automatically.
2) HALT mode is released by a system reset or an interrupt .
Continued on next page.
No.A1954-4/31
LC88F85D0A
Continued from preceding page.
• HOLD mode: Suspends instruction execution and the operation of the peripheral circuits.
1) OSC1, RC, and OSC0 oscillations automatically stop.
2) There are five ways of releasing the HOLD mode:
<1> Setting the reset pin to the low level
<2> Having an interrupt source established at port 0
<3> Having an interrupt source established at SIO0
<4> Having an interrupt source established at UART2
<5> Having an interrupt source established at SEGINT
• HOLDX mode: Suspends instruction execution and the operation of all the circuits except the peripheral circuits
running on OSC0.
1) OSC1 and RC oscillators automatically stop operation.
2) OSC0 retains the state established when the HOLDX mode is entered.
3) There are seven ways of releasing the HOLDX mode:
<1> Setting the reset pin to the low level
<2> Having an interrupt source established at port 0
<3> Having an interrupt source established at SIO0
<4> Having an interrupt source established at UART2
<5> Having an interrupt source established at SEGINT
<6> Having an interrupt source established in the base timer or RTC2 circuit
<7> Having an interrupt source established in the infrared remote control receiver circuit
On-chip debugger function
• Supports software debugging with the microcontroller mounted on the target board.
• Supports source line debugging, tracing, breakpoint manipulation, and realtime display.
• Single-wire communication
Operating temperature
• -20 to +75°C
Package form
• TQFP120 (14×14) (lead-free type)
Development tools
• On-chip debugger: EOCUIF1 + LC88F85D0A
Package Dimensions
unit : mm (typ)
3257A
16.0
14.0
120
1
0.15
0.125
0.4
(1.2)
SANYO : TQFP120(14X14)
No.A1954-5/31
LC88F85D0A
Pad Assignment
• Chip size (X × Y)
• PAD opening siz
• PAD pitch
: 4.10mm × 3.40mm
: 59μm
: 80μm
• Chip thickness
: 280μm 20μm
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
□
□
□
□
□
□
□
□
□
□
□
□
□
□
□
□
□
□
□
□
□
□
□
□
□
□
□
□
□
□
□
□
□
□
□
□
□
□
□
□
□
□
□
□
□
62
61
60
59
58
57
56
55
54
53
□
52
51
50
49
48
47
46
45
□
□
□
□
□
□
□
Y
X
(0, 0)
□
□
□
□
□
□
□
□
44
43
42
41
40
39
38
37
□
36
35
34
33
□
□
□
135
136
□
□
• Note: Package pin numbers differ from chip pad numbers. The numbers shown in the above figure are pad numbers.
No.A1954-6/31
LC88F85D0A
Table of PAD Coordinates
Coordinate
Coordinate
Pad No.
Pin Name
Pad No.
Pin Name
X μm
-1647.9
-1567.9
-1483.2
-1403.2
-1184.0
-890.0
-781.5
-670.0
-494.5
-374.5
-263.5
-165.0
-85.0
Y μm
X μm
1958.5
1958.5
1958.5
1958.5
1958.5
1919.9
1919.9
1919.9
1919.9
1919.9
1919.9
1919.9
1919.9
1919.9
1919.9
1420.0
1300.0
1190.0
1080.0
990.0
910.0
830.0
750.0
670.0
590.0
510.0
430.0
350.0
270.0
190.0
110.0
30.0
Y μm
208.2
298.2
388.2
478.2
568.2
710.0
790.0
870.0
950.0
1030.0
1110.0
1190.0
1280.0
1370.0
1460.0
1569.9
1569.9
1569.9
1569.9
1569.9
1569.9
1569.9
1569.9
1569.9
1569.9
1569.9
1569.9
1569.9
1569.9
1569.9
1569.9
1569.9
1569.9
1569.9
1569.9
1569.9
1569.9
1569.9
-
1
V
V
V
V
4
3
2
1
-1569.9
-1569.9
-1569.9
-1569.9
-1569.9
-1569.9
-1569.9
-1569.9
-1569.9
-1569.9
-1569.9
-1569.9
-1569.9
-1569.9
-1569.9
-1569.9
-1569.9
-1569.9
-1569.9
-1569.9
-1569.9
-1569.9
-1569.9
-1569.9
-1569.9
-1569.9
-1569.9
-1569.9
-1569.9
-1569.9
-1569.9
-1569.9
-1415.0
-1325.0
-1192.0
-1057.0
-871.8
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
SEG52
SEG51
SEG50
SEG49
SEG48
SEG47
SEG46
SEG45
SEG44
SEG43
SEG42
SEG41
SEG40
SEG39
SEG38
LCD
LCD
LCD
2
3
4
LCD
TST
5
6
XT2
XT1
7
8
RESB
9
V
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
DD
CF1
CF2
10.0
V
110.0
SS
210.0
LCDV
1
SS
P00
P01
300.0
SEG37
SEG36
SEG35
SEG34
SEG33
SEG32
SEG31
SEG30
SEG29
SEG28
SEG27
SEG26
SEG25
SEG24
SEG23
SEG22
SEG21
SEG20
SEG19
SEG18
SEG17
SEG16
-
380.0
P02
460.0
P03
540.0
P04
620.0
P05
700.0
P06
780.0
P07
860.0
P10
940.0
P11
1020.0
1100.0
1180.0
1260.0
1340.0
1420.0
1500.0
1919.9
1919.9
1919.9
1919.9
1958.5
1958.5
1958.5
1958.5
1958.5
1958.5
1958.5
1958.5
1958.5
1958.5
1958.5
P12
P13
P14
P15
P16
P17
P20
-50.0
P21
-130.0
-210.0
-290.0
-370.0
-450.0
-
P22
P23
SEG63
SEG62
SEG61
SEG60
SEG59
SEG58
SEG57
SEG56
SEG55
SEG54
SEG53
-781.8
-691.8
-601.8
COM31/SEG15
-620.0
-
1569.9
-
-511.8
-
-421.8
COM30/SEG14
-780.0
-
1569.9
-
-331.8
-
-241.8
COM29/SEG13
-940.0
-
1569.9
-
-61.8
-
28.2
COM28/SEG12
-
-1100.0
-
1569.9
-
118.2
Continued on next page.
No.A1954-7/31
LC88F85D0A
Continued from preceding page.
Coordinate
Coordinate
Pad No.
Pin Name
Pad No.
Pin Name
X μm
Y μm
X μm
Y μm
-
95
COM27/SEG11
-1260.0
1569.9
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
-
COM16/SEG0
COM15
COM14
COM13
COM12
COM11
COM10
COM9
-
96
-
-
-
-1919.9
-1919.9
-1919.9
-1919.9
-1919.9
-1919.9
-1919.9
-1919.9
-1919.9
-1919.9
-1919.9
-1919.9
-1919.9
-1919.9
-1919.9
-1919.9
-1919.9
-1919.9
-1919.9
-1919.9
60.0
97
COM26/SEG10
-1420.0
1569.9
-20.0
98
-
-
-
-100.0
-180.0
-260.0
-340.0
-420.0
-500.0
-580.0
-660.0
-740.0
-820.0
-900.0
-980.0
-1060.0
-1140.0
-1220.0
-1320.0
-1443.3
-1523.3
99
COM25/SEG9
-1580.0
1569.9
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
-
-
-
COM24/SEG8
-1919.9
1340.0
-
-
-
COM23/SEG7
-1919.9
1180.0
-
-
-
COM8
COM22/SEG6
-1919.9
1020.0
COM7
-
-
-
COM6
COM21/SEG5
-1919.9
860.0
COM5
-
-
-
700.0
-
COM4
COM20/SEG4
-1919.9
COM3
-
-
COM2
COM19/SEG3
-1919.9
-
540.0
-
COM1
-
COM0
COM18/SEG2
-
-1919.9
-
380.0
-
LCSV
0
SS
CUP00
CUP01
COM17/SEG1
-1919.9
220.0
Note:
• The coordinate values shown in the above table represent the coordinates of the pin pads measured with the center
coordinates of the IC set to (0, 0).
• There are three pads for each of the V
DD
and V pins. They should be triple bonded.
SS
No.A1954-8/31
LC88F85D0A
Pin Assignment
91
92
93
94
95
96
97
98
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
SEG38
SEG39
SEG40
SEG41
SEG42
SEG43
SEG44
SEG45
COM24/SEG8
COM23/SEG7
COM22/SEG6
COM21/SEG5
COM20/SEG4
COM19/SEG3
COM18/SEG2
COM17/SEG1
COM16/SEG0
COM15
99
SEG46
SEG47
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
SEG48/SGND15/SGIN15
SEG49/SGND14/SGIN14
SEG50/SGND13/SGIN13
SEG51/SGND12/SGIN12
SEG52/SGND11/SGIN11
SEG53/SGND10/SGIN10
SEG54/SGND9/SGIN9
SEG55/SGND8/SGIN8
SEG56/SGND7/SGIN7/SGINT7
SEG57/SGND6/SGIN6/SGINT6
SEG58/SGND5/SGIN5/SGINT5
SEG59/SGND4/SGIN4/SGINT4
SEG60/SGND3/SGIN3/SGINT3
SEG61/SGND2/SGIN2/SGINT2
SEG62/SGND1/SGIN1/SGINT1/T3IH
SEG63/SGND0/SGIN0/SGINT0/T3IL
P23/AN3/SM0DA
COM14
COM13
COM12
COM11
COM10
COM9
COM8
COM7
COM6
COM5
COM4
COM3
COM2
COM1
COM0
LC88F85D0A
LCSV
CUP00
CUP01
0
SS
P22/AN2/SM0CK
P21/AN1/T5O
P20/AN0/T4O/RMIN
Top view
SANYO: TQFP120 (14×14) “Lead-free Type”
No.A1954-9/31
LC88F85D0A
System Block Diagram
CF
RC
RC
X’tal
RC
Low
speed
RC
Base timer
Watchdog timer
Timer 0
Xstormy16
CPU
FLASH ROM
RAM
Timer 1
On-chip debugger
Timer 3
Port 0
Port 1
Port 2
Timer 4
Timer 5
UART0
UART2
AD
RTC2
SIO0
SMIIC0
LCD control
Infrared
remote control
receiver
LCD display RAM
No.A1954-10/31
LC88F85D0A
Pin Description
Pin Name
I/O
Description
V
-
-
-
-
- Power supply pin
+ Power supply pin
SS
V
DD
V
1 to 4
LCD bias power source (connected to capacitors)
LCD port power source (-)
LCD
LCDV 0,
SS
LCDV
1
SS
CUP00, CUP01
-
Switching pins for generating the LCD drive voltage. A capacitor must be connected across both pins.
PORT 0
I/O
• 8-bit I/O port
P00 to P07
• I/O specifiable in 1 bit units
• Pull-up registers can be turned on and off in 1-bit units.
• HOLD releaset inputs (P00 to P03, P04, P05)
• Port 0 interrupt inputs (P00 to P03, P04, P05)
• Pin functions
P00 (AN8) to P07 (AN15): AD converter inputs
P06: Timer 0L output
P07: Timer 0H output/UART0 clock input
• 8-bit I/O port
PORT 1
I/O
P10 to P17
• I/O specifiable in 1-bit units
• Pull-up registers can be turned on and off in 1-bit units.
• Pin functions
P10: SIO0 data output
P11: SIO0 data input/bus input/output
P12: SIO0 clock input/output
P13: Timer 3L output
P14: Timer 3H output/UART0 receive
P15: UART0 transmit
P16: UART2 receive
P17: UART2 transmit
PORT 2
I/O
• 4-bit I/O port
P20 to P23
• I/O specifiable in 1-bit units
• Pull-up registers can be turned on and off in 1-bit units.
• Pin functions
P20 (AN0) to P23 (AN3): AD converter inputs
P20: Timer 4 output/remote controller receive
P21: Timer 5 output
P22: SMIIC0 clock input/output
P23: SMIIC0 bus input/output/data input
• LCD common output
COM0 to COM15
O
O
COM16/SEG0 to
COM31/SEG15
SEG16 to SEG47
• LCD common output/segment output
Common output/segment output switched by a register
• LCD segment output
O
SEG48 to SEG63
I/O
• LCD segment output
• SEG63-SEG48: General-purpose N-channel open drain output/general-purpose input
SEG63-SEG48: LCD output in 4-bit units/general-purpose N-channel open drain output/general-purpose
input selectable
• SEG63-SEG56: Interrupt function (4-bit units)
Chatter removal sampling frequency select (4-bit units)
Level/edge sense mode select (4-bit units)
Hi/low level or rising/falling edge sense mode select (1-bit units)
• SEG63-SEG62: Timer 3 external input
TEST
I/O
• TEST pin
• On-chip debugger communication pin
• An external 100kΩ pull-down resistor must be connected.
Reset pin
RESB
CF1
CF2
XT1
I
I
Ceramic oscillator input/RC oscillator resistor to be connected
Ceramic oscillator output
O
I
32.768kHz crystal oscillator input/RC oscillator resistor to be connected
32.768kHz crystal oscillator output
XT2
O
No.A1954-11/31
LC88F85D0A
Port Output Types
The table below lists the types of port outputs and the presence/absence of a pull-up resistor.
Data can be read into any input port even if it is in the output mode.
Port Name
P00 to P07
Options Selected in Units of
1 bit
Output Type
Pull-up Resistor
Programmable
CMOS
P10 to P17
1 bit
Multiplexed pin outputs are programmable either as CMOS
or N-channel open drain output.
N-channel open drain
Programmable
P20 to P23
SEG48 to SEG63
4 bits
None
(LCD segment output)
Table of User Options
Option Name
Option
Description
X'tal OSC (*1)
Normal
Normal XT mode
Low Power
Normal
Low power XT mode
Interrupt Vector (*2)
Interrupt vector switching
LC888300 Compatible
*1 The circuit constant values of the external components and oscillation stabilization time differ between the normal
XT mode and low power XT mode.
*2 The "LC888300 Compatible" mode is an option that is available to provide compatibility between this model and the
LC888300. It is to be unavailable in future models.
No.A1954-12/31
LC88F85D0A
Application circuit
LCD panel 64×16/48×32
CUP01
CUP00
C1
P00
P01
P02
P03
P04
P05
P06
P07
I/O
C2
C3
V
LCD
V
LCD
4
3
C4
C5
V
LCD
V
LCD
2
1
LC88F85D0A
P10 (SIO0-OUT)
P11 (SIO0-IN)
P12 (SIO0-CLK)
P13
P14
P15
I/O
2.3V to 5.5V
V
DD
+
P16 (UART2-RX)
P17 (UART2-TX)
UART device
Pulse output
RESB
C
DEN
C
RES
P20
P21
P22
P23
I/O
V
SS
0
1
LCDV
SS
SS
LCDV
On-chip
debugger
TST
R
TST
*1: Crystal oscillation
*2: Internal RC oscillation
*3: Ceramic oscillation
X'tal
CF
C
GC
*3
C
*1
GX
C
DC
C
DX
C
R
CR1
C
R
CR0
CR1
CR0
*4
*5
X'tal
Crystal resonator
C
Trimmer capacitor
GX
C
Capacitor for X’tal oscillator
Resistor for low-speed oscillator
DX
R
*4: RC oscillation type
CR0
C
Capacitor for low-speed oscillation stabilization
*4: RC oscillation type (*1)
CR0
(*1)
CF
0.1μF capacitor is recommended when using XT1/XT2 as the system clock source.
Ceramic resonator
C
Capacitor for CF oscillator
Capacitor for CF oscillator
GC
C
DC
R
C
Resistor for high-speed oscillation
Capacitor for high-speed oscillation stabilization
Capacitor
*5: RC oscillation type
*5: RC oscillation type
CR1
CR1
C1 to C5
C
Electrolytic capacitor
DEN
C
Capacitance for RESB
RES
R
Resistor used when using the on-chip debugger
TST
No.A1954-13/31
LC88F85D0A
Absolute Maximum Ratings at Ta = 25°C, V = LCDV 0 = LCDV 1 = 0V
SS
SS
SS
Specification
typ max
Parameter
Symbol
max
Pin/Remarks
DD
Conditions
V
[V]
min
-0.3
unit
DD
Maximum supply
voltage
V
V
V
V
V
DD
DD
+6.5
+6.5
LCD supply
voltage
max
2 to V
4
V
V
LCD
LCD LCD
DD
-0.3
Maximum LCD
supply voltage
Input voltage
LCD max
SEG0 to SEG63
, V
4
V
DD LCD
-0.3
-0.3
-0.3
+6.5
+0.3
+0.3
COM0 to COM31
CF1, XT1, RESB
V (1)
I
V
V
DD
Input/output
voltage
V
(1)
Ports 0, 1, 2
SEG63 to SEG48
Ports 0, 2
IO
DD
Peak output
current
IOPH(1)
CMOS output select
Per 1 applicable pin
Per 1 applicable pin
-5
-14
-3
IOPH(2)
IOMH(1)
Port 1
Mean output
current
Ports 0, 2
CMOS output select
Per 1 applicable pin
CMOS output select
Per 1 applicable pin
Total of all applicable pins
(Note 1-1)
IOMH(2)
Port 1
-9
Total output
current
ΣIOAH(1)
ΣIOAH(2)
ΣIOAH(3)
IOPL(1)
Ports 0, 2
Port 1
-22.5
-25
Total of all applicable pins
Total of all applicable pins
Per 1 applicable pin
Ports 0, 1, 2
Ports 0, 2
Port 1
-47.5
mA
Peak output
current
13
17
IOPL(2)
Per 1 applicable pin
Mean output
current
IOML(1)
IOML(2)
Ports 0, 2
Port 1
Per 1 applicable pin
7.5
Per 1 applicable pin
10.5
35
(Note 1-1)
Total output
current
ΣIOAL(1)
ΣIOAL(2)
ΣIOAL(3)
Pd max
Topr
Ports 0, 2
Port 1
Total of all applicable pins
Total of all applicable pins
Total of all applicable pins
Ta=-20 to +75°C
60
80
Ports 0, 1, 2
Allowable power
dissipation
250
+75
mW
Operating ambient
temperature
-20
-65
°C
Storage ambient
temperature
Tstg
+125
Note 1-1: The mean output current is a mean value measured over 100ms.
No.A1954-14/31
LC88F85D0A
Allowable Operating Conditions at Ta = -20°C to +75°C, V = LCDV 0 = LCDV 1 = 0V
SS SS SS
Ratings
typ
Parameter
Symbol
Pin/Remarks
Conditions
V
[V]
min
max
5.5
unit
DD
Operating
V
(1)
V
0.098μs≤tCYC≤66μs
0.123μs≤tCYC≤66μs
0.490μs≤tCYC≤66μs
4.5
3.0
2.0
DD
DD
supply voltage
(Note2-1)
5.5
5.5
LCD drive
voltage
V
(1)
V
V
2 to V 4
LCD
LCD
LCD
5.5
Memory
VHD
RAM and register contents
sustained in HOLD mode.
DD
sustaining
supply voltage
High level
input voltage
2.0
DD
5.5
V
V
(1)
Ports 0, 1, 2
Output disabled
Output disabled
0.30V
IH
V
DD
+0.70
V
V
(2)
CF1, RESB
Ports 0, 1, 2
0.75V
V
IH
DD
DD
Low level
(1)
0.10V
IL
DD
+0.40
V
SS
input voltage
V
(2)
CF1, RESB
V
0.25V
IL
SS
DD
66
Instruction
cycle time
(Note 2-2)
tCYC
4.5 to 5.5
3.0 to 5.5
2.0 to 5.5
0.098
0.123
0.490
μs
66
66
External
FEXCF(1)
CF1
• CF2 pin open
4.5 to 5.5
3.0 to 5.5
2.0 to 5.5
0.1
0.1
0.1
10
8
system clock
frequency
• System clock frequency
division ratio=1/1
• External system clock
duty=50±5%
MHz
2
Oscillation
frequency
range
FmCF(1)
FmCF(2)
FmCF(3)
CF1,CF2
CF1,CF2
CF1,CF2
10MHz ceramic oscillation
See Fig. 1.
4.5 to 5.5
3.0 to 5.5
2.4 to 5.5
10
8
8MHz ceramic oscillation
See Fig. 1.
(Note 2-3)
MHz
4MHz ceramic oscillation
See Fig. 1.
4
FmRC
Internal RC oscillation
2.0 to 5.5
2.0 to 5.5
0.5
18
1.0
30
2.0
45
FmSLRC
FsX'tal
Internal SLRC oscillation
XT1, XT2
CF1
32.768kHz crystal oscillation
See Fig. 2.
2.2 to 5.5
2.4 to 5.5
2.0 to 5.5
2.2 to 5.5
32.768
FmRC1(1)
FmRC1(2)
FsRC0
High-speed RC oscillation
(Note 2-4)
400
400
30
4200
2000
80
kHz
CF1
High-speed RC oscillation
(Note 2-4)
XT1
Low-speed RC oscillation
(Note 2-4)
Note2-1: V
must be held greater than or equal to 3.0V when onboard writing to flash ROM.
DD
Note2-2: Relationship between tCYC and oscillation frequency is 1/FmCF at a frequency division ratio of 1/1 and
2/FmCF at a division ratio of 1/2.
Note2-3: See Tables 1 and 2 for the oscillation constants.
Note2-4: Ta=0°C to 60°C
No.A1954-15/31
LC88F85D0A
Electrical Characteristics at Ta = -20°C to +75°C, V = LCDV 0 = LCDV 1 = 0V
SS
SS
SS
Specification
typ
Parameter
Symbol
(1)
Pin/Remarks
Conditions
V
[V]
min
max
unit
DD
High level input
current
I
I
Ports 0, 1, 2
Output disabled
Pull-up resistor off
=V
IH
RESB
V
2.0 to 5.5
2.7 to 5.5
1
μA
IN DD
(including output Tr off
leakage current)
Low level input
current
(1)
IL
Ports 0, 1, 2
Output disabled
Pull-up resistor off
V
=V
-1
-1
μA
IN SS
(including output Tr off
leakage current)
High-level output
voltage
V
V
V
V
(1)
Ports 0, 1, 2
I
I
I
I
=-1.0mA
=-0.4mA
=-0.1mA
=-25μA
4.5 to 5.5
3.0 to 5.5
2.0 to 5.5
V
DD
OH
OH
OH
OH
OH
OH
OH
OH
(2)
(3)
(4)
V
V
-0.4
-0.4
DD
DD
COM0 to COM31
SEG0 to SEG63
Ports 0, 1, 2
V
4
LCD
-0.05
2.0 to 5.5
2.0 to 5.5
V
(5)
I
=-10μA
V 4
LCD
OH
OH
-0.05
V
Low level output
voltage
V
V
V
V
(1)
(2)
(3)
(4)
I
I
I
I
(1)=10mA
(1)=1.6mA
(1)=0.7mA
4.5 to 5.5
3.0 to 5.5
2.0 to 5.5
1.5
0.4
0.4
OL
OL
OL
OL
OL
OL
OL
COM0 to COM31
SEG0 to SEG63
Ports 0, 1, 2
=25μA
V
SS
+0.05
OLH
2.0 to 5.5
2.0 to 5.5
V
(5)
I
=10μA
V
SS
+0.05
OL
OL
Pull-up resistance
Rpu(1)
Rpu(2)
VHYS
CP
V
=0.9V
4.5 to 5.5
2.0 to 4.5
2.0 to 5.5
15
18
35
55
80
OH
DD
kΩ
180
Hysteresis voltage
Pin capacitance
Ports 0, 1, 2 RESB
All pins
0.1V
V
DD
For pins other than that
under test
V
=V
2.0 to 5.5
10
pF
IN SS
f=1MHz
Ta=25°C
No.A1954-16/31
LC88F85D0A
LCD Drive Voltage at Ta = -20°C to +75°C, V = LCDV 0 = LCDV 1 = 0V
SS
Special notes: 0.1μF capacitors are connected to V
SS
SS
1, V
LCD
2, V
LCD
3, and V
4. (with no panel load)
LCD
LCD
Specification
Parameter
Symbol
Pin/Remarks
Conditions
V
[V]
min
typ
max
unit
DD
LCD drive voltage
V
1
V
V
Contrast “00”
Contrast “01”
Contrast “02”
Contrast “03”
Contrast “04”
Contrast “05”
Contrast “06”
Contrast “07”
Contrast “08”
Contrast “09”
Contrast “10”
Contrast “11”
Contrast “12”
Contrast “13”
Contrast “14”
Contrast “15”
1.030
1.045
1.060
1.075
1.090
1.105
1.120
1.135
1.150
1.165
1.180
1.195
1.210
1.225
1.240
1.255
LCD
DD
1
LCD
Typ
×0.88
Typ
×1.10
2.0 to 5.5
V
V
V
V
2
3
4
2×V
1
1
1
LCD
LCD
LCD
LCD
LCD
LCD
3×V
4×V
No.A1954-17/31
LC88F85D0A
Serial I/O Characteristics at Ta = -20°C to +75°C, V = LCDV 0 = LCDV 1 = 0V
SS SS SS
SIO0 Serial I/O Characteristics (When wakeup function is not in used) (Note 4-1-1)
Specification
Parameter
Frequency
Symbol
tSCK(1)
Pin/Remarks
SCK0(P12)
Conditions
• See Fig. 6.
V
[V]
min
typ
max
unit
DD
4
2
2
Low level
tSCKL(1)
tSCKH(1)
tSCKHA(1)
pulse width
High level
pulse width
• Automatic communication
mode
2.0 to 5.5
6
tCYC
• See Fig. 6.
tSCKHBSY(1a)
tSCKHBSY(1b)
• Automatic communication
mode
23
• See Fig. 6.
• Mode other than automatic
communication mode
• See Fig. 6.
4
4
Frequency
tSCK(2)
SCK0(P12)
• CMOS output type selected
• See Fig. 6.
Low level
tSCKL(2)
tSCKH(2)
tSCKHA(2)
1/2
1/2
pulse width
High level
pulse width
tSCK
• Automatic communication
mode
6
2.0 to 5.5
• CMOS output type selected
• See Fig. 6.
tSCKHBSY(2a)
• Automatic communication
mode
tCYC
4
4
23
• CMOS output type selected
• See Fig. 6.
tSCKHBSY(2b)
tsDI(1)
• Mode other than automatic
communication mode
• See Fig. 6.
Data setup time
Data hold time
SI0(P11),
SB0(P11)
• Specified with respect to
rising edge of SIOCLK.
• See Fig. 6.
0.03
0.03
2.0 to 5.5
thDI(1)
Output
tdD0(1)
SO0(P10),
SB0(P11)
• (Note4-1-2)
• (Note4-1-2)
delay time
μs
1tCYC
+0.05
2.0 to 5.5
tdDO(2)
1tCYC
+0.05
Note 4-1-1: These specifications are theoretical values. Margins must be allowed according to the actual operating
conditions.
Note 4-1-2: Specified with respect to the falling edge of SIOCLK. Specified as the time up to the time the output state is
changed in the open drain output mode. See Fig. 6.
No.A1954-18/31
LC88F85D0A
SIO1 Serial I/O Characteristics (When wakeup function is not in used) (Note 4-2-1)
Specification
typ max
Parameter
Period
Symbol
tSCK(3)
Pin/Remarks
SCK0(P12)
Conditions
• See Fig. 6.
V
[V]
min
unit
DD
2
1
1
2
Low level
tSCKL(3)
tSCKH(3)
tSCKHBSY(3)
tsDI(2)
pulse width
High level
pulse width
2.0 to 5.5
tCYC
Data setup time
Data hold time
SI0(P11),
SB0(P11)
• Specified with respect to
rising edge of SIOCLK.
• See Fig. 6.
0.03
0.03
2.0 to 5.5
thDI(2)
tdD0(3)
μs
Output
SO0(P10),
SB0(P11)
• (Note4-2-2)
delay time
1tCYC
+0.05
2.0 to 5.5
Note 4-2-1: These specifications are theoretical values. Margins must be allowed according to the actual operating
conditions.
Note 4-2-2: Specified with respect to the falling edge of SIOCLK. Specified as the time up to the time the output state is
changed in the open drain output mode. See Fig. 6.
SMIIC0 Simple SIO Mode I/O Characteristics
Specification
Parameter
Period
Symbol
Pin/Remarks
Conditions
V
[V]
min
typ
max
unit
DD
tSCK(7)
SM0CK
(P22)
• See Fig. 6.
4
2
2
4
Low level
pulse width
High level
pulse width
Period
tSCKL(7)
tSCKH(7)
tSCK(8)
tSCKL(8)
tSCKH(8)
tsDI(5)
2.0 to 5.5
2.0 to 5.5
2.0 to 5.5
2.0 to 5.5
tCYC
SM0CK
(P22)
• CMOS output type selected
• See Fig. 6.
Low level
pulse width
1/2
1/2
tSCK
High level
pulse width
Data setup time
SM0DA
(P23)
• Specified with respect to
rising edge of SIOCLK
• See Fig. 6.
0.03
0.03
Data hold time
thDI(5)
tdD0(7)
μs
Output delay time
SM0DA
(P23)
• Specified with respect to
falling edge of SIOCLK
• Specified as the time up to
the beginning of output
change .
1tCYC
+0.05
• See Fig. 6.
Note 4-3-1: These specifications are theoretical values. Margins must be allowed according to the actual operating
conditions.
No.A1954-19/31
LC88F85D0A
SMIIC0 I2C Mode I/O Characteristics
Specification
Parameter
Period
Symbol
Pin/Remarks
Conditions
V
[V]
min
typ
max
unit
Tfilt
DD
tSCL
SM0CK
(P22)
• See Fig. 8.
5
Low level
pulse width
High level
pulse width
Period
tSCLL
tSCLH
tSCLx
tSCLLx
tSCLHx
tsp
2.0 to 5.5
2.5
2
SM0CK
(P22)
• Specified as the time up to
the beginning of output
change.
10
Low level
pulse width
2.0 to 5.5
2.0 to 5.5
1/2
1/2
tSCL
Tfilt
High level
pulse width
SM0CK, SM0DA pin
input spike suppression
time
SM0CK(P22)
SM0DA(P23)
• See Fig. 8.
• See Fig. 8.
1
Start-to-stop
period bus
release time
tBUF
SM0CK(P22)
SM0DA(P23)
2.5
Tfilt
tBUFx
SM0CK(P22)
SM0DA(P23)
• Standard clock mode
• Specified as the time up to
the beginning of output
change.
2.0 to 5.5
2.0 to 5.5
2.0 to 5.5
5.5
1.6
μs
• High-speed clock mode
• Specified as the time up to
the beginning of output
change.
Start/restart
condition hold
time
tHD;STA
SM0CK(P22)
SM0DA(P23)
• When SMIIC register
control bit I2CSHDS=0
• See Fig. 8.
2.0
2.5
Tfilt
• When SMIIC register
control bit I2CSHDS=1
• See Fig. 8.
tHD;STAx
SM0CK(P22)
SM0DA(P23)
• Standard clock mode
• Specified as the time up to
the beginning of output
change.
4.1
1.0
μs
Tfilt
μs
• High-speed clock mode
• Specified as the time up to
the beginning of output
change.
Restart condition
setup time
tSU;STA
SM0CK(P22)
SM0DA(P23)
• See Fig. 8.
1.0
tSU;STAx
SM0CK(P22)
SM0DA(P23)
• Standard clock mode
• Specified as the time up to
the beginning of output
change.
5.5
1.6
• High-speed clock mode
• Specified as the time up to
the beginning of output
change.
Continued on next page.
No.A1954-20/31
LC88F85D0A
Continued from preceding page.
Parameter Symbol
Specification
typ max
Pin/Remarks
Conditions
V
[V]
min
Unit
Tfilt
DD
Stop condition
tSU;STO
SM0CK(P22)
SM0DA(P23)
• See Fig. 8.
1.0
4.9
setup time
tSU;STOx
SM0CK(P22)
SM0DA(P23)
• Standard clock mode
• Specified as the time up to
the beginning of output
change.
2.0 to 5.5
μs
• High-speed clock mode
• Specified as the time up to
the beginning of output
change.
1.1
Data hold time
tHD;DAT
SM0CK(P22)
SM0DA(P23)
• See Fig. 8.
0
1
2.0 to 5.5
Tfilt
Tfilt
tHD;DATx
SM0CK(P22)
SM0DA(P23)
• Specified as the time up to
the beginning of output
change.
1.5
Data setup time
tSU;DAT
SM0CK(P22)
SM0DA(P23)
• See Fig. 8.
1
2.0 to 5.5
2.0 to 5.5
tSU;DATx
SM0CK(P22)
SM0DA(P23)
• Specified as the time up to
the beginning of output
change.
1tSCL-
1.5Tfilt
SM0CK, SM0DA
pin fall time
tF
tF
SM0CK(P22)
SM0DA(P23)
• See Fig. 8.
300
SM0CK(P22)
SM0DA(P23)
• When SMIIC register control
5
3
20+0.1Cb
20+0.1Cb
250
250
bits PSLW=1, P5V=1
• When SMIIC register control
bits PSLW=1, P5V=0
• When SM0CK and SM0DA
port outputs are placed in
fast mode
ns
3.0 to 5.5
100
• Cb≤400pF
Note 4-4-1: These specifications are theoretical values. Margins must be allowed according to the actual operating
conditions.
Note 4-4-2: Tfilt denotes the value that is determined by the values of register SMIC0BRG, bits 7 and 6 (BRP1, BRP0)
and the system clock frequency.
BRP1
BRP0
Tfilt
0
0
1
1
0
1
0
1
tCYC×1
tCYC×2
tCYC×3
tCYC×4
Set up (BPR1, BPR0) so that Tfilt falls within the following range:
250ns ≥ Tfilt > 140ns
Note 4-4-3: Cb denotes the total capacitance (in pF) of the loads connected to each bus. Cb ≤ 400pF
Note 4-4-4: The standard clock mode refers to a mode that is entered by configuring SMIC0BRG within the following
ranges:
250ns ≥ Tfilt > 140ns
BRDQ (bit 5) = 1
SCL frequency setting ≤ 100kHz
The high-speed clock mode refers to a mode that is entered by configuring SMIC0BRG as follows:
250ns ≥ Tfilt > 140ns
BRDQ (bit 5) = 0
SCL frequency setting ≤ 400kHz
No.A1954-21/31
LC88F85D0A
UART0 Operating Conditions at Ta = -20 to +75°C, V = LCDV 0 = LCDV 1 = 0V
SS
SS
SS
Specification
max
Parameter
Symbol
UBR0
Pin/Remarks
Conditions
V
[V]
min
typ
unit
DD
U0RX(P14),
U0TX(P15),
U0BRG(P07)
Transfer rate
2.0 to 5.5
4
8
tBGCYC
Note 4-5: tBGCYC denotes 1 period of the baudrate clock source.
UART2 Operating Conditions at Ta = -20 to +75°C, V = LCDV 0 = LCDV 1 = 0V
SS
SS
SS
Specification
max
Parameter
Symbol
UBR2
Pin/Remarks
Conditions
V
[V]
min
typ
unit
DD
Transfer rate
U2RX(P16),
U2TX(P17)
2.0 to 5.5
8
4096
tBGCYC
Note 4-6: tBGCYC denotes 1 period of the baudrate clock source.
Pulse Input Conditions at Ta = -20 to +75°C, V = LCDV 0 = LCDV 1 = 0V
SS SS SS
Specification
max
Symbol
tPIL(2)
Pin/Remarks
RESB
Conditions
Resettable.
Parameter
V
[V]
min
10
typ
unit
DD
2.0 to 5.5
μs
AD Converter Characteristics at Ta = -20 to +75°C, V = LCDV 0 = LCDV 1 = 0V
SS
SS
SS
12-bits AD Conversion Mode
Specification
typ max
12
Parameter
Symbol
Pin/Remarks
Conditions
V
[V]
min
unit
DD
Resolution
NAD
AN0(P20),
AN1(P21),
AN2(P22),
AN3(P23),
AN8(P00) to
AN15(P07)
2.9 to 5.5
2.9 to 5.5
4.5 to 5.5
2.9 to 5.5
bit
Absolute accuracy
Conversion time
ETAD
(Note 6-1)
16
LSB
TCAD12
Conversion time is calculated.
27
209
209
μs
V
67
Analog input
voltage range
Analog port input
current
VAIN
2.9 to 5.5
V
V
SS
DD
IAINH
IAINL
VAIN=V
DD
2.9 to 5.5
2.9 to 5.5
1
μA
VAIN=V
SS
-1
• Conversion time calculation method: TCAD12= ((52/(AD division ratio))+2) × tCYC
8-bits AD Conversion Mode
Specification
typ max
Parameter
Symbol
Pin/Remarks
Conditions
V
[V]
min
unit
bit
DD
Resolution
NAD
AN0(P20),
AN1(P21),
AN2(P22),
AN3(P23),
AN8(P00) to
AN15(P07)
2.9 to 5.5
2.9 to 5.5
4.5 to 5.5
2.9 to 5.5
8
Absolute accuracy
Conversion time
ETAD
(Note 6-1)
1.5
129
129
LSB
TCAD8
Conversion time is calculated.
17
μs
V
42
Analog input
voltage range
Analog port input
current
VAIN
2.9 to 5.5
V
V
SS
DD
IAINH
IAINL
VAIN=V
DD
2.9 to 5.5
2.9 to 5.5
1
μA
VAIN=V
SS
-1
• Conversion time calculation method: TCAD8= ((32/(AD division ratio))+2) × tCYC
Note 6-1: The quantization error (±1/2LSB) is excluded from the absolute accuracy.
Note 6-2: The conversion time refers to the interval from the time a conversion starting instruction is issued till the time
the complete digital value against the analog input value is loaded in the result register.
The conversion time is twice the normal value when one of the following conditions occurs:
• The first AD conversion is executed in the 12-bit AD conversion mode after a system reset.
• The first AD conversion is executed after the AD conversion mode is switched from 8-bit to 12-bit AD
conversion mode.
No.A1954-22/31
LC88F85D0A
Consumption Current Characteristics at Ta = -20 to +75°C, V = LCDV 0 = LCDV 1 = 0V
SS
SS
SS
Specification
typ max
Pin/
Parameter
Symbol
Conditions
Remarks
V
[V]
min
unit
DD
Normal mode
consumption
current
IDDOP(1)
V
• FOSC0=32.768kHz
LCD
DD
2.0 to 5.5
2.0 to 3.6
2.0 to 5.5
2.0 to 3.6
2.0 to 5.5
2.0 to 3.6
2.0 to 5.5
2.0 to 3.6
87
170
110
155
95
• System clock set to FOSC0 side
• Internal RC oscillation stopped
• FOSC1=0Hz (oscillation stopped)
• Frequency division ratio set to 1/1
• Normal XT mode
display
ON
IDDOP(2)
IDDOP(3)
IDDOP(4)
IDDOP(5)
IDDOP(6)
IDDOP(7)
IDDOP(8)
IDDOP(9)
44
75
35
53
35
48
31
(Note 7-1)
LCD
display
OFF
[No panel load]
μA
• FOSC0=32.768kHz
LCD
100
65
• System clock set to FOSC0 side
• Internal RC oscillation stopped
• FOSC1=0Hz (oscillation stopped)
• Frequency division ratio set to 1/1
• Low power XT mode
display
ON
LCD
92
display
OFF
[No panel load]
55
• FmCF=10MHz ceramic oscillator
• FOSC0=0Hz (oscillation stopped)
• System clock set to 10MHz side
• Internal RC oscillation stopped
• Frequency division ratio set to 1/1
4.5 to 5.5
8.4
15.2
IDDOP(10)
• FmCF=8MHz ceramic oscillator oscillator
• FOSC0=0Hz (oscillation stopped)
• System clock set to 8MHz side
• Internal RC oscillation stopped
• Frequency division ratio set to 1/1
• FmCF=4MHz ceramic oscillator
• FOSC0=0Hz (oscillation stopped)
• System clock set to 4MHz
4.5 to 5.5
3.0 to 4.5
4.5 to 5.5
7.6
5.8
3.6
14.7
11
IDDOP(11)
IDDOP(12)
5.5
IDDOP(13)
IDDOP(14)
IDDOP(15)
IDDOP(16)
mA
• Internal RC oscillation stopped
• Frequency division ratio set to 1/2
2.2 to 4.5
2.0 to 5.5
2.0 to 3.6
2.2
2.2
1.2
4.7
5.6
3.6
• System clock set to internal RC side
• Internal RC oscillation oscillated
• FOSC0=0Hz (oscillation stopped)
• FOSC1=0Hz (oscillation stopped)
• Frequency division ratio set to 1/1
• FOSC1=1MHz
R
=470kΩ
CR1
• System clock set to FOSC1 side
• Internal RC oscillation stopped
• FOSC0=0Hz (oscillation stopped)
• Frequency division ratio set to 1/1
*Ta=0 to 60°C
2.0 to 5.5
2.0 to 3.6
2.0 to 5.5
2.0 to 3.6
1.5
1.0
100
62
2.6
2.5
IDDOP(17)
IDDOP(18)
IDDOP(19)
• FOSC0=64kHz
R
=910kΩ
CR0
• System clock set to FOSC0 side
• Internal RC oscillation stopped
• FOSC1=0Hz (oscillation stopped)
• Frequency division ratio set to 1/1
*Ta=0 to 60°C
187
120
μA
Note 7-1: The consumption current value includes none of the currents that flow into the output Tr and internal pull-up
resistors.
Continued on next page.
No.A1954-23/31
LC88F85D0A
Continued from preceding page.
Specification
typ max
Pin/
Parameter
Symbol
Conditions
Remarks
V
[V]
min
unit
DD
HALT mode
consumption
current
IDDHALT(1)
V
HALT mode
LCD
DD
2.0 to 5.5
2.0 to 3.6
2.0 to 5.5
2.0 to 3.6
2.0 to 5.5
2.0 to 3.6
2.0 to 5.5
2.0 to 3.6
45
110
50
90
51
53
30
40
30
• FOSC0=32.768kHz
display
ON
• System clock set to FOSC0 side
• Internal RC oscillation stopped
• FOSC1=0Hz (oscillation stopped)
• Frequency division ratio set to 1/1
• Normal XT mode
IDDHALT(2)
IDDHALT(3)
IDDHALT(4)
IDDHALT(5)
IDDHALT(6)
IDDHALT(7)
IDDHALT(8)
IDDHALT(9)
16
36
(Note 7-2)
LCD
display
OFF
7.8
15.5
12
[No panel load]
μA
HALT mode
LCD
• FOSC0=32.768kHz
display
ON
• System clock set to FOSC0 side
• Internal RC oscillation stopped
• FOSC1=0Hz (oscillation stopped)
• Frequency division ratio set to 1/1
• Low power XT mode
LCD
6.5
4
display
OFF
[No panel load]
HALT mode
• FmCF=10MHz ceramic oscillator
• FOSC0=0Hz (oscillation stopped)
• System clock set to 10MHz side
• Internal RC oscillation stopped
• Frequency division ratio set to 1/1
HALT mode
4.5 to 5.5
2.0
3.4
IDDHALT(10)
• FmCF=8MHz ceramic oscillator
• Internal RC oscillation stopped
• FOSC0=0Hz (oscillation stopped)
• System clock set to 8MHz side
• Internal RC oscillation stopped
• Frequency division ratio set to 1/1
HALT mode
4.5 to 5.5
3.0 to 4.5
1.7
1.2
2.9
2.1
IDDHALT(11)
IDDHALT(12)
• FmCF=4MHz ceramic oscillator
• FOSC0=0Hz (oscillation stopped)
• System clock set to 4MHz side
• Internal RC oscillation stopped
• Frequency division ratio set to 1/2
HALT mode
4.5 to 5.5
2.2 to 4.5
2.0 to 5.5
2.0 to 3.6
0.7
0.3
0.7
0.3
1.2
0.85
1.3
mA
IDDHALT(13)
IDDHALT(14)
• System clock set to internal RC side
• Internal RC oscillation oscillated
• FOSC0=0Hz (oscillation stopped)
• FOSC1=0Hz (oscillation stopped)
• Frequency division ratio set to 1/1
HALT mode
IDDHALT(15)
IDDHALT(16)
0.6
• FOSC1=1MHz
R
=470kΩ
CR1
2.0 to 5.5
2.0 to 3.6
2.0 to 5.5
2.0 to 3.6
0.2
0.1
20
0.5
0.3
60
• System clock set to FOSC1 side
• Internal RC oscillation stopped
• FOSC0=0Hz (oscillation stopped)
• Frequency division ratio set to 1/1
*Ta=0 to 60°C
IDDHALT(17)
IDDHALT(18)
HALT mode
• FOSC0=64kHz
R
=910kΩ
CR0
• System clock set to FOSC0 side
• Internal RC oscillation stopped
• FOSC1=0Hz (oscillation stopped)
• Frequency division ratio set to 1/1
*Ta=0 to 60°C
μA
IDDHALT(19)
10
40
Note 7-2: The consumption current value includes none of the currents that flow into the output Tr and internal pull-up
resistors.
Continued on next page.
No.A1954-24/31
LC88F85D0A
Continued from preceding page.
Specification
Pin/
Parameter
Symbol
Conditions
Remarks
V
[V]
min
typ
max
unit
DD
HOLD mode
consumption
current
IDDHOLD(1)
V
HOLD mode
• CF1=V
DD
2.0 to 5.5
2.0 to 3.6
0.08
0.02
35
25
or open (external clock mode)
DD
IDDHOLD(2)
IDDHOLD(3)
HOLDX mode
consumption
current
HOLDX mode
• CF1=V or open (external clock mode)
2.0 to 5.5
2.0 to 3.6
2.0 to 5.5
2.0 to 3.6
30
5
65
55
35
25
DD
μA
• FOSC0=32.768kHz
• Normal XT mode
HOLDX mode
IDDHOLD(4)
IDDHOLD(5)
IDDHOLD(6)
0.6
0.4
• CF1=V
DD
• FOSC0=32.768kHz
• Low power XT mode
or open (external clock mode)
Note 7-3: The consumption current value includes none of the currents that flow into the output Tr and internal pull-up
resistors.
F-ROM Writing Characteristics at Ta = +10°C to +55°C, V = LCDV 0 = LCDV 1 = 0V
SS SS SS
Specification
typ
Pin/
Parameter
Symbol
Conditions
Remarks
V
[V]
min
max
unit
mA
DD
Onboard writing
current
IDDFW(1)
V
• Excluding power dissipation
in the microcontroller block
• 512-/1K-byte erase operation
DD
3.0 to 5.5
15
Writing time
tFW(1)
tFW(2)
3.0 to 5.5
3.0 to 5.5
30
60
ms
• 2-byte writing operation
μs
Characteristics of a Sample OSC1 System Clock Oscillation Circuit
Sample main system clock oscillation circuit characteristics
Given below are the characteristics of a sample main system clock oscillation circuit that are measured using a
SANYO-designated oscillation characteristics evaluation board and external components with circuit constant values
with which the oscillator vendor confirmed normal and stable oscillation.
Table 1 Characteristics of the Main System Clock Oscillation Circuit that Uses a Ceramic Oscillator
Operating
Voltage
Range
[V]
Oscillation
Circuit Constant
Nominal
Stabilization Time
Vendor Name
Oscillator Name
Remarks
Frequency
C3
C4
Rf
Rd2
Typ
max
[ms]
[pF]
[pF]
[Ω]
[Ω]
[ms]
C1 and C2
integrated type
C1 and C2
10MHz
8MHz
CSTCE10M0G52-R0
CSTCE8M00G52-R0
CSTCR4M00G53-R0
CSTCR4M00G53095-R0
(10)
(10)
(15)
(15)
(10)
(10)
(15)
(15)
OPEN
OPEN
OPEN
OPEN
150
470
2.4 to 5.5
2.4 to 5.5
2.2 to 5.5
2.0 to 5.5
0.02
0.02
0.02
0.02
0.5
0.5
0.5
0.5
MURATA
Manufacturing
Co., Ltd.
integrated type
C1 and C2
1.5K
1.5K
integrated type
C1 and C2
4MHz
integrated type
The oscillation stabilization time refers to the time interval that is required for the oscillation to get stabilized after V
exceeds its lower limit operating voltage (see Figure 4).
DD
No.A1954-25/31
LC88F85D0A
Characteristics of a Sample Subsystem Clock Oscillation Circuit
Given below are the characteristics of a sample subsystem clock oscillation circuit that are measured using a SANYO-
designated oscillation characteristics evaluation board and external components with circuit constant values with which
the oscillator vendor confirmed normal and stable oscillation.
Table 2 Characteristics of a Sample Subsystem Clock Oscillator Circuit that uses a Crystal Oscillator
Circuit Constant
Nominal Frequency Vendor Name Oscillator Name
Remarks
C3
C4
Rf2
Rd2
[pF]
[pF]
[Ω]
[Ω]
Normal XT mode
32.768kHz
32.768kHz
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
Low power XT mode
The oscillation stabilization time refers to the time interval that is required for the oscillation to get stabilized after an
instruction for starting the subclock oscillator circuit is issued or the time interval that is required for the oscillation to
get stabilized after the HOLD mode is released (see Figure 4).
Note: The components that are involved in oscillation should be placed as close to the IC and to one another as possible
because they are vulnerable to the influences of the circuit pattern.
Rf2
Rf1
CF1
CF2
XT1
XT2
Rd1
Rd2
C1
C2
C3
C4
CF
X’tal
Figure 1 CF Oscillator Circuit
Figure 2 XT Oscillator Circuit
0.5V
DD
Figure 3 AC Timing Measurement Point
No.A1954-26/31
LC88F85D0A
V
DD
Operating V
lower limit
0V
DD
Power supply
RESB
Reset time
Internal RC oscillation
tmsCF
CF1, CF2
XT1, XT2
tmsX’tal
VMRC
Initialization instruction executed
Unpredictable
Reset
Operating mode
User instruction executed
Reset Time and Oscillation Stabilization Time
No.A1954-27/31
LC88F85D0A
HOLD release
No HOLD release signal
HOLD release signal valid
Interrupt operation
Internal RC oscillator
tmsCF
CF1, CF2
tmsX’tal
XT1, XT2
VMRC
State
HOLD
Instruction executed
HALT
HOLD Reset and Oscillation Stabilization Time
Figure 4 Oscillation Stabilization Time
V
DD
Note:
Make sure that reset is in effect when power is
R
C
RES
turned on. Determine the values of C
R
and
so that the reset is in effect for a period of
RES
RES
10μs after the power gets stabilized.
RESB
RES
Figure 5 Reset Circuit
No.A1954-28/31
LC88F85D0A
tSCKHBSY
tSCKHBSY
RUN:
SIOCLK:
DATAIN:
DI0
DI1
DI6
DI7
DI8
DIx
DATAOUT:
DO0
tdDO
tdDO
DO1
DO6
DO7
DO8
DOx
Data transfer period
(SIO0, 1 only)
tSCK
SIOCLK:
DATAIN:
tSCKL
tSCKH
thDI
tsDI
DATAOUT:
Data transfer period
(SIO0, 1 only)
SIOCLK:
DATAIN:
tSCKL
tSCKHA
thDI
tsDI
DATAOUT:
*: Remarks: DIx and DOx are the final communication bits. X = 0 to 32768
Figure 6 Serial I/O Waveforms Examples
tPIL
tPIH
Figure 7 Pulse Input Timing Signal Waveform
No.A1954-29/31
LC88F85D0A
P
S
Sr
P
SDA
SCK
tBUF
tHD;STA tR
tF
tHD;STA
tsp
tLOW
tHIGH
tHD;DAT
tSU;DAT
tSU;STO
tSU;STA
S: Start condition
P: Stop condition
Sr: Restart condition
Figure 8 I2C Timing
Note: The oscillation frequency of any RC oscillator using OSC1 or OSC0 varies according to the printed circuit
patterns and components mounted on the board. It also varies greatly according to the shape and form of the
product (chip, plastic package, etc.) and board capacitance. Consequently, the characteristics charts given below
should be used merely as reference values and the resistance value be determined after evaluating them with the
actual product.
Frequency - Resistor
Frequency - Resistor
10
1000
Ta=25°C, typ
Ta=25°C, typ
7
7
5
5
3
2
3
2
1.0
100
7
5
7
5
3
2
3
2
0.1
10
0
200
400
600
800
1000
1200
0
200
400
600
800
1000
1200
Resistor - kΩ
ILC05653
Resistor - kΩ
ILC05654
Figure 9 OSC1 Oscillation Frequency vs.
Resistance Characteristics
Figure 10 OSC0 Oscillation Frequency vs.
Resistance Characteristics
No.A1954-30/31
LC88F85D0A
SANYO Semiconductor Co.,Ltd. assumes no responsibility for equipment failures that result from using
products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition
ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor Co.,Ltd.
products described or contained herein.
SANYO Semiconductor Co.,Ltd. strives to supply high-quality high-reliability products, however, any and all
semiconductor products fail or malfunction with some probability. It is possible that these probabilistic failures or
malfunction could give rise to accidents or events that could endanger human lives, trouble that could give rise
to smoke or fire, or accidents that could cause damage to other property. When designing equipment, adopt
safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not
limited to protective circuits and error prevention circuits for safe design, redundant design, and structural
design.
In the event that any or all SANYO Semiconductor Co.,Ltd. products described or contained herein are
controlled under any of applicable local export control laws and regulations, such products may require the
export license from the authorities concerned in accordance with the above law.
No part of this publication may be reproduced or transmitted in any form or by any means, electronic or
mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise,
without the prior written consent of SANYO Semiconductor Co.,Ltd.
Any and all information described or contained herein are subject to change without notice due to
product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the
SANYO Semiconductor Co.,Ltd. product that you intend to use.
Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed
for volume production.
Upon using the technical information or products described herein, neither warranty nor license shall be granted
with regard to intellectual property rights or any other rights of SANYO Semiconductor Co.,Ltd. or any third
party. SANYO Semiconductor Co.,Ltd. shall not be liable for any claim or suits with regard to a third party's
intellectual property rights which has resulted from the use of the technical information and products mentioned
above.
This catalog provides information as of April, 2011. Specifications and information herein are subject
to change without notice.
No.A1954-31/31
PS
相关型号：
©2020 ICPDF网 联系我们和版权申明