LC895196K [SANYO]
ATA-PI Compatible CD-ROM Decoder IC; ATA -PI兼容CD - ROM解码器IC
| 型号： | LC895196K |
| 厂家： | 
SANYO SEMICON DEVICE |
| 描述： | ATA-PI Compatible CD-ROM Decoder IC |
| 文件： | 总12页 (文件大小：145K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Ordering number : EN *5852
CMOS LSI
LC895196K
ATA-PI Compatible CD-ROM Decoder IC
Preliminary
Overview
The LC895196K is a large scale integrated circuit
equipped with CD-ROM functions and an internal ATA-
PI (IDE) interface.
decoding, CD-R compatibility)
• Built in subcode P-W buffering function (NO-ECC) and
CD-TEXT compatibility
Package Dimensions
unit: mm
Functions
• CD-ROM ECC functions, SUB-CODE read function,
ATA-PI (IDE) interface (Registers, etc.).
3214-SQFP144
[LC895196K]
Features
• Built-in ATA-PI (IDE) interface.
• 32× speed supported
Uses the EDO-DRAM (× 16, 50 ns)
16.6 Mbyte/s (with IORDY)
Operating frequency: 33.8688 MHz
• 24× speed supported
Uses the EDO-DRAM (× 16, 60 ns)
16.6 Mbyte/s (without IORDY)
Operating frequency: 33.8688 MHz
• Supports between 1 Mbit and 4 Mbit of buffer RAM
when DRAM is used
• The user can flexibly set the CD main channel, the C2
flags, and the subcode regions in the buffer RAM
• Built-in batch transfer function. (Where the batch
transfer function is a function that transmit the CD main
channel, C2 flags, subcodes, etc. all at once.)
• Built-in multitransmit function. (Where the
multitransmit function is a function that automatically
transmits multiple blocks at once.)
SANYO: SQFP144
• Built-in intelligent functions (auto buffering, auto
Specifications
Absolute Maximum Ratings at V = 0 V
SS
Parameter
Maximum power supply voltage
I/O voltage
Symbol
Condition
Ratings
Unit
V
V
DD max
VI, VO
Pd max
Topr
Ta = 25°C
Ta = 25°C
Ta ≤ 70°C
–0.3 to +7.0
–0.3 to VDD + 0.3
550
V
Allowable power dissipation
Operating temperatures
Storage temperatures
mW
°C
°C
°C
mA
–30 to +70
–55 to +125
235
Tstg
Soldering temperature (terminals only)
I/O current
For 10 seconds
II, IO max
±20*
Note: * Per basic I/O cell
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110 JAPAN
D3097HA (OT) No. 5852-/12
LC895196K
Allowable Operating Ranges at Ta = –30 to +70°C, V = 0 V
SS
Ratings
typ
Parameter
Symbol
Conditions
Unit
min
4.5
max
5.5
VDD
Supply voltage
Input voltage range
VDD
VIN
5.0
V
V
0
DC Characteristics at V = 0 V, V = 4.5 to 5.5 V, Ta = –30 to +70°C
SS
DD
Conditions
Ratings
typ
Parameter
Input high level voltage
Symbol
Unit
Applicable pins (see below)
min
max
V
IH1
IL1
VIH
IL2
IH3
IL3
OH1
OL1
OH2
OL2
OH3
OL3
VOL
TTL compatible (1)
2.2
V
V
Input low level input
V
TTL compatible (1)
0.8
0.8
0.8
0.4
0.4
Input high level voltage
Input low level input
2
TTL compatible with pull-up resistor: (10)
TTL compatible with pull-up resistor: (10)
TTL compatible Schmitt: (2), (3), (11)
TTL compatible Schmitt: (2), (3), (11)
IOH = –2 mA: (4), (10)
2.2
V
V
V
Input high level voltage
Input low level input
V
2.2
V
V
V
Output high level voltage
Output low level voltage
Output high level voltage
Output: Low level voltage
Output high level voltage
Output low level voltage
Output low level voltage
Output low level voltage
Input leakage current
Output leakage current
Pull-up resistor
V
VDD – 2.1
VDD – 2.1
VDD – 2.1
V
V
IOL = 2 mA: (4), (10)
V
V
IOH = –8 mA: (5)
V
V
IOL = 8 mA: (5)
V
V
IOH = –4 mA: (8), (11)
V
V
IOL = 24 mA: (8), (11)
0.4
0.4
V
4
IOL = 24 mA: (9)
V
VOL5
IOL = 8 mA: (6), (7)
0.4
V
IIL
VI = VSS, VDD: (1), (2), (3), (11)
When high impedance output: (6), (8), (9), (11)
(7), (10)
–10
–10
40
+10
+10
160
µA
µA
kΩ
IOZ
RUP
80
Note: The applicable pins correspond to the following names.
[INPUT]
(1) ..........ATPINSEL, CSCTRL, SUA0 to SUA6, BCK, C2PO, LRCK, SDATA, SBSO, SCOR, WFCK, TEST0 to TEST1
(2) ..........ZRESET, ZCS, ZRD, ZWR, CSEL
(3) ..........DA0 to DA2, ZCS1FX, ZCS3FX, ZDIOR, ZDIOW, ZDMACK, ZHRST
[OUTPUT]
(4) ..........RA0 to RA8, ZCAS0, ZCAS1, ZUWE, ZLWE, ZOE, ZRAS0, EXCK
(5) ..........MCK, MCK2, MCK3
(6) ..........ZRSTCPU, ZRSTIC
(7) ..........ZINT, ZINT1, ZSWAIT
(8) ..........DMARQ, HINTRQ
(9) ..........IORDY, ZIOCS16
[INPUT]
(10) ..........D0 to D7, IO0 to IO15
(11) ..........DD0 to DD15, ZDASP, ZPDIAG
* The XTAL0, XTALCK0, XTAL1, XTALCK1 pins are not included in the CD characteristics.
Recommended Example of Oscillator Circuit
R1 = 1 MΩ
R2 = 47 Ω
C1 = 0
C2 = 47 pF
Ceramic oscillator frequency = 33.8688 MHz.
The 33.8688 MHz recommended example is for a 3× overtone.
Because the specific values are influenced by the circuit board,
confer with the oscillator manufacturer.
No. 5852-2/12
LC895196K
Block Diagram
[0:18]
CD-DSP I/F
& SYNC
detector
Each block
bus control
signal
buffer
Each block
register
R0 to R118
*1
*2
*3
*4
*5
*6
*7
*8
*9
**1
WFCK, SBSO, SCOR
BCK, SDATA, LRCK, C2PO
DD0 to DD15, ZDASP, ZPDIAG
ZCS1FX, ZCS3FX, DA0 to DA2, ZDIOR, ZDIOW, ZDMACK, CSEL
DMARQ, HINTRQ, ZIOCS16, IORDY, ZHRST
ZRD, ZWR, SUA0 to SUA6, ZCS, CSCTRL
D0 to D7
IO0 to IO15
RA0 to RA8, ZRAS0, ZCAS0, ZCAS1, ZOE, ZUWE, ZLWE
HISIDE (WD25C32) is made by WESTERN DIGITAL
No. 5852-3/12
LC895196K
Pin Functions
The LC895196K can be set to the opposite of the ATAPI pin layout using the setting of pin 19.
Pin 29 ATPINSEL = 0
I: Input pin B: Bi-directional pin NC: Not connected O: Output pin P: Power supply pin
Function
Pin No.
1
Symbol
VSS0
Type
P
2
ZRAS0
O
NC
O
O
O
O
O
P
RAS signal output pin 0 to the buffer DRAM (Normally uses 0).
3
4
ZCAS0
ZCAS1
ZOE
ZUWE
ZLWE
VSS0
RA0
CAS signal output pin 0 to the buffer DRAM (Normally uses 0).
CAS signal output pin 1 to the buffer DRAM
Buffer DRAM output enable
5
6
7
Buffer DRAM upper write enable
8
Buffer DRAM lower write enable
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
O
O
O
O
O
O
O
O
P
RA1
RA2
RA3
Address signal output pins to the data buffer DRAM
RA4
RA5
RA6
RA7
VDD
VSS0
RA8
P
O
NC
B
Address signal output pins to the data buffer DRAM
IO0
IO1
B
IO2
B
Data I/O pin to the data buffer DRAM.
Built-in pull-up resistor.
IO3
B
IO4
B
IO5
B
IO6
B
ATPINSEL
IO7
I
ATAPI pin assignment select pin. Connect to VSS0.
B
IO8
B
IO9
B
Data I/O pin to the data buffer DRAM.
Built-in pull-up resistor.
IO10
IO11
IO12
VSS0
VDD
B
B
B
P
P
IO13
IO14
IO15
B
Data I/O pin to the data buffer DRAM.
Built-in pull-up resistor.
B
B
NC
P
VSS0
VSS0
VSS0
P
P
NC
NC
Continued on next page.
No. 5852-4/12
LC895196K
Continued from preceding page.
Pin No.
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
Symbol
C2PO
SDATA
BCK
Type
I
Function
I
CD-DSP interface
Subcode I/O
I
LRCK
EXCK
WFCK
SBSO
VDD
I
O
I
I
P
P
I
VSS0
SCOR
Subcode I/O
NC
NC
NC
O
I
MCK
TEST0
TEST1
CSEL
XTALCK1 1/1, 1/2 and STOP output
Test input pin. Connect to VSS
.
I
I
ATAPI control signal
ZRSTIC
CSCTRL
MCK2
MCK3
VSS0
O
I
Reset signal to the drive reset IC
Microcontroller-side CS active low/high select pin
XTALCK0 1/1, 1/2, 1/5, 1/512 and STOP output
XTALCK0 1/1, 1/5, 2/5, 1/512 and STOP output
O
O
P
NC
I
XTALCK0
XTAL0
VSS0
VDD
X’tal oscillator circuit input
X’tal oscillator circuit input
O
P
P
I
ZRESET
ZRD
LSI reset
I
Microcontroller data read signal input
Microcontroller data write signal input
ZWR
ZCS
I
I
Input pin for the register chip select signal from the microcontroller
VSS0
SUA0
SUA1
SUA2
SUA3
SUA4
SUA5
SUA6
D0
P
I
I
I
I
Microcontroller register select signals
I
I
I
B
B
B
B
P
P
B
B
B
B
O
O
O
O
I
D1
Microcontroller data signals.
Built-in pull-up resistors.
D2
D3
VDD
VSS0
D4
D5
Microcontroller data signals.
Built-in pull-up resistors.
D6
D7
ZINT0
ZINT1
ZSWAIT
ZRSTCPU
XTAL1
Output pin for interrupt request signal to the microcontroller (set by the ECC-side registers)
Output pin for interrupt request signal to the microcontroller (set by the ATAPI-side registers)
Wait signal to the microcontroller
Reset signal to the CPU
X’tal oscillator circuit input
Continued on next page.
No. 5852-5/12
LC895196K
Continued from preceding page.
Pin No.
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
Symbol
XTAL1
VSS0
Type
O
P
I
Function
X’tal oscillator circuit output
ATAPI control signals
ZHRST
ZDASP
ZCS3FX
ZCS1FX
DA2
B
I
I
I
VSS0
P
P
I
VDD
DA0
ZPDIAG
DA1
B
I
ZIOCS16
INTRQ
ZDMACK
VSS1
O
O
I
ATAPI control signals
P
O
I
IORDY
ZDIOR
ZDIOW
DMARQ
DD15
VSS1
ATAPI control signals
ATAPI data bus
I
O
B
P
B
B
B
P
P
B
B
B
B
P
B
B
B
P
P
B
B
B
P
B
B
P
DD0
DD14
DD1
ATAPI data bus
VDD
VSS1
DD13
DD2
ATAPI data bus
ATAPI data bus
DD12
DD3
VSS1
DD11
DD4
DD10
VSS1
VDD
DD5
DD9
ATAPI data bus
ATAPI data bus
DD6
VSS1
DD8
DD7
VDD
Leave the NC pins OPEN.
Those pin names starting with the letter “Z” indicate negative logic.
VSS0 is the logic system ground, and VSS1 is the ID interface driver ground.
No. 5852-6/12
LC895196K
Pin 29 ATPINSEL = 1
I: Input pin B: Bi-directional pin NC: Not connected O: Output pin P: Power supply pin
Function
Pin No.
1
Symbol
VSS0
Type
P
2
ZRAS0
O
NC
O
O
O
O
O
P
RAS signal output pin 0 to the buffer DRAM (Normally uses 0).
3
4
ZCAS0
ZCAS1
ZOE
ZUWE
ZLWE
VSS0
RA0
CAS signal output pin 0 to the buffer DRAM (Normally uses 0).
CAS signal output pin 1 to the buffer DRAM
Buffer DRAM output enable
5
6
7
Buffer DRAM upper write enable
8
Buffer DRAM lower write enable
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
O
O
O
O
O
O
O
O
P
RA1
RA2
RA3
Address signal output pin to the data buffer DRAM
RA4
RA5
RA6
RA7
VDD
VSS0
RA8
P
O
NC
B
Address signal output pin to the data buffer DRAM
IO0
IO1
B
IO2
B
Data I/O pin to the data buffer DRAM.
Built-in pull-up resistor.
IO3
B
IO4
B
IO5
B
IO6
B
ATPINSEL
IO7
I
ATAPI pin assignment select pin. Connect to VSS0.
B
IO8
B
IO9
B
Data I/O pin to the data buffer DRAM.
Built-in pull-up resistor
IO10
IO11
IO12
VSS0
VDD
B
B
B
P
P
IO13
IO14
IO15
B
Data I/O pin to the data buffer DRAM.
Built-in pull-up resistor.
B
B
NC
P
VSS0
VSS0
VSS0
P
P
NC
NC
Continued on next page.
No. 5852-7/12
LC895196K
Continued from preceding page.
Pin No.
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
Symbol
C2PO
SDATA
BCK
Type
I
Function
I
CD-DSP interface
Subcode I/O
I
LRCK
EXCK
WFCK
SBSO
VDD
I
O
I
I
P
P
I
VSS0
SCOR
Subcode I/O
NC
NC
NC
O
I
MCK
TEST0
TEST1
CSEL
XTALCK1 1/1, 1/2 and STOP output
Test input pin. Connect to VSS
.
I
I
ATAPI control signal
ZRSTIC
CSCTRL
MCK2
MCK3
VSS0
O
I
Reset signal to the drive reset IC
Microcontroller-side CS active low/high select pin
XTAKCK0 1/1, 1/2, 1/5, 1/512 and STOP output
XTAKCK0 1/1, 1/5, 2/5, 1/512 and STOP output
O
O
P
NC
I
XTALCK0
XTAL0
VSS0
VDD
X’tal oscillator circuit input
X’tal oscillator circuit input
O
P
P
I
ZRESET
ZRD
LSI reset
I
Microcontroller data read signal input
Microcontroller data write signal input
ZWR
ZCS
I
I
Input pin for the register chip select signal from the microcontroller
VSS0
SUA0
SUA1
SUA2
SUA3
SUA4
SUA5
SUA6
D0
P
I
I
I
I
Microcontroller register select signals
I
I
I
B
B
B
B
P
P
B
B
B
B
O
O
O
O
I
D1
Microcontroller data signals.
Built-in pull-up resistors.
D2
D3
VDD
VSS0
D4
D5
Microcontroller data signals
Built-in pull-up resistors.
D6
D7
ZINT0
ZINT1
ZSWAIT
ZRSTCPU
XTAL1
Output pin for interrupt request signal to the microcontroller (set by the ECC-side registers)
Output pin for interrupt request signal to the microcontroller (set by the ATAPI-side registers)
Wait signal to the microcontroller
Reset signal to the CPU
X’tal oscillator circuit input
Continued on next page.
No. 5852-8/12
LC895196K
Continued from preceding page.
Pin No.
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
Symbol
XTAL1
VSS0
Type
O
P
B
B
B
B
B
P
P
B
B
B
B
B
B
P
B
B
B
B
B
P
O
I
Function
X’tal oscillator circuit output
ATAPI data bus
DD7
DD8
DD6
DD9
DD5
VSS1
VDD
DD10
DD4
DD11
DD3
ATAPI data bus
DD12
DD2
VSS1
DD13
DD1
DD14
DD0
ATAPI data bus
DD15
VSS1
DMARQ
ZDIOW
ZDIOR
VDD
ATAPI control signals
I
P
P
O
I
VSS1
IORDY
ZDMACK
INTRQ
ZIOCS16
VSS1
ATAPI control signals
ATAPI control signals
O
O
P
I
DA1
ZPDIAG
DA0
B
I
VSS1
P
P
I
VDD
DA2
ZCS1FX
ZCS3FX
VSS1
I
ATAPI control signals
ATAPI control signals
I
P
B
I
ZDASP
ZHRST
VDD
P
Leave the NC pins OPEN.
Those pin names starting with the letter “Z” indicate negative logic.
VSS0 is the logic system ground, and VSS1 is the ID interface driver ground.
No. 5852-9/12
LC895196K
Pin Descriptions
1. ATAPI
ZCS1FX (input)
Chip select signal for selecting the command block register.
ZCS3FX (input)
Chip select signal for selecting the control block register.
DA0 to 2 (input)
Addresses for accessing the various ATAPI addresses.
ZDASP (input/output)
Drive 1 is output and drive 0 is input.
Signal for indicating the existence of drive 1 to drive 0. Attach external pull-up resistors.
DD0 to DD15 (input/output)
16-bit data bus. Can be used for transferring 8 bit and 16 bit data.
ZDIOR (input)
Read strobe signal from the host.
ZDIOW (input)
Write strobe signal from the host.
ZDMACK (input)
During DMA transmission, this is the acknowledged signal from the host responding to the DMARQ drive request
signal. There is no built-in pull-up resistor.
DMARQ (output)
This is the drive request signal during DMA transmission.
HINTRQ (output)
Drive interrupt signal to the host.
ZIOCS16 (output)
This signal is asserted depending on the drive when the drive can support 16-bit transfers. This signal is not asserted
during DMA transfers.
IORDY (output)
This signal indicates that the drive is ready to respond during data transfer. This signal is low if the drive is not ready.
Attach an external pull-up resistor.
ZPDIAG (input/output)
This signal is asserted by drive 1 to inform drive 0 that the diagnostics are complete. Attach an external pull-up
resistor.
ZHRST (input)
This is the reset signal from the host. Applying a low signal to this pin causes ZRSTIC to go low and resets the drive.
There is no built-in pull-up resistor.
ZINT1 (output)
This is the interrupt request signal from the IDE block to the MC.
CSEL (input)
This is the cable select signal that determines master/slave. Attach an external pull-up resistor.
2. Microcontroller Interface
ZCS (input)
This is the MC-side chip select.
CSCTRL (input)
This signal selects the MC-side chip select logic.
High: ZCS is active low
Low: ZCS is active high
ZRD, ZWR, SUA0 to SUA6 (inputs)
These are the MC interface control signals. Addressing uses SUA0 to SUA6.
ZSWAIT (output)
When the microcontroller accesses the RAM, the SUB-CPU must wait while this pin is low.
No. 5852-10/12
LC895196K
D7 to D0 (input/output)
This is the MC-side data bus. Built-in pull-up resistor.
ZINT (output)
This is the interrupt signal to the microcontroller.
3. The Buffer RAM
IO0 to IO15 (input/output)
This is the buffer DRAM data bus. Built-in pull-up resistors.
RA0 to RA8 (output)
These are the address pins for the buffer RAM.
ZRAS0 (output)
These are the RAS output pins for the buffer DRAM.
ZCAS0 and ZCAS1 (output)
This is the CAS output pin for the buffer DRAM. Normally ZCAS0 is used. When two 1M (64K × 16 bit) DRAMS
are used, connect the ZCAS0 output to the CAS pin of each DRAM. When the 2CAS types is used, connect ZCAS0
to UCAS and connect ZCAS1 to LCAS.
ZOE (output)
The read output signal for the buffer DRAM.
ZUWE, ZLWE (output)
This is the write output signal for the buffer DRAM. This connects to various DRAM pins. When the 2CAS type is
used, connect ZLWE to the write enable signal.
4. Subcode Interface
EXCK, WFCK, SBSO, SCOR (input or output)
These are the subcode interface pins. By connecting these to the CD-DSP the subcode data is accepted by the
LC895196K and transferred to the host.
5. The CD-DSP Data
BCK, SDATA, LRCK, C2PO (input)
When connected to CD-DSP, CD-ROM data is acquired. C2PO is a pin for use by the C2 flag.
6. Other Pins
ZRESET (input)
This is the LC895196K reset pin. The LC895196K is reset when this signal is low. This signal must be kept low for
at least a period of 1 µs after power on.
XTALCK0, XTAL0
These cause oscillation at 33.8688 MHz. Frequencies from the outside may also be input into XTALCK0.
XTALCK1, XTAL1
Basically, these pins cannot oscillate. If these pins are not used, connect XTALCK1 (pin 100) to ground.
MCK (output)
This outputs the XTALCK1 and XTALCK1/2 frequencies. The output can also be turned off.
No. 5852-11/12
LC895196K
MCK2 (output)
This outputs the XTALCK0, XTALCK0/2, XTALCK0/5 and XTALCK0/512 frequencies. The output can also be
turned off.
MCK3 (output)
This outputs the XTALCK0, XTALCK*0/2, XTALCK0/5 and XTALCK0/512 frequencies. The output can also be
turned off.
ZRSTIC (output)
The ZRSTIC output goes low when the microcontroller register R46-bit7 (ZSYSRET) or the ZHRST pin is put low.
When both the ZSYSRET and ZHRST pins are high, ZRSTIC enters a high impedance state. Attach and external
pull-up resistor.
ZRSTCPU (output)
When an ATAPI soft reset command (08h) is received, a low pulse is generated for approximately 1 ms (when
XTALCK1 = 34 MHz). When this happens, an interrupt is sent to the microcontroller. When the ZRESET pin has
become active, the ZRESET signal is output directly at the ZRSTCPU. Attach an external pull-up resistor.
ATPINSEL (input)
By changing the input to this pin, the ATAPI-side pin layout can be reversed.
■ No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace
equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of
which may directly or indirectly cause injury, death or property loss.
■ Anyone purchasing any products described or contained herein for an above-mentioned use shall:
➀ Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and
distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all
damages, cost and expenses associated with such use:
➁ Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on
SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees
jointly or severally.
■ Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for
volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied
regarding its use or any infringements of intellectual property rights or other rights of third parties.
This catalog provides information as of December, 1997. Specifications and information herein are subject to
change without notice.
No. 5852-12/12
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