LE24LB1283 [SANYO]
Two Wire Serial Interface EEPROM (128k EEPROM); 两线串行接口EEPROM （ 128K EEPROM ）
| 型号： | LE24LB1283 |
| 厂家： | 
SANYO SEMICON DEVICE |
| 描述： | Two Wire Serial Interface EEPROM (128k EEPROM) |
| 文件： | 总14页 (文件大小：127K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Ordering number : ENA1706B
CMOS IC
Two Wire Serial Interface
EEPROM (128k EEPROM)
LE24LB1283
Overview
The LE24LB1283 is a 2-wire serial interface EEPROM. It realizes high speed and a high level reliability by
incorporating SANYO’s high performance CMOS EEPROM technology. This device is compatible with I2C memory
protocol, therefore it is best suited for application that requires small-scale re-writable nonvolatile parameter memory.
Functions
• Capacity: 128k bits (16k × 8 bits)
• Single supply voltage: 1.8V to 3.6V
• Interface: Two wire serial interface (I2C Bus*)
• Operating clock frequency: 400kHz
• Low power consumption
: Standby: 2μA (max)
: Active (Read): 0.5mA (max)
• Automatic page write mode: 64 Bytes
• Read mode: Sequential read and random read
• Erase/Write cycles: 106 cycles
• Data Retention: 20 years
• High reliability: Adopts SANYO’s proprietary symmetric memory array configuration (USP6947325)
Noise filters connected to SCL and SDA pins
Incorporates a feature to prohibit write operations under low voltage conditions.
• Package : LE24LB1283M : MFP8(225mil)
* I2C Bus is a trademark of Philips Corporation.
* This product is licensed from Silicon Storage Technology, Inc. (USA), and manufactured and sold by
SANYO Semiconductor Co., Ltd.
Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to
"standard application", intended for the use as general electronics equipment (home appliances, AV equipment,
communication device, office equipment, industrial equipment etc.). The products mentioned herein shall not be
intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace
instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety
equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case
of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee
thereof. If you should intend to use our products for applications outside the standard applications of our
customer who is considering such use and/or outside the scope of our intended standard applications, please
consult with us prior to the intended use. If there is no consultation or inquiry before the intended use, our
customer shall be solely responsible for the use.
Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate
the performance, characteristics, and functions of the described products in the independent state, and are not
guarantees of the performance, characteristics, and functions of the described products as mounted in the
customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent
device, the customer should always evaluate and test devices mounted in the customer
's products or
equipment.
33111 SY/10511 SY/42810 SY 20100330-S00006 No.A1706-1/14
LE24LB1283
Pin Assignment
Pin Descriptions
PIN.1
PIN.2
PIN.3
PIN.4
PIN.5
PIN.6
PIN.7
PIN.8
S0
Slave device address 0
Slave device address 1
Slave device address 2
Ground
S0
S1
1
2
3
4
V
DD
8
7
6
5
S1
WP
S2
S2
SCL
SDA
GND
SDA
SCL
WP
Serial data input/output
Serial clock input
Write protect
GND
V
Power supply
DD
Package Dimensions
unit:mm (typ)
3032E
[LE24LB1283M]
5.0
8
1
2
(0.6)
1.27
0.15
0.35
SANYO : MFP8(225mil)
Block Diagram
Write controller
High voltage generator
EEPROM Array
WP
S0
S1
S2
SCL
Y decoder & Sense AMP
Serial-Parallel converter
SDA
No.A1706-2/14
LE24LB1283
Specifications
Absolute Maximum Ratings
Parameter
Supply voltage
Symbol
Conditions
Ratings
-0.5 to +4.6
unit
V
DC input voltage
Over-shoot voltage
-0.5 to V +0.5
DD
V
Below 20ns
-1.0 to V +1.0
DD
V
Storage temperature
Tstg
-65 to +150
°C
Note: If an electrical stress exceeding the maximum rating is applied, the device may be damaged.
Operating Conditions
Parameter
Operating supply voltage
Operating temperature
Symbol
Conditions
Ratings
unit
V
1.8 to 3.6
-40 to +85
°C
DC Electrical Characteristics
Standard value
Parameter
Symbol
1
Conditions
unit
min
typ
max
I
I
I
I
I
f=400kHz, V =V
DD DD
max
0.5
5
mA
mA
μA
μA
μA
V
Supply current at reading
Supply current at writing
Standby current
CC
2
f=400kHz, t
=10ms, V =V max
CC
SB
LI
WC DD DD
V
V
V
=V
or GND, V =V
DD DD
max
max
2
IN DD
=GND to V , V =V
DD DD DD
-2.0
+2.0
+2.0
*0.3
Input leakage current
Output leakage current (SDA)
Input low voltage
IN
=GND to V , V =V max
DD DD DD
-2.0
LO
OUT
V
V
V
V
V
DD
IL
0.2
V
Input low voltage (CMOS)
Input high voltage
ILC
IH
V
*0.7
-0.2
V
DD
V
V
Input high voltage (CMOS)
IHC
DD
I
=0.7mA, V =1.8V
0.2
0.4
0.4
V
OL
DD
I
I
=1.0mA, V =1.8V
DD
V
Output low voltage
V
OL
OL
=2.0mA, V =2.5V
DD
V
OL
Capacitance/Ta=25°C, f=1MHz
Parameter
In/Output pin capacitance
Input pin capacitance
Symbol
Conditions
max
unit
C
C
V
=0V (SDA)
I/O
10
10
pF
pF
I/O
V
=0V (other than SDA)
IN
I
Note: This parameter is sampled and not 100% tested.
AC Electric Characteristics
Input pulse level
0.1×V
to 0.9×V
DD
V
DD
DD
DD
Input pulse rise / fall time
Output detection voltage
Output load
20ns
0.5×V
R=3.0kΩ
50pF+Pull up resistor 3.0kΩ
SDA
C=50pF
Output Load Circuit
No.A1706-3/14
LE24LB1283
Fast Mode
Standard value
typ
Parameter
Symbol
unit
min
max
Slave mode SCL clock frequency
SCL clock low time
f
0
1200
600
100
100
600
600
100
0
400
900
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
SCLS
t
LOW
SCL clock high time
SDA output delay time
SDA data output hold time
Start condition setup time
Start condition hold time
Data in setup time
t
HIGH
t
AA
t
DH
t
SU.STA
t
HD.STA
t
SU.DAT
Data in hold time
t
HD.DAT
Stop condition setup time
SCL SDA rise time
t
600
SU.STO
t
300
300
R
SCL SDA fall time
t
F
Bus release time
t
1200
BUF
Noise suppression time
Write cycle time
t
100
5
SP
t
WC
Standard Mode
Standard value
typ
Parameter
Symbol
unit
min
max
Slave mode SCL clock frequency
SCL clock low time
f
0
4700
4000
100
100
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
SCLS
t
LOW
SCL clock high time
SDA output delay time
SDA data output hold time
Start condition setup time
Start condition hold time
Data in setup time
t
HIGH
t
3500
AA
t
100
DH
t
4700
4000
250
SU.STA
t
HD.STA
t
SU.DAT
Data in hold time
t
0
HD.DAT
Stop condition setup time
SCL SDA rise time
t
4000
SU.STO
t
1000
300
R
SCL SDA fall time
t
F
Bus release time
t
4700
BUF
Noise suppression time
Write cycle time
t
100
5
SP
t
WC
No.A1706-4/14
LE24LB1283
Bus Timing
t
HIGH
t
LOW
t
t
R
F
t
SP
SCL
SDA/IN
t
t
t
SU.STO
t
t
SU.STA
t
HD.DAT
HD.STA
SU.DAT
t
SP
t
BUF
t
AA
DH
SDA/OUT
Write Timing
t
WC
SCL
SDA
D0
Stop
condition
Start
condition
Write data
Acknowledge
Pin Functions
SCL (serial clock input) pin
The SCL pin is a serial clock input pin that processes signals at the rising and falling edges of SCL clock signals.
The SCL pin must be pulled up by a resistor to the V
output device for use.
level and wired-ORed with an open drain (or open collector)
DD
SDA (serial data input/output) pin
The SDA pin is used to transfer serial data to the input/output, and it consists of a signal input pin and n-channel
transistor open drain output pin.
Like the SCL pin, the SDA pin must be pulled up by a resistor to the V
(or open collector) output device for use.
level and wired-ORed with an open drain
DD
WP (write protect) pin
When the WP pin is high, write protection is enabled, and writing into the all memory areas is prohibited. When the
pin is low, writing is possible to all memory areas. Read operations can be performed regardless of the WP pin status.
S0, S1, S2 (slave device address) pin
An individual product is selected by using S0 pin, S1 pin and S2 pin when it connects on the same bus. This product
can set the slave address by connecting S0 pin, S1 pin and S2 pin with V
is necessary to fix the terminal not used as a slave address to V
DD
or GND when the substrate is mounted. It
or GND on the substrate.
DD
No.A1706-5/14
LE24LB1283
Functional Description
1 Start condition
When the SCL line is at the high level, the start condition is established by changing the SDA line from high to low.
The operation of the EEPROM as a slave starts in the start condition.
2 Stop condition
When the SCL line is at the high level, the stop condition is established by changing the SDA line from low to high.
When the device is set up for the read sequence, the read operation is suspended when the stop condition is received,
and the device is set to standby mode. When it is set up for the write sequence, the capture of the write data is ended
when the stop condition is received, and the EEPROM internal write operation is started.
t
t
t
HD.STA
SU.STA
SU.STO
SCL
SDA
Start
condition
Stop
condition
3 Data transfer
Data is transferred by changing the SDA line while the SCL line is low. When the SDA line is changed while the SCL
line is high, the resulting condition will be recognized as the start or stop condition.
t
t
HD.DAT
SU.DAT
SCL
SDA
No.A1706-6/14
LE24LB1283
4 Acknowledge
During data transfer, 8-bits are transferred in succession, and then in the ninth clock cycle period the device on the
system bus receiving the data sets the SDA line to low, and sends the acknowledge signal indicating that the data has
been received. The acknowledge signal is not sent during an EEPROM internal write operation.
SCL
(EEPROM input)
8
9
1
SDA
(Master output)
Acknowlwdge
bit output
SDA
(EEPROM output)
Start
condition
t
t
AA
DH
5 Device addressing
For the purposes of communication, the master device in the system generates the start condition for the slave device
(EEPROM). Communication with a particular slave device is enabled by sending along the SDA bus the device
address, which is 7-bits long, and the read/write command code, which is 1 bit long, immediately following the start
condition.
The upper four bits of the device address are called the device code which, for this product, is fixed as “1010.” Two
or more pieces cannot be connected about this IC because there is no slave address.
This product can connect EEPROM devices up to eight on the system bus by having slave address S0, S1, and S2 in
three bits following the device code, and setting the slave address with S0 pin, S1 pin and S2 pin when the substrate is
mounted.
Device code + slave address input from SDA and the slave address set when this product device code + slave address
for mounted are compared, this product returns the acknowledge for the period of the ninth clock cycle when agreeing,
and the Read or the Write operates according to Read/Write instruction code. It becomes a standby mode if not
agreeing. When reading is executed immediately after the slave device was switched, the random lead command is
used.
Slave
Address
Device Code
LE24LB1283
1
0
1
0
S2
S1
S0
R/W
MSB
LSB
Device address word
No.A1706-7/14
LE24LB1283
6 EEPROM write operation
6-1. Byte writing
When the EEPROM receives the 7-bit device address and write command code "0" after the start condition, it
generates an acknowledge signal. After this, if it receives word address (A15 to A8) generates an acknowledge signal,
receives the word address (A7 to A0), and generates an acknowledge signal when it receives the stop condition, the
rewrite operation of the EEPROM in the designated memory address will start. Rewriting is completed in the t
WC
period after the stop condition. During an EEPROM rewrite operation, no input is accepted and no acknowledge
signals are generated.
Word Address
Data
A A A
A A
12 11
A
10
SDA
1
0
1
0 S2
A9
A1
D0
S1
A8
A7 A6 A5 A4
A0
D7D6D5D4D3 D2D1
ACK
S0 W
A3
A2
15 14 13
ACK
ACK
R/W
Access from master side
6-2. Page writing
This product enables pages with up to 64 bytes to be written. The basic data transfer procedure is the same as for byte
writing: Following the start condition, the 7-bit device address and write command code “0,” word address (n), and
data (n) are input in this order while confirming acknowledge “0” every 9 bits. The page write mode is established if,
after data (n) is input, the write data (n+1) is input without inputting the stop condition. After this, the write data
equivalent to the largest page size can be received by a continuous process of repeating the receiving of the 8-bit
write data and generating the acknowledge signals.
At the point when the write data (n+1) has been input, the lower 6 bits (A0-A5) of the word addresses are
automatically incremented to form the (n+1) address. In this way, the write data can be successively input, and the
word address on the page is incremented each time the write data is input. If the write data exceeds 64 bytes or the
last address of the page is exceeded, the word address on the page is rolled over. Write data will be input into the
same address two or more times, but in such cases the write data that was input last will take effect. Finally, the
EEPROM internal write operation corresponding to the page size for which the write data is received starts from the
designated memory address when the stop condition is received.
Word Address
Data(n)
A
13
A
11
A
A
A
12
A
10
SDA
1
0
1
0 S2
A9
A0
S1
A8
S0 W
A7 A6 A5A4 A3A2 A1
ACK
D7
D6D5D4D3 D2D1D0
15 14
ACK
ACK
ACK
R/W
Data(n+1)
D0
Data(n+x)
D7D6
D1
D7D6
ACK
D1D0
D7
D6
D1D0
D7D6
D1D0
ACK
Access from master side
ACK
ACK
No.A1706-8/14
LE24LB1283
6-3. Acknowledge polling
Acknowledge polling is used to find out when the EEPROM internal write operation is completed. When the stop
condition is received and the EEPROM starts rewriting, all operations are prohibited, and no response can be given to
the signals sent by the master device. Therefore, in order to find out when the EEPROM internal write operation is
completed, the start condition, device address and write command code are sent from the master device to the
EEPROM (slave device), and the response of the slave device is detected.
In other words, if the slave device does not send the acknowledge signal, it means that the internal write operation is
in progress; conversely, if it does send the acknowledge signal, it means that the internal write operation has been
completed.
Execute "0" of the write instruction when you do write or ramdom read continuously by the code that the master
device sends in the acknowledge polling and execute "1" of the lead instruction when you continuously do current
read or sequential read.
Moreover, the command is canceled by inputting the start condition / stop condition after "0" of the write instruction
is executed and ACK=L is confirmed, and it shifts to the standby mode.
Write timing
S0 W
Writting end
0 S2 S1
S0 W
Write timing
SDA
0
1
0
1
0
1
1
0 S2 S1
1
0 1
S1
S0 W
S2
NO ACK
R/W
NO ACK
R/W
ACK
R/W
Access from master side
No.A1706-9/14
LE24LB1283
7 EEPROM read operations
7-1. Current address reading
The address equivalent to the memory address accessed last +1 is held as the internal address of the EEPROM for
both write* and read operations. Therefore, provided that the master device has recognized the position of the
EEPROM address pointer, data can be read from the memory address with the current address pointer without
specifying the word address.
As with writing, current address reading involves receiving the 7-bit device address and read command code “1”
following the start condition, at which time the EEPROM generates an acknowledge signal. After this, the 8-bit data
of the (n+1) address is output serially starting with the highest bits. After the 8 bits have been output, by not sending
an acknowledge signal and inputting the stop condition, the EEPROM completes the read operation and is set to
standby mode.
If the previous read address is the last address, the address for the current address reading is rolled over to become
address 0.
*: If the write data is 1 or more bytes but less than 64 bytes, the current address after page writing is the address
equivalent to the number of bytes to be written in the specified word address +1. If the write data is 64 or more bytes,
it is the designated word address. If the last address (A5-A0=1111b) on the page has been designated by byte write as
the word address, the first address (A5-A0=0000b) on the page serves as the internal address after writing.
Device Address
0 1
0 S2
Data(n+1 address)
SDA
1
S1
S0 R
D7
D6D5D4D3 D2D1D0
ACK
R/W
NO ACK
Access from master side
7-2. Random read
Random read is a mode in which a selected memory address is specified and its data is read. The address is specified
by a dummy write input.
First, when the EEPROM receives the 7-bit device address and write command code "0" following the start condition,
it generates an acknowledge signal. It then receives word address (A15 to A8) and generates an acknowledge signal,
and receives word address (A7 to A0) and generates an acknowledge signal. These operations are used to load the
word address to the address counter in the EEPROM.
Next, the start condition is input again, and the current read is performed. This generates the word address data that
was input using the dummy write input. After the data is generated, if the stop condition is input without the input of
an acknowledge signal, reading is completed, and standby mode is established.
Word Address
Device Address
A
A A
A
12
A A
11 10
SDA
1
0
1
0
A9
A1
A0
S2 S1S0 W
A8
A7 A6 A5 A4 A3 A2
ACK
15
14 13
ACK
R/W
ACK
Dummy Write
Device Address
Data(n)
1
0 1
0
S2 S1
S0 R
D7D6
D1D0
ACK
NO ACK
ACK
R/W
Current Read
Access from master side
No.A1706-10/14
LE24LB1283
7-3. Sequential read
In this mode, the data is read continuously, and sequential read operations can be performed with both current address
read and random read. If, after the 8-bit data has been output, acknowledge “0” is input and reading is continued
without issuing the stop condition, the address is incremented, and the data of the next address is output.
If acknowledge “0” continues to be input after the data has been output in this way, the data is successively output
while the address is incremented. When the last address is reached, it is rolled over to address 0, and the data
continues to be read. As with current address read and random read, the operation is completed by inputting the stop
condition without sending an acknowledge signal.
Device Address
Data(n)
D7D6
D1D0
Data(n+1)
D7
Data(n+2)
D6 D1D0
Data(n+x)
D7D6
D1
ACK
Access from master side
SDA
1
0 1
0
S2
S1
D6
ACK
D1D0
D0
S0 R
D7
ACK
ACK
R/W
ACK
No.A1706-11/14
LE24LB1283
Application Notes
1) Software reset function
Software reset (start condition + 9 dummy clock cycles + start condition), shown in the figure below, is executed in
order to avoid erroneous operation after power-on and to reset while the command input sequence. During the
dummy clock input period, the SDA bus must be opened (set to high by a pull-up resistor). Since it is possible for
the ACK output and read data to be output from the EEPROM during the dummy clock period, forcibly entering H
will result in an overcurrent flow.
Note that this software reset function does not work during the internal write cycle.
Dummy clock cycle × 9
SCL
SDA
2
8
9
1
Start
Start
condition
condition
2) Pull-up resistor of SDA pin
Due to the demands of the I2C bus protocol function, the SDA pin must be connected to a pull-up resistor (with a
resistance from several kΩ to several tens of kΩ) without fail. The appropriate value must be selected for this
resistance (R ) on the basis of the V and I of the microcontroller and other devices controlling this product as
PU IL IL
well as the V –I characteristics of the product. Generally, when the resistance is too high, the operating
OL OL
frequency will be restricted; conversely, when it is too low, the operating current consumption will increase.
R
PU
maximum resistance
The maximum resistance must be set in such a way that the bus potential, which is determined by the sum total (I )
L
of the input leaks of the devices connected to the SDA bus and by R , can completely satisfy the input high level
PU
(V min) of the microcontroller and EEPROM. However, a resistance value that satisfies SDA rise time t and fall
IH
time t must be set.
R
F
R
PU
maximum value = (V
- V )/I
IH L
DD
Example: When V =3.0V and I = 2μA
DD
L
R
PU
maximum value = (3.0V − 3.0V × 0.8)/2μA = 300kΩ
R
PU
R
PU
minimum value
EEPROM
A resistance corresponding to the low-level output
voltage (V max) of SANYO’s EEPROM must be set.
Master
device
SDA
OL
I
I
C
BUS
L
L
R
PU
minimum value = (V
− V )/I
DD OL OL
Example: When V =3.0V, V
DD
PU
= 0.4V and I = 1mA
OL
OL
minimum value = (3.0V − 0.4)/1mA = 2.6kΩ
R
Recommended R
setting
is set to strike a good balance between the operating frequency requirements and power consumption. If it is
PU
R
PU
assumed that the SDA load capacitance is 50pF and the SDA output data strobe time is 500ns, R
will be about
PU
R
PU
= 500ns/50pF = 10kΩ.
No.A1706-12/14
LE24LB1283
3) Precautions when turning on the power
This product contains a power-on reset circuit for preventing the inadvertent writing of data when the power is
turned on. The following conditions must be met in order to ensure stable operation of this circuit. No data
guarantees are given in the event of an instantaneous power failure during the internal write operation.
Standard value
Item
Symbol
unit
min
typ
max
Power rise time
t
t
100
0.2
ms
ms
V
RISE
Power off time
10
OFF
Power bottom voltage
V
bot
t
RISE
V
DD
t
OFF
Vbot
0V
Notes:
1) The SDA pin must be set to high and the SCL pin to low or high.
2) Steps must be taken to ensure that the SDA and SCL pins are not placed in a high-impedance state.
A. If it is not possible to satisfy the instruction 1 in Note above, and SDA is set to low during power rise
After the power has stabilized, the SCL and SDA pins must be controlled as shown below, with both pins set to high.
V
V
DD
DD
t
LOW
SCL
SDA
SCL
SDA
t
t
SU.DAT
SU.DAT
t
DH
B. If it is not possible to satisfy the instruction 2 in Note above
After the power has stabilized, software reset must be executed.
C. If it is not possible to satisfy the instructions both 1 and 2 in Note above
After the power has stabilized, the steps in A must be executed, then software reset must be executed.
4) Noise filter for the SCL and SDA pins
This product contains a filter circuit for eliminating noise at the SCL and SDA pins. Pulses of 100ns or less are not
recognized because of this function.
5) Function to inhibit writing when supply voltage is low
This product contains a supply voltage monitoring circuit that inhibits inadvertent writing below the guaranteed
operating supply voltage range. The data is protected by ensuring that write operations are not started at voltages (typ.)
of 1.3V and below.
No.A1706-13/14
LE24LB1283
6) Notes on write protect operation
This product prohibits all memory area writing when the WP pin is high. To ensure full write protection, the WP is
set high for all periods from the start condition to the stop condition, and the conditions below must be satisfied.
Standard value
Item
Symbol
unit
min
typ
max
WP Setup time
WP Hold time
t
t
600
600
ns
ns
SU.WP
HD.WP
WP
t
t
HD.WP
SU.WP
SCL
SDA
Stop condition
Start condition
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This catalog provides information as of March, 2011. Specifications and information herein are subject
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PS
No.A1706-14/14
相关型号：
LE25ABD-TRLE
2.5V FIXED POSITIVE LDO REGULATOR, 0.5V DROPOUT, PDSO8, ROHS COMPLIANT, SOP-8
STMICROELECTR
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