LV4141W_技术文档

Ordering number : EN8927A

Bi-CMOS LSI

For LCD Panel Drive

LV4141W

Single Chip IC

Overview

The LV4141W is single chip IC for LCD panel drive.

Functions

• Analog block RGB Decoder/Driver

• Digital block Timing Generator

Specifications

Absolute Maximum Ratings at Ta = 25°C

Parameter

Symbol

Conditions

Ratings

Unit

V

Maximum supply voltage

V

1 max

Analog LOW type

6

12

CC

2 max

max

Analog HIGH type

V

CC

V

Digital type

4.5

V

DD

Allowable power dissipation

Operating temperature

Storage temperature

Input pin voltage

Pd max

Ta ≤ 75°C * Mounted on a board.

350

mW

°C

V

Topr

Tstg

-15 to +75

-40 to +125

V

A

D

Analog input pin (other than pin 33)

Analog input pin (33PIN)

-0.3 to V 1

CC

IN

-0.3 to 10

V

Digital input pin (other than pins 6, 7, and 8)

Digital input pin (6, 7, 8PIN)

-0.3 to V +0.3

DD

V

-0.3 to +4.5

V

* : Mounted on a board : 30×30×1.6mm³, glass epoxy board

Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to

"standard application", intended for the use as general electronics equipment (home appliances, AV equipment,

communication device, office equipment, industrial equipment etc.). The products mentioned herein shall not be

intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace

instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety

equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case

of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee

thereof. If you should intend to use our products for applications outside the standard applications of our

customer who is considering such use and/or outside the scope of our intended standard applications, please

consult with us prior to the intended use. If there is no consultation or inquiry before the intended use, our

customer shall be solely responsible for the use.

Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate

the performance, characteristics, and functions of the described products in the independent state, and are not

guarantees of the performance, characteristics, and functions of the described products as mounted in the

customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent

device, the customer should always evaluate and test devices mounted in the customer

's products or

equipment.

41107 TI PC B8-6227, 6576 No.8927-1/27

LV4141W

Operating Ratings at Ta = 25°C

Parameter

Symbol

Conditions

Ratings

Unit

V

Maximum supply voltage

V

1

Analog LOW type

3.0

7.0

CC

V

2

Analog HIGH type

Digital type

V

4.5

V

DD

Operating voltage range

V

1op

2op

op

Analog LOW type

Analog HIGH type

Digital type

2.7 to 3.6

6 to 9.5

2.7 to 3.6

V

CC

V

DD

Input Signal Voltage

Ratings

typ

Parameter

Conditions

R, G, B input pin (RGB input mode)

Unit

min

max

0.42

Recommended input amplitude

0.35

Vp-p

Electrical DC Characteristics

Unless otherwise specified, the setting 2 must be made.

Unless otherwise specified, V 1 = 3V, V 2 = V COM = 7V, GND1 = GND2 = GNDCON = 0,

CC CC CC

V

1 = V 2 = V 0 = 3V, V 1 = V 2 = V 0 = 0, Ta = 25°C

DD DD DD SS SS SS

[Current Characteristics]

Ratings

typ

Parameter

Symbol

Conditions

Unit

min

9.5

max

18.5

2

Current dissipation V

1

2

I

11

Enter SIG4 (V = 0mV) to (A).

L

Measure the current value of I 1.

CC

Normal

14

mA

CC

Standby

Normal

Standby

Normal

Standby

Sleep

1

1.5

0

1.5

2.8

0.1

6.5

6

Current dissipation V

I

2

Enter SIG4 (V = 0mV) to (A).

L

Measure the current value of I 2.

CC

3.5

0.2

8.5

8

CC

Current dissipation V , logic

DD

I

1

2

3

Enter SIG4 (V = 0mV) to (A).

L

Measure the current value of I 11

DD

3.5

3

DD

and I 22.

DD

I

1

1.6

2.5

1, I 2, I 3 = I 11+I 22

DD DD DD DD DD

[Digital block input/output characteristics]

Ratings

typ

Parameter

Symbol

Conditions

Unit

min

max

L-level input voltage

H-level input voltage

H-level output voltage

L-level output voltage

Output transition time

V

Digital block input pin (Note 1)

0.3V

DD

V

IH

V

0.7V

IL

DD

2.8

VOHT

V

I

= 3.0V I

= -1.0mA (Note 2)

OH

V

DD

= 1.0mA (Note 2)

V

0.3

30

10

V

OL

t

Load 30pF (see Fig. 2)

ns

TLH

t

THL

Cross point time difference

CHK duty

ΔT

Load 30pF

Measure CKH1 and CKH2.(see Fig. 3)

Load 30pF

DTYHC

47

50

53

%

Measure the duty of CKH1 and CKH2.

(Note 1) Digital block input pins : LOAD, DATA, SCLK, VDIN, HDIN, CLPIN

(Note 2) Digital block output pin (pins 17 to 30)

No.8927-2/27

LV4141W

Electrical AC Characteristics (1)

Unless otherwise specified, the setting 1 and 2 must be made.

Unless otherwise specified, V 1 = 3V, V 2 = V COM = 7V, GND1 = GND2 = GNDCON = 0,

CC CC CC

V

1 = V 2 = V 0 = 3V, V 1 = V 2 = V 0 = 0, Ta = 25°C

DD DD DD SS SS SS

Unless otherwise specified, measure non-inverted output for P TP40, TP43, TP45 outputs.

[RGB signal system]

Ratings

typ

Parameter

Symbol

GTP

Conditions

Unit

dB

min

max

Input-output gain TYP

Enter SIG3 to (A) and measure the ratio between

the output amplitude (white to black) and input

amplitude of TP43.

14

-2

16

18

Input-output gain MIN

GMN

GMX

Enter SIG3 to (A) and measure the ratio between

the output amplitude (white to black) and input

amplitude of TP43.

1

4.5

dB

Input-output maximum gain,

MAX

Enter SIG3 to (A) and measure the ratio between

the output amplitude (white to black) and input

amplitude of TP43.

19.5

21.5

23.5

Frequency characteristics

FCH

FCL

Assume that the output amplitude of TP43 when

SIG1 (0dB, 100kHz) is entered to (A) is 0dB.

Change the input signal frequency to change and

determine the frequency at which the output

amplitude becomes -3dB.

3.5

2.5

MHz

FCH when the serial bus LPF = HIGH and FCL

when LPF = LOW

Input/output delay rate

TD

Enter SIG8 to (A). Measure the delay time from the

input signal 2T pulse peak to the peak of TP43

non-inverted output.

0

3.55

3.4

100

200

ns

Antipole output DC voltage

change amount

COMBMX

COMBMN

Measure TP38 output. DC I

=

1m

V

O

ACOMBMX when COMB = 63 and COMBMN

when COMB = 0

2.6

3.6

Output DC voltage

VDSDH

Measure the TP50 voltage by setting V 2 = 8,5V

CC

and SIG center level changeover = low voltage

3.5

V

2 = 8.5V

CC

mode.

Output DC voltage

2 = 7V

VDSD

Measure the TP50 voltage by setting V 2 = 7V

CC

and SIG center level changeover = high voltage

3.4

3.6

3.7

V

CC

mode.

RGB signal output DC voltage

2 = 8.5V

V

H

Set V 2 = 8.5V and SIG center level changeover

CC

= low voltage mode and enter SIG4 (V = 0mV)

L

3.3

OUT

V

CC

into (A). Adjust the serial bus BRIGHT to set TP43

output to 3Vp-p and measure the DC voltage of

TP40, TP43, and TP45.

RGB signal output DC voltage

2 = 7V

V

Set V 2 = 7V and SIG center level changeover =

CC

high voltage mode, and enter SIG4 (V = 0mV) to

L

3.3

3.5

3.7

V

OUT

V

CC

(A). Adjust the serial bus BRIGHT to set the TP43

output to 3Vp-p and measure the DC voltage of

TP40, TP43, and TP45.

RGB signal output DC voltage

difference

ΔVOUT

Determine the maximum of differences among

0

120

mV

V

measurements of TP40, TP43, and TP45 of V

OUT

of previous item.

Brightness change rate

BRTMX

Measure the change rate of the black level of

TP40, TP43, and TP45 outputs when SIG2 is

entered to (A) and BRT is changed from 128 to

255.

2

2.5

BRTMN

COMWMX

COMWMN

Measure the change rate of the white level of

TP40, TP43, and TP45 outputs when SIG2 is

entered to (A) and BRT is changed from 128 to 0.

Measure the difference between non-inverted and

inverted levels of TP38 output when (A) = SIG2 is

entered and COMW is set to 255.

-2.5

-2

V

Antipole output change

amount

4.6

Measure the difference between non-inverted and

inverted levels of TP38 output when (A) = SIG2 is

entered and COMW is set to 0.

0.1

Continued on next page.

No.8927-3/27

LV4141W

Continued from preceding page.

Ratings

typ

Parameter

Symbol

Conditions

Unit

V

min

1.3

max

Sub-brightness R change

rates

SBBRTR

Measure the change amount of TP45 output black

level when SIG2 is entered in (A) and COMW is

changed from 128 to 255 and that of TP45 output

white level change amount when COMW is

changed from 128 to 0.

1.7

Sub-brightness B change

rates

SBBRTR

Measure the change amount of TP40 output black

level when SIG2 is entered in (A) and COMW is

changed from 128 to 255 and that of TP45 output

white level when COMW is changed from 128 to 0.

Determine the level difference of non-inverted

output amplitude (white to black) of TP40, TP43,

and TP45 when SIG3 is entered to (A).

1.3

1.7

0

V

Gain difference between RGB

signals

ΔGRGB

-0.6

2.0

0.6

dB

Sub-contrast R change rate

SBCNTR

Measure the non-inverted output (white to black) of

TP45 for the non-inverted output (white to black) of

TP43 when SIG3 is entered to (A) and when

R-CNT = 0 and R-CNT = 255.

Sub-contrast B change rate

SBCNTB

Measure the non-inverted output (white to black) of

TP40 for the non-inverted output (white to black) of

TP43 when SIG3 is entered to (A) and when

B-CNT = 0 and B-CNT = 255.

2.0

dB

RGB inverted/non-inverted

gain difference

ΔGINV

Determine the difference of inverted output

amplitude for the non-inverted output amplitude

(white to black) of TP40, TP43, and TP45 when

SIG3 is entered to (A).

-0.5

0

0.5

[RGB signal system]

Ratings

typ

Parameter

Symbol

Conditions

Unit

mV

min

max

Black level potential difference

between RGB signals

ΔVBL

Determine the difference between highest and

lowest black levels for inverted and non-inverted

outputs of TP40, TP43, and TP45 when SIG3 is

entered to (A).

300

Gamma gain

GγL

GγM

GγH

Enter SIG7 into (A) and set the non-inverted output

amplitude (black and white) of TP43 at γ1 = 120, γ2

= 0 to 2.7Vp-p with CONT. Adjust the amplitude

(black and white) to 3.5Vp-p with γ2 and the black

level to 1.5V with BRT. Measure VG1, VG2 and

VG3 and calculate as follows :

23

12

23

26

15

26

29

18

29

dB

GγL = 20log (VG1/0.0357)

GγM = 20log (VG2/0.0357)

GγH = 20log (VG3/0.0357)

(See Fig. 4.)

γ1 adjustment variable range

γ2 adjustment variable range

Antipole transition time

Vγ1MN

Vγ1MX

Enter SIG7 to (A) and set the TP43 output (black to

black) to 3Vp-p through BRIGHT adjustment.

Read the γ gain change point at γ2 = 0, γ2 = 255 by

referring to the IRE level of input signal :

Vγ1MN forγ1 = 0 Vγ1MX for γ1 = 255

Enter SIG7 to (A) and set the TP43 output (black to

black) to 3Vp-p through BRIGHT adjustment.

Read the γ gain change point atγ1 = 0, γ1 = 255 by

referring to the IRE level of input signal :

Vγ2MN forγ2 = 0 Vγ2MX for γ2 = 255

Enter SIG3 to (A) and set the output amplitude of

TP38 to 3Vp-p. Measure tCOMH for rise and

tCOML for fall. Load : 1000pF

0

IRE

100

Vγ2MN

Vγ2MX

IRE

tCOMH

tCOML

1

1.5

μs

RGB output black limiter

variablerange

VBLIMN

VBLIMX

Enter SIG2 to (A) and measure the amplitude of

the black side limiter of inverted/non-inverted

TP38, 40, 43 and 45 output.

4.5

4

Vp-p

2

RGB output white limiter

variablerange

VWLIMN

VWLIMX

Enter SIG2 to (A) and measure the amplitude of

the white side limiter of inverted/non-inverted

TP38, 40, 43 and 45 output.

Vp-p

2.2

Continued on next page.

No.8927-4/27

LV4141W

Continued from preceding page.

Parameter

Ratings

typ

Symbol

Conditions

Unit

V

min

3.3

max

3.7

Black limiter Dcvoltage

DVBLIM

Enter SIG4 (V = 0 mV) to (A) and adjust BLIM to

L

3.5

set the TP43 output to 3Vp-p. Measure the DC

voltage of TP40, Tp43, and TP45.

White limiter Dcvoltage

DVWLIM

Enter SIG4 (V = 350mV) into (A), measure the

L

3.3

3.5

3.7

V

DC voltage of TP40, TP43, and TP45, and

determine the difference from the above V

.

OUT

[Sync. separation, TG]

Ratings

typ

Parameter

Symbol

WSSEP

Conditions

Unit

min

max

Input sync signal width

sensitivity

Enter SIG4 (V = 0mV, VS = 143mV, WS variable)

L

2.0

μs

to (A) and confirm synchronization with the

TP15HD output. Narrow WS of SIG4 from 4.7μs

and determine WS at which synchronization

between the input and TP15HD output is lost.

Sync separation input

sensitivity

VSSEP

Enter SIG4 (V = 0mV, WS = 4.7μs, VS variable)

40

60

mV

L

to (A) and confirm synchronization with the

TP15HD output. Reduce VS of SIG4 from 143mV

and determine VS at which synchronization

between the input and TP15HD output is lost.

Sync separation output delay

rate

TDSY1

TDSY2

Enter SIG4 (V = 0mV, WS = 4.7μs, VS = 143mV)

300

150

500

300

700

550

ns

L

into (A) and measure the delay amount from the

TP2RPD output. Assume that the period from fall

of input HSYNC to a front edge of RPD output is

TDSY1 and the period from rise of input HSYNC to

the rear edge of RPD output is TDSY2.

Horizontal pull-in range

HPLLN

HPLLP

Enter SIG4 (V = 0mV, WS = 4.7μs, and VS =

500

Hz

L

143mV, horizontal frequency variable) to (A) and

confirm synchronization with TP15HD output.

Determine the horizontal frequency f of SIG4 and

H

calculate

HPLLN = f -15734

H

HPLLP = f -15625.

H

Package Dimensions

unit : mm (typ)

3190A

12.0

10.0

48

33

49

32

17

64

1

16

0.15

0.5

0.18

(1.25)

SANYO : SQFP64(10X10)

No.8927-5/27

LV4141W

Conditions of setting to measure the electric characteristic

Following settings must be made before measurement of electric characteristics.

Setting 1. System reset

Turn ON SW56 and start V56 from GND in order to perform system reset for MOS block.

(See fig. 1-1.)

The default value is set for the serial bus.

Setting 2. Horizontal AFC adjustment

Enter SIG4 (V = 0mV) to (A) and adjust VR1 so that the width of WL and WH

L

becomes equal in the TP2 output waveform.(See fig 1-2.)

(Note) In order to measure the 2MHz or more band for measurement items, such as the RGB signal frequency

characteristics, etc., it is necessary to pass through the sample hold circuit via serial bus.

V

1,V

DD

2

DD

V56 (RESET)

Tr

Tr > 10μs

Fig.1-1 System reset

SIG4

V-sync

TP2

Approx.1/2V

DD

Fig.1-2 Horizontal AFC adjustment

No.8927-6/27

LV4141W

Electric characteristics measurement method

t

THL

TLH

90%

10%

Fig.2 Output transition time measurement conditions

ΔT

50%

ΔT

Fig.3 Cross point time difference measurement conditions

White

VG3

VG2

3.5V

VG1

1.5V

Black

Input

Fig.4 γ characteristics measurement conditions

No.8927-7/27

LV4141W

Block Diagram

No.8927-8/27

LV4141W

Pin Description

Pin No.

Pin Name

I/O

Pin Description

Oscillation cell power supply (3V)

1

V

1

-

O

-

DD

RPD

2

Phase comparison output

GND for oscillation cell

3

V

1

SS

4

TEST4

TEST5

LOAD

DATA

SCLK

I

Oscillator cell input (also used for test)

Oscillator cell output

5

O

I

6

Load input for serial bus

Data input for serial bus

Clock input for serial bus

Test pin 8

7

I

8

I

9

TEST8

TEST3

I

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

I

Test pin 3

V

2

-

Digital system power supply (3V)

Digital output system power supply (3V)

Backlight control pulse output

Backlight drive pulse output

H-drive output

DD

O

-

DD

BLSW

BLHD

HD

O

-

V

O

Digital output system ground

H-start pulse output (inverted)

H-start pulse output

SS

XSTH

STH

O

-

CKH2

CKH1

TEST6

TEST7

XDSG

DSG

H-clock 2 pulse output

H-clock 1 pulse output

Test pin 6

Test pin 7

Drain hold timing pulse output (inverted)

Drain hold timing pulse output

V-start pulse output (inverted)

V-start pulse output

XSTV

STV

CKV2

CKV1

XENB

ENB

V-clock 2 pulse output

V-clock 1 pulse output

Enable pulse output (inverted)

Enable pulse output

VD

V-drive pulse output(positive polarity)

Digital system ground

V

2

SS

SHIN

I

Input pin for test

CSVO

O

-

Open collector output for vertical scan changeover

Open collector output for lateral scan changeover

Time constant pin for antipole output DC return

Antipole output ground

CSHO

FBCOM

GNDCOM

COMOUT

O

-

Antipole output

V

COM

CC

Power supply for antipole output (7V)

B output

BOUT

FBB

O

-

Time constant pin for B-output DC return

7V ground

GND2

GOUT

FBG

O

-

G output

Time constant pin for G-output DC return

R output

ROUT

FBR

Time constant pin for R-output DC return

7V power supply

V

2

CC

SIGCENT

I

Time constant pin for R, G, B, COM, and DSD output DC voltage

Analog 3V power supply

Drain hold data output

V

1

-

CC

DSDOUT

NC

O

-

NC

VREG

RIN

-

Reference power supply

R signal input

I

GIN

I

G signal input

BIN

I

B signal input

Continued on next page.

No.8927-9/27

LV4141W

Continued from preceding page.

Pin No.

Pin Name

I/O

Pin Description

56

57

58

59

60

61

62

63

64

RESET

SYNC IN

VSEP TC

VDIN

I

System reset

Sync signal input (composite)

O

I

Time constant pin for separation of vertical sync

VSYNC input

HDIN

I

CSYNC/HSYNC input

Test pin 1

TEST1

TEST2

CLPIN

GND1

I

Test pin 2

I

External clamp input

Analog 3V power supply

-

Analog pin function description

Pin No.

Pin Name

Pin Voltage

Pin Description

Input pin for test

Equivqlent Circuit

33

SHIN

-

Normally, connect to the ground for use.

V

2

DD

10kΩ

1kΩ

33

40kΩ

10kΩ

V

2

SS

34

35

CSVO

CSHO

-

Vertical and horizontal inversion control

output pin. Output is made from the open

collector. Connect a resistor to CSVO and

CSHO pins of the panel power supply. The

resistance must comply with the panel

specification.

V

2

CC

34

35

GND2

36

41

44

46

FBCOM

FBR

1.5V

Feedback circuit smoothing capacitor pin for

control of antipole output DC level and RGB

output DC level.

V

1

CC

FBG

FBB

Because of high impedance, a capacitor with

small leakage is used.

1kΩ

36

41

44

46

1kΩ

100kΩ

GND1

37

38

GNDCOM

COMOUT

0V

Ground pin of antipole output

2.6 to 3.55V

Antipole AC output pin that can adjust the

output DC voltage with variable resistor of

serial bus. When the signal output DC voltage

V

COM

CC

150Ω

has been changed to V 2/2 and

CC

V

2*21/51 with the serial bus and the

CC

38

voltage has been applied to SIC.C from the

outside, the DC voltage of antipole output

follows.

20Ω

GNDCOM

39

V

COM

7V

Power pin of antipole output

CC

Continued on next page.

No.8927-10/27

LV4141W

Continued from preceding page.

Pin No.

Pin Name

Pin Voltage

Pin Description

Equivqlent Circuit

40

43

45

ROUT

GOUT

BOUT

V

2/2

RGB elementary color signal output pin. Can

be changed to V 2/2 and V 2*21/51 with

CC

V

2

CC

V

2*21/51

CC

the serial bus.

40

43

45

20Ω

1kΩ

GND2

42

47

48

GND2

0V

7V

2/2

V

2 ground.

CC

V

2

7V power supply.

CC

SIGCENT

V

Pin to set the DC voltage of R/G/B/COM/DSD

output. Connect a capacitor of 0.01μF

CC

V

2

CC

between this pin and GND2. When the signal

output DC voltage is to be used with the

setting other than V 2/2 and V 2*21/51,

150kΩ

300Ω

CC

48

set to the SIG center level changeover: high

voltage mode with the serial bus and apply the

voltage (3.3 - 3.7V) from the outside.

105kΩ

GND2

49

50

V

1

3.0V

Analog 3V power supply.

CC

DSDOUT

V

2/2

Drain hold data power output pin. The output

CC

2*21/51

V

CC

DC voltage can be set to V 2/2 and

CC

V

2

CC

1kΩ

V

2*21/51 with the serial bus. Connect a

CC

capacitor of 1μF between this pin and GND2.

10Ω

20Ω

1kΩ

50

1kΩ

GND2

10kΩ

51

52

NC

-

Pin not used

VREG

2.0V

Regulator output pin. Connect an external

capacitor of 1μF or more.

V

1

CC

52

18.5kΩ

30kΩ

GND1

1

53

54

55

RIN

GIN

BIN

1.45V

Analog RGB signal input pin.The standard

input signal level is 0.5Vp-p (from sink chip to

white 100%). Pedestal clamp is made with an

external coupling capacitor.

V

CC

53

54

55

1kΩ

20μA

GND1

Continued on next page.

No.8927-11/27

LV4141W

Continued from preceding page.

Pin No.

56

Pin Name

RESET

Pin Voltage

-

Pin Description

Equivqlent Circuit

C-MOS circuit reset pin. Normally, this is used

with the capacity connected to the ground.

(Threshold value = 2.0V)

V

1

DD

2μA

300Ω

56

1kΩ

GND1

57

58

64

SYNCIN

VSEPTC

GND1

1.6V

1.7V

-

Input pin for sync separation.

V

1

Input is made via the external capacitor.

DD

1kΩ

57

500Ω

0.6μA

12μA

GND1

Time constant connection pin for vertical sync

separation.

V

1

DD

500Ω

1kΩ

58

1kΩ

20μA

GND1

Analog 3V power supply.

Digital pin function description

Pin No.

Pin Name

Pin Voltage

Pin Description

Equivqlent Circuit

1

2

V

1

-

Power supply dedicated for VCO

Phase comparator output pin

DD

RPD

V

1

DD

2

1kΩ

6kΩ

100kΩ

1.5V

100kΩ

V

1

SS

3

V

1

0

-

Groud pin for VCO

SS

4

5

TEST4

TEST5

TEST4 is an input pin for test.

TEST5 is an output pin for test.

Use while fixing TEST4 to the ground potential

and keeping TEST5 open.

V

1

DD

4

5

600Ω

V

1

SS

Continued on next page.

No.8927-12/27

LV4141W

Continued from preceding page.

Pin No.

Pin Name

Pin Voltage

-

Pin Description

Equivqlent Circuit

6

7

8

LOAD

DATA

SCLK

Serial bus input pin.

Input possible up to 4.5V regardless of the

2 power voltage.

V

2

DD

V

DD

2kΩ

6

7

8

V

2

SS

9

TEST8

TEST3

TEST1

TEST2

CLPIN

-

TEST8, TEST3, TEST1, and TEST2 are input

pins for test.

V

2

DD

10

61

62

63

Normally, this is used at the ground potential

or in the open state. CLPIN is an input pin for

external clamp. Use after setting to the

external clamp input with the serial bus.

Connect the CLPIN pin to the ground in cases

other than external clamp input.

9

2kΩ

10

61

62

63

50kΩ

V

2

SS

11

12

V

2

0

-

Power pin for digital block

Power pin for digital system output

Digital output pin.

DD

13

14

15

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

16

BLSW

BLHD

HD

XSTH

STH

CKH2

CKH1

TEST6

TEST7

XDSG

DSG

V

0

DD

XSTV

STV

V

0

SS

CKV2

CKV1

XENB

ENB

VD

V

O

-

Power pin for digital system output.

Ground

SS

32

V

2

0

-

Digital ground pin.

SS

59

60

VDIN

HDIN

External VD and HD input pins. When using,

set them to the external synchronous signal

input with the serial bus. Connect VDIN and

HDIN pins to the ground in cases other than

the external synchronous signal input.

V

2

DD

50kΩ

2kΩ

59

60

V

2

SS

No.8927-13/27

LV4141W

No.8927-14/27

LV4141W

No.8927-15/27

LV4141W

Input sine wave (1)

SG No.

Sine wave

SIG1

With/without sine wave video signal

(Amplitude and frequency variable)

150m

← Value shown in the left 0dB

143m

SIG2

357mV

143mV

SIG3

SIG4

150

5-step staircase wave

143

V

amplitude variable

L

VS variable:

143mV, unless otherwise specified.

WS variable:

4.7μs, unless otherwise specified.

variable :

V

L

VS

f

H

WS

NTSC 15.734kHz

f

H

PAL 15.625kHz

unless otherwise specified.

Input sine wave (2)

SG No.

Sine wave

SIG5

30μs

5μs

GND

V

amplitude variable

L

V

L

SYNC

Timing

SIG6

SIG7

SIG8

75mV

Frequency variable

10-step staircase wave

2T pulse

175mV

143mV

357mV

143mV

357mV

143mV

No.8927-16/27

LV4141W

Serial bus communication specifications

(1) Conditions for serial transfer

DATA

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

D15

ts1

th1

50%

SCLK

tw1H

tw1L

LOAD

50%

ts0

th0

tw2

Parameter

Symbol

Conditions

min

typ

max

unit

Serial transfer

Data setup time

ts0

LOAD setup time to start SCLK.

DATA setup time to start SCLK.

Hold time of LOAD for fall of SCLK.

Data hold time to start SCLK.

SCLK pulse width.

150

ns

μs

ts1

150

160

1.0

Data hold time

Pulse width

th0

th1

tw1L

tw1H

tw2

SCLK pulse width.

LOAD pulse width.

No.8927-17/27

LV4141W

(2) 3-wave serial format

DATA

SCLK

LOAD

Data length : 16bit

Clock frequency : 3MHz or less

DATA loaded at start of "LOAD" only when 16-clock of "SCLK" is entered in the "LOAD" "L" period.

(Note) Data not loaded in case of 15 or less clocks or 17 or more clocks in "LOAD" "L" period

(3) Data output timing

1. Various mode settings

Some items (with a circle in the V latch column of data specification) have data set at fall of the vertical

synchronous signal and some (without a mark in the V latch column) do not.

When data immediately before the vertical synchronous signal is transferred for multiple times, data immediately

before vertical synchronous signal becomes effective for items to be set with the vertical synchronous signal. For

items for whcih no setting is made, data becomes effective each time "DATA" is loaded.

2. Setting of the electric volume

D/A output data is changed at the same time with loading of "DATA."

No.8927-18/27

LV4141W

(4) Data specifications

(4-1) Various mode settings 1

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

Description

V latch

Default

0

1

0

1

0

1

0

1

0

1

0

1

0

Not used

○

LPF characteristic changeover : High

LPF characteristic changeover : Low

Not used

○

Not used

System changeover NTSC

System changeover PAL

External VD input changeover OFF (used to

separate IC sync)

0

1

0

External VD input changeover ON (with

external VD input)

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

Normal mode

○

For test. Do not set.

HD output polarity, positive

HD output polarity, negative

VD output polarity, positive

VD output polarity, negative

Panel selection, 521×218 :L1

Panel selection, 557×234 :L2

Not used

○

Not used

Field overlap method, odd number on even

number

○

0

1

0

1

0

Field overlap method, even number on odd

number

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

Horizontal inversion, normal scan

○

Horizontal inversion, reverse scan

Vertical inversion, from top to bottom

Vertical inversion, from bottom to top

Not used

Normal mode

For test. Do not set.

External SYNC input polarity change, negative

polarity

○

0

1

0

1

0

External SYNC input polarity, positive polarity

External clamp input changeover OFF (IC

internal pulse used)

0

1

0

1

0

External clamp input changeover ON (external

pulse input)

HSYNC/CSYNC input changeover. SYNC IN

valid

○

HSYNC input changeover. HD IN valid

No.8927-19/27

LV4141W

(4-1) Various mode settings 2

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

Description

V latch

Default

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

×

0

1

0

1

0

×

0

1

0

1

0

×

0

1

0

1

0

1

0

1

0

1

0

1

0

Normal mode

○

For test. Do not set.

VGATE function ON

○

VGATE function OFF

Normal mode

For test. Do not set.

SIG center level changeover Low voltage

SIG center level changeover High voltage

Normal mode

○

For test. Do not set.

HC5 HC4 HC3 HC2 HC1 H-position setting, 2fh×31Step (Note 1)

VP2 VP1 VP0 V-position setting, 1H×4Step (Note 2)

○

10000

010

×

HD6 HD5 HD4 HD3 HD2 HD phase setting, 4fh×31Step (Note 3)

HW5 HW4 HW3 HW2 HW1 BLHD pulse setting, 2fh×31Step (Note 4)

00000

10000

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

Not used

Normal mode

○

For test. Do not set.

V blanking period CKH?STH stop OFF

V blanking period CKH/STH stop ON

H blanking period CKH stop OFF

H blanking period STH stop ON

Normal mode

○

For test. Do not set.

HD/VD output ON

○

HD/VD output OFF (HD generation counter stop)

BLHD output ON

BLHD output OFF (BLHD generation counter

stop)

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

Backlight OFF (BLSW = 3V)

Backlight ON (BLSW = 0V)

Normal mode

○

For test. Do not set.

Horizontal system counter operation

○

Horizontal system counter stop

(effective at standby only)

0

1

0

1

0

1

0

1

0

1

0

Not used

No.8927-20/27

LV4141W

(4-1) Various mode settings 3

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

Description

Standby mode (Note 6)

V latch

Note 6

Default

0

1

0

1

0

1

0

1

0

1

0

○

Sleep mode (Note 6)

Normal mode (Note 6)

Not used

Blanking at transfer to normal ON

Blanking at transfer to normal OFF

○

Blanking period at transfer to normal changed to 0.25

sec

0

1

0

1

0

Blanking period at transfer to normal changed to 0.5

sec

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

×

0

Normal mode

○

For test. Do not set.

Sample hold phase SHS1 (Note 5)

Sample hold phase SHS2 (Note 5)

Sample hold phase SHS3 (Note 5)

Sample hold phase SHS4 (Note 5)

Sample hold phase SHS5 (Note 5)

Sample hold phase SHS6 (Note 5)

Sample hold phase, ALL through (Note 5)

Normal mode

○

For test. Do not set.

(4-2) Electronic volume setting

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

Description

Default

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 Not used

DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 BRIGHT adjustment

DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 CONTRAST adjustment

DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 R-BRIGHT adjustment

DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 B-BRIGHT adjustment

10010101

10001100

10000000

01100100

00000000

DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0

γ

-1 adjustment

-2 adjustment

γ

DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 Not used

DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 R-CONT adjustment

DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 B-CONT adjustment

DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 BLKLIMT adjustment

DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 Not used

DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 VCO adjustment

10000000

10101100

10000000

0000

×

DA3 DA2 DA1 DA0 WHTLIMT adjustment

DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 COM amplitude adjustment

DA5 DA4 DA3 DA2 DA1 DA0 COM level adjustment

DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 For test. Do not set.

10000000

100000

×

No.8927-21/27

LV4141W

(Note 1) H-Position set

(1Step = 2×1/fh) : 1/fh = 90ns

CLK(fh)

STH

10001(+1)

10000(Default)

01111(-1)

Step 1 Step 1

Center

Step 15

Step 16

(Note 2) V-Position set

-2H

-1H

(VD)

2H

(VD)

STV(Default)

+1H

(VD)

+2H

(VD)

(Note 3) HD phase set

(1Step = 4×1/fh)

HSYNC

HD

Approx.6.5μs

00000

Approx.2μs

(Default)

11111

HD

Step 31

No.8927-22/27

LV4141W

(Note 4) BLHD phase set

(1Step = 2×1/fh)

00000

Step 16

Approx.7μs

BLHD

10000

(Default)

Step 15

11111

(Note 5) Sample hold phase

S/H pulse timing

CKH

A

S/H3

S/H4

B

R

G

B

S/H2

S/H4

C

S/H1

SH1

D

E

SH3 SH2

SH4

F

CSH = H (Normal)

SHS1

SHS2

SHS3

SHS4

SHS5

SHS6

SH1

SH2

SH3

SH4

B

F

C

A

E

D

B

F

E

C

A

F

D

B

A

E

C

B

D

C

CSH = L (Inverted)

SHS1

SHS2

SHS3

SHS4

SHS5

SHS6

SH1

SH2

SH3

SH4

D

F

E

A

C

D

F

B

D

E

A

C

E

F

B

D

F

C

E

A

B

C

A

SH1 : SH pulse for G signal

SH3 : SH pulse for B signal

SH2 : SH pulse for R signal

SH4 : SH pulse for RGB signal

No.8927-23/27

LV4141W

(Note 6) Powr save function

a) Signal output in each mode

Output Pin

RGBout

DSD

Normal

Standb

Sleep

Normal output

all OFF

COM

CKH1

CKH2

STH

CKH1 = H

CKH2 = L

STH = H

XSTH

DSG

XSTH = L

PCG1 = H

PCG2 = L

ENB = H

XDSG

ENB

Normal output

XENB

CKV1

CKV2

STV

XENB = L

CKV1 = H *

CKV2 = L *

STV = H *

XSTV = L *

all “L”

XSTV

HD

VD

Normal output

BLHD

BLSW

Normal output

* After transfer from normal to standby, the respective state becomes effective after normal output for the 1V period.

b) Transfer/return to each mode

• Transfer/return between normal and standby modes is acknowledged with the vertical synchronous signal.

• Transfer/return between standby and sleep modes is changed over each time the serial data is transmitted.

• Transfer/return between normal and sleep modes cannot be made directly.

Be sure to carry out changeover via the standby mode.

No.8927-24/27

LV4141W

Sampl Application Circuit (at input of internal synchronous separate signal)

To LCD

Panel

+7V

+

10kΩ

47μF

0.47μF

+3V

48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33

+

47μF

V

2

49

32

31

V

1

SS

CC

To LCD

Panel

+

1μF

VD

50 DSDOUT

51 NC

ENB 30

+

VREG

RIN

XENB

CKV1

52

53

54

29

28

1μF

+

R

G

B

To LCD

Panel

1μF

+

GIN

CKV2 27

STV

1μF

+

55 BIN

26

XSTV 25

1μF

56 RESET

57 SYNC IN

58 VSEP TC

LV4141W

22000pF

24

23

22

21

20

19

18

17

DSG

XDSG

TEST7

TEST6

CKH1

CKH2

STH

0.01μF

0.33μF

59

60

61

VDIN

HDIN

TEST1

62 TEST2

To LCD

Panel

63

64

CLPIN

GND1

XSTH

+3V

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16

To Serial

Controller

+

+3V

47μF

+

10kΩ

0.01μF

47μF

6800pF

+

1μF

No.8927-25/27

LV4141W

Sampl Application Circuit (at input of external synchronous separate signal)

To LCD

Panel

+7V

+

10kΩ

47μF

0.47μF

+3V

48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33

+

47μF

V

2

49

32

V

1

SS

CC

To LCD

Panel

+

50 DSDOUT

VD 31

1μF

NC

ENB

51

52

53

54

55

56

30

29

28

27

26

25

+

VREG

RIN

XENB

CKV1

CKV2

STV

1μF

+

R

G

B

1μF

+

GIN

To LCD

Panel

1μF

+

BIN

1μF

RESET

XSTV

22000pF

LV4141W

57 SYNC IN

DSG 24

VSEP TC

VDIN

XDSG

TEST7

TEST6

CKH1

CKH2

STH

58

59

60

61

62

63

23

22

21

20

19

18

0.33μF

*1

(VD)

*2

HDIN

CSYNC,(HD)

TEST1

TEST2

CLPIN

To LCD

Panel

64 GND1

XSTH 17

+3V

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16

To Serial

Controller

+

1kΩ

+3V

47μF

+

6800pF

+

0.01μF

47μF

1μF

*1 Delete (open) at input of external VD.

*2 Connect pin 59 to GND at input of composite sink

No.8927-26/27

LV4141W

SANYO Semiconductor Co.,Ltd. assumes no responsibility for equipment failures that result from using

products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition

ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor Co.,Ltd.

products described or contained herein.

SANYO Semiconductor Co.,Ltd. strives to supply high-quality high-reliability products, however, any and all

semiconductor products fail or malfunction with some probability. It is possible that these probabilistic failures or

malfunction could give rise to accidents or events that could endanger human lives, trouble that could give rise

to smoke or fire, or accidents that could cause damage to other property. When designing equipment, adopt

safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not

limited to protective circuits and error prevention circuits for safe design, redundant design, and structural

design.

In the event that any or all SANYO Semiconductor Co.,Ltd. products described or contained herein are

controlled under any of applicable local export control laws and regulations, such products may require the

export license from the authorities concerned in accordance with the above law.

No part of this publication may be reproduced or transmitted in any form or by any means, electronic or

mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise,

without the prior written consent of SANYO Semiconductor Co.,Ltd.

Any and all information described or contained herein are subject to change without notice due to

product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the

SANYO Semiconductor Co.,Ltd. product that you intend to use.

Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed

for volume production.

Upon using the technical information or products described herein, neither warranty nor license shall be granted

with regard to intellectual property rights or any other rights of SANYO Semiconductor Co.,Ltd. or any third

party. SANYO Semiconductor Co.,Ltd. shall not be liable for any claim or suits with regard to a third party's

intellctual property rights which has resulted from the use of the technical information and products mentioned

above.

This catalog provides information as of April, 2007. Specifications and information herein are subject

to change without notice.

PS No.8927-27/27


型号：	LV4141W
厂家：	SANYO SEMICON DEVICE
描述：	Bi-CMOS LSI For LCD Panel Drive Single Chip IC BI -CMOS LSI对于液晶面板驱动单芯片IC 驱动 CD
文件：	总27页 (文件大小：470K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LV4141W [SANYO]

相关型号：

LV4147W

LV4149W

LV4150W

LV420M150BP443025

LV420M150BPF-3025

LV420M220BP342545

LV420M330BP3-3535

LV420M330BP343045

LV420M82BP342525

LV426128

LV426157

LV426251