LV5230LG_10 [SANYO]
7ch x 17ch LED Driver; 7CH X 17ch LED驱动器
| 型号： | LV5230LG_10 |
| 厂家： | 
SANYO SEMICON DEVICE |
| 描述： | 7ch x 17ch LED Driver |
| 文件： | 总27页 (文件大小：176K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Ordering number : ENA1359A
Bi-CMOS IC
LV5230LG
7ch×17ch LED Driver
Overview
The LV5230LG is a dot-matrix LED driver IC for cell phones.
Features
• 7×17 dot-matrix LED driver
(5×15 dot-matrix supported)
• Each dot can be set for display over the serial bus.
Functions
• LED driver
Column (anode) driving P-channel driver × 17 channels
Row (cathode ) driving N-channel driver × 7 channels
LED current per dot : 25mA maximum
Two flames of 7×17 (5×15) patterns can be set.
7 grayscale level adjustment on a dot basis (PWM duty factor switching)
Reverse display
Horizontal scroll (1 frame/2 frames)
Continuous/single scroll selectable
Vertical scroll (1 frame/2 frames)
Continuous/single scroll selectable
Automatic flashing can be specified per each dot
Interupt output at the end of scroll
Ring tone synchronization function
• LED driving open drain output × 2
Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to
"standard application", intended for the use as general electronics equipment (home appliances, AV equipment,
communication device, office equipment, industrial equipment etc.). The products mentioned herein shall not be
intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace
instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety
equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case
of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee
thereof. If you should intend to use our products for applications outside the standard applications of our
customer who is considering such use and/or outside the scope of our intended standard applications, please
consult with us prior to the intended use. If there is no consultation or inquiry before the intended use, our
customer shall be solely responsible for the use.
Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate
the performance, characteristics, and functions of the described products in the independent state, and are not
guarantees of the performance, characteristics, and functions of the described products as mounted in the
customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent
device, the customer should always evaluate and test devices mounted in the customer
's products or
equipment.
O0610 SY/10709 MS PC 20081114-S00001 No.A1359-1/27
LV5230LG
Specifications
Maximum Ratings at Ta = 25°C
Parameter
Symbol
Conditions
Ratings
Unit
V
Maximum supply voltage
V
V
max1
SV , V
CC DD
5.5
6
CC
max2
LEDV
V
CC
DD
Mounted on a board *
Allowable power dissipation
Operating temperature
Storage temperature
Pd max
Topr
1.2
W
-30 to +85
-40 to +125
°C
°C
Tstg
∗ Designated board : 40mm×50mm×0.8mm, glass epoxy 4-layter board (2S2P)
Operating Conditions at Ta = 25°C
Parameter
Symbol
Conditions
Ratings
Unit
V
Supply voltage 1
V
V
SV
V
3 to 4.5
1.65 to 3
2.7 to 5.5
BAT
DD
CC
Supply voltage 2
Supply voltage 3
V
DD
VLEDV
LEDV
V
DD
DD
* Power application sequence : 1. V
BAT
2. V
V
> V , No restriction on VLEDV
.
DD
DD BAT
DD
* Same level of voltage LEDV
CC
must be applied to the 4 pins as VLEDV voltage.
DD
Electrical Characteristics, Analog Block Ta = 25°C, V
= 3.7V, V
DD
= 2.6V, LEDV
= 3.7V,
BAT
DD
unless otherwise specified
Ratings
typ
Parameter
Symbol
Conditions
Unit
min
max
Consumption current (SV +V +LEDV
CC DD
)
DD
Consumption current 1
Consumption current 2
Consumption current 3A
I
I
I
1
RESET : L
0
0.3
1.9
5
5
3
μA
μA
CC
CC
CC
2
RESET : H, serial default
3A
When STBY mode is released, RT external
resistance value is 27kΩ
mA
Consumption current 3B
I
3B
When STBY mode is released, RT external
resistance value is 160kΩ
1
2
mA
CC
LEDSW
On resistance 1
On resistance 2
LED current 1
Ron1
Ron2
ILED1
ROW1 to 7 : IL = 425mA
1
2
2
4
Ω
Ω
LEDO1, LED02 : IL = 20mA
COL1 to COL17 : V = LEDV -0.5V
20
22.5
25
mA
O
DD
RT external resistance value : 27kΩ
LED current 2
ILED2
COL1 to COL17 : V = LEDV -0.5V
2.8
3.8
4.8
mA
O
DD
RT external resistance value : 160kΩ
Leakage current 1
Leakage current 2
Leakage current 3
OSC
IL1
IL2
IL3
ROW1 to ROW : V = 5V
1
1
1
μA
μA
μA
O
COL1 to COL17 : V = 0V, LEDV
= 5V
DD
O
LEDO1, LED02 : V = 5V
O
Oscillator frequency
F1
F1
When RT external resistance is 27kΩ,
CT external capacitance is 120pF
When RT external resistance is 160kΩ,
CT external capacitance is 10pF
900
900
1000
1000
1100
1100
kHz
kHz
Oscillator frequency
RT
Maximum. LED drive
current setting
LI1
RT external resistance : 27kΩ
20
22.5
25
mA
LED maximum drive current = 607.5/RT resistance
Continued on next page.
No.A1359-2/27
LV5230LG
Continued from preceding page.
Ratings
typ
Parameter
Symbol
Conditions
Unit
min
max
Control Circuit Block
H level 1
V
V
V
V
1
2
Input H level, SDA, SCL
V
×0.8
V
V
INH
DD
L level 1
1
Input L level, SDA, SCL
0
1.5
0
V
×0.2
INL
DD
H level 2
Input H level, RESET, SCTL
Input L level, RESET, SCTL
V
INH
L level 2
2
0.3
1
V
INL
H input current 3
I
I
I
I
3
Inflow-outflow current, when VBAT voltage is
applied to RESET pin.
-1
0
0
μA
HIN
L input current 3
H input current 4
L input current 4
3
Inflow-outflow current, when 0V is applied to
RESET pin.
-1
15
-1
1
75
1
μA
μA
μA
LIN
4
Inflow-outflow current, when VBAT voltage is
applied to SCTL pin.
47
0
HIN
4
Inflow-outflow current, when 0V is applied to SCTL
pin.
LIN
H output level 1
L output level 1
VH1
VL1
INTO pin, H level, I = 1mA
O
V
-0.3
0
V
V
V
DD
DD
0.3
INTO pin, L level, I = 1mA
O
Package Dimensions
unit : mm (typ)
3359
Pd max – Ta
1.4
Specified board : 50 × 40 × 0.8mm3
4-layer glass epoxy (2S2P) board
5.0
0.45
1.2
0.55
1.0
0.8
0.6
0.4
0.48
G
F
E
D
C
B
A
0.65
0.35
0.2
0
–
–
30 20
0
20
40
60
80
100
Ambient temperature, Ta – °C
SANYO : FLGA49J(5.0X5.0)
Pin Assignment
Top view
G
F
E
D
C
B
A
LEDGND
1
1
NC
COL16
CT
SGND
ROW2 TEST
1
2
3
4
5
6
7
2
3
4
5
6
7
LEDV
COL17 SV
SDA ROW1 ROW3
RT
DD
CC
LEDGND
COL15 COL14 COL13 SCL
V
ROW4
DD
2
LEDGND
3
LEDV
COL12 COL11 RESET INTO ROW5
DD
LEDGND
4
COL10 COL9 COL4 COL2
GPI
ROW6
LEDV
COL8 COL5 COL3 LEDO2 LEDO1 ROW7
DD
LEDGND
NC
G
COL7 COL6 LEDV
COL1
C
NC
A
DD
5
F
E
D
B
No.A1359-3/27
LV5230LG
Block Diagram
V
BAT
I/F level shift
OSC
IREF
I2C bus
control
PWM
COUNTER
shift register
LEDV
DD
No.A1359-4/27
LV5230LG
Dot Matrix LED 7 × 17
ROW1
ROW2
ROW3
ROW4
ROW5
ROW6
ROW7
2ms
ROW1
ROW2
ROW3
ROW4
ROW5
ROW6
ROW7
Dynamic Display
Dot Matrix LED 5 × 15
ROW1
ROW2
ROW3
ROW4
ROW5
2ms
ROW1
ROW2
ROW3
ROW4
ROW5
Dynamic Display
No.A1359-5/27
LV5230LG
Pin Functions
Pin No.
Pin name
Pin Description
Equivalent Circuit
A1
TEST
Test signal input pin.
SV
CC
Be sure to connect the pin to GND.
A1 pin
A2
RT
Reference current setting resistor connection pin.
SV
CC
By connecting the external resistor between this pin and GND, the
reference current is generated. The pin voltage is about 0.61V. Change
of this current value enables change of the oscillation frequency and
LED driver current value (COL1 to COL17 only).
A2 pin
A3
A6
B1
B2
B4
B5
C2
ROW4
ROW7
ROW2
ROW3
ROW5
ROW6
ROW1
N-channel driver output pins 1 to 7 for row (cathode) drive.
Must be connected to GND when not to be used.
A3, A6, B1, B2,
B4, B5, C2 pin
A4
A5
LEDGND3
LEDGND4
NC
ROW SW GND.
ROW SW GND.
No connection.
A7
G1
G7
B3
LEDGND2
ROW SW GND.
B6
C6
LEDO1
LEDO2
Open drain output pins for LED drive.
B6, C6 pin
Must be connected to GND when not to be used.
B7
C1
C3
C4
LEDGND5
LEDGND1
GND pin dedicated for LEDO1 and LEDO2.
ROW SW GND.
V
Power supply for serial I/F.
Interrupt signal output pin.
DD
INTO
V
SV
CC
DD
C4 pin
Continued on next page.
No.A1359-6/27
LV5230LG
Continued from preceding page.
Pin No.
C5
Pin name
GPI
Pin Description
Equivalent Circuit
BAT
Ringing tone synchronization signal input pin.
Must be connected to GND when not to be used.
SV
C5 pin
C7
D5
D6
E3
E4
E5
E6
E7
F1
F2
F3
F4
F5
F6
F7
G3
G5
D7
G2
G4
G6
D1
COL1
COL2
COL3
COL13
COL11
COL4
COL5
COL6
COL16
COL17
COL14
COL12
COL9
COL8
COL7
COL15
COL10
LEDV
P-channel driver output pins 1 to 17 for column (anode) drive.
Must be connected to GND when not to be used.
LEDV
DD
C7, D5, D6,
E3, E4, E5,
E6, E7, F1,
F2, F3, F4,
F5, F6, F7,
G3, G5 pin
Dot matrix LED drive voltage supply pins.
DD
SGND
SDA
Analog circuit GND pin.
D2
Serial data signal input pin.
V
DD
D2 pin
D3
SCL
Serial clock signal input pin.
V
DD
D3 pin
Continued on next page.
No.A1359-7/27
LV5230LG
Continued from preceding page.
Pin No.
D4
Pin name
RESET
Pin Description
Equivalent Circuit
Reset signal input pin.
Reset state when low.
SV
CC
D4 pin
E1
CT
Oscillator frequency setting capacitor connection pin.
The oscillation frequency can be adjusted by changing the value of
capacitor at CT pin.
SV
CC
E1 pin
E2
SV
CC
Analog circuit power supply.
No.A1359-8/27
LV5230LG
Serial Bus Communication Specifications
I2C serial transfer timing conditions
twH
SCL
th1
twL
th2
tbuf
SDA
th1
ts2
ts1
ts3
Start condition
Resend start condition
Stop condition
ton
tof
Input waveform condition
Standard mode
Parameter
SCL clock frequency
Data set up time
symbol
Conditions
min
typ
max
unit
kHz
μs
ns
fscl
ts1
ts2
ts3
th1
th2
twL
twH
ton
tof
SCL clock frequency
0
100
SCL setup time relative to the fall of SDA
SDA setup time relative to the rise of SCL
SCL setup time relative to the rise of SDA
SCL data hold time relative to the fall of SDA
SDA hold time relative to the fall of SCL
SCL pulse width for the L period
4.7
250
4.0
4.0
0
μs
μs
μs
μs
μs
ns
Data hold time
Pulse width
4.7
4.0
SCL pulse width for the H period
Input waveform conditions
Bus free time
SCL and SDA (input) rise time
1000
300
SCL and SDA (input) fall time
ns
tbuf
Time between STOP and START conditions
4.7
μs
High-speed mode
Parameter
SCL clock frequency
Data setup time
Symbol
fscl
ts1
Conditions
SCL clock frequency
min
typ
max
unit
kHz
μs
ns
0
0.6
100
0.6
0.6
0
400
SCL setup time relative to the fall of SDA
SDA setup time relative to the rise of SCL
SCL setup time relative to the rise of SDA
SCL data hold time relative to the fall of SDA
SDA hold time relative to the fall of SCL
SCL pulse width for the L period
ts2
ts3
μs
μs
μs
μs
μs
ns
Data hold time
th1
th2
Pulse width
twL
twH
ton
1.3
0.6
SCL pulse width for the H period
Input waveform conditions
Bus free time
SCL and SDA (input) rise time
300
300
tof
SCL and SDA (input) fall time
ns
tbuf
Time between STOP and START conditions
1.3
μs
No.A1359-9/27
LV5230LG
I2C bus transmission method
Start and stop conditions
In the I2C bus, SDA must basically be kept in the constant state while SCL is “H” as shown below during data
transfer.
SCL
SDA
ts2
th2
When data transfer is not made, both SCL and SDA are in the “H” state.
When SCL = SDA = “H”, change of SDA from “H” to “L” enables the start conditions to start access.
When SCL is “H”, change of SDA from “L” to “H” enables the stop conditions to stop access.
Start condition
Stop condition
SCL
SDA
th1
ts3
No.A1359-10/27
LV5230LG
Data transfer and acknowledgement response
After establishment of start conditions, data transfer is made by one byte (8 bits).
Data transfer enables continuous transfer of any number of bytes.
Each time the 8-bit data is transferred, the ACK signal is sent from the receive side to the send side.
The ACK signal is issued when SDA on the send side is released and SDA on the receive side is set “L” immediately
after fall of the clock pulse at the SCL eighth bit of data transfer to “L”.
When the next 1-byte transfer is left in the receive state after transmission of the ACK signal from the receive side,
the receive side releases SDA at fall of the SCL ninth clock.
In the I2C bus, there is no CE signal. Instead, 7-bit slave address is assigned to each device and the first byte of
transfer is assigned to the command (R/W) representing the 7-bit slave address and subsequent transfer direction.
The 7-bit address is transferred sequentially from MSB and if the eighth bit is “L”, the second byte is WRITE mode
and if “H”, the second byte is READ mode.
In the READ mode, the ACK signal issued immediately before sending the stop condition must be 1.
In LV5230, the slave address is specified as (1110111).
Write mode
M
S
B
L
S
B
A
C
K
M
S
B
L
S
B
A
C
K
M
S
B
L
S
B
A
C
K
Start
Slave address
W
Register address
Data
Stop
SCL
SDA
1
1
1
0
1
1
1
0
0
0
0
0
0
1
0
0
0
0
1
0
0
0 1
Read mode
Start
M
S
B
L
S
B
A
C
K
M
S
B
L
S
B
A
C
K
M
S
B
L
S
B
A
C
K
Slave address
W
Data
Data
Stop
SCL
SDA
1
1
1
0
1
1
1
1
0
1
STATUS
STATUS
No.A1359-11/27
LV5230LG
Serial modes setting
address : 00h CTRL1
00h CTRL1
D7
STBY
W
D6
-
D5
D4
D3
-
D2
DFCLR
W
D1
D0
Register name
R/W
MXMODE
MSWEN
FADECLR
SCRLCLR
W
0
W
0
W
0
W
0
Default
0
0
D0 : SCRLCLR Scroll interrupt signal clear
0 : Scroll interrupt signal stays active.
1 : Scroll interrupt signal cleared. * Automatically updated to 0 after being set to 1.
D1 : FADECLR Fade interrupt signal clear
0 : Fade interrupt signal stays active.
1 : Fade interrupt signal cleared. * Automatically updated to 0 after being set to 1.
D2 : DFCLR Pallete fade interrupt signal clear
0 : Pallete fade interrupt signal stays active.
1 : Pallete fade interrupt signal cleared. * Automatically updated to 0 after being set to 1.
D4 : MSWEN Ringing tone synchronization enable
0 : Ringing tone synchronization enabled. * GPI = L : All LEDs turned off, GPI = H : Normal operation
1 : Ringing tone synchronization disabled.
D5 : MXMODE LED matrix mode switchingr
0 : 7 × 17 LED matrix
1 : 5 × 15 LED matrix
D7: STBY Standby mode
0 : Standby
1 : Operation
No.A1359-12/27
LV5230LG
address : 01h CTRL2
01h CTRL2
Register name
R/W
D7
D6
-
D5
LED2
W
D4
LED1
W
D3
-
D2
D1
D0
PAGE
W
LEDOFF
ROTHEN
ROTVEN
W
0
W
0
W
0
Default
0
0
0
D0 : PAGE Display page
0 : Frame 1 displayed
1 : Frame 2 displayed
D1 : ROTVEN Vertical rotation
0 : Normal display
1 : Vertically rotated display
D2 : ROTHEN Horizontal rotation
0 : Normal display
1 : Horizontally rotated display
D4 : LED1 LED1 enable
0 : LED1 turned off
1 : LED1 turned on
D5 : LED2 LED2 enable
0 : LED2 turned off
1 : LED2 turned on
D7 : LEDOFF Screen display ON/OFF
0 : Normal operation
1 : All matrix LEDs turned off
No.A1359-13/27
LV5230LG
address : 02h DOTMODE
02h DOTMODE
Register name
R/W
D7
DOTEN
W
D6
D5
-
D4
-
D3
D2
D1
D0
DOTMODE
DOTSP [3]
DOTSP [2]
DOTSP [1]
DOTSP [0]
W
0
W
0
W
0
W
0
W
0
Default
0
D3-D0 : DOTSP Flashing/brightness inversion speed
D3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
D2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
D1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
D0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
ON : 0.05s
ON : 0.10s
ON : 0.15s
ON : 0.20s
ON : 0.25s
ON : 0.30s
ON : 0.35s
ON : 0.40s
ON : 0.45s
ON : 0.50s
ON : 0.55s
ON : 0.60s
ON : 0.65s
ON : 0.70s
ON : 0.75s
ON : 0.80s
OFF : 0.05s
OFF : 0.10s
OFF : 0.15s
OFF : 0.20s
OFF : 0.25s
OFF : 0.30s
OFF : 0.35s
OFF : 0.40s
OFF : 0.45s
OFF : 0.50s
OFF : 0.55s
OFF : 0.60s
OFF : 0.65s
OFF : 0.70s
OFF : 0.75s
OFF : 0.80s
D6 : DOTMODE Flashing/brightness inversion display switching
0 : Flashing
1 : Brightness inversion
D7 : DOTEN Flashing/brightness inversion display enable
0 : Disable
1 : Enable
No.A1359-14/27
LV5230LG
address : 03h AUTOPAGE
03h AUTOPAGE
Register name
R/W
D7
PGEN
W
D6
-
D5
-
D4
-
D3
D2
D1
D0
PGSP [3]
PGSP [2]
PGSP [1]
PGSP [0]
W
0
W
0
W
0
W
0
Default
0
D3 top D0 : PGSP Page switching speed
D3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
D2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
D1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
D0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Page1 : 0.05s
Page1 : 0.10s
Page1 : 0.15s
Page1 : 0.20s
Page1 : 0.25s
Page1 : 0.30s
Page1 : 0.35s
Page1 : 0.40s
Page1 : 0.45s
Page1 : 0.50s
Page1 : 0.55s
Page1 : 0.60s
Page1 : 0.65s
Page1 : 0.70s
Page1 : 0.75s
Page1 : 0.80s
Page2 : 0.05s
Page2 : 0.10s
Page2 : 0.15s
Page2 : 0.20s
Page2 : 0.25s
Page2 : 0.30s
Page2 : 0.35s
Page2 : 0.40s
Page2 : 0.45s
Page2 : 0.50s
Page2 : 0.55s
Page2 : 0.60s
Page2 : 0.65s
Page2 : 0.70s
Page2 : 0.75s
Page2 : 0.80s
D7 : PGEN Automatic page switching enable
0 : Disable
1 : Enable
No.A1359-15/27
LV5230LG
address : 04h SCCON1
04h SCCON1
Register name
R/W
D7
SCEN
W
D6
D5
D4
D3
D2
D1
D0
SCDIR [1]
SCDIR [0]
SCMODE
SCSP [3]
SCSP [2]
SCSP [1]
SCSP [0]
W
0
W
0
W
0
W
0
W
0
W
0
W
0
Default
0
D3 to D0 : SCSP Scroll speed per dot
D3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
D2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
D1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
D0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
50ms
100ms
150ms
200ms
250ms
300ms
350ms
400ms
450ms
500ms
550ms
600ms
650ms
700ms
750ms
800ms
D4 : SCMODE Page mode when scrolling
0 : Scrolls and displays the current page repeatedly.
1 : Scrolls and displays the current and other pages alternately.
D6 to D5 : SCDIR Scroll direction
D6
D5
0
0
Right
Left
0
1
1
0
Up
1
1
Down
D7 : SCEN Scroll enable
0 : Disable
1 : Enable
No.A1359-16/27
LV5230LG
address : 05h SCCON2
05h SCCON2
Register name
R/W
D7
SCGO
W
D6
-
D5
D4
D3
D2
D1
D0
SCCNT [5]
SCCNT [4]
SCCNT [3]
SCCNT [2]
SCCNT [1]
SCCNT [0]
W
0
W
0
W
0
W
0
W
0
W
0
Default
0
D0 to D5 : SCCNT Scroll increment
17 × 7 mode
When SCCON1.SCDIR = 0 or 1 : 1 to 34
When SCCON1.SCDIR = 2 or 3 : 1 to 14
15 × 5 mode
When SCCON1.SCDIR = 0 or 1 : 1 to 30
When SCCON1.SCDIR = 2 or 3 : 1 to 10
* Scrolls one page when SCCNT = 0.
D7 : SCGO Scroll start
0 : Standby
1 : Scroll start
* The scrolled state is maintained until SCCON1 and SCEN are set low.
No.A1359-17/27
LV5230LG
address : 06h FADECON
06h FADECON
Register name
R/W
D7
D6
D5
D4
D3
D2
D1
D0
FADEEN
FADEGO
FADEIO
FADEMOD
FDSP [3]
FDSP [2]
FDSP [1]
FDSP [0]
W
0
W
0
W
0
W
0
W
0
W
0
W
0
W
0
Default
D3 to D0 : FDSP Fade speed per 1 grayscale level (It takes (following set value × 64) seconds to complete fading)
D3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
D2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
D1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
D0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
2ms
4ms
6ms
8ms
10ms
12ms
14ms
16ms
18ms
20ms
22ms
24ms
26ms
28ms
30ms
32ms
D4 : FADEMOD Single/continuous switching
0 : Single fade-in/fade-out operation
1 : Fade-in/fade-out operation repeated
D5 : FADEIO Fade-in/fade-out switching
0 : Fade in
1 : Fade out
D6 : FADEGO Fade-in/fade-out start
0 : Standby
1 : Fade-in/fade-out operation start
D7 : FADEEN Fade-in/fade-out enable
0 : Disable
1 : Enable
* The interrupt flag is set high after a fade operation has completed. Manual clearing is required.
* All LEDs are turned off if FADEEN is set to 1 when FADEO is set to 0.
If GO is set to 1 in that state, fade-in operation starts and LEDs are turned on.
No.A1359-18/27
LV5230LG
address : 07h ROWSW
07h ROWSW
Register name
R/W
D7
D6
D5
D4
D3
D2
D1
D0
ROWSWEN
ROWSW7
ROWSW6
ROWSW5
ROWSW4
ROWSW3
ROWSW2
ROWSW1
W
0
W
0
W
0
W
0
W
0
W
0
W
0
W
0
Default
D0 : ROWSW1 Row 1 display ON/OFF
0 : ON
1 : OFF
D1 : ROWSW2 Row 2 display ON/OFF
0 : ON
1 : OFF
D2 : ROWSW3 Row 3 display ON/OFF
0 : ON
1 : OFF
D3 : ROWSW4 Row 4 display ON/OFF
0 : ON
1 : OFF
D4 : ROWSW5 Row 5 display ON/OFF
0 : ON
1 : OFF
D5 : ROWSW6 Row 6 display ON/OFF
0 : ON
1 : OFF
D6 : ROWSW7 Row 7 display ON/OFF
0 : ON
1 : OFF
D7 : ROWSWEN Each row ON/OFF enable
0 : Disable
1 : Enable
No.A1359-19/27
LV5230LG
address : 08h COLSW1
08h COLSW1
Register name
R/W
D7
D6
-
D5
-
D4
-
D3
-
D2
-
D1
-
D0
COLSWEN
COLSW17
W
0
W
0
Default
D0 : COLSW17 Row 17 display ON/OFF
0 : ON
1 : OFF
D7 : COLSWEN Column ON/OFF enable
0 : Disable
1 : Enable
address : 09h COLSW2
09h COLSW2
Register name
R/W
D7
D6
D5
D4
D3
D2
D1
D0
COLSW16
COLSW15
COLSW14
COLSW13
COLSW12
COLSW11
COLSW10
COLSW9
W
0
W
0
W
0
W
0
W
0
W
0
W
0
W
0
Default
D0 : COLSW9 Column 9 display ON/OFF
0 : ON
1 : OFF
D1 : COLSW10 Column 10 display ON/OFF
0 : ON
1 : OFF
D2 : COLSW11 Column 11 display ON/OFF
0 : ON
1 : OFF
D3 : COLSW12 Column 12 display ON/OFF
0 : ON
1 : OFF
D4 : COLSW13 Column 13 display ON/OFF
0 : ON
1 : OFF
D5 : COLSW14 Column 14 display ON/OFF
0 : ON
1 : OFF
D6 : COLSW15 Column 15 display ON/OFF
0 : ON
1 : OFF
D7 : COLSW16 Column 16 display ON/OFF
0 : ON
1 : OFF
No.A1359-20/27
LV5230LG
address : 0Ah COLSW3
0Ah COLSW3
Register name
R/W
D7
D6
D5
D4
D3
D2
D1
D0
COLSW8
COLSW7
COLSW6
COLSW5
COLSW4
COLSW3
COLSW2
COLSW1
W
0
W
0
W
0
W
0
W
0
W
0
W
0
W
0
Default
D0 : COLSW1 Column 1 display ON/OFF
0 : ON
1 : OFF
D1 : COLSW2 Column 2 display ON/OFF
0 : ON
1 : OFF
D2 : COLSW3 Column 3 display ON/OFF
0 : ON
1 : OFF
D3 : COLSW4 Column 4 display ON/OFF
0 : ON
1 : OFF
D4 : COLSW5 Column 5 display ON/OFF
0 : ON
1 : OFF
D5 : COLSW6 Column 6 display ON/OFF
0 : ON
1 : OFF
D6 : COLSW7 Column 7 display ON/OFF
0 : ON
1 : OFF
D7 : COLSW8 Column 8 display ON/OFF
0 : ON
1 : OFF
No.A1359-21/27
LV5230LG
address : 0Bh DFCON1
0Bh DFCON1
Register name
R/W
D7
DFEN
W
D6
DFGO
W
D5
-
D4
-
D3
DFDIR
W
D2
D1
D0
DFNUM [2]
DFNUM [1]
DFNUM [0]
W
0
W
0
W
0
Default
0
0
0
D2 to D0 : DFNUM Number of palette to be faded to
0 : Invalid
1 to 7 : Correspond to PWMDUTY1 to PWMDUTY7.
D3 : DFDIR Fading direction
0 : Fade in
1 : Fade out
D6 : DFGO Fade start
0 : Standby
1 : Start
D7 : DFEN Fade enable
0 : Disable
1 : Enable
* The interrupt flag is set high after a fade operation has completed. Manual clearing is required.
address : 0Ch DFCON2
0Ch DFCON2
Register name
R/W
D7
D6
D5
D4
D3
D2
D1
D0
-
-
-
-
DFSP [3]
DFSP [2]
DFSP [1]
DFSP [0]
W
0
W
0
W
0
W
0
Default
D3 to D0 : DFSP Fading speed per grayscale
D3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
D2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
D1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
D0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
2ms
4ms
6ms
8ms
10ms
12ms
14ms
16ms
18ms
20ms
22ms
24ms
26ms
28ms
30ms
32ms
No.A1359-22/27
LV5230LG
address : 0Dh MAXDUTY
0Dh MAXDUTY
Register name
R/W
D7
-
D6
-
D5
D4
D3
D2
D1
D0
MXDTY [5]
MXDTY [4]
MXDTY [3]
MXDTY [2]
MXDTY [1]
MXDTY [0]
W
0
W
0
W
0
W
0
W
0
W
0
Default
D5 to D0 : MXDTY Maximum DUTY value
n : 0 to 63 Maximum DUTY value (n/64) × 100[%]
* 100[%] when n = 63.
address : 10h PWMDUTY1
10h PWMDUTY1
Register name
R/W
D7
-
D6
-
D5
D4
D3
D2
D1
D0
DUTY1 [5]
DUTY1 [4]
DUTY1 [3]
DUTY1 [2]
DUTY1 [1]
DUTY1 [0]
W
0
W
0
W
0
W
0
W
0
W
0
Default
D5 to D0 : DUTY1 DUTY value for brightness 1 setting
n : 0 to 63 DUTY value ((n + 1)/64) × 100 [%]
* 0 [%] when n = 0.
address : 11h PWMDUTY2
11h PWMDUTY2
Register name
R/W
D7
-
D6
-
D5
D4
D3
D2
D1
D0
DUTY2 [5]
DUTY2 [4]
DUTY2 [3]
DUTY2 [2]
DUTY2 [1]
DUTY2 [0]
W
0
W
0
W
0
W
0
W
0
W
0
Default
D5 to D0 : DUTY2 DUTY value for brightness 2 setting
n : 0 to 63 DUTY value ((n + 1)/64) × 100 [%]
* 0 [%] when n = 0.
address : 12h PWMDUTY3
12h PWMDUTY3
Register name
R/W
D7
-
D6
-
D5
D4
D3
D2
D1
D0
DUTY3 [5]
DUTY3 [4]
DUTY3 [3]
DUTY3 [2]
DUTY3 [1]
DUTY3 [0]
W
0
W
0
W
0
W
0
W
0
W
0
Default
D5 to D0 : DUTY3 DUTY value for brightness 3 setting
n : 0 to 63 DUTY value ((n + 1)/64) × 100 [%]
* 0 [%] when n = 0.
address : 13h PWMDUTY4
13h PWMDUTY4
Register name
R/W
D7
-
D6
-
D5
D4
D3
D2
D1
D0
DUTY4 [5]
DUTY4 [4]
DUTY4 [3]
DUTY4 [2]
DUTY4 [1]
DUTY4 [0]
W
0
W
0
W
0
W
0
W
0
W
0
Default
D5 to D0 : DUTY4 DUTY value for brightness 4 setting
n : 0 to 63 DUTY value ((n + 1)/64) × 100 [%]
* 0 [%] when n = 0.
No.A1359-23/27
LV5230LG
address : 14h PWMDUTY5
14h PWMDUTY5
Register name
R/W
D7
-
D6
-
D5
D4
D3
D2
D1
D0
DUTY5 [5]
DUTY5 [4]
DUTY5 [3]
DUTY5 [2]
DUTY5 [1]
DUTY5 [0]
W
0
W
0
W
0
W
0
W
0
W
0
Default
D5 to D0 : DUTY5 DUTY factor value for brightness 5 setting
n : 0 to 63 DUTY value ((n + 1)/64) × 100 [%]
* 0 [%] when n = 0.
address : 15h PWMDUTY6
15h PWMDUTY6
Register name
R/W
D7
-
D6
-
D5
D4
D3
D2
D1
D0
DUTY6 [5]
DUTY6 [4]
DUTY6 [3]
DUTY6 [2]
DUTY6 [1]
DUTY6 [0]
W
0
W
0
W
0
W
0
W
0
W
0
Default
D5 to D0 : DUTY6 DUTY factor value for brightness 6 setting
n : 0 to 63 DUTY value ((n + 1)/64) × 100 [%]
* 0 [%] when n = 0.
address : 16h PWMDUTY7
16h PWMDUTY7
Register name
R/W
D7
-
D6
-
D5
D4
D3
D2
D1
D0
DUTY7 [5]
DUTY7 [4]
DUTY7 [3]
DUTY7 [2]
DUTY7 [1]
DUTY7 [0]
W
0
W
0
W
0
W
0
W
0
W
0
Default
D5 to D0 : DUTY7 DUTY factor value for brightness 7 setting
n : 0 to 63 DUTY value ((n + 1)/64) × 100 [%]
* 0 [%] when n = 0.
No.A1359-24/27
LV5230LG
address : 20h to 9Dh FRAMEDATA
20h to 9Dh FRAMEDATA
Register name
R/W
D7
BRn
W
D6
LMn [2]
W
D5
LMn [1]
W
D4
LMn [0]
W
D3
BRm
W
D2
LMm [2]
W
D1
LMm [1]
W
D0
LMm [0]
W
Default
0
0
0
0
0
0
0
0
D2 to D0 : LM11m Frame 1 : vertical 1st : horizontal (n + 1) th LED brightness
D2
D1
D0
0
0
0
Off
0
0
1
On at brightness set by PWMDUTY1 register
On at brightness set by PWMDUTY2 register
On at brightness set by PWMDUTY3 register
On at brightness set by PWMDUTY4 register
On at brightness set by PWMDUTY5 register
On at brightness set by PWMDUTY6 register
On at brightness set by PWMDUTY7 register
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
D3 : BR11m Frame 1 : vertical 1: horizontal (n + 1) th LED flashing/brightness inversion enable
0 : Flashing/brightness inversion disabled
1 : Flashing/brightness inversion enabled
D6 to D4 : LM11n Frame 1 : vertical 1 : horizontal (n) th LED brightness
D2
D1
D0
0
0
0
Off
0
0
1
On at brightness set by PWMDUTY1 register
On at brightness set by PWMDUTY2 register
On at brightness set by PWMDUTY3 register
On at brightness set by PWMDUTY4 register
On at brightness set by PWMDUTY5 register
On at brightness set by PWMDUTY6 register
On at brightness set by PWMDUTY7 register
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
D7 : BR11n Frame 1 : vertical 1 : horizontal (n) th LED flashing/brightness inversion enable
0 : Flashing/brightness inversion disabled
1 : Flashing/brightness inversion enabled
* These are used for each LED data. One register is loaded with two LEDs data.
See the table on the following page for the storage address of each dot.
No.A1359-25/27
LV5230LG
Frame Data Register Tables xxH : higher-order 4 bits of register xx xxL : lower-order 4 bits of register xx
17 × 7 mode
Frame 1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
1
2
3
4
5
6
7
20H
29H
32H
3BH
44H
4DH
56H
20L
29L
32L
3BL
44L
4DL
56L
21H
2AH
33H
3CH
45H
4EH
57H
21L
2AL
33L
3CL
45L
4EL
57L
22H
2BH
34H
3DH
46H
4FH
58H
22L
2BL
34L
3DL
46L
4FL
58L
23H
2CH
35H
3EH
47H
50H
59H
23L
2CL
35L
3EL
47L
50L
59L
24H
2DH
36H
3FH
48H
51H
5AH
24L
2DL
36L
3FL
48L
51L
5AL
25H
2EH
37H
40H
49H
52H
5BH
25L
2EL
37L
40L
49L
52L
5BL
26H
2FH
38H
41H
4AH
53H
5CH
26L
2FL
38L
41L
4AL
53L
5CL
27H
30H
39H
42H
4BH
54H
5DH
27L
30L
39L
42L
4BL
54L
5DL
28H
31H
3AH
43H
4CH
55H
5EH
Frame 2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
1
2
3
4
5
6
7
5FH
68H
71H
7AH
83H
8CH
95H
5FL
68L
71L
7AL
83L
8CL
95L
60H
69H
72H
7BH
84H
8DH
96H
60L
69L
72L
7BL
84L
8DL
96L
61H
6AH
73H
7CH
85H
8EH
97H
61L
6AL
73L
7CL
85L
8EL
97L
62H
6BH
74H
7DH
86H
8FH
98H
62L
6BL
74L
7DL
86L
8FL
98L
63H
6CH
75H
7EH
87H
90H
99H
63L
6CL
75L
7EL
87L
90L
99L
64H
6DH
76H
7FH
88H
91H
9AH
64L
6DL
76L
7FL
88L
91L
9AL
65H
6EH
77H
80H
89H
92H
9BH
65L
6EL
77L
80L
89L
92L
9BL
66H
6FH
78H
81H
8AH
93H
9CH
66L
6FL
78L
81L
8AL
93L
9CL
67H
70H
79H
82H
8BH
94H
9DH
15 × 5 mode
Frame 1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
1
2
3
4
5
20H
29H
32H
3BH
44H
20L
29L
32L
3BL
44L
21H
2AH
33H
3CH
45H
21L
2AL
33L
3CL
45L
22H
2BH
34H
3DH
46H
22L
2BL
34L
3DL
46L
23H
2CH
35H
3EH
47H
23L
2CL
35L
3EL
47L
24H
2DH
36H
3FH
48H
24L
2DL
36L
3FL
48L
25H
2EH
37H
40H
49H
25L
2EL
37L
40L
49L
26H
2FH
38H
41H
4AH
26L
2FL
38L
41L
4AL
27H
30H
39H
42H
4BH
Frame 2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
1
2
3
4
5
4DH
56H
5FH
68H
71H
4DL
56L
5FL
68L
71L
4EH
57H
60H
69H
72H
4EL
57L
60L
69L
72L
4FH
58H
61H
6AH
73H
4FL
58L
61L
6AL
73L
50H
59H
62H
6BH
74H
50L
59L
62L
6BL
74L
51H
5AH
63H
6CH
75H
51L
5AL
63L
6CL
75L
52H
5BH
64H
6DH
76H
52L
5BL
64L
6DL
76L
53H
5CH
65H
6EH
77H
53L
5CL
65L
6EL
77L
54H
5DH
66H
6FH
78H
No.A1359-26/27
LV5230LG
address : FFh STATUS
FFh STATUS
Register name
R/W
D7
-
D6
-
D5
-
D4
-
D3
-
D2
DFIF
R
D1
FEDIF
R
D0
SCRIF
R
Default
X
X
X
X
X
D0 : SCRIF End of scroll interrupt occurrence flag
0 : No end of scroll interrupt has occurred.
1 : An end of scroll interrupt has occurred.
* The flag needs to be cleared manually (CTRL1.SCRLCLR).
D1 : FEDIF End of fade interrupt occurrence flag
0 : No end of fade interrupt has occurred.
1 : An end of fade interrupt has occurred.
* The flag needs to be cleared manually (CTRL1.FADECLR).
D2 : DFIF End of palette fade interrupt occurrence flag
0 : No end of palette fade interrupt has occurred.
1 : An end of palette fade interrupt has occurred.
* The flag needs to be cleared manually (CTRL1.DFCLR).
The OR of SCRIF, FEDIF and DFIF appear at the interrupt pin.
* The addresses used here are all dummy and not used in actual communications.
SANYO Semiconductor Co.,Ltd. assumes no responsibility for equipment failures that result from using
products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition
ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor Co.,Ltd.
products described or contained herein.
SANYO Semiconductor Co.,Ltd. strives to supply high-quality high-reliability products, however, any and all
semiconductor products fail or malfunction with some probability. It is possible that these probabilistic failures or
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limited to protective circuits and error prevention circuits for safe design, redundant design, and structural
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without the prior written consent of SANYO Semiconductor Co.,Ltd.
Any and all information described or contained herein are subject to change without notice due to
product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the
SANYO Semiconductor Co.,Ltd. product that you intend to use.
Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed
for volume production.
Upon using the technical information or products described herein, neither warranty nor license shall be granted
with regard to intellectual property rights or any other rights of SANYO Semiconductor Co.,Ltd. or any third
party. SANYO Semiconductor Co.,Ltd. shall not be liable for any claim or suits with regard to a third party's
intellctual property rights which has resulted from the use of the technical information and products mentioned
above.
This catalog provides information as of October, 2010. Specifications and information herein are subject
to change without notice.
PS No.A1359-27/27
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