SDC4563JTR-G1 [SDC]
Current Mode PWM Controller;型号: | SDC4563JTR-G1 |
厂家: | Shaoxing Devechip Microelectronics Co., Ltd |
描述: | Current Mode PWM Controller |
文件: | 总13页 (文件大小:415K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Datasheet
General Description
Features
SDC4563 is a highly integrated current mode PWM control
IC optimized for high performance, low standby power
and cost effective offline flyback converter applications in
sub 30W range.
Frequency shuffling technology for improved EMI
performance
Audio noise free operation
Extended burst mode control for improved efficiency
and minimum standby power design
External programmable PWM switching
Internal synchronized slope compensation
Low VDD startup current and low operating current
(1.4mA)
The internal slope compensation improves system large
signal stability and reduces the possible subharmonic
oscillation at high PWM duty cycle output. Leading-edge
blanking on current sense(CS) input removes the signal
glitch due to snubber circuit diode reverse recovery and
thus greatly reduces the external component count and
system cost in the design.
Leading edging on current sense input
Good tion coverage with auto self-recovery
(UVLO/O/OCP/OLP)
SDC4563 offers complete protection coverage with
automatic self-recovery feature including cycle-by-cycle
current limiting (OCP), over load protection (OLP), VDD
over voltage clamp and under voltage lockout (UVLO). The
Gate-drive output is clamped to maximum 18V to protect
the power MOSFET.
Package: SOT-23-6
Aplications
Battery charger
Power adapter
Set-top box power supplies
SOT-23-6
Figure 1. Package Type
December, 2013 Rev. 1.1
1/13
©2013 Shaoxing Devechip Microelectronics Co., Ltd.
www.sdc-semi.com
Datasheet
Pin Configuration
Package: SOT-23-6
1
2
3
6
GND
GATE
VDD
FB
RI
5
4
SENSE
Figure 2. Pin Configuration
Pin Number
Pin Name
Function
1
GND
Ground
Feedback input pin. The PWM duty cycle is determined by voltage level into this
pin and SENSE pin input
2
3
FB
RI
Internal Oscillator frequency setting pin. A resistor connected between RI and
GND set the PWM frequency
4
5
6
SENSE
VDD
nt sense input pin. Connected to MOSFET current sensing resistor node
Chip DC power supply pin
GATE
Totem-pole gate drive output for the power MOSFET
Table 1. Pin Description
December, 2013 Rev. 1.1
©2013 Shaoxing Devechip Microelectronics Co., Ltd.
2/13
www.sdc-semi.com
Datasheet
Functional Block Diagram
RI
Current
Reference
Soft
GATE
Drive
SET
CLR
S
Q
Q
Shuffling
OSC
VDD
POR
UVLO
VDD
R
Burst
Mode controller
Clamping
VTH_OC
Leading
Edge
SENSE
FB
Blanking
Internal
Supply
Regulator
OVP
ope
ensation
OLP
GND
Figure 3. Functional Block Diagram
December, 2013 Rev. 1.1
3/13
©2013 Shaoxing Devechip Microelectronics Co., Ltd.
www.sdc-semi.com
Datasheet
Ordering Information
-
X
SDC4563 X
X
E1: Pb-free
G1: Halogen-free
Circuit Type
Package
SOT-23-6: J
TR: Tape Reel
Part Number
Halogen-free
SDC4563JTRG1
Marking ID
Temperature
Packing
Type
Package
Range
Pb-free
Pb-free
Halogen-free
SOT-23-6
-40°C~85°C
SDC4563JTR-E1
4563
4563G
Tape Reel
December, 2013 Rev. 1.1
©2013 Shaoxing Devechip Microelectronics Co., Ltd.
4/13
www.sdc-semi.com
Datasheet
Absolute Maximum Ratings (NOTE: Stresses greater than those listed under Absolute Maximum Ratings may cause
permanent damage to the device.)
Parameter
Symbol
VDD
Vaule
-0.3~30
34
Unit
V
DC supply voltage
VDD clamp voltage
VDD clamp current
VFB input voltage
SENSE input voltage
Input voltage to RI pin
VDD_CLAMP
ICLAMP
VFB
V
10
mA
V
-0.3~7
-0.3~7
-0.3~7
150
VSENSE
VRI
V
V
Operating junction temperature
Storage temperature
TJ
°C
°C
mA
V
-55~150
200
Latch-up test per JEDEC 78
-
ESD,HBM model per Mil-Std-883H,Method 3015
ESD,MM model per JEDEC EIA/JESD22-A115
BM
MM
2000
200
V
Table 2. Absolute Maximum Ratings
Recommended Operating Conditions
Parameter
Symbol
VDD
Min
10
Max
Unit
DC supply voltage
30
70
85
V
Normal oscillation frequency
Operating Temperature Range
fOSC
60
kHz
°C
TOP
-40
Table 3. Recommended Operating Conditions
December, 2013 Rev. 1.1
©2013 Shaoxing Devechip Microelectronics Co., Ltd.
5/13
www.sdc-semi.com
Datasheet
Electrical Characteristics (Ta=25°C, unless otherwise specified)
Parameter
Symbol
Conditions
Supply Voltage (VDD)
VDD=12.5V, RI=100k
Min
Typ Max
Unit
VDD start up current
Operation current
ISTART
IDD
-
-
3
20
-
uA
VDD=16V, RI=100k, VFB=3V
1.4
mA
VDD under voltage lockout
(enter)
VUVLO(ON)
-
7.8
8.8
9.8
V
VDD under voltage lockout (exit)
VDD clamp voltage
VUVLO(OFF)
VDD_CLAMP
-
13
-
14
34
15
-
V
V
ICLAMP =10mA
Feedback Input Section(FB Pin)
△VFB/△VCS
PWM input gain
AVCS
-
-
2.0
4.8
-
-
V/V
V
FB open loop voltage
VFB_OPEN
-
Short FB to GND and
Measure Current
FB pin short circuit current
Input impedance
IFB_SHORT
ZFB
-
-
-
0.8
6
-
-
mA
kΩ
V
-
Zero duty cycle FB threshold
voltage
VFB_0D
VDD=16V, RI=100k
-
0.75
Power limiting fb threshold
voltage
tFB_PL
-
-
-
-
-
3.7
35
75
-
-
-
V
ms
%
Power limiting debounce time
VDD=18V, RI=100k,
FB=3V, CS=0
Maximum duty cycle
DCMAX
Current Sense Input(Sense Pin)
Leading edge blanking time
Input impedance
TLEB
ZSENSE
RI=100k
-
-
-
300
40
-
-
ns
kΩ
Over current detection and
coelay
VDD=16V,
tD_OC
-
75
-
ns
V
CS> VTH_OC, FB=3.3V
Over current threshold voltage at
zero duty cycle
VTH_OC
FB=3.3V, RI=100k
0.70
0.75 0.80
Oscillator
Normal oscillation frequency
Frequency temperature stability
Frequency voltage stability
fOSC
RI =100K
60
-
65
5
70
-
kHz
%
VDD=16V, RI=100k,
△fTEMP
△fVDD
Ta=-20°C~100°C
VDD=12V~25V, RI=100k
-
5
-
%
December, 2013 Rev. 1.1
©2013 Shaoxing Devechip Microelectronics Co., Ltd.
6/13
www.sdc-semi.com
Datasheet
Parameter
Operating ri range
Symbol
RRI
Conditions
Min
Typ Max
Unit
kΩ
-
50
-
100
2
150
RI open load voltage
Burst mode base frequency
VRI_OPEN
fOSC_BM
-
-
-
V
VDD =16V, RI =100K
-
22
kHz
Gate Drive Output
Output low level
VOL
VOH
VDD=16V, IO=-20mA
VDD=16V, IO=20mA
-
-
10
-
-
-
0.8
V
V
Output high level
-
-
-
-
Output clamp voltage level
Output rising time
Output falling time
VO_CLAMP
tr
18
220
70
V
VDD=16V, CL=1nf
VDD=16V, CL=1n
-
ns
ns
tf
-
Frequency Shuffling
Shuffling frequency
fSHUFFLING
=100k
RI=100k
-
64
-
-
Hz
%
Modulation range/Base
frequency
△fOSC
-3
3
Table 4. Electrical Characteristics
December, 2013 Rev. 1.1
7/13
©2013 Shaoxing Devechip Microelectronics Co., Ltd.
www.sdc-semi.com
Datasheet
Function Description
The SDC4563 is a highly integrated PWM controller IC
optimized for offline flyback converter applications in sub
30W power range. The extended burst mode control
greatly reduces the standby power consumption and helps
the design easily meet the international power
conservation requirements.
condition, the FB input drops below burst mode threshold
level, device enters burst mode control. The gate drive
output switches only when VDD voltage drops below a
preset level and FB input is active to output an on state,
otherwise the gate drive remains at off state to minimize
the switching loss and reduces the standby power
consumption to the greatest extend. The frequency
control also eliminates the audio noise at any loading
conditions.
Startup Current and Start up Control
Startup current of SDC4563 is designed to be very low so
that VDD could be charged up above UVLO threshold level
and device starts up quickly. A large value startup resistor
can therefore be used to minimize the power loss yet
provides reliable startup in application.
Oscillator Open
A resistor cted between RI and GND sets the
constant current source to charge/discharge the internal
cap and thus the PWM oscillator frequency is determined.
Threlationship between RI and switching frequency
follows the below equation within the specified RI in kΩ
range at nominal loading operational condition.
Operating Current
The Operating current of SDC4563 is low at 1.4mA. Good
efficiency is achieved with SDC4563 low operating current
together with extended burst mode control features.
6500
fosc =
(kHz)
Frequency shuffling for EMI improvement
RI(kΩ)
The frequency shuffling/jittering (switfrequency
modulation) is implemented in SDC4563. The oscillation
frequency is modulated with a random source so that the
tone energy is spread out. The spread spectrum minimizes
the conduction band End therefore reduces system
design challenge.
Current Sensing and Leading Edge Blanking
Cycle-by-cycle current limiting is offered in SDC4563
current mode PWM control. The switch current is
detected by a sense resistor into the sense pin. An internal
leading edge blanking circuit chops off the sense voltage
spike at initial MOSFET on state due to snubber diode
reverse recovery so that the external RC filtering on sense
input is no longer required. The current limit comparator
is disabled and thus cannot turn off the external MOSFET
during the blanking period. PWM duty cycle is determined
by the current sense input voltage and the FB input
voltage.
Extended Burst Mode Operation
Under zeo load or light load condition, majority of the
powssipation in a switching mode power supply is
from tching loss on the MOSFET transistor, the core
loss of the transformer and the loss on the snubber circuit.
The magnitude of power loss is in proportion to the
number of switching events within a fixed period of time.
Reducing switching events leads to the reduction on the
power loss and thus conserves the energy.
Internal Synchronized Slope Compensation
Built-in slope compensation circuit adds voltage ramp
onto the current sense input voltage for PWM generation.
This greatly improves the close loop stability at CCM and
prevents the sub-harmonic oscillation and thus reduces
SDC4563 adjusts the switching mode according to the
loading condition. Under no load to light/medium load
December, 2013 Rev. 1.1
8/13
©2013 Shaoxing Devechip Microelectronics Co., Ltd.
www.sdc-semi.com
Datasheet
the output ripple voltage.
and good EMI system design is easier to achieve with
this dedicated control scheme. An internal 18V clamp is
added for MOSFET gate protection at higher than
expected VDD input.
Gate Drive
SDC4563 gate is connected to an external MOSFET gate
for power switch control. Too weak the gate drive
strength results in higher conduction and switch loss of
MOSFET while too strong gate drive output
compromises the EMI. A good tradeoff is achieved
through the built-in totem pole gate design with right
output strength and dead time control. The low idle loss
Protection Controls
Good power supply system reliability is achieved with its
rich protection features including cycle-by-cycle current
limiting (OCP), over load protection (OLP) and over
voltage clamp, under voltage ockout on VDD (UVLO).
Typical Application
V+
GND
GND GATE
VDD
FB
RI
SENSE
SDC4563
Figure 4. Typical Application
December, 2013 Rev. 1.1
©2013 Shaoxing Devechip Microelectronics Co., Ltd.
9/13
www.sdc-semi.com
Datasheet
Typical Performance Characteristics
20
15
10
5
5.0
4.6
4.2
3.8
3.4
3.0
0
0
8
2
6
10 12
14
16
4
-20
10
40
Temp(°C)
130
70
100
VDD (V)
Figure 5. VDD Startup Current vs. Voltage
Fige 6. ISTART vs. Temp
9.0
2.0
1.6
1.2
0.8
0.4
0
8.8
8.6
8.4
8.2
8.0
5
10
20
30
0
15
DD(V)
-20
10
40
70
100
130
V
Temp(°C)
Figure 7. VDD UVLO vs. Operation Current
14.5
Figure 8. VUVLO(ON) vs. Temp
140
115
14.4
14.3
14.2
14
14.0
90
65
40
-20
10
40
Temp(°C)
70
100
130
50
70
90
110
RI(kΩ)
130
150
Figure 9. VUVLO(OFF) vs. Temp
Figure 10. RI vs. fOSC
December, 2013 Rev. 1.1
©2013 Shaoxing Devechip Microelectronics Co., Ltd.
10/13
www.sdc-semi.com
Datasheet
Typical Performance Characteristics(Continued)
66.5
66
65.5
65
64.5
64
63.5
-20
5
30
55
Temp(°C)
80
105
130
Figure 11. fOSC vs. Temp
December, 2013 Rev. 1.1
11/13
©2013 Shaoxing Devechip Microelectronics Co., Ltd.
www.sdc-semi.com
Datasheet
Package Dimension
SOT-23-6
Dimensions In Millimeters
Dimensions In Inches
Symbol
Min
Max
1.250
0.100
1.150
0.500
0.200
3.020
1.700
2.950
Min
Max
0.049
0.004
0.045
0.020
0.008
0.119
0.067
0.116
A
A1
A2
b
1.050
0.000
1.050
0.300
0.100
2.820
1.500
2.650
0.041
0000
0.041
0.012
0.004
0.111
0.059
0.104
c
D
E
E1
e
0.950(BSC)
0.037(BSC)
e1
L
1.800
0.300
0°
2.000
0.600
8°
0.071
0.012
0°
0.079
0.024
8°
θ
December, 2013 Rev. 1.1
©2013 Shaoxing Devechip Microelectronics Co., Ltd.
12/13
www.sdc-semi.com
Datasheet
Shaoxing Devechip MicroelectronCo., Ltd.
http://www.sdc-semi.com/
IMPORTANT NOTICE
Information in this document is provided solely in connection with Shaoxing Devechip Microelectronics Co., Ltd. (abbr. SDC) products.
SDC reserves the right to hanges, corrections, modifications or improvements, to this document, and the products and services
described herein at anytimthout notice. SDC does not assume any responsibility for use of any its products for any particular
purpose, nor does SDC asume any liability arising out of the application or use of any its products or circuits. SDC does not convey
any license under its patent rights or other rights nor the rights of others.
© 2013 Devechip Microelectronics - All rights reserved
Contact
Headquarters of Shaoxing
Address: Tian Mu Road, No13,
Shaoxing city, Zhejiang province, China
Zip code: 312000
Shenzhen Branch
Address: 22A, Shangbu building, Nan Yuan Road, No.68,
Futian District, Shenzhen city, Guangdong province, China
Zip code: 518031
Tel: (86) 0575-8861 6750
Tel: (86) 0755-8366 1155
Fax: (86) 0575-8862 2882
Fax: (86) 0755-8301 8528
December, 2013 Rev. 1.1
©2013 Shaoxing Devechip Microelectronics Co., Ltd.
13/13
www.sdc-semi.com
相关型号:
©2020 ICPDF网 联系我们和版权申明