E0C62A81F [SEIKO]
4-BIT, MROM, 0.032768MHz, MICROCONTROLLER, PQFP64, PLASTIC, QFP6-64;
| 型号： | E0C62A81F |
| 厂家： | 
SEIKO EPSON CORPORATION |
| 描述： | 4-BIT, MROM, 0.032768MHz, MICROCONTROLLER, PQFP64, PLASTIC, QFP6-64 时钟 外围集成电路 |
| 文件： | 总10页 (文件大小：105K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PF468-09
E0C6281
4-bit Single Chip Microcomputer
● Core CPU Architecture
● SVD Circuit/Comparator
● Melody Circuit
■ DESCRIPTION
The E0C6281 is an advanced single-chip CMOS 4-bit microcomputer consisting of the E0C6200 CMOS 4-bit
core CPU. It also contains the ROM, RAM, LCD driver, time base counter and melody generation circuit.
The E0C6281 provides an excellent solution for low-power consumption systems with clock functions.
■ FEATURES
● CMOS LSI .............................................4-bit parallel processing
● Clock .....................................................32.768kHz (Typ.)
● Instruction set........................................100 instructions
● Instruction cycle time ............................153µsec, 214µsec or 366µsec (depending on instruction)
● ROM capacity .......................................1,024 × 12 bits
● RAM capacity ........................................96 × 4 bits
● Input port ...............................................5 bits
(pull-down resistors are available by mask option)
● Output port ............................................4 bits (general purpose port)
2 bits (for melody output): MO, MO (also used as the external CR
connecting terminal for envelope)
1 bit (for lamp output)
1 bit (for clock output: frequency can be selected from 256Hz
through 32kHz by mask option)
● I/O port ..................................................4 bits
● LCD driver .............................................26 segments × 3 commons, 1/3 duty or 4 commons, 1/4 duty
● Built-in stopwatch timer
● Built-in supply voltage detection (SVD) circuit
● Built-in comparator................................1 ch.
● Built-in melody generation circuit..........Equivalent to SVM7500 (80-word melody ROM is built in)
● Interrupts ...............................................External : Input interrupt
Internal : Timer interrupt
2 lines
1 line
1 line
Stopwatch interrupt
Melody completion interrupt 1 line
● Supply voltage ......................................1.5V/3.0V (Minimum operating voltage: 0.9V/1.8V)
● Current consumption ............................E0C6281/62L81
HALT mode
OPERATING mode : 2.5µA (Typ.)
HALT mode : 5.5µA (Typ.)
OPERATING mode : 7.2µA (Typ.)
: 1.0µA (Typ.)
E0C62A81/62B81
● Package ................................................QFP6-64pin-S1 (plastic)
Die form
■LINE UP
Model
Supply voltage
Clock
E0C6281
E0C62L81
E0C62A81
E0C62B81
3.0V (1.8V to 3.5V)
1.5V (0.9V to 3.5V)
3.0V (1.8V to 3.5V)
1.5V (0.9V to 3.5V)
32kHz (Crystal oscillation)
32kHz (Crystal oscillation)
32kHz (CR oscillation)
32kHz (CR oscillation)
SEIKO EPSON CORPORATION
1
E0C6281
< Detail of Melody Function >
• Melody memory capacity .................. 80 words
• Interval memory capacity .................. 16 words (including one pause note)
• Interval generated ............................. C3 to C6#, or C4 to C7# (mask option)
• Useful note ........................................ 8 (from sixteenth note to a half note)
• Tempo................................................ Basic: Select 2 tempos out of 16 tempos (30 to 480)(mask option)
(The tempo selected is changed by the software control.)
The tempo having 8 times, 16 times or 32 times the basic tempo is available by software.
• Envelope............................................ External CR is required. (not available for the piezoelectic direct drive type)
• Piezoelectic direct drive .................... Envelope not available
• Melody control function ..................... (1) 1 music: Melody start address is controlled by the software.
(2) Repeating: The address is controlled by the software when repeated.
(3) Forcible music change: The new music address is designated with the software
while a music is now played.
■ BLOCK DIAGRAM
ROM
System Reset
Control
OSC
1,024 words x 12 bits
Core CPU E0C6200
RAM
96 words x 4 bits
Interrupt
Generator
K00~03, K10
MTEST
TEST
COM0~3
SEG0~25
Input Port
Test Port
LCD Driver
VDD
V
L1~3
I/O Port
Output Port
Timer
P00~03
Power
Controller
CA~CC
VS1
VSS
R00~03, R10, R11
CMPP
CMPM
Comparator
& SVD
MO
Stop Watch
Melody
R12
■ PIN CONFIGURATION
No. Pin name No. Pin name No. Pin name No. Pin name
QFP6-64pin-S1
48
33
1
2
3
4
5
6
7
8
9
COM1
COM2
COM3
SEG25
SEG0
SEG1
SEG2
SEG3
SEG4
17 SEG12
18 TEST
33 P01
34 P02
35 P03
36 CMPM
37 CMPP
38 MTEST
39 RESET
40 K00
41 K01
42 K02
43 K03
44 K10
45 R10
46 R11
47 R12
48 MO
49 R00
50 R01
51 R02
52 R03
19 SEG13
20 SEG14
21 SEG15
22 SEG16
23 SEG17
24 SEG18
25 SEG19
26 SEG20
27 SEG21
28 SEG22
29 SEG23
30 SEG24
31 N.C.
49
32
53
54
55
V
V
V
S1
DD
SS
56 OSC2
57 OSC1
E0C6281
INDEX
10 SEG5
11 SEG6
12 SEG7
13 SEG8
14 SEG9
15 SEG10
16 SEG11
58
59
60
61 CC
62 CB
V
V
V
L3
L2
L1
64
17
63 CA
64 COM0
1
16
32 P00
N.C. = No Connection
2
E0C6281
■ PIN DESCRIPTION
Pin name
Pin No.
In/Out
Function
V
V
V
V
V
V
DD
SS
S1
L1
L2
L3
54
55
53
60
59
58
61–63
57
I
I
Power source (+) terminal
Power source (-) terminal
O
O
O
O
–
I
O
I
I/O
O
O
O
O
O
I
Oscillation and internal logic system regulated voltage output terminal
LCD system regulated voltage output terminal (approx. -1.05 V)
LCD system booster output terminal (VL1 x 2)
LCD system booster output terminal (VL1 x 3)
Booster capacitor connecting terminal
Crystal or CR oscillation input terminal
Crystal or CR oscillation output terminal
Input terminal
CA–CC
OSC1
OSC2
K00–K03, K10
P00–P03
R00–R03
R10
R11
R12
MO
CMPP
CMPM
SEG0–25
COM0–3
RESET
TEST
56
40–44
32–35
49–52
45
46
47
48
37
36
I/O terminal
Output terminal
Output terminal (FOUT output available by mask option)
Output terminal
Output terminal (Melody inverted output and envelope function available by mask option)
Melody signal output terminal
Analog comparator non-inverted input terminal
Analog comparator inverted input terminal
LCD segment output terminal (Convertible to DC output by mask option)
LCD common output terminal
I
4–17, 19–30
64, 1–3
39
O
O
I
Initial reset input terminal
Test input terminal
18
I
MTEST
38
I
Melody test input terminal
■ ELECTRICAL CHARACTERISTICS
● Absolute Maximum Ratings
(VDD=0V)
Rating
Supply voltage
Symbol
VSS
Value
-5.0 to 0.5
Unit
V
Input voltage (1)
Input voltage (2)
Permissible total output current *1 ΣIVSS
Operating temperature
Storage temperature
Soldering temperature / Time
Permissible dissipation *2
VI
VIOSC
VSS - 0.3 to 0.5
VSS - 0.3 to 0.5
10
-20 to 70
-65 to 150
V
V
mA
°C
°C
–
Topr
Tstg
Tsol
PD
260°C, 10sec (lead section)
250
mW
1: The permissible total output current is the sum total of the current (average current) that simultaneously flows from the output pins (or is draw in).
2: In case of plastic package (QFP6-64pin).
● Recommended Operating Conditions
E0C6281/62A81
(Ta=-20 to 70°C)
Condition
Supply voltage
Oscillation frequency
Symbol
Remark
Min.
-3.5
–
Typ.
-3.0
32.768
Max.
-1.8
–
Unit
V
kHz
V
SS
V
DD=0V
f
OSC
E0C62L81/62B81
(Ta=-20 to 70°C)
Condition
Supply voltage
Symbol
Remark
Min.
-3.5
-3.5
-3.5
–
Typ.
-1.5
-1.5
-1.5
32.768
Max.
-1.1
-0.9 *2
-1.3
–
Unit
V
V
V
kHz
VSS
V
V
V
DD=0V
DD=0V, With software control *1
DD=0V, When the analog comparator is used
Oscillation frequency
f
OSC
1: When switching to heavy load protection mode. The SVD circuit and analog voltage comparator are turned OFF.
2: The possibility of LCD panel display differs depending on the characteristics of the LCD panel.
3
E0C6281
● DC Characteristics
E0C6281/62A81
(Unless otherwise specified: VDD=0V, VSS=-3.0V, fOSC=32.768kHz, Ta=25°C, VS1/VL1–VL3 are internal voltage, C1–C6=0.1µF)
Characteristic
High level input voltage (1)
Symbol
VIH1
Condition
Min.
Typ.
Max.
0
Unit
V
K00–K03, K10, P00–P03 0.2•VSS
MTEST
High level input voltage (2)
Low level input voltage (1)
VIH2
VIL1
RESET, TEST
K00–K03, K10, P00–P03
MTEST
0.10•VSS
VSS
0
V
V
0.8•VSS
Low level input voltage (2)
High level input current (1)
VIL2
IIH1
RESET, TEST
K00–K03, K10, P00–P03
CMPP, CMPM
VSS
0
0.90•VSS
0.5
V
µA
VIH1=0V
No pull down resistor
VIH2=0V
With pull down resistor
VIH3=0V
With pull down resistor
VIL=VSS
High level input current (2)
High level input current (3)
Low level input current
IIH2
IIH3
IIL
K00–K03, K10
5
16
100
0
µA
µA
µA
P00–P03
30
RESET, TEST, MTEST
K00–K03, K10, P00–P03
CMPP, CMPM
RESET, TEST, MTEST
R11
R00–R03, R10, P00–P03
MO, R12
R11
-0.5
High level output current (1)
High level output current (2)
High level output current (3)
Low level output current (1)
Low level output current (2)
Low level output current (3)
Common output current
IOH1
IOH2
IOH3
IOL1
IOL2
IOL3
IOH4
IOL4
IOH5
IOL5
IOH6
IOL6
VOH1=0.1•VSS
VOH2=0.1•VSS
VOH3=0.1•VSS
VOL1=0.9•VSS
VOL2=0.9•VSS
VOL3=0.9•VSS
VOH4=-0.05V
VOL4=VL3+0.05V
VOH5=-0.05V
VOL5=VL3+0.05V
VOH6=0.1•VSS
VOL6=0.9•VSS
-1.0
-1.0
-2.0
mA
mA
mA
mA
mA
mA
µA
µA
µA
µA
µA
3.0
3.0
4.5
R00–R03, R10, P00–P03
MO, R12
COM0–COM3
-3
-3
3
3
Segment output current
(during LCD output)
Segment output current
(during DC output)
SEG0–SEG25
SEG0–SEG25
-300
300
µA
E0C62L81/62B81
(Unless otherwise specified: VDD=0V, VSS=-1.5V, fOSC=32.768kHz, Ta=25°C, VS1/VL1–VL3 are internal voltage, C1–C6=0.1µF)
Characteristic
High level input voltage (1)
Symbol
Condition
Min.
Typ.
Max.
0
Unit
V
V
IH1
K00–K03, K10, P00–P03 0.2•VSS
MTEST
High level input voltage (2)
Low level input voltage (1)
V
V
IH2
IL1
RESET, TEST
K00–K03, K10, P00–P03
MTEST
0.10•VSS
0
V
V
V
SS
0.8•VSS
Low level input voltage (2)
High level input current (1)
V
IL2
RESET, TEST
K00–K03, K10, P00–P03
CMPP, CMPM
V
0
SS
0.90•VSS
0.5
V
µA
I
I
I
I
IH1
V
IH1=0V
No pull down resistor
V
With pull down resistor
V
With pull down resistor
V
High level input current (2)
High level input current (3)
Low level input current
IH2
IH2=0V
K00–K03, K10
2.0
9.0
-0.5
10
60
0
µA
µA
µA
IH3
IL
IH3=0V
P00–P03
RESET, TEST, MTEST
K00–K03, K10, P00–P03
CMPP, CMPM
RESET, TEST, MTEST
R11
R00–R03, R10, P00–P03
MO, R12
MO
IL=VSS
High level output current (1)
High level output current (2)
High level output current (3)
High level output current (4)
I
I
I
I
OH1
OH2
OH3
OH4
V
V
V
V
OH1=0.1•VSS
OH2=0.1•VSS
OH3=0.1•VSS
OH4=0.1•VSS
-450
-200
-0.8
-0.4
µA
µA
mA
mA
When envelope is used
(R12=Normal H level)
R11
R00–R03, R10, P00–P03
MO, R12
Low level output current (1)
Low level output current (2)
Low level output current (3)
Low level output current (4)
I
I
I
I
OL1
OL2
OL3
OL4
V
V
V
V
OL1=0.9•VSS
OL2=0.9•VSS
OL3=0.9•VSS
OL4=0.9•VSS
1,300
700
1.5
µA
µA
mA
µA
MO
750
When envelope is used
(R12=Normal L level)
COM0–COM3
Common output current
I
I
I
I
I
I
OH5
OL5
OH6
OL6
OH7
OL7
V
V
V
V
V
V
OH5=-0.05V
OL5=VL3+0.05V
OH6=-0.05V
OL6=VL3+0.05V
OH7=0.1•VSS
OL7=0.9•VSS
-3
-3
µA
µA
µA
µA
µA
µA
3
3
Segment output current
(during LCD output)
Segment output current
(during DC output)
SEG0–SEG25
SEG0–SEG25
-100
130
4
E0C6281
● Analog Circuit Characteristics and Current Consumption
E0C6281 (Normal Operating Mode)
(Unless otherwise specified: VDD=0V, VSS=-3.0V, fOSC=32.768kHz, Ta=25°C, C
G
=25pF, VS1/VL1–VL3 are internal voltage, C1–C6=0.1µF)
Characteristic
Internal voltage
Symbol
Condition
Min.
-1.15
Typ.
-1.05
Max.
-0.95
Unit
V
V
V
V
V
L1
Connect 1MΩ load resistor between VDD and VL1
(without panel load)
Connect 1MΩ load resistor between VDD and VL2
(without panel load)
Connect 1MΩ load resistor between VDD and VL3
(without panel load)
L2
2•VL1
-0.1
3•VL1
-0.1
2•VL1
×0.9
3•VL1
×0.9
-2.25
100
V
V
L3
SVD voltage
SVD
-2.55
-2.40
V
µS
V
SVD circuit response time
Analog comparator
input voltage
Analog comparator
offset voltage
t
SVD
V
V
V
IP
Noninverted input (CMPP)
Inverted input (CMPM)
V
SS+0.3
V
DD-0.9
IM
OF
10
mV
mS
Analog comparator
response time
t
CMP
V
IP=-1.5V, VIM=VIP±15mV
3
Current consumption
I
OP
During HALT
During operation *1
1.0
2.5
2.5
5.0
µA
µA
Without panel load
1: The SVD circuit and analog voltage comparator are turned OFF.
E0C6281 (Heavy Load Protection Mode)
(Unless otherwise specified: VDD=0V, VSS=-3.0V, fOSC=32.768kHz, Ta=25°C, CG=25pF, VS1/VL1–VL3 are internal voltage, C1–C6=0.1µF)
Characteristic
Internal voltage
Symbol
Condition
Min.
-1.15
Typ.
-1.05
Max.
-0.95
Unit
V
V
V
V
V
L1
Connect 1MΩ load resistor between VDD and VL1
(without panel load)
Connect 1MΩ load resistor between VDD and VL2
(without panel load)
Connect 1MΩ load resistor between VDD and VL3
(without panel load)
L2
2•VL1
-0.1
3•VL1
-0.1
2•VL1
×0.85
3•VL1
×0.85
-2.25
100
V
V
L3
SVD voltage
SVD
-2.55
-2.40
V
µS
V
SVD circuit response time
Analog comparator
input voltage
Analog comparator
offset voltage
t
SVD
V
V
V
IP
Noninverted input (CMPP)
Inverted input (CMPM)
V
SS+0.3
V
DD-0.9
IM
OF
10
mV
mS
Analog comparator
response time
t
CMP
V
IP=-1.5V, VIM=VIP±15mV
3
Current consumption
I
OP
During HALT
During operation *1
2.0
5.5
5.5
10.0
µA
µA
Without panel load
1: The SVD circuit and analog voltage comparator are turned OFF.
E0C62L81 (Normal Operating Mode)
(Unless otherwise specified: VDD=0V, VSS=-1.5V, fOSC=32.768kHz, Ta=25°C, CG=25pF, VS1/VL1–VL3 are internal voltage, C1–C6=0.1µF)
Characteristic
Internal voltage
Symbol
Condition
Min.
-1.15
Typ.
-1.05
Max.
-0.95
Unit
V
V
V
V
V
L1
Connect 1MΩ load resistor between VDD and VL1
(without panel load)
Connect 1MΩ load resistor between VDD and VL2
(without panel load)
Connect 1MΩ load resistor between VDD and VL3
(without panel load)
L2
2•VL1
-0.1
3•VL1
-0.1
2•VL1
×0.9
3•VL1
×0.9
-1.10
100
V
V
L3
SVD voltage
SVD
-1.30
-1.20
V
µS
V
SVD circuit response time
Analog comparator
input voltage
Analog comparator
offset voltage
t
SVD
V
V
V
IP
Noninverted input (CMPP)
Inverted input (CMPM)
V
SS+0.3
V
DD-0.9
IM
OF
20
mV
mS
Analog comparator
response time
t
CMP
V
IP=-1.1V, VIM=VIP±30mV
3
Current consumption
I
OP
During HALT
During operation *1
1.0
2.5
2.5
5.0
µA
µA
Without panel load
1: The SVD circuit and analog voltage comparator are turned OFF.
5
E0C6281
E0C62L81 (Heavy Load Protection Mode)
(Unless otherwise specified: VDD=0V, VSS=-1.5V, fOSC=32.768kHz, Ta=25°C, CG=25pF, VS1/VL1–VL3 are internal voltage, C1–C6=0.1µF)
Characteristic
Internal voltage
Symbol
Condition
Min.
-1.15
Typ.
-1.05
Max.
-0.95
Unit
V
V
V
V
V
L1
Connect 1MΩ load resistor between VDD and VL1
(without panel load)
Connect 1MΩ load resistor between VDD and VL2
(without panel load)
Connect 1MΩ load resistor between VDD and VL3
(without panel load)
L2
2•VL1
-0.1
3•VL1
-0.1
2•VL1
×0.85
3•VL1
×0.85
-1.10
100
V
V
L3
SVD voltage
SVD
-1.30
-1.20
V
µS
V
SVD circuit response time
Analog comparator
input voltage
Analog comparator
offset voltage
t
SVD
V
V
V
IP
Noninverted input (CMPP)
Inverted input (CMPM)
V
SS+0.3
V
DD-0.9
IM
OF
20
mV
mS
Analog comparator
response time
t
CMP
V
IP=-1.1V, VIM=VIP±30mV
3
Current consumption
I
OP
During HALT
During operation *1
2.0
5.5
5.5
10.0
µA
µA
Without panel load
1: The SVD circuit and analog voltage comparator are turned OFF.
E0C62A81 (Normal Operating Mode)
(Unless otherwise specified: VDD=0V, VSS=-3.0V, fOSC=32.768kHz, Ta=25°C, CG=25pF, VS1/VL1–VL3 are internal voltage, C1–C6=0.1µF)
Characteristic
Internal voltage
Symbol
Condition
Min.
-1.15
Typ.
-1.05
Max.
-0.95
Unit
V
V
V
V
V
L1
Connect 1MΩ load resistor between VDD and VL1
(without panel load)
Connect 1MΩ load resistor between VDD and VL2
(without panel load)
Connect 1MΩ load resistor between VDD and VL3
(without panel load)
L2
2•VL1
-0.1
3•VL1
-0.1
2•VL1
×0.9
3•VL1
×0.9
-2.25
100
V
V
L3
SVD voltage
SVD
-2.55
-2.40
V
µS
V
SVD circuit response time
Analog comparator
input voltage
Analog comparator
offset voltage
t
SVD
V
V
V
IP
Noninverted input (CMPP)
Inverted input (CMPM)
V
SS+0.3
VDD-0.9
IM
OF
10
mV
mS
Analog comparator
response time
t
CMP
V
IP=-1.5V, VIM=VIP±15mV
3
Current consumption
I
OP
During HALT
During operation *1
5.5
7.2
10.0
12.0
µA
µA
Without panel load
1: The SVD circuit and analog voltage comparator are turned OFF.
E0C62A81 (Heavy Load Protection Mode)
(Unless otherwise specified: VDD=0V, VSS=-3.0V, fOSC=32.768kHz, Ta=25°C, CG=25pF, VS1/VL1–VL3 are internal voltage, C1–C6=0.1µF)
Characteristic
Internal voltage
Symbol
Condition
Min.
-1.15
Typ.
-1.05
Max.
-0.95
Unit
V
V
V
V
V
L1
Connect 1MΩ load resistor between VDD and VL1
(without panel load)
Connect 1MΩ load resistor between VDD and VL2
(without panel load)
Connect 1MΩ load resistor between VDD and VL3
(without panel load)
L2
2•VL1
-0.1
3•VL1
-0.1
2•VL1
×0.85
3•VL1
×0.85
-2.25
100
V
V
L3
SVD voltage
SVD
-2.55
-2.40
V
µS
V
SVD circuit response time
Analog comparator
input voltage
Analog comparator
offset voltage
t
SVD
V
V
V
IP
Noninverted input (CMPP)
Inverted input (CMPM)
V
SS+0.3
V
DD-0.9
IM
OF
10
mV
mS
Analog comparator
response time
t
CMP
V
IP=-1.5V, VIM=VIP±15mV
3
Current consumption
I
OP
During HALT
During operation *1
11.0
15.0
20.0
25.0
µA
µA
Without panel load
1: The SVD circuit and analog voltage comparator are turned OFF.
6
E0C6281
E0C62B81 (Normal Operating Mode)
(Unless otherwise specified: VDD=0V, VSS=-1.5V, fOSC=32.768kHz, Ta=25°C, C
G
=25pF, VS1/VL1–VL3 are internal voltage, C1–C6=0.1µF)
Characteristic
Internal voltage
Symbol
Condition
Min.
-1.15
Typ.
-1.05
Max.
-0.95
Unit
V
V
V
V
V
L1
Connect 1MΩ load resistor between VDD and VL1
(without panel load)
Connect 1MΩ load resistor between VDD and VL2
(without panel load)
Connect 1MΩ load resistor between VDD and VL3
(without panel load)
L2
2•VL1
-0.1
3•VL1
-0.1
2•VL1
×0.9
3•VL1
×0.9
-1.10
100
V
V
L3
SVD voltage
SVD
-1.30
-1.20
V
µS
V
SVD circuit response time
Analog comparator
input voltage
Analog comparator
offset voltage
t
SVD
V
V
V
IP
Noninverted input (CMPP)
Inverted input (CMPM)
V
SS+0.3
V
DD-0.9
IM
OF
20
mV
mS
Analog comparator
response time
t
CMP
V
IP=-1.1V, VIM=VIP±30mV
3
Current consumption
I
OP
During HALT
During operation *1
5.5
7.2
10.0
12.0
µA
µA
Without panel load
1: The SVD circuit and analog voltage comparator are turned OFF.
E0C62B81 (Heavy Load Protection Mode)
(Unless otherwise specified: VDD=0V, VSS=-1.5V, fOSC=32.768kHz, Ta=25°C, CG=25pF, VS1/VL1–VL3 are internal voltage, C1–C6=0.1µF)
Characteristic
Internal voltage
Symbol
Condition
Min.
-1.15
Typ.
-1.05
Max.
-0.95
Unit
V
V
V
V
V
L1
Connect 1MΩ load resistor between VDD and VL1
(without panel load)
Connect 1MΩ load resistor between VDD and VL2
(without panel load)
Connect 1MΩ load resistor between VDD and VL3
(without panel load)
L2
2•VL1
-0.1
3•VL1
-0.1
2•VL1
×0.85
3•VL1
×0.85
-1.10
100
V
V
L3
SVD voltage
SVD
-1.30
-1.20
V
µS
V
SVD circuit response time
Analog comparator
input voltage
Analog comparator
offset voltage
t
SVD
V
V
V
IP
Noninverted input (CMPP)
Inverted input (CMPM)
V
SS+0.3
V
DD-0.9
IM
OF
20
mV
mS
Analog comparator
response time
t
CMP
V
IP=-1.1V, VIM=VIP±30mV
3
Current consumption
I
OP
During HALT
During operation *1
11.0
15.0
20.0
25.0
µA
µA
Without panel load
1: The SVD circuit and analog voltage comparator are turned OFF.
7
E0C6281
● Oscillation Characteristics
The oscillation characteristics change depending on the conditions (components used, board pattern, etc.). Use the follow-
ing characteristics as reference values.
E0C6281 (Crystal)
(Unless otherwise specified: VDD=0V, VSS=-3.0V, Crystal: C-002R (C
I
=35kΩ), C
G
=25pF, CD=built-in, Ta=25°C)
Characteristic
Oscillation start voltage
Oscillation stop voltage
Built-in capacitance (drain)
Frequency/voltage deviation
Frequency/IC deviation
Frequency adjustment range
Harmonic oscillation start voltage
Permitted leak resistance
Symbol
Vsta
Vstp
Condition
Min.
-1.8
-1.8
Typ.
Max.
Unit
V
V
t
t
sta≤3sec
stp≤10sec
(VSS
(VSS
)
)
C
D
Including the parasitic capacity inside the IC
20
pF
∂f/∂V
∂f/∂IC
V
SS=-1.8 to -3.5V
=5 to 25pF
Between OSC1 and VDD, VSS
5
10
ppm
ppm
ppm
V
-10
40
∂f/∂CG
CG
V
hho
(VSS
)
-3.5
Rleak
200
MΩ
E0C62L81 (Crystal)
(Unless otherwise specified: VDD=0V, VSS=-1.5V, Crystal: C-002R (C
I
=35kΩ), C
G
=25pF, CD=built-in, Ta=25°C)
Characteristic
Oscillation start voltage
Oscillation stop voltage
Built-in capacitance (drain)
Frequency/voltage deviation
Frequency/IC deviation
Frequency adjustment range
Harmonic oscillation start voltage
Permitted leak resistance
Symbol
Vsta
Vstp
Condition
Min.
-1.1
-1.1(-0.9)*1
Typ.
Max.
Unit
V
V
t
t
sta≤3sec
stp≤10sec
(VSS
(VSS
)
)
C
D
Including the parasitic capacity inside the IC
20
pF
∂f/∂V
∂f/∂IC
V
SS=-1.1 to -3.5V (-0.9) *1
=5 to 25pF
Between OSC1 and VDD, VSS
5
10
ppm
ppm
ppm
V
-10
40
∂f/∂CG
CG
V
hho
(VSS
)
-3.5
Rleak
200
MΩ
1: Items enclosed in parentheses ( ) are those used when operating at heavy load protection mode.
E0C62A81 (CR)
(Unless otherwise specified: VDD=0V, VSS=-3.0V, RCR=850kΩ, Ta=25°C)
Characteristic
Oscillation frequency dispersion
Oscillation start voltage
Oscillation start time
Symbol
Condition
Min.
-20
-1.8
Typ.
32.768kHz
Max.
20
Unit
%
V
mS
V
f
OSC
Vsta
sta
(VSS
(VSS
)
)
t
V
SS=-1.8 to -3.5V
3
Oscillation stop voltage
Vstp
-1.8
E0C62B81 (CR)
(Unless otherwise specified: VDD=0V, VSS=-1.5V, RCR=850kΩ, Ta=25°C)
Characteristic
Oscillation frequency dispersion
Oscillation start voltage
Oscillation start time
Symbol
Condition
Min.
-20
-0.9
Typ.
32.768kHz
Max.
20
Unit
%
V
mS
V
f
OSC
Vsta
sta
Vstp
(VSS
(VSS
)
)
t
V
SS=-0.9 to -3.5V
3
Oscillation stop voltage
-0.9
8
E0C6281
■ BASIC EXTERNAL CONNECTION DIAGRAM
LCD PANEL
LCD PANEL
K00
CA
CB
CC
K00
CA
C1
C2
C3
C4
C5
C1
C2
C3
C4
C5
CB
CC
I
I
K03
K10
P00
K03
K10
P00
V
L1
L2
L3
DD
V
L1
L2
L3
DD
V
V
V
V
V
V
I/O
I/O
P03
P03
C
G
C
G
OSC1
OSC1
E0C6281
/62L81
E0C6281
/62L81
X'tal
CMPP
CMPM
X'tal
CMPP
CMPM
OSC2
OSC2
C6
1.5V
or
3.0V
C6
1.5V
or
V
S1
V
S1
3.0V
R00
RESET
R00
RESET
O
R03
R10
R11
TEST
MTEST
Vss
O
R03
R10
R11
TEST
MTEST
Vss
C7
Piezo Buzzer
Coil
R1
R2
R3
Piezo Buzzer
X'tal
Crystal oscillator 32.768kHz, C
Trimmer capacitor 5–25pF
I
(Max.)=35kΩ
X'tal
CG
Crystal oscillator 32.768kHz, C
Trimmer capacitor 5–25pF
I
(Max.)=35kΩ
CG
C1–C6 Capacitor
Cp Capacitor
R1, R2 Protection resistor 100Ω
0.1µF
3.3µF
C1–C6 Capacitor
0.1µF
1µF–10µF
3.3µF
C7
Cp
R3
Capacitor
Capacitor
Resistor
1kΩ or more
Note: The above tables are simply an example, and are not guaranteed to work.
9
E0C6281
■ PACKAGE DIMENSIONS
Plastic QFP6-64pin-S1
16.8±0.4
14±0.1
48
33
49
32
INDEX
64
17
1
16
0.35±0.1
0.8
0.15±0.05
0°
10°
0.6±0.15
1.4
Unit: mm
NOTICE:
No part of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko Epson. Seiko
Epson reserves the right to make changes to this material without notice. Seiko Epson does not assume any liability of any kind arising out of
any inaccuracies contained in this material or due to its application or use in any product or circuit and, further, there is no representation that
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© Seiko Epson Corporation 1999 All right reserved.
SEIKO EPSON CORPORATION
ELECTRONIC DEVICES MARKETING DIVISION
IC Marketing & Engineering Group
ED International Marketing Department I (Europe & U.S.A.)
421-8, Hino, Hino-shi, Tokyo 191-8501, JAPAN
Phone : 042-587-5812 FAX : 042-587-5564
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Phone : 042-587-5814 FAX : 042-587-5110
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