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RX-8581SA-0 [SEIKO]

0 TIMER(S), REAL TIME CLOCK, PDSO14, SOP-14;
RX-8581SA-0
型号： RX-8581SA-0
厂家： SEIKO EPSON CORPORATION    SEIKO EPSON CORPORATION
描述：

0 TIMER(S), REAL TIME CLOCK, PDSO14, SOP-14

时钟 光电二极管 外围集成电路
文件： 总31页 (文件大小：405K)
中文：  中文翻译
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MQ372-01  
Application Manual  
Real Time Clock Module  
RX-8581SA/JE/NB  
Model  
Product Number  
RX-8581SA  
RX-8581JE  
RX-8581NB  
Q41858151000200  
Q41858171000200  
Q41858191000200  
In pursuit of "Saving" Technology ,Epson electronic device.  
Our Lineup of semiconductors, Liquid crystal displays and quartz devices  
assists in creating the products of our customers' dreams.  
Epson IS energy savings.  
NOTICE  
• The material is subject to change without notice.  
• Any part of this material may not be reproduced or duplicated in any form or any means without the  
written permission of Seiko Epson.  
• The information, applied circuit, program, using way etc., written in this material is just for reference.  
Seiko Epson does not assume any liability for the occurrence of infringing any patent or copyright of third  
party. This material does not authorize the licence for any patent or intellectual property rights.  
• Any product described in this material may contain technology or the subject relating to strategic  
products under the control of the Foreign Exchange and Foreign Trade Law of Japan and may require an  
export licence from the Ministry of International Trade and industry or other approval from another  
government agency.  
• The products (except for some product for automotive applications) listed up on this material are designed  
to be used with ordinary electronic equipment (OA equipment, AV equipment, communications equipment,  
measuring instruments etc). Seiko Epson does not assume any liability for the case using the products with  
the appoication required high reliability or safety extremely (such as aerospace equipment etc).  
When intending to use any our product with automotive application and the other application than  
ordinary electronic equipments as above, please contact our sales representatives in advance.  
RX - 8581 SA/ JE / NB  
Contents  
1. Overview.................................................................................................................. 1  
2. Block Diagram....................................................................................................... 1  
3. Terminal description............................................................................................ 2  
3.1. Terminal connections.............................................................................................................. 2  
3.2. Pin Functions............................................................................................................................. 2  
4. Absolute Maximum Ratings.............................................................................. 3  
5. Recommended Operating Conditions .......................................................... 3  
6. Frequency Characteristics................................................................................ 3  
7. Electrical Characteristics................................................................................... 3  
7.1. DC characteristics........................................................................................................................ 3  
7.2. AC Characteristics................................................................................................................... 4  
8. Use Methods.......................................................................................................... 5  
8.1. Overview of Functions............................................................................................................ 5  
8.2. Description of Registers......................................................................................................... 6  
8.3. Fixed-cycle Timer Interrupt Function............................................................................... 13  
8.4. Time Update Interrupt Function......................................................................................... 16  
8.5. Alarm Interrupt Function ...................................................................................................... 18  
2
8.6. Reading/Writing Data via the I C Bus Interface........................................................... 21  
8.7. Backup and Recovery........................................................................................................... 25  
8.8. Connection with Typical Microcontroller ......................................................................... 25  
9. External Dimensions / Marking Layout....................................................... 26  
10. Reference Data ................................................................................................ 27  
RX - 8581 SA/ JE / NB  
I2C-Bus Interface Real-time Clock Module  
RX - 8581 SA / JE / NB  
• Features built-in 32.768-kHz crystal oscillator, frequency adjusted  
• Supports I2C-Bus's high speed mode (400 kHz)  
• Alarm interrupt function for day, date, hour, and minute settings  
• Fixed-cycle timer interrupt function  
(Seconds, minutes)  
(FOE and FOUT pins)  
(from 2000 to 2099)  
• Time update interrupt function  
• 32.768-kHz output with OE function  
• Auto correction of leap years  
• Wide interface voltage range: 1.8 V to 5.5 V  
• Wide time-keeping voltage range:1.6 V to 5.5 V  
• Low current consumption: 0.45 µA /3 V (Typ.)  
• Compact package (NB: SON−22 pin PKG)  
The I2C-Bus is a trademark of PHILIPS ELECTRONICS N.V.  
1. Overview  
This module is an I2C bus interface-compliant real-time clock which includes a 32.768-kHz crystal oscillator.  
In addition to providing a calendar (year, month, date, day, hour, minute, second) function and a clock counter  
function, this module provides an abundance of other functions including an alarm function, fixed-cycle timer  
function, time update interrupt function, and 32.768-kHz output function.  
The devices in this module are fabricated via a C-MOS process for low current consumption, which enables  
long-term battery back-up.  
All of these many functions are implemented in a thin, compact SON package, which makes it suitable for  
various kinds of mobile telephones and other small electronic devices.  
2. Block Diagram  
32.768 kHz  
OSC  
CLOCK  
and  
DIVIDER  
CALENDAR  
FOUT  
FOE  
FOUT  
CONTROLLER  
TIMER  
REGISTER  
INTERRUPT  
CONTROLLER  
ALARM  
/ INT  
REGISTER  
CONTROL  
REGISTER  
I2C-BUS  
INTERFACE  
CIRCUIT  
SCL  
SDA  
and  
SYSTEM  
CONTROLLER  
Page - 1  
MQ - 372 - 01  
RX - 8581 SA/ JE / NB  
3. Terminal description  
3.1. Terminal connections  
RX - 8581 SA  
RX - 8581 JE  
RX - 8581 NB  
SOP − 14 pin  
VSOJ − 20 pin  
SON − 22 pin  
# 1  
# 14  
# 1  
# 14  
# 1  
# 14  
(#12)  
# 11  
# 10  
# 11  
# 7  
# 8  
No. Pin terminal No. Pin terminal  
No. Pin terminal No. Pin terminal  
No. Pin terminal No. Pin terminal  
1
2
3
4
5
6
7
N.C.  
SCL  
SDA  
N.C.  
GND  
N.C.  
/ INT  
14 FOUT  
13 N.C.  
12 N.C.  
DD  
1
2
3
4
5
6
7
8
9
N.C.  
N.C.  
FOE  
20 N.C.  
19 N.C.  
18 N.C.  
17 N.C.  
16 N.C.  
15 N.C.  
14 N.C.  
13 N.C.  
12 N.C.  
11 N.C.  
1
2
3
4
5
6
7
8
9
/ INT  
GND  
22 N.C.  
21 N.C.  
20 N.C.  
19 N.C.  
18 N.C.  
17 N.C.  
16 N.C.  
15 N.C.  
14 N.C.  
DD  
( V  
)
DD  
V
11  
V
N.C.  
SDA  
SCL  
FOUT  
DD  
V
10 FOE  
FOUT  
SCL  
SDAT  
9
8
N.C.  
N.C.  
DD  
( V  
)
GND  
/ INT  
FOE  
10  
10 N.C.  
11 N.C.  
(13)  
(12)  
−
−
3.2. Pin Functions  
Signal  
name  
I/O  
Function  
SCL  
I
This is the serial clock input pin for I2C Bus communications.  
This pin's signal is used for input and output of address, data, and ACK bits,  
synchronized with the serial clock used for I2C communications.  
Since the SDA pin is an N-ch open drain pin during output, be sure to connect a suitable  
pull-up resistance relative to the signal line capacity.  
SDA  
I/O  
O
This is the C-MOS output pin with output control provided via the FOE pin.  
When FOE = "H" (high level), this pin outputs a 32.768-kHz signal.  
When output is stopped, the FOUT pin = "L" (low level).  
FOUT  
This is an input pin used to control the output mode of the FOUT pin.  
When this pin's level is high, the FOUT pin is in output mode. When it is low, output via the  
FOUT pin is stopped.  
FOE  
/INT  
I
This pins is used to output alarm signals, timer signals, time update signals, and other  
signals. This pin is an open drain pin.  
O
VDD  
(VDD)  
GND  
This pin is connected to a positive power supply.  
−
−
−
Although this pin has the same potential as VDD, it should not be connected externally.  
This pin is connected to a ground.  
This pin is not connected to the internal IC.  
Leave N.C. pins open or connect them to GND or VDD.  
N.C.  
−
(Note) Note with caution that in the RX-8581NB (SON-22 pin), the N.C. pins (pins 14 to  
22) are interconnected via the internal frame.  
Note: Be sure to connect a bypass capacitor rated at least 0.1 µF between VDD and GND.  
Page - 2  
MQ - 372 - 01  
RX - 8581 SA/ JE / NB  
4. Absolute Maximum Ratings  
GND = 0 V  
Unit  
Item  
Symbol  
Condition  
Rating  
to +7.0  
Supply voltage  
Input voltage (1)  
Input voltage (2)  
Output voltage (1)  
VDD  
VIN1  
VIN2  
Between VDD and GND  
FOE pin  
V
V
V
V
−0.3  
GND−0.3  
GND−0.3  
GND−0.3  
to VDD+0.3  
to +8.0  
SCL and SDA pins  
FOUT pin  
VOUT1  
to VDD+0.3  
Output voltage (2)  
VOUT2  
SDA and /INT pins  
to +8.0  
V
GND−0.3  
When stored separately,  
without packaging  
Storage temperature  
TSTG  
to +125  
−55  
°C  
5. Recommended Operating Conditions  
GND = 0 V V  
Max. Unit  
Item  
Symbol  
Condition  
Min.  
Typ.  
Operating supply voltage  
Clock supply voltage  
Operating temperature  
VDD  
VCLK  
TOPR  
1.8  
1.6  
−40  
3.0  
3.0  
+25  
5.5  
5.5  
+85  
V
V
°C  
−
−
No condensation  
6. Frequency Characteristics  
GND = 0 V  
Unit  
× 10-6  
Item  
Symbol  
Condition  
Rating  
(∗1)  
Frequency precision  
∆ f /f  
Ta = +25 °C, VDD = 3.0 V  
5
23.0  
Frequency/voltage  
characteristics  
× 10-6 /V  
f /V  
Ta = +25 °C, VDD = 2.0 V to 5.0 V  
2 Max.  
Frequency/temperature  
characteristics  
Oscillation start time  
Aging  
Ta = −10 °C to +70 °C,  
VDD = 3.0 V ; +25 °C reference  
Ta = +25 °C, VDD = 3.0 V  
× 10−6  
Top  
+10 / −120  
tSTA  
fa  
3 Max.  
5 Max.  
s
Ta = +25 °C, VDD = 3.0 V, first year  
× 10−6 /year  
(∗1)  
Precision gap per month: 1 minutes (excluding offset value)  
7. Electrical Characteristics  
7.1. DC characteristics  
*Unless otherwise specified, GND = 0 V , VDD = 1.8 V to 5.5 V , Ta = −40 °C to +85 °C  
Item  
Current  
consumption (1)  
Current  
consumption (2)  
Symbol  
Condition  
Min.  
Typ.  
Max.  
Unit  
fSCL = 0 Hz  
IDD1  
0.65  
1.2  
VDD = 5 V  
VDD = 3 V  
/INT = VDD, FOE = GND  
FOUT; output OFF  
µA  
IDD2  
IDD3  
0.45  
3.0  
0.8  
7.5  
( low level )  
fSCL = 0 Hz  
/INT, FOE = VDD  
FOUT;  
Current  
consumption (3)  
VDD = 5 V  
VDD = 3 V  
VDD = 5 V  
VDD = 3 V  
µA  
Current  
consumption (4)  
32.768 kHz output ON ,  
IDD4  
IDD5  
IDD6  
1.7  
8.0  
5.0  
4.5  
20.0  
12.0  
CL = 0 pF  
fSCL = 0 Hz  
/INT, FOE = VDD  
FOUT ;  
Current  
consumption (5)  
µA  
Current  
consumption (6)  
32.768 kHz output ON ,  
CL = 30 pF  
VIH1  
VIH2  
FOE pin  
SCL and SDA pins  
VDD + 0.3  
6.0  
V
V
High-level  
input voltage  
0.7 × VDD  
0.7 × VDD  
Low-level  
input voltage  
VIL  
Input pin  
V
GND − 0.3  
0.3 × VDD  
VOH1  
VOH2  
VOH3  
VOL1  
VOL2  
VOL3  
VOL4  
VOL5  
VOL6  
4.5  
2.2  
2.9  
GND  
GND  
GND  
GND  
GND  
GND  
5.0  
3.0  
3.0  
VDD=5 V, IOH=−1 mA  
VDD=3 V, IOH=−1 mA  
VDD=3 V, IOH=−100 µA  
VDD=5 V, IOL=1 mA  
VDD=3 V, IOL=1 mA  
VDD=3 V, IOL=100 µA  
VDD=5 V, IOL=1 mA  
VDD=3 V, IOL=1 mA  
VDD ≥2 V, IOL=3 mA  
High-level  
output voltage  
FOUT pin  
V
GND+0.5  
GND+0.8  
GND+0.1  
GND+0.25  
GND+0.4  
GND+0.4  
FOUT pin  
V
Low-level  
output voltage  
/INT pin  
SDA pin  
V
V
Input leakage  
current  
Output leakage  
current  
ILK  
Input pin, VIN = VDD or GND  
0.5  
0.5  
−0.5  
−0.5  
µA  
IOZ  
/INT, SDA, FOUT pins, VOUT = VDD or GND  
µA  
Page - 3  
MQ - 372 - 01  
RX - 8581 SA/ JE / NB  
* Unless otherwise specified,  
GND = 0 V , VDD = 1.8 V to 5.5 V , Ta = −40 °C to +85 °C  
7.2. AC Characteristics  
Item  
Symbol  
Condition  
Min.  
Typ.  
Max.  
Unit  
SCL clock frequency  
fSCL  
400  
kHz  
Start condition setup time  
Start condition hold time  
Data setup time  
tSU;STA  
tHD;STA  
tSU;DAT  
tHD;DAT  
tSU;STO  
0.6  
0.6  
100  
0
µs  
µs  
ns  
ns  
µs  
Data hold time  
Stop condition setup time  
Bus idle time between  
start condition and stop condition  
0.6  
tBUF  
1.3  
µs  
tLOW  
1.3  
0.6  
µs  
µs  
µs  
µs  
ns  
Time when SCL = "L"  
Time when SCL = "H"  
Rise time for SCL and SDA  
Fall time for SCL and SDA  
Allowable spike time on bus  
tHIGH  
tr  
tf  
0.3  
0.3  
50  
tSP  
VDD = 2.4 V ∼ 5.5 V  
50% of VDD level  
FOUT duty  
tW /t  
45  
50  
55  
%
Timing chart  
START  
CONDITION  
BIT 7  
MSB  
(A7)  
BIT 0  
LSB  
(R/W)  
ACK  
(A)  
STOP  
CONDITION  
(P)  
START  
CONDITION  
(S)  
Protocol  
(S)  
tSU ; STA  
tLOW  
tHIGH  
1 / fSCL  
tSU ; STA  
SCL  
SDA  
(S)  
(P)  
(S)  
tBUF  
tr  
tf  
(A)  
tHD ; STA  
tSU ; DAT  
tHD ; DAT  
tSP  
tSU ; STO  
tHD ; STA  
Caution: When accessing this device, all communication from transmitting the start condition to transmitting the stop  
condition after access should be completed within 0.95 seconds.  
If such communication requires 0.95 seconds or longer, the I2C bus interface is reset by the internal bus  
timeout function.  
Page - 4  
MQ - 372 - 01  
RX - 8581 SA/ JE / NB  
8. Use Methods  
8.1. Overview of Functions  
1) Clock functions  
This function is used to set and read out month, day, hour, date, minute, second, and year (last two digits) data.  
Any (two-digit) year that is a multiple of 4 is treated as a leap year and calculated automatically as such until the year  
2099.  
∗ For details, see "8.2. Description of Registers".  
2) Fixed-cycle interrupt generation function  
The fixed-cycle timer interrupt generation function generates an interrupt event periodically at any fixed cycle set  
between 244.14 µs and 4095 minutes.  
When an interrupt event is generated, the /INT pin goes to low level ("L") and "1" is set to the TF bit to report that an  
event has occurred. (However, when a fixed-cycle timer interrupt event has been generated, low-level output from the  
/INT pin occurs only when the value of the control register's TIE bit is "1". Up to 7.8 ms after the interrupt occurs, the  
/INT status is automatically cleared (/INT status changes from low level to Hi-Z).  
∗ For details, see "8.3. Fixed-cycle Interrupt Function". .  
3) Time update interrupt function  
The time update interrupt function generates interrupt events at one-second or one-minute intervals, according to the  
timing of the internal clock.  
When an interrupt event occurs, the UF bit value becomes "1" and the /INT pin goes to low level to indicate that an  
event has occurred. (However, when a fixed-cycle timer interrupt event has been generated, low-level output from the  
/INT pin occurs only when the value of the control register's UIE bit is "1". This /INT status is automatically cleared  
(/INT status changes from low level to Hi-Z) 7.8 ms (a fixed value) after the interrupt occurs.  
∗ For details, see "8.4. Time Update Interrupt Function".  
4) Alarm interrupt function  
The alarm interrupt generation function generates interrupt events for alarm settings such as date, day, hour, and  
minute settings.  
When an interrupt event occurs, the AF bit value is set to "1" and the /INT pin goes to low level to indicate that an  
event has occurred.  
∗ For details, see "8.5. Alarm Interrupt Function".  
5) 32.768-kHz clock output  
The 32.768-kHz clock (with precision equal to that of the built-in crystal oscillator) can be output via the FOUT pin.  
The FOUT pin is a CMOS output pin which can be set for clock output when the FOE pin is at high level and for  
low-level output when the FOE pin is at low level.  
6) Interface with CPU  
Data is read and written via the I2C bus interface using two signal lines: SCL (clock) and SDA (data).  
Since neither SCL nor SDA includes a protective diode on the VDD side, a data interface between hosts with differing  
supply voltages can still be implemented by adding pull-up resistors to the circuit board.  
The SCL's maximum clock frequency is 400 kHz (when VDD ≥ 1.8 V), which supports the I2C bus's high-speed mode.  
∗ For further description of data read/write operations, see "8.6 Reading/Writing Data via the I2C Bus Interface".  
Page - 5  
MQ - 372 - 01  
RX - 8581 SA/ JE / NB  
8.2. Description of Registers  
8.2.1. Register table  
Remark  
Address  
Function  
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0  
¡
0
1
2
3
4
5
6
7
8
9
SEC  
MIN  
40  
40  
¡
20  
20  
20  
5
10  
10  
10  
4
8
8
8
3
8
8
8
•
4
4
4
2
4
4
4
•
2
2
2
1
2
2
2
•
1
1
1
0
1
1
1
•
∗3  
∗3  
∗3  
∗3  
∗3  
∗3  
−
∗4  
−
∗4  
¡
¡
¡
¡
¡
HOUR  
WEEK  
DAY  
6
¡
¡
20  
¡
10  
10  
10  
•
MONTH  
YEAR  
RAM  
80  
•
AE  
40  
•
40  
20  
•
20  
MIN Alarm  
10  
8
4
2
1
HOUR Alarm  
WEEK Alarm  
DAY Alarm  
AE  
20  
5
20  
32  
10  
4
10  
16  
8
3
8
8
4
2
4
4
2
1
2
2
1
0
1
1
•
6
•
A
AE  
∗4  
B
C
D
E
F
Timer Counter 0  
128  
64  
−
∗4  
Timer Counter 1  
Extension Register  
Flag Register  
2048 1024  
¡
512  
256  
•
•
•
•
¡
¡
¡
TEST WADA USEL  
¡
TE  
TF  
TIE  
TSEL1 TSEL0  
∗1, ∗3, ∗5  
∗1, ∗2, ∗3  
∗3  
¡
¡
UF  
AF  
AIE  
VLF  
¡
¡
Control Register  
UIE  
STOP RESET  
Note  
When after the initial power-up or when the result of read out the VLF bit is "1" , initialize all registers, before  
using the module.  
Be sure to avoid entering incorrect date and time data, as clock operations are not guaranteed when the data  
or time data is incorrect.  
∗1)  
During the initial power-up, the TEST bit is reset to "0" and the VLF bit is set to "1".  
∗ At this point, all other register values are undefined, so be sure to perform a reset before using the module.  
Only a "0" can be written to the UF, TF, AF, or VLF bit.  
∗2)  
∗3)  
∗4)  
∗5)  
Any bit marked with "¡" should be used with a value of "0" after initialization.  
Any bit marked with "•" is a RAM bit that can be used to read or write any data.  
The TEST bit is used by the manufacturer for testing. Be sure to set "0" for this bit when writing.  
Page - 6  
MQ - 372 - 01  
RX - 8581 SA/ JE / NB  
8.2.2. Control register (Reg F)  
Address  
Function  
bit 7  
bit 6  
bit 5  
bit 4  
bit 3  
bit 2  
bit 1  
bit 0  
¡
¡
¡
Control Register  
UIE  
(−)  
TIE  
(−)  
AIE  
(−)  
STOP RESET  
F
(Default)  
(0)  
(0)  
(0)  
(−)  
(−)  
∗1) The default value is the value that is read (or is set internally) after powering up from 0 V.  
∗2) "o" indicates write-protected bits. A zero is always read from these bits.  
∗3) "−" indicates no default value has been defined.  
• This register is used to control interrupt event output from the /INT pin and the stop/start status of clock and  
calendar operations.  
1) UIE (Update Interrupt Enable) bit  
When a time update interrupt event is generated (when the UF bit value changes from "0" to "1"), this bit's value  
specifies if an interrupt signal is generated (/INT status changes from Hi-Z to low) or is not generated (/INT  
status remains Hi-Z).  
When a "1" is written to this bit, an interrupt signal is generated (/INT status changes from Hi-Z to low) when an  
interrupt event is generated.  
When a "0" is written to this bit, no interrupt signal is generated when an interrupt event occurs.  
UIE  
Data  
Function  
When a time update interrupt event occurs, an interrupt signal is not  
generated or is canceled (/INT status changes from low to Hi-Z).  
0
When a time update interrupt event occurs, an interrupt signal is generated  
(/INT status changes from Hi-Z to low).  
∗ When a time update interrupt event occurs, low-level output from the /INT pin occurs only when  
the value of the control register's UIE bit is "1". This /INT status is automatically cleared (/INT  
status changes from low to Hi-Z) 7.8 ms after the interrupt occurs.  
Write/Read  
1
∗ For details, see "8.4. Time Update Interrupt Function".  
2) TIE (Timer Interrupt Enable) bit  
When a fixed-cycle timer interrupt event occurs (when the TF bit value changes from "0" to "1"), this bit's value  
specifies if an interrupt signal is generated (/INT status changes from Hi-Z to low) or is not generated (/INT  
status remains Hi-Z).  
When a "1" is written to this bit, an interrupt signal is generated (/INT status changes from Hi-Z to low) when an  
interrupt event is generated.  
When a "0" is written to this bit, no interrupt signal is generated when an interrupt event occurs.  
TIE  
Data  
Function  
When a fixed-cycle timer interrupt event occurs, an interrupt signal is not  
generated or is canceled (/INT status changes from low to Hi-Z).  
0
When a fixed-cycle timer interrupt event occurs, an interrupt signal is  
generated (/INT status changes from Hi-Z to low).  
* When a fixed-cycle timer interrupt event has been generated low-level output from the /INT pin  
occurs only when the value of the control register's TIE bit is "1". Up to 7.8 ms after the interrupt  
occurs, the /INT status is automatically cleared (/INT status changes from low to Hi-Z).  
Write/Read  
1
∗ For details, see "8.3. Fixed-cycle Timer Interrupt Function".  
3) AIE (Alarm Interrupt Enable) bit  
When an alarm timer interrupt event occurs (when the AF bit value changes from "0" to "1"), this bit's value  
specifies if an interrupt signal is generated (/INT status changes from Hi-Z to low) or is not generated (/INT  
status remains Hi-Z).  
When a "1" is written to this bit, an interrupt signal is generated (/INT status changes from Hi-Z to low) when an  
interrupt event is generated.  
When a "0" is written to this bit, no interrupt signal is generated when an interrupt event occurs.  
AIE  
Data  
Function  
When an alarm interrupt event occurs, an interrupt signal is not generated  
or is canceled (/INT status changes from low to Hi-Z).  
0
When an alarm interrupt event occurs, an interrupt signal is generated  
(/INT status changes from Hi-Z to low).  
∗ When an alarm interrupt event has been generated low-level output from the /INT pin occurs  
only when the value of the control register's AIE bit is "1". This setting is retained until the AF bit  
value is cleared to zero. (No automatic cancellation)  
Write/Read  
1
∗ For details, see "8.5. Alarm Interrupt Function".  
[Caution]  
(1) The /INT pin is a shared interrupt output pin for three types of interrupts. It outputs the OR'ed result of these interrupt outputs.  
When an interrupt has occurred (when the /INT pin is at low level), the UF, TF, read AF flags to determine which flag has a value of "1"  
(this indicates which type of interrupt event has occurred).  
(2) To keep the /INT pin from changing to low level, write "0" to the UIE, TIE, and AIE bits. To check whether an event has occurred without  
outputting any interrupts via the /INT pin, use software to monitor the value of the UF, TF, and AF interrupt flags.  
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4) STOP bit  
This bit is used to stop functions related to the RTC's internal counter operations.  
Writing a "1" to this bit stops the counter operations.  
Writing a "0" to this bit cancels stop status (restarts operations).  
∗ For optimum performance, do not use this bit for functions other than the clock and calendar functions.  
STOP  
Data  
Description  
[Normal operation mode]  
This bit is used to cancel stop status for (i.e., restart) the clock and calendar  
function. Also, when "1" is written to the STOP bit, it cancels stop status for  
the fixed-cycle timer function.  
0
∗ When the RESET bit value is "1" operation will not be restarted. To restart operation, a "0" must  
be written to both the STOP bit and the RESET bit.  
[Operation stop mode]  
Stops updating of year, month, date, day, hour, minute, and second values  
and partially stops the fixed-cycle timer function.  
(Stop 1) Stops updating of year, month, date, day, hour, minute, and  
second values  
Write/Read  
• This stops all clock and calendar update operations.  
Once this occurs, no more time update interrupt events or alarm  
interrupt events occur.  
1
(Stop 2) Partially stops the fixed-cycle timer function  
• If the fixed-cycle timer's source clock settings include an update  
setting of 64 Hz, 1 Hz, or "Minute", the fixed-cycle timer function does  
not operate.  
∗ However, this function does operate when the fixed-cycle timer's source  
clock setting is 4096 Hz.  
When this bit value is "1", internal divider stops from 2048Hz to 1 Hz .  
5) RESET bit  
Like the STOP function described above, this function stops functions related to counter operations. It also  
resets the RTC module's internal counter value when the value is less than one second.  
Writing a "1" to this bit stops the counter operation and resets the RTC module's internal counter value when the  
value is less than one second.  
Writing a "0" to this bit cancels stop status for (restarts) these operations. If a STOP condition or repeated  
START condition is received while the 0.95-second bus timeout function is operating, stop status is automatically  
canceled (the RESET bit value is changed from "1" to "0").  
∗ For optimum performance, do not use this bit for functions other than the clock and calendar functions.  
RESET  
Data  
0
Description  
[Normal operation mode]  
This bit is used to cancel stop status for (i.e., restart) the clock and calendar  
function. Also, when "1" is written to the RESET bit, it cancels stop status for  
the fixed-cycle timer function.  
∗ Since operation is not restarted when the STOP bit value is "1", to restart operation, a "0" must be  
written to both the STOP bit and the RESET bit.  
[Operation stop mode]  
Stops updating of year, month, date, day, hour, minute, and second values  
and partially stops the fixed-cycle timer function.  
(Stop 1) Stops updating of year, month, date, day, hour, minute, and  
second values  
Write/Read  
• This stops all clock and calendar update operations.  
Once this occurs, no more time update interrupt events or alarm  
interrupt events occur.  
1
(Stop 2) Partially stops the fixed-cycle timer function  
• If the fixed-cycle timer's source clock settings include an update  
setting of 64 Hz, 1 Hz, or "Minute", the fixed-cycle timer function does  
not operate.  
∗ However, this function does operate when the fixed-cycle timer's source clock setting is  
4096 Hz.  
(Note) When this bit value is "1", the internal divider keeps the reset state, from 2048Hz to 1 Hz .  
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8.2.3. Flag register (Reg-E)  
Address  
E
Function  
bit 7  
bit 6  
bit 5  
bit 4  
bit 3  
bit 2  
bit 1  
bit 0  
¡
¡
¡
¡
Flag register  
UF  
(−)  
TF  
(−)  
AF  
(−)  
VLF  
(1)  
(Default)  
(0)  
(0)  
(0)  
(0)  
∗1) The default value is the value that is read (or is set internally) after powering up from 0 V.  
∗2) "o" indicates write-protected bits. A zero is always read from these bits.  
∗3) "−" indicates a default value is undefined.  
• This register is used to detect the occurrence of various interrupt events and reliability problems in internal data.  
1) UF (Update Flag) bit  
If set to "0" beforehand, this flag bit's value changes from "0" to 1" when a time update interrupt event has  
occurred. Once this flag bit's value is "1", its value is retained until a "0" is written to it.  
∗ For details, see "8.4. Time Update Interrupt Function".  
2) TF (Timer Flag) bit  
If set to "0" beforehand, this flag bit's value changes from "0" to 1" when a fixed-cycle timer interrupt event has  
occurred. Once this flag bit's value is "1", its value is retained until a "0" is written to it.  
∗ For details, see "8.3. Fixed-cycle Timer Interrupt Function".  
3) AF (Alarm Flag) bit  
If set to "0" beforehand, this flag bit's value changes from "0" to 1" when an alarm interrupt event has occurred.  
Once this flag bit's value is "1", its value is retained until a "0" is written to it.  
∗ For details, see "8.5. Alarm Interrupt Function".  
4) VLF (Voltage Low Flag) bit  
This flag bit indicates the retained status of clock operations or internal data. Its value changes from "0" to "1"  
when data loss occurs, such as due to a supply voltage drop. Once this flag bit's value is "1", its value is retained  
until a "0" is written to it.  
This bit's value is "1" after powering up from 0 V.  
VLF  
Data  
0
Description  
The VLF bit is cleared to zero to prepare for the next status detection.  
Write  
1
0
This bit is invalid after a "1" has been written to it.  
Data loss is not detected.  
Read  
Data loss is detected.  
1
All registers must be initialized.  
(This setting is retained until a "zero" is written to this bit.)  
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8.2.4. Extension register (Reg-D)  
Address  
D
Function  
bit 7  
bit 6  
bit 5  
bit 4  
bit 3  
bit 2  
bit 1  
bit 0  
¡
¡
Extension Register  
TEST  
(0)  
WADA  
(−)  
USEL  
(−)  
TE  
(−)  
TSEL1 TSEL0  
(−)  
(Default)  
(0)  
(0)  
(−)  
∗1) The default value is the value that is read (or is set internally) after powering up from 0 V.  
∗2) "o" indicates write-protected bits. A zero is always read from these bits.  
∗3) "−" indicates a default value is undefined.  
• This register is used to specify the target for the alarm function or time update interrupt function and to select or  
set operations such as fixed-cycle timer operations.  
1) TEST bit  
This is the manufacturer's test bit. Its value should always be "0".  
Be careful to avoid writing a "1" to this bit when writing to other bits.  
∗ If a "1" is inadvertently written to this TEST bit, there is a safety function where by this bit will be automatically cleared to zero when a STOP  
condition or Repeated START condition is received or when the 0.95-second bus timeout function operates.  
TEST  
Data  
0
Description  
∗ Default  
Normal operation mode  
Setting prohibited (manufacturer's test bit)  
Write/Read  
1
2) WADA (Week Alarm/Day Alarm) bit  
This bit is used to specify either WEEK or DAY as the target of the alarm interrupt function.  
Writing a "1" to this bit specifies DAY as the comparison object for the alarm interrupt function.  
Writing a "0" to this bit specifies WEEK as the comparison object for the alarm interrupt function.  
∗ For details, see "8.5. Alarm Interrupt Function".  
3) USEL (Update Interrupt Select) bit  
This bit is used to specify either "second update" or "minute update" as the update generation timing of the time  
update interrupt function.  
Writing a "1" to this bit specifies the internal clock's "minute update" (once per minute) operation as the timing  
by which time update interrupts are generated.  
Writing a "0" to this bit specifies the internal clock's "second update" (once per second) operation as the timing  
by which time update interrupts are generated.  
∗ For details, see "8.4. Time Update Interrupt Function".  
4) TE (Timer Enable) bit  
This bit controls the start/stop setting for the fixed-cycle timer interrupt function.  
Writing a "1" to this bit specifies starting of the fixed-cycle timer interrupt function (a countdown starts from a  
preset value).  
Writing a "0" to this bit specifies stopping of the fixed-cycle timer interrupt function.  
∗ For details, see "8.3. Fixed-cycle Timer Interrupt Function".  
5) TSEL0,1 (Timer Select 0, 1) bits  
The combination of these two bits is used to set the countdown period (source clock) for the fixed-cycle timer  
interrupt function (four settings can be made).  
TSEL1  
(bit 1)  
TSEL0  
(bit 0)  
TSEL0,1  
Source clock  
4096 Hz  
0
0
1
1
0
1
0
1
/Once per 244.14 µs  
64 Hz / Once per 15.625 ms  
"Second" update /Once per second  
"Minute" update /Once per minute  
Write/Read  
∗ For details, see "8.3. Fixed-cycle Timer Interrupt Function".  
8.2.5. RAM register (Reg - 7)  
Address  
7
Function  
RAM  
bit 7  
bit 6  
bit 5  
bit 4  
bit 3  
bit 2  
bit 1  
bit 0  
•
•
•
•
•
•
•
•
• This RAM register is read/write accessible for any data in the range from 00 h to FF h.  
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8.2.6. Clock counter (Reg - 0 ∼ 2)  
Address  
Function  
bit 7  
bit 6  
40  
40  
¡
bit 5  
bit 4  
bit 3  
bit 2  
bit 1  
bit 0  
¡
¡
¡
0
1
2
SEC  
MIN  
HOUR  
20  
20  
20  
10  
10  
10  
8
8
8
4
4
4
2
2
2
1
1
1
∗) "o" indicates write-protected bits. A zero is always read from these bits.  
• The clock counter counts seconds, minutes, and hours.  
• The data format is BCD format. For example, when the "seconds" register value is "0101 1001" it indicates 59  
seconds.  
∗ Note with caution that writing non-existent time data may interfere with normal operation of the clock counter.  
1) Second counter  
Address  
0
Function  
SEC  
bit 7  
bit 6  
40  
bit 5  
20  
bit 4  
10  
bit 3  
8
bit 2  
4
bit 1  
2
bit 0  
1
¡
• This second counter counts from "00" to "01," "02," and up to 59 seconds, after which it starts again from  
00 seconds.  
• When data was written to seconds counter, the internal divider is reset from 2048Hz to 1Hz.  
2) Minute counter  
Address  
Function  
MIN  
bit 7  
bit 6  
40  
bit 5  
20  
bit 4  
10  
bit 3  
8
bit 2  
4
bit 1  
2
bit 0  
1
¡
1
• This minute counter counts from "00" to "01," "02," and up to 59 minutes, after which it starts again from  
00 minutes.  
3) Hour counter  
Address  
Function  
HOUR  
bit 7  
bit 6  
bit 5  
20  
bit 4  
10  
bit 3  
8
bit 2  
4
bit 1  
2
bit 0  
1
¡
¡
2
• This hour counter counts from "00" hours to "01," "02," and up to 23 hours, after which it starts again from  
00 hours.  
8.2.7. Day counter (Reg - 3)  
Address  
3
Function  
WEEK  
bit 7  
bit 6  
6
bit 5  
5
bit 4  
4
bit 3  
3
bit 2  
2
bit 1  
1
bit 0  
0
¡
∗) "o" indicates write-protected bits. A zero is always read from these bits.  
• The day (of the week) is indicated by 7 bits, bit 0 to bit 6.  
The day data values are counted as: Day 01h → Day 02h → Day 04h → Day 08h → Day 10h → Day  
20h → Day 40h → Day 01h → Day 02h, etc.  
• The correspondence between days and count values is shown below.  
WEEK  
bit 7  
bit 6  
bit 5  
bit 4  
bit 3  
bit 2  
bit 1  
bit 0  
Day  
Data [h]  
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
1
0
0
0
0
0
1
0
0
0
0
0
1
0
0
0
0
0
1
0
0
0
0
0
1
0
0
0
0
0
1
0
0
0
0
0
0
Sunday  
Monday  
Tuesday  
Wednesday  
Thursday  
Friday  
01 h  
02 h  
04 h  
08 h  
10 h  
20 h  
40 h  
Write/Read  
Saturday  
∗ Do not set "1" to more than one day at the same time.  
Also, note with caution that any setting other than the  
seven shown above should not be made as it may  
interfere with normal operation.  
Write prohibit  
−
−
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8.2.8. Calendar counter (Reg 4 to 6)  
Address  
Function  
bit 7  
bit 6  
bit 5  
bit 4  
bit 3  
bit 2  
bit 1  
bit 0  
¡
¡
4
5
6
DAY  
MONTH  
YEAR  
20  
¡
10  
10  
10  
8
8
8
4
4
4
2
2
2
1
1
1
¡
¡
80  
40  
20  
∗) "o" indicates write-protected bits. A zero is always read from these bits.  
• The auto calendar function updates all dates, months, and years from January 1, 2001 to December 31, 2099.  
• The data format is BCD format. For example, a date register value of "0011 0001" indicates the 31st.  
∗ Note with caution that writing non-existent date data may interfere with normal operation of the calendar counter.  
1) Date counter  
Address  
4
Function  
DAY  
bit 7  
bit 6  
bit 5  
20  
bit 4  
10  
bit 3  
8
bit 2  
4
bit 1  
2
bit 0  
1
¡
¡
• The updating of dates by the date counter varies according to the month setting.  
∗ A leap year is set whenever the year value is a multiple of four (such as 04, 08, 12, 88, 92, or 96). In  
February of a leap year, the counter counts dates from "01," "02," "03," to "28," "29," "01," etc.  
DAY  
Month  
Date update pattern  
1, 3, 5, 7, 8, 10, or 12  
4, 6, 9, or 11  
February in normal year  
February in leap year  
01, 02, 03 ∼ 30, 31, 01 ∼  
01, 02, 03 ∼ 30, 01, 02 ∼  
01, 02, 03 ∼ 28, 01, 02 ∼  
01, 02, 03 ∼ 28, 29, 01 ∼  
Write/Read  
2) Month counter  
Address  
5
Function  
MONTH  
bit 7  
bit 6  
bit 5  
bit 4  
10  
bit 3  
8
bit 2  
4
bit 1  
2
bit 0  
1
¡
¡
¡
• The month counter counts from 01 (January), 02 (February), and up to 12 (December), then starts again  
at 01 (January).  
3) Year counter  
Address  
Function  
Years  
bit 7  
Y80  
bit 6  
Y40  
bit 5  
Y20  
bit 4  
Y10  
bit 3  
Y8  
bit 2  
Y4  
bit 1  
Y2  
bit 0  
Y1  
6
• The year counter counts from 00, 01, 02 and up to 99, then starts again at 00.  
• Any year that is a multiple of four (04, 08, 12, 88, 92, 96, etc.) is handled as a leap year.  
8.2.9. Alarm registers (Reg - 8 ∼ A)  
Address  
Function  
bit 7  
bit 6  
bit 5  
bit 4  
bit 3  
bit 2  
bit 1  
bit 0  
8
9
MIN Alarm  
HOUR Alarm  
WEEK Alarm  
DAY Alarm  
AE  
AE  
40  
•
20  
20  
5
10  
10  
4
8
8
3
8
4
4
2
4
2
2
1
2
1
1
0
1
6
A
AE  
20  
10  
•
• The alarm interrupt function is used, along with the AEI, AF, and WADA bits, to set alarms for specified date, day,  
hour, and minute values.  
• When the settings in the above alarm registers and the WADA bit match the current time, the /INT pin goes to low  
level and "1" is set to the AF bit to report that and alarm interrupt event has occurred.  
∗ For details, see "8.5. Alarm Interrupt Function".  
8.2.10. Fixed-cycle timer control registers (Reg - B ∼ C)  
Address  
Function  
bit 7  
bit 6  
bit 5  
bit 4  
bit 3  
bit 2  
bit 1  
bit 0  
B
C
Timer Counter 0  
Timer Counter 1  
128  
•
64  
•
32  
•
16  
•
8
4
2
512  
1
256  
2048  
1024  
• These registers are used to set the preset countdown value for the fixed-cycle timer interrupt function.  
The TE, TF, TIE, and TSEL0/1 bits are also used to set the fixed-cycle timer interrupt function.  
• When the value in the above fixed-cycle timer control register changes from 001h to 000h, the /INT pin goes to  
low level and "1" is set to the TF bit to report that a fixed-cycle timer interrupt event has occurred.  
∗ For details, see "8.3. Fixed-cycle Timer Interrupt Function".  
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8.3. Fixed-cycle Timer Interrupt Function  
The fixed-cycle timer interrupt generation function generates an interrupt event periodically at any fixed cycle set  
between 244.14 µs and 4095 minutes.  
When an interrupt event is generated, the /INT pin goes to low level and "1" is set to the TF bit to report that an  
event has occurred. (However, when a fixed-cycle timer interrupt event has been generated low-level output from  
the /INT pin occurs only when the value of the control register's TIE bit is "1". Up to 7.8 ms after the interrupt  
occurs, the /INT status is automatically cleared (/INT status changes from low-level to Hi-Z).  
∗ Example of  
/INT operation  
7.8ms  
(Max.)  
period  
TIE = " 1 "  
TE = " 0 " → " 1 "  
TIE = " 1 " → " 0 "  
8.3.1. Diagram of fixed-cycle timer interrupt function  
Fixed-cycle timer starts  
Fixed-cycle timer stops  
" 1 "  
" 0 "  
(1)  
(7)  
TE bit  
Operation of fixed-cycle timer  
(9)  
" 1 "  
" 1 "  
" 0 "  
(5)  
TIE bit  
Hi - z  
" L "  
/INT output  
(6)  
tRTN  
(7)  
∗ Even when the TE bit is  
tRTN  
tRTN  
cleared to zero, /INT  
remains low during the  
tRTN time.  
tRTN  
(8)  
∗
Even when the TF  
" 1 "  
" 0 "  
(4)  
bit is cleared to zero,  
the /INT status does  
not change.  
(3)  
TF bit  
period  
period  
period  
period  
(2)  
• • • 001 h → 000 h  
(1)  
Event occurs  
(7)  
∗ When the TE bit value changes from "0" to "1" the fixed-cycle timer function starts.  
The counter always starts counting down from the preset value when the TE value changes from "0" to "1".  
RTC internal operation  
Write operation  
(1) When a "1" is written to the TE bit, the fixed-cycle timer countdown starts from the preset value.  
(2) A fixed-cycle timer interrupt event starts a countdown based on the countdown period (source clock). When  
the count value changes from 001h to 000h, an interrupt event occurs.  
∗ After the interrupt event that occurs when the count value changes from 001h to 000h, the counter  
automatically reloads the preset value and again starts to count down. (Repeated operation)  
(3) When a fixed-cycle timer interrupt event occurs, "1" is written to the TF bit.  
(4) When the TF bit = "1" its value is retained until it is cleared to zero.  
(5) If the TIE bit = "1" when a fixed-cycle timer interrupt occurs, /INT pin output goes low.  
∗ If the TIE bit = "0" when a fixed-cycle timer interrupt occurs, /INT pin output remains Hi-Z.  
(6) Output from the /INT pin remains low during the tRTN period following each event, after which it is  
automatically cleared to Hi-Z status.  
∗ /INT is again set low when the next interrupt event occurs.  
(7) When a "0" is written to the TE bit, the fixed-cycle timer function is stopped and the /INT pin is set to Hi-Z  
status.  
∗ When /INT = low, the fixed-cycle timer function is stopped. The tRTN period is the maximum amount of time  
before the /INT pin status changes from low to Hi-Z.  
(8) As long as /INT = low, the /INT pin status does not change when the TF bit value changes from "1" to "0".  
(9) When /INT = low, the /INT pin status changes from low to Hi-Z as soon as the TIE bit value changes from "1" to  
"0".  
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8.3.2. Related registers for function of time update interrupts.  
Address  
Function  
bit 7  
bit 6  
bit 5  
bit 4  
bit 3  
bit 2  
bit 1  
bit 0  
B
C
D
E
F
Timer Counter 0  
Timer Counter 1  
Extension Register  
Flag Register  
128  
•
64  
•
32  
•
16  
•
TE  
TF  
TIE  
8
2048  
¡
4
2
512  
1
256  
1024  
¡
¡
¡
TEST  
WADA  
USEL  
TSEL1 TSEL0  
VLF  
¡
¡
¡
UF  
AF  
¡
¡
UIE  
AIE  
STOP  
RESET  
Control Register  
∗1) "o" indicates write-protected bits. A zero is always read from these bits.  
∗2) Bits marked with "•" are RAM bits that can contain any value and are read/write-accessible.  
∗ Before entering settings for operations, we recommend writing a "0" to the TE and TIE bits to prevent hardware  
interrupts from occurring inadvertently while entering settings.  
∗ When the STOP bit or RESET bit value is "1" the time update interrupt function operates only partially.  
(Operation continues if the source clock setting is 4096 Hz. Otherwise, operation is stopped.)  
∗ When the fixed-cycle timer interrupt function is not being used, the fixed-cycle timer control register (Reg – B to  
C) can be used as a RAM register. In such cases, stop the fixed-cycle timer function by writing "0" to the TE and  
TIE bits.  
1) TSEL0,1 bits (Timer Select 0, 1)  
The combination of these two bits is used to set the countdown period (source clock) for the fixed-cycle timer  
interrupt function (four settings can be made).  
TSEL1 TSEL0  
(bit 1) (bit 0)  
Auto reset time Effects of STOP  
TSEL0,1  
Source clock  
tRTN  
and RESET bits  
0
0
1
1
0
1
0
1
4096 Hz /Once per 244.14 µs  
64 Hz / Once per 15.625 ms  
"Second" update /Once per second  
"Minute" update /Once per minute  
122 µs  
7.8125 ms ∗ Does not operate  
7.8125 ms  
7.8125 ms  
−
Write/Read  
when the STOP bit  
or RESET bit value  
is "1".  
∗1) The /INT pin's auto reset time (tRTN) varies as shown above according to the source clock setting.  
∗2) When the source clock has been set to "second update" or "minute update", the timing of both  
countdown and interrupts is coordinated with the clock update timing.  
2) Fixed-cycle Timer Control register (Reg - B ∼ C)  
This register is used to set the default (preset) value for the counter. Any count value from 1 (001 h) to  
4095 (FFFh) can be set. The counter counts down based on the source clock's period, and when the count value  
changes from 001h to 000h, the TF bit value becomes "1".  
The countdown that starts when the TE bit value changes from "0" to "1" always begins from the preset value.  
Be sure to write "0" to the TE bit before writing the preset value. If a value is written while TE = "1" the first  
subsequent event will not be generated correctly.  
Address C  
Address B  
Timer Counter 1  
Timer Counter 0  
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0  
2048 1024 512 256 128 64 32 16  
8
4
2
1
•
•
•
•
3) TE (Timer Enable) bit  
This bit controls the start/stop setting for the fixed-cycle timer interrupt function.  
TE  
Data  
Description  
Stops fixed-cycle timer interrupt function.  
Starts fixed-cycle timer interrupt function.  
0
Write/Read  
1
∗ The countdown that starts when the TE bit value changes from "0" to "1" always begins from the  
preset value.  
4) TF (Timer Flag) bit  
If set to "0" beforehand, this flag bit's value changes from "0" to 1" when a fixed-cycle timer interrupt event has  
occurred. Once this flag bit's value is "1", its value is retained until a "0" is written to it.  
TF  
Data  
Description  
The TF bit is cleared to zero to prepare for the next status detection  
∗ Clearing this bit to zero does not enable the /INT low output status to be cleared (to Hi-Z).  
0
Write  
1
0
This bit is invalid after a "1" has been written to it.  
Fixed-cycle timer interrupt events are not detected.  
Read  
Fixed-cycle timer interrupt events are detected.  
(Result is retained until this bit is cleared to zero.)  
1
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5) TIE (Timer Interrupt Enable) bit  
When a fixed-cycle timer interrupt event occurs (when the TF bit value changes from "0" to "1"), this bit's value  
specifies whether an interrupt signal is generated (/INT status changes from Hi-Z to low) or is not generated  
(/INT status remains Hi-Z).  
TIE  
Data  
Description  
1) When a fixed-cycle timer interrupt event occurs, an interrupt signal is not  
generated or is canceled (/INT status remains Hi-Z).  
2) When a fixed-cycle timer interrupt event occurs, the interrupt signal is  
canceled (/INT status changes from low to Hi-Z).  
0
∗ Even when the TIE bit value is "0" another interrupt event may change the /INT status to low (or  
may hold /INT = "L").  
Write/Read  
When a fixed-cycle timer interrupt event occurs, an interrupt signal is  
generated (/INT status changes from Hi-Z to low).  
∗ When a fixed-cycle timer interrupt event has been generated low-level output from the /INT pin  
occurs only when the value of the control register's TIE bit is "1". Up to 7.8 ms after the interrupt  
occurs, the /INT status is automatically cleared (/INT status changes from low to Hi-Z).  
1
8.3.3. Fixed-cycle timer interrupt interval (example)  
Timer  
Source clock  
"Second"  
update  
"Minute"  
update  
Counter  
setting  
4096 Hz  
64 Hz  
TSEL1,0 = 0,0  
TSEL1,0 = 0,1  
TSEL1,0 = 1,0  
TSEL1,0 = 1,1  
0
1
2
−
−
−
1 s  
2 s  
−
15.625 ms  
31.25 ms  
1 min  
2 min  
244.14 µs  
488.28 µs  
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
41  
205  
410  
10.010 ms  
50.049 ms  
100.10 ms  
500.00 ms  
640.63 ms  
3.203 s  
6.406 s  
41 s  
205 s  
410 s  
41 min  
205 min  
410 min  
2048 min  
2048  
32.000 s  
2048 s  
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
4095  
0.9998 s  
63.984 s  
4095 s  
4095 min  
• Time error in fixed-cycle timer  
A time error in the fixed-cycle timer will produce a positive or negative time period error in the selected  
source clock. The fixed-cycle timer's time is within the following range relative to the time setting.  
(Fixed-cycle timer's time setting (∗) − source clock period) to (timer's time setting)  
∗) The timer's time setting = source clock period × timer counter's division value.  
∗ The time actually set to the timer is adjusted by adding the time described above to the  
communication time for the serial data transfer clock used for the setting.  
8.3.4. Fixed-cycle timer start timing  
Counting down of the fixed-cycle timer value starts at the rising edge of the SCL signal that occurs when the TE  
value is changed from "0" to "1" (after bit 0 is transferred).  
Address D  
SCL pin  
TSEL1 TSEL0 ACK  
TE  
0
0
SDA pin  
Internal timer  
/INT pin  
Operation of timer  
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8.4. Time Update Interrupt Function  
The time update interrupt function generates interrupt events at one-second or one-minute intervals, according to  
the timing of the internal clock.  
When an interrupt event occurs, the UF bit value becomes "1" and the /INT pin goes to low level to indicate that  
an event has occurred. (However, when a fixed-cycle timer interrupt event has been generated, low-level output  
from the /INT pin occurs only when the value of the control register's UIE bit is "1". This /INT status is  
automatically cleared (/INT status changes from low level to Hi-Z) 7.8 ms (fixed value) after the interrupt occurs.  
∗ /INT operation  
example  
7.8ms  
period  
UIE = " 1 "  
UIE = " 1 " → " 0 "  
8.4.1. Time update interrupt function diagram  
(7)  
" 1 "  
" 1 "  
" 0 "  
(4)  
UIE bit  
Hi - z  
" L "  
/INT output  
(5)  
tRTN  
tRTN  
tRTN  
tRTN  
(6)  
∗ /INT status does not  
change when UF bit is  
cleared to zero.  
" 1 "  
" 0 "  
(3)  
(2)  
UF bit  
period  
period  
period  
period  
(1)  
Events  
Operation in RTC  
Write operation  
(1) A time update interrupt event occurs when the internal clock's value matches either the second update time or  
the minute update time. The USEL bit's specification determines whether it is the second update time or the  
minute update time that must be matched.  
(2) When a time update interrupt event occurs, the UF bit value becomes "1".  
(3) When the UF bit value is "1" its value is retained until it is cleared to zero.  
(4) When a time update interrupt occurs, /INT pin output is low if UIE = "1".  
∗ If UIE = "0" when a timer update interrupt occurs, the /INT pin status remains Hi-Z.  
(5) Each time an event occurs, /INT pin output is low only up to the tRTN time (which is fixed as 7.1825 ms for  
time update interrupts) after which it is automatically cleared to Hi-Z.  
∗ /INT pin output goes low again when the next interrupt event occurs.  
(6) As long as /INT = low, the /INT pin status does not change, even if the UF bit value changes from "1" to "0".  
(7) When /INT = low, the /INT pin status changes from low to Hi-Z as soon as the UIE bit value changes from "1"  
to "0".  
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8.4.2. Related registers for time update interrupt functions.  
Address  
Function  
bit 7  
bit 6  
bit 5  
bit 4  
bit 3  
¡
bit 2  
bit 1  
bit 0  
¡
¡
¡
TEST  
WADA  
TE  
TF  
TSEL1  
VLF  
TSEL0  
D
E
F
Extension Register  
Flag Register  
Control Register  
USEL  
UF  
UIE  
¡
¡
¡
AF  
¡
¡
TIE  
AIE  
STOP  
RESET  
∗) "o" indicates write-protected bits. A zero is always read from these bits.  
∗ Before entering settings for operations, we recommend writing a "0" to the UIE bit to prevent hardware interrupts  
from occurring inadvertently while entering settings.  
∗ When the STOP bit or RESET bit value is "1" time update interrupt events do not occur.  
∗ Although the time update interrupt function cannot be fully stopped, if "0" is written to the UIE bit, the time update  
interrupt function can be prevented from changing the /INT pin status to low.  
1) USEL (Update Interrupt Select) bit  
This bit is used to select "second" update or "minute" update as the timing for generation of time update interrupt  
events.  
USEL  
Data  
Description  
Selects "second update" (once per second) as the timing for generation of  
interrupt events  
0
Write/Read  
Selects "minute update" (once per minute) as the timing for generation of  
interrupt events  
1
2) UF (Update Flag) bit  
Once it has been set to "0", this flag bit value changes from "0" to "1" when a time update interrupt event occurs.  
When this flag bit = "1" its value is retained until a "0" is written to it.  
UF  
Data  
Description  
The UF bit is cleared to zero to prepare for the next status detection  
∗ Clearing this bit to zero does not enable the /INT low output status to be cleared (to Hi-Z).  
0
Write  
1
0
This bit is invalid after a "1" has been written to it.  
Time update interrupt events are not detected.  
Read  
Time update interrupt events are detected.  
(The result is retained until this bit is cleared to zero.)  
1
3) UIE (Update Interrupt Enable) bit  
When a time update interrupt event occurs (UF bit value changes from "0" to "1"), this bit selects whether to  
generate an interrupt signal (/INT status changes from Hi-Z to low) or to not generate it (/INT status remains  
Hi-Z).  
UIE  
Data  
Description  
1) Does not generate an interrupt signal when a time update interrupt event  
occurs (/INT remains Hi-Z)  
2) Cancels interrupt signal triggered by time update interrupt event (/INT  
changes from low to Hi-Z).  
0
∗ Even when the UIE bit value is "0" another interrupt event may change the /INT status to low (or  
may hold /INT = "L").  
Write/Read  
When a time update interrupt event occurs, an interrupt signal is generated  
(/INT status changes from Hi-Z to low).  
∗ When a time update interrupt event occurs, low-level output from the /INT pin occurs only when  
the UIE bit value is "1". Up to 7.8 ms after the interrupt occurs, the /INT status is automatically  
cleared (/INT status changes from low to Hi-Z).  
1
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8.5. Alarm Interrupt Function  
The alarm interrupt generation function generates interrupt events for alarm settings such as date, day, hour, and  
minute settings.  
When an interrupt event occurs, the AF bit value is set to "1" and the /INT pin goes to low level to indicate that an  
event has occurred.  
∗ Example of  
/INT operation  
AIE = " 1 "  
( AF = " 0 " → " 1 " )  
AF = " 1 " → " 0 " or  
AIE = " 1 " → " 0 "  
8.4.1. Diagram of alarm interrupt function  
" 1 "  
" 1 "  
" 0 "  
(4)  
AIE bit  
(5)  
Hi - z  
" L "  
(7)  
/INT output  
AF bit  
(6)  
" 1 "  
" 0 "  
(3)  
(2)  
(1)  
Event  
occurs  
RTC internal operation  
Write operation  
(1) The hour, minute, date or day when an alarm interrupt event is to occur is set in advance along with the  
WADA bit, and when the setting matches the current time an interrupt event occurs.  
(Note) Even if the current date/time is used as the setting, the alarm will not occur until the counter counts up  
to the current date/time (i.e., an alarm will occur next time, not immediately).  
(2) When a time update interrupt event occurs, the AF bit values becomes "1".  
(3) When the AF bit = "1", its value is retained until it is cleared to zero.  
(4) If AIE = "1" when an alarm interrupt occurs, the /INT pin output goes low.  
∗ When an alarm interrupt event occurs, /INT pin output goes low, and this status is then held until it is  
cleared via the AF bit or AIE bit.  
(5) If the AIE value is changed from "1" to "0" while /INT is low, the /INT status immediately changes from low to  
Hi-Z. After the alarm interrupt occurs and before the AF bit value is cleared to zero, the /INT status can be  
controlled via the AIE bit.  
(6) If the AF bit value is changed from "1" to "0" while /INT is low, the /INT status immediately changes from low  
to Hi-Z.  
(7) If the AIE bit value is "0" when an alarm interrupt occurs, the /INT pin status remains Hi-Z.  
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8.5.2. Related registers  
Address  
Function  
bit 7  
bit 6  
bit 5  
bit 4  
bit 3  
bit 2  
bit 1  
bit 0  
¡
¡
¡
¡
1
2
3
4
MIN  
HOUR  
WEEK  
DAY  
40  
¡
20  
20  
5
10  
10  
4
8
8
3
8
4
4
2
4
2
2
1
2
1
1
0
1
6
¡
20  
10  
8
9
MIN Alarm  
HOUR Alarm  
WEEK Alarm  
DAY Alarm  
AE  
AE  
40  
•
20  
20  
5
20  
USEL  
10  
10  
4
10  
TE  
TF  
TIE  
8
4
2
2
1
1
1
0
1
8
3
8
¡
4
2
4
¡
6
A
AE  
2
•
WADA  
¡
TEST  
TSEL1  
VLF  
STOP  
TSEL0  
D
E
F
Extension Register  
Flag Register  
Control Register  
¡
¡
¡
UF  
AF  
AIE  
¡
¡
¡
UIE  
RESET  
∗1) "o" indicates write-protected bits. A zero is always read from these bits.  
∗2) Bits marked with "•" are RAM bits that can contain any value and are read/write-accessible.  
∗ Before entering settings for operations, we recommend writing a "0" to the AIE bit to prevent hardware interrupts  
from occurring inadvertently while entering settings.  
∗ When the STOP bit or RESET bit value is "1" alarm interrupt events do not occur.  
∗ When the alarm interrupt function is not being used, the Alarm registers (Reg - 8 to A) can be used as a RAM  
register. In such cases, be sure to write "0" to the AIE bit.  
∗ When the AIE bit value is "1" and the Alarm registers (Reg - 8 to A) is being used as a RAM register, /INT may be  
changed to low level unintentionally.  
1) WADA (Week Alarm /Day Alarm) bit  
The alarm interrupt function uses either "Day" or "Week" as its target. The WADA bit is used to specify either  
WEEK or DAY as the target for alarm interrupt events.  
WADA  
Data  
Description  
Sets WEEK as target of alarm function  
(DAY setting is ignored)  
0
Write/Read  
Sets DAY as target of alarm function  
(WEEK setting is ignored)  
1
2) Alarm registers (Reg - 8 to A)  
Address  
8
Function  
bit 7  
bit 6  
bit 5  
bit 4  
bit 3  
bit 2  
bit 1  
bit 0  
MIN Alarm  
AE  
AE  
40  
•
6
20  
20  
5
10  
10  
4
8
8
3
8
4
4
2
4
2
2
1
2
1
1
0
1
9
HOUR Alarm  
WEEK Alarm  
DAY Alarm  
A
AE  
20  
10  
•
The hour, minute, date or day when an alarm interrupt event will occur is set using this register and the  
WADA bit.  
In the WEEK alarm /Day alarm register (Reg - A), the setting selected via the WADA bit determines whether  
WEEK alarm data or DAY alarm data will be set. If WEEK has been selected via the WADA bit, multiple  
days can be set (such as Monday, Wednesday, Friday, Saturday).  
When the settings made in the alarm registers and the WADA bit match the current time, the AF bit value is  
changed to "1". At that time, if the AIE bit value has already been set to "1", the /INT pin goes low.  
∗1) The register that "1" was set to "AE" bit, doesn't compare alarm.  
(Example) Write 80h (AE = "1") to the WEEK Alarm /DAY Alarm register (Reg - A):  
Only the hour and minute settings are used as alarm comparison targets. The week and date settings  
are not used as alarm comparison targets.  
As a result, alarm occurs if only an hour and minute accords with alarm data.  
∗2) If all three AE bit values are "1" the week/date settings are ignored and an alarm interrupt event will  
occur once per minute.  
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3) AF (Alarm Flag) bit  
When this flag bit value is already set to "0", occurrence of an alarm interrupt event changes it to "1". When this  
flag bit value is "1", its value is retained until a "0" is written to it.  
AF  
Data  
Description  
The AF bit is cleared to zero to prepare for the next status detection  
0
∗ Clearing this bit to zero enables /INT low output to be canceled (/INT remains Hi-Z) when an alarm  
Write  
interrupt event has occurred.  
1
0
This bit is invalid after a "1" has been written to it.  
Alarm interrupt events are not detected.  
Read  
Alarm interrupt events are detected.  
(Result is retained until this bit is cleared to zero.)  
1
4) AIE (Alarm Interrupt Enable) bit  
When an alarm interrupt event occurs (when the AF bit value changes from "0" to "1"), this bit's value specifies  
whether an interrupt signal is generated (/INT status changes from Hi-Z to low) or is not generated (/INT status  
remains Hi-Z).  
AIE  
Data  
Description  
1) When an alarm interrupt event occurs, an interrupt signal is not  
generated or is canceled (/INT status remains Hi-Z).  
2) When an alarm interrupt event occurs, the interrupt signal is canceled  
(/INT status changes from low to Hi-Z).  
0
∗ Even when the AIE bit value is "0" another interrupt event may change the /INT status to low  
(or may hold /INT = "L").  
Write/Read  
When an alarm interrupt event occurs, an interrupt signal is generated (/INT  
status changes from Hi-Z to low).  
1
∗
When an alarm interrupt event occurs, low-level output from the /INT pin occurs only when the  
AIE bit value is "1". This value is retained (not automatically cleared) until the AF bit is cleared  
to zero.  
8.5.2. Examples of alarm settings  
1) Example of alarm settings when "Day" has been specified (and WADA bit = "0")  
Reg – A  
Reg - 9  
Reg - 8  
Day is specified  
bit bit bit bit bit bit bit bit  
HOUR  
Alarm  
MIN  
Alarm  
7
6
5
4
3
2
1
0
WADA bit = "0"  
AE S  
F
T
W
T
M
S
Monday through Friday, at 7:00 AM  
∗ Minute value is ignored  
0
0
0
1
1
0
1
0
1
0
1
0
1
0
0
1
07 h  
80 h ∼ FF h  
Every Saturday and Sunday, for 30 minutes  
each hour ∗ Hour value is ignored  
30 h  
80 h ∼ FF h  
0
1
1
1
1
1
1
1
1
Every day, at 6:59 AM  
18 h  
59 h  
Χ
Χ
Χ
Χ
Χ
Χ
Χ
Χ: Don't care  
2) Example of alarm settings when "Day" has been specified (and WADA bit = "1")  
Reg - A  
Reg - 9  
Reg - 8  
Day is specified  
bit  
6
bit  
7
bit bit bit bit bit bit  
HOUR  
Alarm  
MIN  
Alarm  
5
4
3
2
1
0
WADA bit = "1"  
AE  
20 10 08 04 02 01  
•
First of each month, at 7:00 AM  
∗ Minute value is ignored  
15th of each month, for 30 minutes each  
hour ∗ Hour value is ignored  
0
0
0
0
0
1
0
0
0
1
0
0
1
1
07 h  
80 h ∼ FF h  
0
1
0
30 h  
80 h ∼ FF h  
Every day, at 6:59 PM  
18 h  
59 h  
Χ
Χ
Χ
Χ
Χ
Χ
Χ
Χ: Don't care  
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2
8.6. Reading/Writing Data via the I C Bus Interface  
8.6.1. Overview of I2C-BUS  
The I2C bus supports bi-directional communications via two signal lines: the SDA (data) line and SCL (clock) line. A  
combination of these two signals is used to transmit and receive communication start/stop signals, data transfer  
signals, acknowledge signals, and so on.  
Both the SCL and SDA signals are held at high level whenever communications are not being performed.  
The starting and stopping of communications is controlled at the rising edge or falling edge of SDA while SCL is at  
high level.  
During data transfers, data changes that occur on the SDA line are performed while the SCL line is at low level, and  
on the receiving side the data is output while the SCL line is at high level.  
The I2C bus device does not include a chip select pin such as is found in ordinary logic devices. Instead of using a  
chip select pin, slave addresses are allocated to each device and the receiving device responds to communications  
only when its slave address matches the slave address in the received data. In either case, the data is transferred  
via the SCL line at a rate of one bit per clock pulse.  
8.6.2. System configuration  
All ports connected to the I2C bus must be either open drain or open collector ports in order to enable AND  
connections to multiple devices.  
SCL and SDA are both connected to the VDD line via a pull-up resistance. Consequently, SCL and SDA are both  
held at high level when the bus is released (when communication is not being performed).  
V
DD  
SDA  
SCL  
Master  
Slave  
Master  
Slave  
Transmitter/  
Receiver  
Transmitter/  
Receiver  
Transmitter/  
Receiver  
Transmitter/  
Receiver  
Other I2C bus device  
CPU, etc.  
RX - 8581  
Any device that controls the data transmission and data reception is defined as a "Master".  
and any device that is controlled by a master device is defined as a “Slave”.  
The device transmitting data is defined as a “Transmitter” and the device receiving data is defined as a receiver”  
In the case of this RTC module, controllers such as a CPU are defined as master devices and the RTC module is  
defined as a slave device. When a device is used for both transmitting and receiving data, it is defined as either a  
transmitter or receiver depending on these conditions.  
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8.6.3. Starting and stopping I2C bus communications  
START  
condition  
Repeated START(RESTART)  
condition  
STOP  
condition  
SCL  
SDA  
[ S ]  
[ Sr ]  
[ P ]  
0.95 s ( Max. )  
1) START condition, repeated START condition, and STOP condition  
(1) START condition  
•
The SDA level changes from high to low while SCL is at high level.  
(2) STOP condition  
2
• This condition regulates how communications on the I C-BUS are terminated.  
The SDA level changes from low to high while SCL is at high level.  
(3) Repeated START condition (RESTART condition)  
• In some cases, the START condition occurs between a previous START condition and the next  
STOP condition, in which case the second START condition is distinguished as a RESTART  
condition. Since the required status is the same as for the START condition, the SDA level changes  
from high to low while SCL is at high level.  
2) Caution points  
∗1) The master device always controls the START, RESTART, and STOP conditions for communications.  
∗2) The master device does not impose any restrictions on the timing by which STOP conditions affect  
transmissions, so communications can be forcibly stopped at any time while in progress. (However,  
this is only when this RTC module is in receiver mode (data reception mode = SDA released).  
∗3) When communicating with this RTC module, the series of operations from transmitting the START  
condition to transmitting the STOP condition should occur within 0.95 seconds. (A RESTART  
condition may be sent between a START condition and STOP condition, but even in such cases the  
series of operations from transmitting the START condition to transmitting the STOP condition should  
still occur within 0.95 seconds.)  
If this series of operations requires 0.95 seconds or longer, the I2C bus interface will be automatically  
cleared and set to standby mode by this RTC module's bus timeout function. Note with caution that  
both write and read operations are invalid for communications that occur during or after this auto  
clearing operation. (When the read operation is invalid, all data that is read has a value of "1").  
Restarting of communications begins with transfer of the START condition again  
∗4) When communicating with this RTC module, wait at least 1.3 µs (see the tBUF rule) between  
transferring a STOP condition (to stop communications) and transferring the next START condition (to  
start the next round of communications).  
STOP  
condition  
START  
condition  
SCL  
SDA  
[ P ]  
[ S ]  
61 µs (Min.)  
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8.6.4. Data transfers and acknowledge responses during I2C-BUS communications  
1) Data transfers  
Data transfers are performed in 8-bit (1 byte) units once the START condition has occurred. There is no limit  
on the amount (bytes) of data that are transferred between the START condition and STOP condition.  
(However, the transfer time must be no longer than 0.95 seconds.)  
The address auto increment function operates during both write and read operations.  
After address Fh, incrementation goes to address 0h.  
Updating of data on the transmitter (transmitting side)'s SDA line is performed while the SCL line is at low  
level. The receiver (receiving side) receives data while the SCL line is at high level.  
SCL  
SDA  
Data is valid  
Data can be  
when data line is  
changed  
stable  
∗ Note with caution that if the SDA data is changed while the SCL line is at high level, it will be treated as a  
START, RESTART, or STOP condition.  
2) Data acknowledge response (ACK signal)  
When transferring data, the receiver generates a confirmation response (ACK signal, low active) each time an  
8-bit data segment is received. If there is no ACK signal from the receiver, it indicates that normal  
communication has not been established. (This does not include instances where the master device intentionally  
does not generate an ACK signal.)  
Immediately after the falling edge of the clock pulse corresponding to the 8th bit of data on the SCL line, the  
transmitter releases the SDA line and the receiver sets the SDA line to low (= acknowledge) level.  
SCL from Master  
1
2
8
9
SDA from transmitter (sending  
side)  
Release SDA  
SDA from receiver (receiving  
side)  
Low active  
ACK signal  
After transmitting the ACK signal, if the Master remains the receiver for transfer of the next byte, the SDA is  
released at the falling edge of the clock corresponding to the 9th bit of data on the SCL line. Data transfer  
resumes when the Master becomes the transmitter.  
When the Master is the receiver, if the Master does not send an ACK signal in response to the last byte sent  
from the slave, that indicates to the transmitter that data transfer has ended. At that point, the transmitter  
continues to release the SDA and awaits a STOP condition from the Master.  
8.6.5. Slave address  
The I2C bus device does not include a chip select pin such as is found in ordinary logic devices. Instead of using a  
chip select pin, slave addresses are allocated to each device.  
All communications begin with transmitting the [START condition] + [slave address (+ R/W specification)]. The  
receiving device responds to this communication only when the specified slave address it has received matches its  
own slave address.  
Slave addresses have a fixed length of 7 bits. This RTC's slave address is [1010 001∗].  
An R/W bit ("*" above) is added to each 7-bit slave address during 8-bit transfers.  
Slave address  
R/W bit  
Transfer data  
bit 7  
bit 6  
bit 5  
bit 4  
bit 3  
bit 2  
bit 1  
bit 0  
Read  
Write  
A3 h  
A2 h  
1 (= Read)  
0 (= Write)  
1
0
1
0
0
0
1
Page - 23  
MQ - 372 - 01  
RX - 8581 SA/ JE / NB  
8.6.6. I2C bus protocol  
In the following sequence descriptions, it is assumed that the CPU is the master and the RX-8581 is the slave.  
a. Address specification write sequence  
Since the RX-8581 includes an address auto increment function, once the initial address has been specified,  
the RX-8581 increments (by one byte) the receive address each time data is transferred.  
(1) CPU transfers start condition [S].  
(2) CPU transmits the RX-8581's slave address with the R/W bit set to write mode.  
(3) Check for ACK signal from RX-8581.  
(4) CPU transmits write address to RX-8581.  
(5) Check for ACK signal from RX-8581.  
(6) CPU transfers write data to the address specified at (4) above.  
(7) Check for ACK signal from RX-8581.  
(8) Repeat (6) and (7) if necessary. Addresses are automatically incremented.  
(9) CPU transfers stop condition [P].  
(1)  
S
(2)  
(3)  
0
(4)  
(5)  
0
(6)  
(7)  
0
(8)  
(9)  
P
Slave address  
0
Address  
Data  
Data  
0
R/W  
ACK signal from RX-8581  
b. Address specification read sequence  
After using write mode to write the address to be read, set read mode to read the actual data.  
(1) CPU transfers start condition [S].  
(2) CPU transmits the RX-8581's slave address with the R/W bit set to write mode.  
(3) Check for ACK signal from RX-8581.  
(4) CPU transfers address for reading from 8581.  
(5) Check for ACK signal from RX-8581.  
(6) CPU transfers RESTART condition [Sr] (in which case, CPU does not transfer a STOP condition [P]).  
(7) CPU transfers RX-8581's slave address with the R/W bit set to read mode.  
(8) Check for ACK signal from RX-8581 (from this point on, the CPU is the receiver and the RX-8581 is  
the transmitter).  
(9) Data from address specified at (4) above is output by the RX-8581.  
(10) CPU transfers ACK signal to RX-8581.  
(11) Repeat (9) and (10) if necessary. Read addresses are automatically incremented.  
(12) CPU transfers ACK signal for "1".  
(13) CPU transfers stop condition [P].  
(1)  
S
(2)  
(3)  
0
(4)  
(5) (6)  
Sr  
(7)  
(8)  
0
(9)  
(10)  
0
(11)  
(12) (13)  
Slave address  
0
Address  
0
Slave address  
1
Data  
Data  
1
P
R/W  
R/W  
ACK from RX-8581  
ACK from CPU  
c. Read sequence when address is not specified  
Once read mode has been initially set, data can be read immediately. In such cases, the address for each read  
operation is the previously accessed address + 1.  
(1) CPU transfers start condition [S].  
(2) CPU transmits the RX-8581's slave address with the R/W bit set to read mode.  
(3) Check for ACK signal from RX-8581 (from this point on, the CPU is the receiver and the RX-8581 is the  
transmitter).  
(4) Data is output from the RX-8581 to the address following the end of the previously accessed address.  
(5) CPU transfers ACK signal to RX-8581.  
(6) Repeat (4) and (5) if necessary. Read addresses are automatically incremented in the RX-8581.  
(7) CPU transfers ACK signal for "1".  
(8) CPU transfers stop condition [P].  
(1)  
S
(2)  
(3)  
0
(4)  
(5)  
0
(6)  
(7) (8)  
Slave address  
1
Data  
Data  
1
P
R/W  
ACK from RX-8581  
ACK from CPU  
Page - 24  
MQ - 372 - 01  
RX - 8581 SA/ JE / NB  
8.7. Backup and Recovery  
VDD  
VCLK  
0 V  
tR1  
tF  
tR2  
Back up  
Item  
Symbol  
t F  
Min.  
Typ.  
Max.  
Power supply drop time  
Initial power-up time  
2 µs /V  
1 µs /V  
1 µs /V  
t R1  
10 ms /V  
Clock maintenance power-up time  
t R2  
8.8. Connection with Typical Microcontroller  
VDD  
SCL  
SDA  
I2C-BUS  
master  
VDD  
SCL  
RX - 8581  
SLAVE ADRS = 1010 001∗  
SDA  
GND  
Pull up resistor  
t
r
R =  
C
BUS  
VDD  
SCL  
SDA  
I2C-BUS  
Device  
GND  
Page - 25  
MQ - 372 - 01  
RX - 8581 SA/ JE / NB  
9. External Dimensions / Marking Layout  
RX-8581 SA (SOP - 14 pin)  
• External dimensions  
• Recommended soldering  
10.1 0.2  
0° - 10°  
#14  
#8  
1.4  
R8581  
5.4  
1.4  
E 1234A  
0.6  
#1  
#7  
0.15  
3.2 0.1  
0.05  
Min.  
1.27  
0.7  
1.27 × 6 = 7.62  
0.35  
1.27 1.2  
Unit : mm  
∗ The crystal oscillator's metal case may be visible in the area (on top) indicated in broken lines  
but this has no effect on the device's characteristics.  
,
RX-8581 JE (VSOJ - 20 pin)  
• External dimensions  
• Recommended soldering  
(0.75)  
7.0 0.3  
#20  
#11  
1.5  
R8581  
3.8  
5.4  
0.35  
0.65  
0.3  
E
1234A  
1.5  
# 1  
#10  
(0.75)  
0.65 × 9 = 5.85  
1.3  
0 Min.  
1.5 Max.  
0.22  
0.65  
Unit : mm  
0.12  
0.1  
∗ The crystal oscillator's metal case may be visible in the area (on front and top) indicated in broken lines  
but this has no effect on the device's characteristics.  
,
RX-8581 NB (SON - 22 pin)  
• External dimensions  
• Soldering pattern  
6.3 Max.  
0.25 0.75  
#14  
#22  
#14  
#22  
#22  
0.7  
#14  
R8564  
E 1234A  
0.25 0.5  
#1  
# 11  
0.7  
#1  
#11  
#11  
#1  
P 0.5 × 10 = 5.0  
5.25  
0.2  
0.5  
0.1  
Unit : mm  
∗1)  
The crystal oscillator's metal case may be visible in the area (on front and top) indicated in broken lines  
,
but this has no effect on the device's characteristics.  
∗2)  
Do not lay out signal patterns on component surfaces indicated by the shaded areas  
in the soldering  
diagram .  
Page - 26  
MQ - 372 - 01  
RX - 8581 SA/ JE / NB  
10. Reference Data  
(1) Example of frequency and temperature characteristics  
[Finding the frequency stability]  
θT = +25 C Typ.  
°
10-6  
= -0.035 10-6 Typ.  
×
α
×
1. Frequency and temperature characteristics can be  
approximated using the following equations.  
∆fT = α (θT - θX)2  
0
: Frequency deviation in any  
temperature  
∆fT  
-50  
-100  
-150  
α
(1 / °C2)  
: Coefficient of secondary temperature  
(−0.035 0.005) × 10-6 / °C2  
: Ultimate temperature (+25 5 °C)  
: Any temperature  
θT (°C)  
θX (°C)  
-50  
0
+50  
+100  
2. To determine overall clock accuracy, add the frequency  
precision and voltage characteristics.  
Temperature [ C]  
°
∆f/f = ∆f/fo + ∆fT + ∆fV  
: Clock accuracy (stable frequency) in any  
temperature and voltage  
: Frequency precision  
: Frequency deviation in any temperature  
: Frequency deviation in any voltage  
∆f/f  
(2) Example of frequency and voltage characteristics  
Condition :  
∆f/fo  
∆fT  
∆fV  
3 V as reference, Ta=+25 °C  
+ 3  
0
3. How to find the date difference  
Date difference = ∆f/f × 86400 (seconds)  
* For example: ∆f/f = 11.574 × 10-6 is an error of  
approximately 1 second/day.  
- 3  
2
3
4
5
DD  
Supply Voltage V [V]  
(3) Current and voltage consumption characteristics  
(3-1) Current consumption when non-accessed (i)  
when FOUT=OFF  
(3-2) Current consumption when non-accessed (ii)  
when FOUT=32.768 kHz  
Condition :  
Condition :  
Ta = +25 °C  
fSCL = 0 Hz  
Ta = +25 °C  
fSCL = 0 Hz  
1.0  
10  
DD  
FOE, /INT = V  
DD  
FOE = GND, /INT = V  
FOUT ; 32.768 kHz output ON  
FOUT ; Output OFF  
CL=30 pF  
0.5  
5
CL=0 pF  
2
3
4
5
2
3
4
5
DD  
DD  
Supply Voltage V [V]  
Supply Voltage V [V]  
Page - 27  
MQ - 372 - 01  
Application Manual  
Distributor  
AMERICA  
EPSON ELECTRONICS AMERICA, INC.  
HEADQUARTER  
150 River Oaks Parkway, San Jose, CA 95134, U.S.A.  
Phone: (1)800-228-3964 (Toll free) : (1)408-922-0200 (Main) Fax: (1)408-922-0238  
http://www.eea.epson.com  
Atlanta Office  
3010 Royal Blvd. South, Ste. 170, Alpharetta, GA 30005, U.S.A.  
Phone: (1)877-332-0020 (Toll free) : (1)770-777-2078 (Main) Fax: (1)770-777-2637  
Boston Office  
Chicago Office  
El Segundo Office  
301Edgewater Place, Ste. 120, Wakefield, MA 01880, U.S.A.  
Phone: (1)800-922-7667 (Toll free) : (1)781-246-3600 (Main) Fax: (1)781-246-5443  
101 Virginia St., Ste. 290, Crystal Lake, IL 60014, U.S.A.  
Phone: (1)800-853-3588 (Toll free) : (1)815-455-7630 (Main) Fax: (1)815-455-7633  
1960 E. Grand Ave., 2nd Floor, El Segundo, CA 90245, U.S.A.  
Phone: (1)800-249-7730 (Toll free) : (1)310-955-5300 (Main) Fax: (1)310-955-5400  
EUROPE  
EPSON EUROPE ELECTRONICS GmbH  
HEADQUARTER  
Riesstrasse 15, 80992 Munich, Germany  
Phone: (49)-(0)89-14005-0 Fax: (49)-(0)89-14005-110  
http://www.epson-electronics.de  
Düsseldorf Branch Office  
Altstadtstrasse 176, 51379 Leverkusen, Germany  
Phone: (49)-(0)2171-5045-0 Fax: (49)-(0)2171-5045-10  
UK & Ireland Branch Office Unit 2.4, Doncastle House, Doncastle Road, Bracknell, Berkshire RG12 8PE, England  
Phone: (44)-(0)1344-381700 Fax: (44)-(0)1344-381701  
French Branch Office  
LP 915 Les Conquérants, 1 Avenue de l' Atlantique, Z.A. de Courtaboeuf 2  
91976 Les Ulis Cedex, France  
Phone: (33)-(0)1-64862350 Fax: (33)-(0)1-64862355  
ASIA  
EPSON (CHINA) CO., LTD.  
23F, Beijing Silver Tower 2# North RD DongSangHuan ChaoYang District, Beijing, China  
Phone: (86) 10-6410-6655 Fax: (86) 10-6410-7319  
http://www.epson.com.cn  
4F, Bldg.,27, No.69, Gui Qing Road, Cao hejing, Shanghai, China  
Phone: (86) 21-6485-0835 Fax: (86) 21-6485-0775  
EPSON HONG KONG LTD.  
20/F., Harbour Centre, 25 Harbour Road, Wanchai, Hong kong  
Phone: (852) 2585-4600 Fax: (852) 2827-2152  
http://www.epson.com.hk  
EPSON ELECTRONIC TECHNOLOGY DEVELOPMENT (SHENZHEN )CO., LTD.  
Flat 16A, 16/F, New Times Plaza, No.1 Taizi Road, Shenzhen, China  
Phone: (86) 755-6811118 Fax: (86) 755-6677786  
EPSON TAIWAN TECHNOLOGY & TRADING LTD.  
14F, No.7, Song Ren Road, Taipei 110  
Phone: (886) 2-8786-6688 Fax: (886)2-8786-6660  
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No.1, Temasek Avenue #36-00, Millenia Tower, Singapore 039192  
Phone: (65) 337-7911 Fax: (65) 334-2716 http://www.epson.com.sg  
SEIKO EPSON CORPORATION KOREA Office  
50F, KLI 63 Building,60 Yoido-dong, Youngdeungpo-Ku, Seoul, 150-763, Korea  
Phone: (82) 2-784-6027 Fax: (82) 2-767-3677 http://www.epson-device.co.kr  
http://www.epson.com.tw  
Gumi Branch Office  
6F, Good Morning Securities Bldg., 56, Songjeong-dong Gumi-City, Gyongsangbuk-Do,  
730-090, Korea  
Phone: (82) 54-454-6027 Fax: (82) 54-454-6093  
ELECTRONIC DEVICE MARKETING DEPARTMENT  
Electronic devices information on WWW server  
http://www.epsondevice.com  

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