S1C62N51F [SEIKO]
4-BIT, MROM, 0.08MHz, MICROCONTROLLER, PQFP64, PLASTIC, QFP6-64;型号: | S1C62N51F |
厂家: | SEIKO EPSON CORPORATION |
描述: | 4-BIT, MROM, 0.08MHz, MICROCONTROLLER, PQFP64, PLASTIC, QFP6-64 时钟 微控制器 外围集成电路 |
文件: | 总178页 (文件大小:1095K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
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MF616 03
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CMOS 4 BIT SINGLE CHIP MICROCOMPUTER
S1C62N51
Technical Manual
S1C62N51 Technical Hardware/S1C62N51 Technical Software
NOTICE
No part of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko
Epson. Seiko Epson reserves the right to make changes to this material without notice. Seiko Epson does not assume any
liability of any kind arising out of any inaccuracies contained in this material or due to its application or use in any product or
circuit and, further, there is no representation that this material is applicable to products requiring high level reliability, such
as medical products. Moreover, no license to any intellectual property rights is granted by implication or otherwise, and there
is no representation or warranty that anything made in accordance with this material will be free from any patent or copyright
infringement of a third party. This material or portions thereof may contain technology or the subject relating to strategic
products under the control of the Foreign Exchange and Foreign Trade Law of Japan and may require an export license from
the Ministry of International Trade and Industry or other approval from another government agency.
© SEIKO EPSON CORPORATION 2001 All rights reserved.
PREFACE
Th is m an u al is in dividu aly described abou t th e h ardware an d th e software
of th e S1C62N51.
I. S1C62N51 Technical Hardware
Th is part explain s th e fu n ction of th e S1C62N51, th e circu it con figu -
ration s, an d details th e con trollin g m eth od.
II. S1C62N51 Technical Software
Th is part explain s th e program m in g m eth od of th e S1C62N51.
The information of the product number change
Starting April 1, 2001, the product number will be changed as listed below. To order from April 1,
2001 please use the new product number. For further information, please contact Epson sales
representative.
Configuration of product number
Devices
S1
C
60N01
F
0A01
00
00
Packing specification
Specification
Package (D: die form; F: QFP)
Model number
Model name (C: microcomputer, digital products)
Product classification (S1: semiconductor)
Development tools
S5U1
C
60R08 D1
1
Packing specification
2
Version (1: Version 1
)
1
)
Tool type (D1: Development Tool
Corresponding model number (60R08: for S1C60R08)
Tool classification (C: microcomputer use)
Product classification
(S5U1: development tool for semiconductor products)
1: For details about tool types, see the tables below. (In some manuals, tool types are represented by one digit.)
2: Actual versions are not written in the manuals.
Comparison table between new and previous number
S1C60 Family processors
S1C62 Family processors
Previous No.
E0C6001
E0C6002
E0C6003
E0C6004
E0C6005
E0C6006
E0C6007
E0C6008
E0C6009
E0C6011
E0C6013
E0C6014
E0C60R08
New No.
S1C60N01
S1C60N02
S1C60N03
S1C60N04
S1C60N05
S1C60N06
S1C60N07
S1C60N08
S1C60N09
S1C60N11
S1C60N13
S1C60140
S1C60R08
Previous No.
E0C621A
E0C6215
E0C621C
E0C6S27
E0C6S37
E0C623A
E0C623E
E0C6S32
E0C6233
E0C6235
E0C623B
E0C6244
E0C624A
E0C6S46
New No.
S1C621A0
S1C62150
S1C621C0
S1C6S2N7
S1C6S3N7
S1C6N3A0
S1C6N3E0
S1C6S3N2
S1C62N33
S1C62N35
S1C6N3B0
S1C62440
S1C624A0
S1C6S460
Previous No.
E0C6247
E0C6248
E0C6S48
E0C624C
E0C6251
E0C6256
E0C6292
E0C6262
E0C6266
E0C6274
E0C6281
E0C6282
E0C62M2
E0C62T3
New No.
S1C62470
S1C62480
S1C6S480
S1C624C0
S1C62N51
S1C62560
S1C62920
S1C62N62
S1C62660
S1C62740
S1C62N81
S1C62N82
S1C62M20
S1C62T30
Comparison table between new and previous number of development tools
Development tools for the S1C60/62 Family
Previous No.
ASM62
New No.
Previous No.
DEV6262
DEV6266
DEV6274
DEV6292
DEV62M2
DEV6233
DEV6235
DEV6251
DEV6256
DEV6281
DEV6282
DEV6S27
DEV6S32
DEV6S37
EVA6008
EVA6011
EVA621AR
EVA621C
EVA6237
EVA623A
New No.
Previous No.
EVA623B
EVA623E
EVA6247
EVA6248
EVA6251R
EVA6256
EVA6262
EVA6266
EVA6274
EVA6281
EVA6282
EVA62M1
EVA62T3
EVA6S27
EVA6S32R
ICE62R
New No.
S5U1C62000A
S5U1C60N01D
S5U1C60N02D
S5U1C60N03D
S5U1C60N04D
S5U1C60N05D
S5U1C60N06D
S5U1C60N07D
S5U1C60N08D
S5U1C60N09D
S5U1C60N11D
S5U1C60R08D
S5U1C621A0D
S5U1C621C0D
S5U1C623B0D
S5U1C62440D
S5U1C624A0D
S5U1C624C0D
S5U1C62480D
S5U1C62470D
S5U1C62620D
S5U1C62660D
S5U1C62740D
S5U1C62920D
S5U1C62M20D
S5U1C62N33D
S5U1C62N35D
S5U1C62N51D
S5U1C62560D
S5U1C62N81D
S5U1C62N82D
S5U1C6S2N7D
S5U1C6S3N2D
S5U1C6S3N7D
S5U1C60N08E
S5U1C60N11E
S5U1C621A0E2
S5U1C621C0E
S5U1C62N37E
S5U1C623A0E
S5U1C623B0E
S5U1C623E0E
S5U1C62470E
S5U1C62480E
S5U1C62N51E1
S5U1C62N56E
S5U1C62620E
S5U1C62660E
S5U1C62740E
S5U1C62N81E
S5U1C62N82E
S5U1C62M10E
S5U1C62T30E
S5U1C6S2N7E
S5U1C6S3N2E2
S5U1C62000H
S5U1C60N03K
S5U1C60N04K
S5U1C60N07K
DEV6001
DEV6002
DEV6003
DEV6004
DEV6005
DEV6006
DEV6007
DEV6008
DEV6009
DEV6011
DEV60R08
DEV621A
DEV621C
DEV623B
DEV6244
DEV624A
DEV624C
DEV6248
DEV6247
KIT6003
KIT6004
KIT6007
S1C62N51
I. Technical Hardware
CONTENTS
CONTENTS
CHAPTER 1
INTRODUCTION ............................................................... I-1
1.1 Configuration ................................................................... I-1
1.2 Features .......................................................................... I-2
1.3 Block Diagram ................................................................. I-3
1.4 Pin Layout Diagram ......................................................... I-4
1.5 Pin Description ................................................................ I-5
CHAPTER 2
POWER SUPPLY AND INITIAL RESET ................................ I-6
2.1 Power Supply .................................................................. I-6
2.2 Initial Reset...................................................................... I-7
Oscillation detection circu it ...................................... I-8
Reset pin (RESET) .................................................... I-8
Sim u ltan eou s h igh in pu t to in pu t ports (K00–K03) ... I-8
In tern al register followin g in itialization ..................... I-9
2.3 Test Pin (TEST)............................................................... I-9
CHAPTER 3
CPU, ROM, RAM ............................................................ I-10
3.1 CPU ................................................................................ I-10
3.2 ROM ............................................................................... I-11
3.3 RAM ............................................................................... I-11
S1C62N51 TECHNICAL HARDWARE
EPSON
I-i
CONTENTS
CHAPTER 4
PERIPHERAL CIRCUITS AND OPERATION ...................... I-12
4.1 Memory Map .................................................................. I-12
4.2 Oscillation Circuit............................................................ I-15
Crystal oscillation circu it ......................................... I-15
CR oscillation circu it ............................................... I-16
4.3 Input Ports (K00–K03) .................................................... I-17
Con figu ration of in pu t ports .................................... I-17
In pu t com parison registers an d in terru pt fu n ction .. I-18
Mask option ............................................................ I-19
Con trol of in pu t ports .............................................. I-19
4.4 Output Ports (R00–R03)................................................. I-21
Con figu ration of ou tpu t ports .................................. I-21
Mask option ............................................................ I-22
Con trol of ou tpu t ports ............................................ I-24
4.5 I/O Ports (P00–P03) ....................................................... I-27
Con figu ration of I/ O ports ....................................... I-27
I/ O con trol register an d I/ O m ode ........................... I-27
Mask option ............................................................ I-28
Con trol of I/ O ports ................................................ I-28
4.6 LCD Driver (COM0–COM3, SEG0–SEG25) .................. I-30
Con figu ration of LCD driver ..................................... I-30
Switch in g between dyn am ic an d static drive ............ I-33
Mask option (segm en t allocation )............................. I-34
Con trol of LCD driver .............................................. I-36
4.7 Clock Timer .................................................................... I-37
Con figu ration of clock tim er .................................... I-37
In terru pt fu n ction ................................................... I-38
Con trol of clock tim er .............................................. I-39
I-ii
EPSON
S1C62N51 TECHNICAL HARDWARE
CONTENTS
4.8 A/D Converter................................................................. I-41
Con figu ration of A/ D con verter ............................... I-41
Operation of A/ D con verter ..................................... I-42
In terru pt fu n ction ................................................... I-47
Usage exam ple of th e A/ D con verter ........................ I-47
Con trol of A/ D con verter ......................................... I-49
4.9 Supply Voltage Detection (SVD) Circuit
and Heavy Load Protection Function ............................. I-53
Con figu ration of SVD circu it
an d h eavy load protection fu n ction .......................... I-53
Operation of SVD detection tim in g .......................... I-55
Operation of h eavy load protection fu n ction ............ I-56
Con trol of SVD circu it
an d h eavy load protection fu n ction .......................... I-57
4.10 Interrupt and HALT ......................................................... I-59
In terru pt factors ...................................................... I-60
Specific m asks an d factor flags for in terru pt ............ I-61
In terru pt vectors ..................................................... I-61
Con trol of in terru pt ................................................. I-62
CHAPTER 5
CHAPTER 6
BASIC EXTERNAL WIRING DIAGRAM............................ I-63
ELECTRICAL CHARACTERISTICS .................................... I-65
6.1 Absolute Maximum Rating ............................................. I-65
6.2 Recommended Operating Conditions ............................ I-66
6.3 DC Characteristics ......................................................... I-67
6.4 Analog Circuit Characteristics
and Power Current Consumption ................................... I-69
6.5 Oscillation Characteristics .............................................. I-73
S1C62N51 TECHNICAL HARDWARE
EPSON
I-iii
CONTENTS
CHAPTER 7
PACKAGE ...................................................................... I-75
7.1 Plastic Package .............................................................. I-75
7.2 Ceramic Package for Test Samples ............................... I-76
CHAPTER 8
PAD LAYOUT .................................................................. I-77
8.1 Diagram of Pad Layout................................................... I-77
8.2 Pad Coordinates............................................................. I-78
I-iv
EPSON
S1C62N51 TECHNICAL HARDWARE
CHAPTER 1: INTRODUCTION
CHAPTER 1
INTRODUCTION
Each m em ber of th e S1C62N51 Series of sin gle ch ip m icro-
com pu ters featu re a 4-bit S1C6200A core CPU, 1,024 words
of ROM (12 bits per word), 80 words of RAM (4 bits per
word), an LCD driver, 4 bits for in pu t ports (K00–K03), 4
bits for ou tpu t ports (R00–R03), on e 4-bit I/ O port (P00–
P03), clock tim er an d A/ D con verter.
Becau se of th eir low voltage operation an d low power con -
su m ption , th e S1C62N51 Series are ideal for a wide ran ge of
application s.
1.1 Config ura tion
Th e S1C62N51 Series are con figu red as follows, depen din g
on th e su pply voltage.
Table 1.1.1
Model
Supply voltage
3.0 V
Oscillation circuits
Crystal or CR
Configuration of the
S1C62N51 Series
S1C62N51
S1C62L51
1.5 V
Crystal or CR
S1C62N51 TECHNICAL HARDWARE
EPSON
I-1
CHAPTER 1: INTRODUCTION
1.2 Fe a ture s
Supply voltage
Built-in oscillation circuit
Instruction set
1.5 V / 3 V
Crystal or CR oscillation circu it, 32,768 Hz (typ.)
100 in stru ction s
ROM capacity
1,024 words × 12 bits
RAM capacity (data RAM)
Input port
80 words × 4 bits
4 bits (Su pplem en tary pu ll-down resistors m ay be u sed)
Output port
4 bits (Piezo bu zzer an d program m able frequ en cy ou tpu t
can be driven directry by m ask option )
Input/output port
LCD driver
Timer
4 bits
26 segm en ts × 4 com m on du ty (or 3 an d 2 com m on du ty)
Clock tim er
A/D converter
CR oscillation type A/ D con verter bu ilt-in
Supply voltage detection
circuit (SVD)
1.2 V / 2.4 V
Interrupts:
External interrupt
Internal interrupt
In pu t port in terru pt
Tim er in terru pt
1 system
1 system
1 system
A/ D con verter in terru pt
Supply voltage
1.5 V (0.9–2.0 V) S1C62L51
1.5 V (1.2–2.0 V) S1C62L51 (Du rin g A/ D con version )
3.0 V (1.8–3.5 V) S1C62N51
Current consumption (typ.)
Supply form
1.0 µA (Crystal oscillation CLK = 32,768 Hz, wh en h alted)
2.5 µA (Crystal oscillation CLK = 32,768 Hz, wh en execu tin g)
64-pin QFP (plastic) or ch ip
I-2
EPSON
S1C62N51 TECHNICAL HARDWARE
CHAPTER 1: INTRODUCTION
1.3 Bloc k Dia g ra m
ROM
System Reset
Control
OSC
1,024 words x 12 bits
Core CPU S1C6200A
RAM
80 words x 4 bits
Interrupt
Generator
COM0–3
SEG0–25
K00–03
TEST
Input Port
Test Port
LCD Driver
VDD
V
L1–3
I/O Port
Output Port
Timer
P00–03
R00–03
Power
Controller
CA–CC
VS1
VSS
SVD
ADOUT
RS
TH
FOUT / BUZZER
BUZZER
Fout & Buzzer
A/D Converter
CS
Fig. 1.3.1
Block diagram
S1C62N51 TECHNICAL HARDWARE
EPSON
I-3
CHAPTER 1: INTRODUCTION
1.4 Pin La yout Dia g ra m
QFP6-60 pin
(ceramic)
Pin No Pin name Pin No Pin name Pin No Pin name Pin No Pin name
1
2
COM3
SEG0
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
SEG10
SEG11
SEG12
TEST
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
SEG13
SEG14
SEG15
SEG16
SEG17
SEG18
SEG19
SEG20
SEG21
SEG22
SEG23
SEG24
SEG25
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
P00
P01
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
TH
45
31
ADOUT
3
P02
VDD
46
30
4
P03
OSC1
OSC2
5
RESET
K00
K01
K02
K03
R00
R01
R02
R03
CS
6
VSS
7
CA
CB
CC
8
9
60
16
10
11
12
13
14
15
V
L1
L2
L3
V
V
1
15
COM0
COM1
COM2
VDD
S1
V
RS
QFP6-64 pin
(plastic)
Pin No Pin name Pin No Pin name Pin No Pin name Pin No Pin name
1
2
COM2
COM3
N.C.
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
TEST
SEG13
SEG14
SEG15
SEG16
SEG17
SEG18
SEG19
SEG20
SEG21
SEG22
SEG23
SEG24
SEG25
VDD
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
P00
P01
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
CS
RS
48
33
3
P02
TH
49
32
4
SEG0
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
SEG10
SEG11
SEG12
P03
ADOUT
VDD
5
RESET
K00
K01
K02
K03
R00
R01
R02
R03
N.C.
N.C.
N.C.
6
OSC1
OSC2
VSS
7
Index
8
9
CA
10
11
12
13
14
15
16
CB
64
17
CC
VL1
1
16
VL2
VL3
COM0
COM1
VS1
Fig. 1.4.1
N.C. = No connection
Pin assignment
I-4
EPSON
S1C62N51 TECHNICAL HARDWARE
CHAPTER 1: INTRODUCTION
1.5 Pin De sc rip tion
Table 1.5.1 Pin description
Pin No.
Terminal name
Input/Output
Function
QFP6-60 pin
(ceramic)
QFP6-64 pin
(plastic)
V
DD
SS
S1
29, 48
51
31, 53
56
(I)
(I)
O
Power source (+) terminal
V
Power source (-) terminal
V
30
32
Oscillation and internal logic system regulated
voltage output terminal
VL1
55
60
O
LCD system regulated voltage output terminal
(approx. -1.05V)
V
L2
56
57
61
62
O
O
–
LCD system booster output terminal (VL1 × 2)
LCD system booster output terminal (VL1 × 3)
Booster capacitor connecting terminal
Crystal or CR oscillation input terminal
Crystal or CR oscillation output terminal
Input terminal
VL3
CA–CC
OSC1
52–54
49
57–59
54
I
OSC2
50
55
O
I
K00–K03
P00–P03
R00–R03
SEG0–25
36–39
31–34
40–43
2–14
16–28
58–60, 1
44
38–41
33–36
42–45
4–16
18–30
63, 64, 1, 2
49
I/O
O
O
I/O terminal
Output terminal
LCD segment output terminal
(convertible to DC output terminal by mask option)
LCD common output terminal
COM0–3
CS
O
I
A/D converter CR oscillation input terminal
A/D converter CR oscillation output terminal
A/D converter CR oscillation output terminal
A/D converter oscillation frequency output terminal
Initial setting input terminal
RS
45
50
O
O
O
I
TH
46
51
ADOUT
RESET
TEST
47
52
35
37
15
17
I
Test input terminal
S1C62N51 TECHNICAL HARDWARE
EPSON
I-5
CHAPTER 2: POWER SUPPLY AND INITIAL RESET
CHAPTER 2
POWER SUPPLY AND INITIAL RESET
2.1 Powe r Sup p ly
With a sin gle extern al power su pply (*1) su pplied to VDD
th rou gh VSS, th e S1C62N51 Series gen erate th e n ecessary
in tern al voltages with th e regu lated voltage circu it (<VS1> for
oscillators an d in tern al circu it, <VL1> for LCDs) an d th e
voltage booster (<VL2, VL3> for LCDs).
Figu re 2.1.1 sh ows th e power su pply con figu ration .
*1 Su pply voltage: 62N51...3 V, 62L51...1.5 V
Note - External loads cannot be driven by the output voltage of the
regulated voltage circuit and voltage booster circuit.
-
See Chapter 6, "ELECTRICAL CHARACTERISTICS", for
voltage values.
V
DD
Internal
circuit
V
S1
Internal system
regulated voltage
circuit
VS1
Oscillation
circuit
OSC1, 2
V
L1
LCD regulated
voltage circuit
V
L1
V
L1
V
V
CA
CB
CC
L2
L3
LCD
voltage
booster
COM0–3
SEG0–25
V
V
L2
L3
External
power
supply
LCD driver
Vss
Fig. 2.1.1
Configuration of
power supply
I-6
EPSON
S1C62N51 TECHNICAL HARDWARE
CHAPTER 2: POWER SUPPLY AND INITIAL RESET
2.2 Initia l Re se t
To in itialize th e S1C62N51 Series circu its, an in itial reset
m u st be execu ted. Th ere are th ree ways of doin g th is.
(1) In itial reset by th e oscillation detection circu it (Note)
(2) Extern al in itial reset via th e RESET pin
(3) Extern al in itial reset by sim u ltan eou s h igh in pu t to pin s
K00–K03 (depen din g on m ask option )
Figu re 2.2.1 sh ows th e con figu ration of th e in itial reset
circu it.
OSC1
OSC1
Oscillation
circuit
OSC2
Oscillation
detection
circuit
K00
Noise
rejection
circuit
Vss
Initial
reset
K01
K02
K03
Noise
rejection
circuit
RESET
Vss
Fig. 2.2.1
Configuration of
initial reset circuit
Note
Since the circuit may sometimes not operate normally with the
initial resetting by the oscillation detection circuit indicated in
number (1), depending on the method of making the power, you
should utilize one of the initial resetting methods mentioned in
numbers (2) and (3).
S1C62N51 TECHNICAL HARDWARE
EPSON
I-7
CHAPTER 2: POWER SUPPLY AND INITIAL RESET
Wh en th e oscillation circu it h as been stopped u n til th e
Osc illa tion d e te c tion
c irc uit
oscillation circu it begin s to oscillate wh en th e power is
tu rn ed on or for an y oth er reason , th e oscillation detection
circu it will ou tpu t an in itial reset sign al, bu t sin ce th e
circu it m ay som etim es n ot operate n orm ally with th e in itial
resettin g du e to th e oscillation detection circu it, depen din g
on th e m eth od of m akin g th e power, you sh ou ld u tilize on e
of th e in itial resettin g m eth ods in dicated h ereafter.
An in itial reset can be in voked extern ally by m akin g th e
reset pin h igh . Th is h igh level m u st be m ain tain ed for at
least 5 m s (wh en oscillatin g frequ en cy, fosc = 32 kHz),
becau se th e in itial reset circu it con tain s a n oise rejection
circu it. Wh en th e reset pin goes low th e CPU begin s to
operate.
Re se t p in (RESET)
An oth er way of in vokin g an in itial reset extern ally is to in pu t
a h igh sign al sim u ltan eou sly to th e in pu t ports (K00–K03)
selected with th e m ask option . Th e specified in pu t port pin s
m u st be kept h igh for at least 4 sec (wh en oscillatin g fre-
qu en cy fosc = 32 kHz), becau se of th e n oise rejection circu it.
Table 2.2.1 sh ows th e com bin ation s of in pu t ports (K00–
K03) th at can be selected with th e m ask option .
Sim ulta ne ous hig h
inp ut to inp ut p orts
(K00–K03)
Table 2.2.1
A
B
C
D
Not used
Input port combinations
K00*K01
K00*K01*K02
K00*K01*K02*K03
Wh en , for in stan ce, m ask option D (K00*K01*K02*K03) is
selected, an in itial reset is execu ted wh en th e sign als in pu t
to th e fou r ports K00–K03 are all h igh at th e sam e tim e.
If you u se th is fu n ction , m ake su re th at th e specified ports
do n ot go h igh at th e sam e tim e du rin g n orm al operation .
I-8
EPSON
S1C62N51 TECHNICAL HARDWARE
CHAPTER 2: POWER SUPPLY AND INITIAL RESET
An in itial reset in itializes th e CPU as sh own in th e table
below.
Inte rna l re g iste r fol-
lowing initia liza tion
Table 2.2.2
CPU Core
Initial values
Name
Signal
PCS
PCP
NPP
SP
X
Number of bits
Setting value
00H
Program counter step
Program counter page
New page pointer
Stack pointer
8
4
4
8
8
8
4
4
4
1
1
1
1
1H
1H
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
0
Index register X
Index register Y
Register pointer
General register A
General register B
Interrupt flag
Y
RP
A
B
I
Decimal flag
D
0
Zero flag
Z
Undefined
Undefined
Carry flag
C
Peripheral circuits
Name
RAM
Number of bits
Setting value
Undefined
Undefined
*1
80 × 4
26 × 4
–
Display memory
Other peripheral circuit
*1: See Section 4.1, "Mem ory Map"
2.3
Te st Pin (TEST)
Th is pin is u sed wh en IC is in spected for sh ipm en t.
Du rin g n orm al operation con n ect it to VSS.
S1C62N51 TECHNICAL HARDWARE
EPSON
I-9
CHAPTER 3: CPU, ROM, RAM
CHAPTER 3
CPU, ROM, RAM
3.1 CPU
Th e S1C62N51 Series em ploys th e S1C6200A core CPU, so
th at register con figu ration , in stru ction s, an d so forth are
virtu ally iden tical to th ose in oth er processors in th e fam ily
u sin g th e S1C6200A. Refer to th e "S1C6200/ 6200A Core
CPU Man u al" for details of th e S1C6200A.
Note th e followin g poin ts with regard to th e S1C62N51
Series:
(1) Th e SLEEP operation is n ot provided, so th e SLP in stru c-
tion can n ot be u sed.
(2) Becau se th e ROM capacity is 1,024 words, 12 bits per
word, ban k bits are u n n ecessary, an d PCB an d NBP are
n ot u sed.
(3) Th e RAM page is set to 0 on ly, so th e page part (XP, YP)
of th e in dex register th at specifies addresses is in valid.
PUSH XP
PUSH YP
POP
LD
XP
POP
LD
YP
XP,r
r,XP
YP,r
r,YP
LD
LD
I-10
EPSON
S1C62N51 TECHNICAL HARDWARE
CHAPTER 3: CPU, ROM, RAM
3.2 ROM
Th e bu ilt-in ROM, a m ask ROM for th e program , h as a
capacity of 1,024 × 12-bit steps. Th e program area is 4
pages (0–3), each con sistin g of 256 steps (00H–FFH). After
an in itial reset, th e program start address is page 1, step
00H. Th e in terru pt vector is allocated to page l, steps 01H–
07H.
Bank 0
00H step
01H step
Program start address
Interrupt vector area
0 page
1 page
2 page
3 page
07H step
08H step
Program area
FFH step
12 bits
Fig. 3.2.1
ROM configuration
RAM
3.3
Th e RAM, a data m em ory for storin g a variety of data, h as a
capacity of 80 words, 4-bit words. Wh en program m in g,
keep th e followin g poin ts in m in d:
(1) Part of th e data m em ory is u sed as stack area wh en
savin g su brou tin e retu rn addresses an d registers, so be
carefu l n ot to overlap th e data area an d stack area.
(2) Su brou tin e calls an d in terru pts take u p th ree words on
th e stack.
(3) Data m em ory 000H–00FH is th e m em ory area poin ted by
th e register poin ter (RP).
S1C62N51 TECHNICAL HARDWARE
EPSON
I-11
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Memory Map)
CHAPTER 4
PERIPHERAL CIRCUITS AND
OPERATION
Periph eral circu its (tim er, I/ O, an d so on ) of th e S1C62N51
Series are m em ory m apped. Th u s, all th e periph eral circu its
can be con trolled by u sin g m em ory operation s to access th e
I/ O m em ory. Th e followin g section s describe h ow th e pe-
riph eral circu its operate.
4.1 Me m ory Ma p
Th e data m em ory of th e S1C62N51 Series h as an address
space of 154 words, of wh ich 32 words are allocated to
display m em ory an d 26 words, to I/ O m em ory. Figu re 4.1.1
sh ow th e overall m em ory m ap for th e S1C62N51 Series, an d
Tables 4.1.1(a) an d (b), th e m em ory m aps for th e periph eral
circu its (I/ O space).
Address
Page
Low
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
High
0
M0 M1 M2 M3 M4 M5 M6 M7 M8 M9 MA MB MC MD ME MF
1
2
RAM area (000H–04FH)
80 words x 4 bits (R/W)
3
4
5
6
7
0
8
9
Display memory area (090H–0AFH)
32 words x 4 bits (Write only)
A
B
C
D
E
F
I/O memory area Table 4.1.1(a), (b)
Unused area
Fig. 4.1.1
Memory map
Note Memory is not mounted in unused area within the memory map
and in memory area not indicated in this chapter. For this reason,
normal operation cannot be assured for programs that have been
prepared with access to these areas.
I-12
EPSON
S1C62N51 TECHNICAL HARDWARE
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Memory Map)
Table 4.1.1(a) I/O memory map
Register
Address
Comment
*1
D3
D2
D1
D0
Name
K03
K02
K01
K00
TM3
TM2
TM1
TM0
TC3
TC2
TC1
TC0
TC7
TC6
TC5
TC4
TC11
TC10
TC9
TC8
TC15
TC14
TC13
TC12
EIK03
EIK02
EIK01
EIK00
0
Init
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
0
0
0
0
1
0
Low
Low
Low
Low
Low
Low
Low
Low
0
*2
*2
*2
*2
*3
*3
*3
*3
*3
*3
*3
*3
*3
*3
*3
*3
*3
*3
*3
*3
*3
*3
*3
*3
High
Input port data K03
K03
K02
K01
K00
High
Input port data K02
0E0H
0E3H
0E4H
0E5H
0E6H
0E7H
0E8H
0EBH
0ECH
0EDH
0EFH
High
Input port data K01
R
High
Input port data K00
High
Clock timer data 2 Hz
TM3
TC3
TM2
TC2
TM1
TC1
TM0
TC0
High
Clock timer data 4 Hz
High
Clock timer data 8 Hz
R
High
Clock timer data 16 Hz
1
Up/down counter data TC3
Up/down counter data TC2
Up/down counter data TC1
Up/down counter data TC0 (LSB)
Up/down counter data TC7
Up/down counter data TC6
Up/down counter data TC5
Up/down counter data TC4
Up/down counter data TC11
Up/down counter data TC10
Up/down counter data TC9
Up/down counter data TC8
Up/down counter data TC15 (MSB)
Up/down counter data TC14
Up/down counter data TC13
Up/down counter data TC12
Interrupt mask register K03
Interrupt mask register K02
Interrupt mask register K01
Interrupt mask register K00
1
0
1
0
R/W
R/W
R/W
R/W
R/W
1
0
1
0
TC7
TC6
TC5
TC4
1
0
1
0
1
0
1
0
TC11
TC15
EIK03
TC10
TC14
EIK02
EIT2
TC9
TC8
1
0
1
0
1
0
1
1
0
TC13
EIK01
TC12
EIK00
EIT32
0
1
0
1
0
Enable
Enable
Enable
Enable
Mask
Mask
Mask
Mask
*5
0
R
0
EIT8
R/W
0
Enable
Enable
Enable
Mask
Mask
Mask
Interrupt mask register (clock timer) 2 Hz
Interrupt mask register (clock timer) 8 Hz
Interrupt mask register (clock timer) 32 Hz
EIT2
EIT8
EIT32
0
0
0
0
*5
*5
*5
0
R
0
EIAD
R/W
IK0
0
0
Enable
Mask
Interrupt mask register (A/D)
Interrupt factor flag (K00–K03)
EIAD
0
0
*5
*5
*5
*4
*5
*4
*4
*4
0
0
0
0
0
R
R
Yes
No
IK0
0
0
IT2
IT8
IT32
Yes
Yes
Yes
No
No
No
Interrupt factor flag (clock timer) 2 Hz
Interrupt factor flag (clock timer) 8 Hz
Interrupt factor flag (clock timer) 32 Hz
IT2
0
0
0
IT8
IT32
*1 In itial valu e followin g in itial reset
*2 Not set in th e circu it
*3 Un defin ed
*4 Reset (0) im m ediately after bein g read
*5 Always "0" wh en bein g read
*6 Refer to m ain m an u al
S1C62N51 TECHNICAL HARDWARE
EPSON
I-13
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Memory Map)
Table 4.1.1(b) I/O memory map
Register
Address
Comment
*1
D3
0
D2
D1
D0
IAD
Name
Init
0
1
0
*5
*5
*5
*4
*5
*5
*5
0
0
0
0
0F0H
0F1H
0
R
Yes
No
Interrupt factor flag (A/D)
IAD
0
0
0
0
ADRUN
R/W
0
0
R
Start
High
High
High
On
High
On
High
High
High
High
1
Stop
Low
Low
Low
Off
Low
Off
Low
Low
Low
Low
0
A/D conversion Start/Stop
Output port data R03
Output port data R02
Output port data R01
Buzzer On/Off control register
Output port data R00
Frequency output control register
I/O port data P03
ADRUN
R03
R02
R01
BUZZER
R00
FOUT
P03
P02
P01
P00
C3
0
0
0
0
0
0
0
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
R01
R00
R03
R02
BUZZER
FOUT
0F3H
R/W
*2
*2
*2
*2
*3
*3
*3
*3
*3
*3
*3
*3
*3
*3
*3
*3
*3
*3
*3
*3
P03
C3
P02
C2
P01
C1
C5
C9
C13
0
P00
C0
I/O port data P02
0F4H
0F5H
0F6H
0F7H
0F8H
0F9H
0FAH
0FBH
0FCH
0FDH
0FEH
I/O port data P01
R/W
R/W
R/W
R/W
R/W
I/O port data P00
Up-counter data C3
Up-counter data C2
Up-counter data C1
Up-counter data C0 (LSB)
Up-counter data C7
Up-counter data C6
Up-counter data C5
Up-counter data C4
Up-counter data C11
Up-counter data C10
Up-counter data C9
Up-counter data C8
Up-counter data C15 (MSB)
Up-counter data C14
Up-counter data C13
Up-counter data C12
1
0
C2
1
0
C1
1
0
C0
1
0
C7
C7
C6
C4
1
0
C6
1
0
C5
1
0
C4
1
0
C11
C10
C9
C11
C15
0
C10
C14
C8
1
0
1
0
1
0
C8
1
0
C15
C14
C13
C12
0
C12
1
0
1
0
1
0
*5
*5
*5
*5
0
R
0
TMRST
W
0
0
Reset
Heavy
–
Clock timer reset
TMRST
HLMOD
0
Reset
0
Normal Heavy load protection mode register
HLMOD
R/W
SVDDT SVDON
R/W
*5
Low
On
Normal Supply voltage detection data
SVDDT
SVDON
CSDC
0
0
0
0
R
Off
Supply voltage detection circuit On/Off
Static
Dynamic LCD drive switch
CSDC
R/W
0
0
R
0
0
*5
*5
*5
*5
*5
*5
0
0
0
0
0
R
0
IOC
R/W
0
0
Out
In
I/O port I/O control register
IOC
XBZR
0
0
0
2 kHz
4 kHz
Buzzer frequency control
XBZR
R/W
0
XFOUT1 XFOUT0
R/W
*5
*6
*6
FOUT frequency control
FOUT frequency control
XFOUT1
XFOUT0
0
0
0
R
0
*5
*5
*5
0
ADCLK
R/W
0
0
R
65 kHz
32 kHz
A/D clock selection 65 kHz/32 kHz
ADCLK
0
I-14
EPSON
S1C62N51 TECHNICAL HARDWARE
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Oscillation Circuit)
4.2 Osc illa tion Circ uit
Th e S1C62N51 Series h ave a bu ilt-in oscillation circu it.
For th e oscillation circu it, eiter crystal oscillation or CR
oscillation m ay be selected by a m ask option .
Th e crystal oscillation circu it gen erates th e operatin g clock
for th e CPU an d periph eral circu it on con n ection to an
extern al crystal oscillator (typ. 32.768 kHz) an d trim m er
capacitor (5–25 pF).
Crysta l osc illa tion
c irc uit
Figu re 4.2.1 is th e block diagram of th e crystal oscillation
circu it.
V
DD
C
G
OSC1
OSC2
To CPU and
peripheral circuits
V
DD
C
D
Fig. 4.2.1
The S1C62N51 Series
Crystal oscillation circuit
As Figu re 4.2.1 in dicates, th e crystal oscillation circu it can
be con figu red sim ply by con n ectin g th e crystal oscillator
(X'tal) between th e OSC1 an d OSC2 pin s an d th e trim m er
capacitor (CG) between th e OSC1 an d VDD pin s.
S1C62N51 TECHNICAL HARDWARE
EPSON
I-15
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Oscillation Circuit)
For th e S1C62N51 Series, CR oscillation circu it (typ. 65
CR osc illa tion c irc uit
kHz) m ay be selected by a m ask option . Figu re 4.2.2 is th e
block diagram of th e CR oscillation circu it.
OSC1
To CPU and
peripheral circuits
RCR
C
OSC2
Fig. 4.2.2
The S1C62N51 Series
CR oscillation circuit
As Figu re 4.2.2 in dicates, th e CR oscillation circu it can be
con figu red sim ply by con n ectin g th e register (RCR) between
pin s OSC1 an d OSC2 sin ce capacity (C) is bu ilt-in .
See Ch apter 6, "ELECTRICAL CHARACTERISTICS" for R
valu e.
I-16
EPSON
S1C62N51 TECHNICAL HARDWARE
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Input Ports)
4.3 Inp ut Ports (K00–K03)
Th e S1C62N51 Series h ave a gen eral-pu rpose in pu t (4 bits).
Each of th e in pu t port pin s (K00–K03) h as an in tern al pu ll-
down resistan ce. Th e pu ll-down resistan ce can be selected
for each bit with th e m ask option .
Config ura tion of
inp ut p orts
Figu re 4.3.1 sh ows th e con figu ration of in pu t port.
VDD
Interrupt
request
Kxx
Address
VSS
Fig. 4.3.1
Configuration of input port
Mask option
Selectin g "pu ll-down resistan ce en abled" with th e m ask
option allows in pu t from a pu sh bu tton , key m atrix, an d so
forth . Wh en "pu ll-down resistan ce disabled" is selected, th e
port can be u sed for slide switch in pu t an d in terfacin g with
oth er LSIs.
S1C62N51 TECHNICAL HARDWARE
EPSON
I-17
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Input Ports)
All fou r in pu t port bits (K00–K03) provide th e in terru pt
Inp ut c om p a rison
re g iste rs a nd inte r-
rup t func tion
fu n ction . Th e con dition s for issu in g an in terru pt can be set
by th e software for th e fou r bits. Also, wh eth er to m ask th e
in terru pt fu n ction can be selected in dividu ally for all fou r
bits by th e software. Figu re 4.3.2 sh ows th e con figu ration of
K00–K03.
Kxx
One for each pin series
Address
Interrupt factor
flag (IK)
Noise
rejector
Interrupt
request
Address
Mask option
(K00–K03)
Interrupt mask
register (EIK)
Address
Fig. 4.3.2
Input interrupt circuit
configuration (K00–K03)
Th e in terru pt m ask registers (EIK00–EIK03) en able th e
in terru pt m ask to be selected in dividu ally for K00–K03. An
in terru pt occu rs wh en th e in pu t valu e wh ich are n ot
m asked ch an ge an d th e in terru pt factor flag (IK0) is set to
"1".
I-18
EPSON
S1C62N51 TECHNICAL HARDWARE
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Input Ports)
Th e con ten ts th at can be selected with th e in pu t port m ask
option are as follows:
Ma sk op tion
(1) An in tern al pu ll-down resistan ce can be selected for each
of th e fou r bits of th e in pu t ports (K00–K03). Havin g
selected "pu ll-down resistan ce disabled", take care th at
th e in pu t does n ot float. Select "pu ll-down resistan ce
en abled" for in pu t ports th at are n ot bein g u sed.
(2) Th e in pu t in terru pt circu it con tain s a n oise rejection
circu it to preven t in terru pts form occu rrin g th rou gh
n oise. Th e m ask option en ables selection of th e n oise
rejection circu it for each separate pin series. Wh en "u se"
is selected, a m axim u m delay of 0.5 m s (fosc = 32 kHz)
occu rs from th e tim e an in terru pt con dition is establish ed
u n til th e in terru pt factor flag (IK) is set to "1".
Table 4.3.1 list th e in pu t port con trol bits an d th eir ad-
dresses.
Control of inp ut p orts
Table 4.3.1 Input port control bits
Register
Address
Comment
Input port data K03
*1
D3
D2
D1
D0
Name
K03
K02
K01
K00
EIK03
EIK02
EIK01
EIK00
0
Init
–
1
0
*2
*2
*2
*2
High
Low
K03
K02
K01
K00
High
Low
Input port data K02
–
0E0H
0E8H
0EDH
High
Low
Input port data K01
–
R
R/W
R
High
Low
Input port data K00
–
Enable
Enable
Enable
Enable
Mask
Mask
Mask
Mask
Interrupt mask register K03
Interrupt mask register K02
Interrupt mask register K01
Interrupt mask register K00
0
EIK03
EIK02
EIK01
EIK00
IK0
0
0
0
*5
*5
*5
*4
0
0
0
0
0
Yes
No
Interrupt factor flag (K00–K03)
IK0
0
*1 In itial valu e followin g in itial reset
*2 Not set in th e circu it
*3 Un defin ed
*4 Reset (0) im m ediately after bein g read
*5 Always "0" wh en bein g read
*6 Refer to m ain m an u al
S1C62N51 TECHNICAL HARDWARE
EPSON
I-19
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Input Ports)
K00–K03 Input port data (0E0H)
Th e in pu t data of th e in pu t port pin s can be read with th ese
registers.
Wh en "1" is read:
High level
Low level
In valid
Wh en "0" is read:
Writin g:
Th e valu e read is "1" wh en th e pin voltage of th e fou r bits of
th e in pu t ports (K00–K03) goes h igh (VDD), an d "0" wh en th e
voltage goes low (VSS). Th ese bits are readin g, so writin g
can n ot be don e.
EIK00–EIK03 Interrupt mask registers (0E8H)
Maskin g th e in terru pt of th e in pu t port pin s can be don e
with th ese registers.
Wh en "1" is written :
Wh en "0" is written :
Readin g:
En able
Mask
Valid
With th ese registers, m askin g of th e in pu t port bits can be
don e for each of th e fou r bits. After an in itial reset, th ese
registers are all set to "0".
IK0 Interrupt factor flags (0EDH D0)
Th ese flags in dicate th e occu rren ce of an in pu t in terru pt.
Wh en "1" is read:
Wh en "0" is read:
Writin g:
In terru pt h as occu rred
In terru pt h as n ot occu rred
In valid
Th e in terru pt factor flag IK0 is associated with K00–K03,
respectively. From th e statu s of th ese flags, th e software
can decide wh eth er an in pu t in terru pt h as occu rred.
Th ese flags are reset wh en th e software h as read th em .
Readin g of in terru pt factor flags is available at EI, bu t be
carefu l in th e followin g cases.
If th e in terru pt m ask register valu e correspon din g to th e
in terru pt factor flags to be read is set to "1", an in terru pt
requ est will be gen erated by th e in terru pt factor flags set
tim in g, or an in terru pt requ est will n ot be gen erated.
After an in itial reset, th ese flags are set to "0".
I-20
EPSON
S1C62N51 TECHNICAL HARDWARE
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Output Ports)
4.4 Outp ut Ports (R00–R03)
Th e S1C62N51 Series h ave 4 bits for gen eral ou tpu t ports
(R00–R03).
Config ura tion of
outp ut p orts
Ou tpu t specification s of th e ou tpu t ports can be selected
in dividu ally with th e m ask option . Th ree kin ds of ou tpu t
specification s are available: com plem en tary ou tpu t an d Pch
open drain ou tpu t. Also, th e m ask option en ables th e
ou tpu t ports R00 an d R01 to be u sed as special ou tpu t
ports. Figu re 4.4.1 sh ows th e con figu ration of th e ou tpu t
ports.
VDD
Register
Rxx
Complementary
Pch open drain
Address
VSS
Fig. 4.4.1
Mask option
Configuration of output ports
S1C62N51 TECHNICAL HARDWARE
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Output Ports)
Th e m ask option en ables th e followin g ou tpu t port selection .
Ma sk op tion
(1) Output specifications of output ports
Th e ou tpu t specification s for th e ou tpu t ports (R00–R03)
m ay be eith er com plem en tary ou tpu t or Pch open drain
ou tpu t for each of th e fou r bits. However, even wh en Pch
open drain ou tpu t is selected, a voltage exceedin g th e
sou rce voltage m u st n ot be applied to th e ou tpu t port.
(2) Special output
In addition to th e regu lar DC ou tpu t, special ou tpu t can
be selected for ou tpu t ports R00 an d R01, as sh own in
Table 4.4.1. Figu re 4.4.2 sh ows th e stru ctu re of ou tpu t
ports R00–R03.
Table 4.4.1
Pin name
R00
When special output is selected
FOUT or BUZZER
BUZZER
Special output
R01
Register
(R03)
R03
Register
(R02)
R02
R01
BUZZER
Register
(R01)
BUZZER
Register
(R00)
R00
Fig. 4.4.2
Structure of output port
R00–R03
FOUT
Address
(0F3H)
Mask option
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S1C62N51 TECHNICAL HARDWARE
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Output Ports)
FOUT (R00) Wh en ou tpu t port R00 is set for FOUT ou tpu t, th is port will
gen erate fosc (CPU operatin g clock frequ en cy) or clock
frequ en cy divided in to fosc. Clock frequ en cy m ay be se-
lected in dividu ally for F1–F4, from am on g 5 types by m ask
option ; on e am on g F1–F4 is selected by software an d u sed.
Th e types of frequ en cy wh ich m ay be selected are sh own in
Table 4.4.2.
Table 4.4.2
Clock frequency (Hz)
F2 F3
fosc = 32,768
F4
Setting
value
FOUT clock frequency
F1
(D1,D0)=(0,0) (D1,D0)=(0,1) (D1,D0)=(1,0) (D1,D0)=(1,1)
256
(fosc/128)
512
(fosc/64)
1,024
(fosc/32)
2,048
(fosc/16)
1
2
3
4
5
4,096
(fosc/8)
512
(fosc/64)
1,024
(fosc/32)
2,048
(fosc/16)
8,192
(fosc/4)
1,024
(fosc/32)
2,048
(fosc/16)
4,096
(fosc/8)
2,048
(fosc/16)
4,096
(fosc/8)
8,192
(fosc/4)
16,384
(fosc/2)
4,096
(fosc/8)
8,192
(fosc/4)
16,384
(fosc/2)
32,768
(fosc/1)
(D1, D0) = (XFOUT1, XFOUT0)
Note A hazard may occur when the FOUT signal is turned on or off.
BUZZER, BUZZER
Ou tpu t ports R01 an d R00 m ay be set to BUZZER ou tpu t
an d BUZZER ou tpu t (BUZZER reverse ou tpu t), respectively,
allowin g for direct drivin g of th e piezo-electric bu zzer.
BUZZER ou tpu t (R00) m ay on ly be set if R01 is set to
BUZZER ou tpu t. In su ch case, wh eth er ON/ OFF of th e
BUZZER ou tpu t is don e th rou gh R00 register or is con trol-
led th rou gh R01 sim u ltan eou sly with BUZZER ou tpu t is
also selected by m ask option .
(R01, R00)
Th e frequ en cy of bu zzer ou tpu t m ay be selected by software
to be eith er 2 kHz or 4 kHz.
S1C62N51 TECHNICAL HARDWARE
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Output Ports)
Table 4.4.3 lists th e ou tpu t port con trol bits an d th eir ad-
dresses.
Control of outp ut
p orts
Table 4.4.3 Control bits of output ports
Register
Address
Comment
Output port data R03
*1
D3
D2
D1
D0
Name
R03
Init
0
1
0
Low
Low
Low
Off
High
High
High
On
R01
R00
R03
R02
Output port data R02
R02
0
BUZZER
FOUT
Output port data R01
R01
0
0F3H
Buzzer On/Off control register
Output port data R00
BUZZER
R00
0
R/W
High
On
Low
Off
0
Frequency output control register
Buzzer frequency control
FOUT
XBZR
0
0
2 kHz
4 kHz
0
XBZR
R/W
0
XFOUT1 XFOUT0
R/W
*5
*6
*6
0FDH
FOUT frequency control
FOUT frequency control
XFOUT1
XFOUT0
0
0
R
*1 In itial valu e followin g in itial reset
*2 Not set in th e circu it
*3 Un defin ed
*4 Reset (0) im m ediately after bein g read
*5 Always "0" wh en bein g read
*6 Refer to m ain m an u al
R00–R03 Output port data (0F3H)
Sets th e ou tpu t data for th e ou tpu t ports.
Wh en "1" is written :
Wh en "0" is written :
Readin g:
High ou tpu t
Low ou tpu t
Valid
Th e ou tpu t port pin s ou tpu t th e data written to th e corre-
spon din g registers (R00–R03) with ou t ch an gin g it. Wh en "1"
is written to th e register, th e ou tpu t port pin goes h igh
(VDD), an d wh en "0" is written , th e ou tpu t port pin goes low
(VSS). After an in itial reset, all registers are set to "0".
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S1C62N51 TECHNICAL HARDWARE
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Output Ports)
R00 (when FOUT Special output port data (0F3H D0)
is selected) Con trols th e FOUT (clock) ou tpu t.
Wh en "1" is written :
Wh en "0" is written :
Readin g:
Clock ou tpu t
Low level (DC) ou tpu t
Valid
FOUT ou tpu t can be con trolled by writin g data to R00. After
an in itial reset, th is register is set to "0".
Figu re 4.4.3 sh ows th e ou tpu t waveform for FOUT ou tpu t.
R00 register
0
1
FOUT output
waveform
Fig. 4.4.3
FOUT output waveform
XFOUT0, XFOUT1 FOUT frequency control (0FDH D0, 0FDH D1)
Selects th e ou tpu t frequ en cy wh en R00 port is set for FOUT
ou tpu t.
Table 4.4.4
XFOUT1
XFOUT0
Frequency selection
FOUT frequency selection
0
0
1
1
0
1
0
1
F1
F2
F3
F4
After an in itial reset, th ese registers are set to "0".
S1C62N51 TECHNICAL HARDWARE
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Output Ports)
R00, R01 (when BUZZER Special output port data (0F3H D0, 0F3H D1)
and BUZZER Con trols th e bu zzer ou tpu t.
is selected)
Wh en "1" is written :
Wh en "0" is written :
Readin g:
Bu zzer ou tpu t
Low level (DC) ou tpu t
Valid
BUZZER an d BUZZER ou tpu t can be con trolled by writin g
data to R00 an d R01.
Wh en BUZZER ou tpu t by R01 register con trol is selected by
m ask option , BUZZER ou tpu t an d BUZZER ou tpu t can be
con trolled sim u ltan eou sly by writin g data to R01 register.
After an in itial reset, th ese registers are set to "0".
Figu re 4.4.4 sh ows th e ou tpu t waveform for bu zzer ou tpu t.
R01 (R00) register
0
1
BUZZER output
waveform
Fig. 4.4.4
BUZZER output
waveform
Buzzer output waveform
XBZR Buzzer frequency control (0FDH D3)
Selects th e frequ en cy of th e bu zzer sign al.
Wh en "1" is written :
Wh en "0" is written :
Readin g:
2 kHz
4 kHz
Valid
Wh en R00 an d R01 port is set to bu zzer ou tpu t, th e fre-
qu en cy of th e bu zzer sign al can be selected by th is register.
Wh en "1" is written to th is register, th e frequ en cy is set in 2
kHz, an d in 4 kHz wh en "0" is written .
After an in itial reset, th is register is set to "0".
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S1C62N51 TECHNICAL HARDWARE
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (I/O Ports)
4.5 I/ O Ports (P00–P03)
Th e S1C62N51 Series h ave a 4-bit gen eral-pu rpose I/ O port.
Figu re 4.5.1 sh ows th e con figu ration of th e I/ O port. Th e
fou r bits of th e I/ O port P00–P03 can be set to eith er in pu t
m ode or ou tpu t m ode. Th e m ode can be set by writin g data
to th e I/ O con trol register (IOC).
Config ura tion of I/ O
p orts
Input
control
Register
Pxx
Address
I/O control
register
(IOC)
Address
VSS
Fig. 4.5.1
Configuration of I/O port
In pu t or ou tpu t m ode can be set for th e fou r bits of I/ O port
P00–P03 by writin g data in to I/ O con trol register IOC.
To set th e in pu t m ode, "0" is written to th e I/ O con trol
register. Wh en an I/ O port is set to in pu t m ode, its im ped-
an ce becom es h igh an d it works as an in pu t port. However,
th e in pu t lin e is pu lled down wh en in pu t data is read.
I/ O c ontrol re g iste r
a nd I/ O m od e
Th e ou tpu t m ode is set wh en "1" is written to th e I/ O con trol
register (IOC). Wh en an I/ O port set to ou tpu t m ode works
as an ou tpu t port, it ou tpu ts a h igh sign al (VDD) wh en th e
port ou tpu t data is "1", an d a low sign al (VSS) wh en th e port
ou tpu t data is "0".
After an in itial reset, th e I/ O con trol register is set to "0",
an d th e I/ O port en ters th e in pu t m ode.
S1C62N51 TECHNICAL HARDWARE
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (I/O Ports)
Th e ou tpu t specification du rin g ou tpu t m ode (IOC = "1") of
Ma sk op tion
th e I/ O port can be set with th e m ask option for eith er
com plem en tary ou tpu t or Pch open drain ou tpu t. Th is
settin g can be perform ed for each bit of th e I/ O port. How-
ever, wh en Pch open drain ou tpu t h as been selected, voltage
in excess of th e su pply voltage m u st n ot be applied to th e
port.
Table 4.5.1 lists th e I/ O port con trol bits an d th eir ad-
dresses.
Control of I/ O p orts
Table 4.5.1 I/O port control bits
Register
Address
Comment
*1
D3
D2
D1
D0
Name
P03
P02
P01
P00
0
Init
–
1
0
*2
*2
*2
*2
High
High
High
High
Low
Low
Low
Low
I/O port data P03
I/O port data P02
I/O port data P01
I/O port data P00
P03
P02
P01
P00
–
0F4H
0FCH
–
R/W
–
*5
*5
*5
0
0
0
IOC
R/W
0
0
R
Out
In
I/O port I/O control register
IOC
0
*1 In itial valu e followin g in itial reset
*2 Not set in th e circu it
*3 Un defin ed
*4 Reset (0) im m ediately after bein g read
*5 Always "0" wh en bein g read
*6 Refer to m ain m an u al
I/O port data (0F4H)
P00–P03
I/ O port data can be read an d ou tpu t data can be written
th rou gh th e port.
• Wh en writin g data
Wh en "1" is written :
Wh en "0" is written :
High level
Low level
Wh en an I/ O port is set to th e ou tpu t m ode, th e written
data is ou tpu t from th e I/ O port pin u n ch an ged. Wh en
"1" is written as th e port data, th e port pin goes h igh
(VDD), an d wh en "0" is written , th e level goes low (VSS).
Port data can also be written in th e in pu t m ode.
• Wh en readin g data
Wh en "1" is read:
Wh en "0" is read:
High level
Low level
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S1C62N51 TECHNICAL HARDWARE
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (I/O Ports)
Th e pin voltage level of th e I/ O port is read. Wh en th e I/
O port is in th e in pu t m ode th e voltage level bein g in pu t
to th e port pin can be read; in th e ou tpu t m ode th e
ou tpu t voltage level can be read. Wh en th e pin voltage is
h igh (VDD) th e port data read is "1", an d wh en th e pin
voltage is low (VSS) th e data is "0". Also, th e bu ilt-in pu ll-
down resistan ce fu n ction s du rin g readin g, so th e I/ O port
pin is pu lled down .
Note - When the I/O port is set to the output mode and a low-imped-
ance load is connected to the port pin, the data written to the
register may differ from the data read.
-
When the I/O port is set to the input mode and a low-level
voltage (Vss) is input by the built-in pull-down resistance, an
erroneous input results if the time constant of the capacitive
load of the input line and the built-in pull-down resistance load is
greater than the read-out time. When the input data is being
read, the time that the input line is pulled down is equivalent to
0.5 cycles of the CPU system clock. Hence, the electric poten-
tial of the pins must settle within 0.5 cycles. If this condition
cannot be met, some measure must be devised, such as
arranging a pull-down resistance externally, or performing
multiple read-outs.
IOC
I/O control register (0FCH D0)
Th e in pu t or ou tpu t I/ O port m ode can be set with th is
register.
Wh en "1" is written :
Wh en "0" is written :
Readin g:
Ou tpu t m ode
In pu t m ode
Valid
Th e in pu t or ou tpu t m ode of th e I/ O port is set in u n its of
fou r bits. For in stan ce, IOC sets th e m ode for P00–P03.
Writin g "1" to th e I/ O con trol register m akes th e I/ O port
en ter th e ou tpu t m ode, an d writin g "0", th e in pu t m ode.
After an in itial reset, th e IOC register is set to "0", so th e I/ O
port is in th e in pu t m ode.
S1C62N51 TECHNICAL HARDWARE
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver)
4.6 LCD Drive r (COM0–COM3, SEG0–SEG25)
Th e S1C62N51 Series h ave fou r com m on pin s an d 26
(SEG0–SEG25) segm en t pin s, so th at an LCD with a m axi-
m u m of 104 (26 × 4) segm en ts can be driven . Th e power for
drivin g th e LCD is gen erated by th e CPU in tern al circu it, so
th ere is n o n eed to su pply power extern ally.
Config ura tion of LCD
d rive r
Th e drivin g m eth od is 1/ 4 du ty (1/ 3 or 1/ 2 du ty by m ask
option ) dyn am ic drive, adoptin g th e fou r types of poten tial,
VDD, VL1, VL2 an d VL3. Th e fram e frequ en cy is 32 Hz for 1/
4 du ty, 42.7 Hz for 1/ 3 du ty, an d 32 Hz for 1/ 2 du ty (in th e
case of fosc = 32,768 Hz). Figu re 4.6.1 sh ows th e drive
waveform for 1/ 4 du ty, Figu re 4.6.2 sh ows th e drive wave-
form for 1/ 3 du ty, an d Figu re 4.6.3 sh ows th e drive wave-
form for 1/ 2 du ty.
Note fosc indicates the oscillation frequency of the oscillation circuit.
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S1C62N51 TECHNICAL HARDWARE
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver)
V
V
V
V
C3
C2
C1
SS
LCD lighting status
COM0
COM1
COM2
COM3
COM0
COM1
COM2
COM3
SEG0~25
Not lit
Lit
VC3
VC2
VC1
VSS
SEG0
~SEG25
Frame freqency
Fig. 4.6.1
Drive waveform
for 1/4 duty
S1C62N51 TECHNICAL HARDWARE
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver)
V
V
V
V
C3
C2
C1
SS
LCD lighting status
COM0
COM1
COM2
COM0
COM1
COM2
COM3
SEG0~25
Not lit
Lit
VC3
VC2
VC1
VSS
SEG0
~SEG25
Fig. 4.6.2
Drive waveform
for 1/3 duty
Frame freqency
V
V
V
V
C3
C2
C1
SS
LCD lighting status
COM0
COM1
COM0
COM1
COM2
COM3
SEG0~25
Not lit
Lit
VC3
VC2
VC1
VSS
SEG0
~SEG25
Fig. 4.6.3
Drive waveform
for 1/2 duty
Frame freqency
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S1C62N51 TECHNICAL HARDWARE
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver)
Th e S1C62N51 Series m em bers allow software settin g of th e
LCD static drive. Th is fu n ction en ables easy adju stm en t
(caden ce adju stm en t) of th e oscillation frequ en cy of th e OSC
circu it.
Switc hing b e twe e n
d yna m ic a nd sta tic
d rive
Th e procedu re for execu tin g of th e LCD static drive is as
follows:
➀ Write "1" to th e CSDC register at address "0FBH D3".
➀ Write th e sam e valu e to all registers correspon din g to
COM0–COM3 of th e display m em ory.
Note
-
-
Even when l/3 or 1/2 duty is selected, the display data corre-
sponding to COM3 is valid for static drive. Hence, for static
drive, set the same value to all display memory corresponding
COM0–COM3.
For cadence adjustment, set the display data including display
data corresponding to COM3, so that all the LCD segments go
on.
Figu re 4.6.4 sh ows th e drive waveform for static drive.
LCD lighting status
COM0
COM1
COM2
COM3
–VDD
–VL1
–VL2
–VL3
COM
0–3
SEG0–25
Not lit
Frame frequency
Lit
–VDD
–VL1
–VL2
–VL3
SEG
0–25
–VDD
–VL1
–VL2
–VL3
Fig. 4.6.4
LCD static drive waveform
S1C62N51 TECHNICAL HARDWARE
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver)
(1) Segment allocation
Ma sk op tion
(se g m e nt a lloc a tion)
As sh own in Figu re 4.l.1, th e S1C62N51 Series display
data is decided by th e display data written to th e display
m em ory (write-on ly) at address "090H–0AFH".
Th e address an d bits of th e display m em ory can be m ade
to correspon d to th e segm en t pin s (SEG0–SEG25) in an y
com bin ation th rou gh m ask option . Th is sim plifies design
by in creasin g th e degree of freedom with wh ich th e liqu id
crystal pan el can be design ed.
Figu re 4.6.5 sh ows an exam ple of th e relation sh ip be-
tween th e LCD segm en ts (on th e pan el) an d th e display
m em ory in th e case of 1/ 3 du ty.
Common 0
9A, D0
(a)
Common 1
9B, D1
(f)
Common 2
9B, D0
(e)
Data
Address
D3
d
D2
c
D1
b
D0
a
SEG10
SEG11
SEG12
09AH
09BH
09CH
09DH
p
g
f
e
9A, D1
(b)
9B, D2
(g)
9A, D3
(d)
d'
p'
c'
g'
b'
f'
a'
e'
9D, D1
(f')
9A, D2
(c)
9B, D3
(p)
Display data memory allocation
Pin address allocation
a
a'
g'
b'
b
f'
f
g
c'
e
c
e'
p'
p
d'
d
SEG10 SEG11 SEG12
Common 0
Common 1
Common 2
Fig. 4.6.5
Segment allocation
I-34
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S1C62N51 TECHNICAL HARDWARE
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver)
(2) Drive duty
Accordin g to th e m ask option , eith er 1/ 4, 1/ 3 or 1/ 2
du ty can be selected as th e LCD drive du ty.
Table 4.6.1 sh ows th e differen ces in th e n u m ber of seg-
m en ts accordin g to th e selected du ty.
Table 4.6.1
Differences according to
selected duty
Pins used
in common
Maximum number
of segments
Frame frequency
(when fosc = 32 kHz)
Duty
1/ 4
1/ 3
1/ 2
COM0–3
COM0–2
COM0, 1
104 (26 × 4)
78 (26 × 3)
52 (26 × 2)
32 Hz
42.7 Hz
32 Hz
(3) Output specification
➀ Th e segm en t pin s (SEG0–SEG25) are selected by m ask
option in pairs for eith er segm en t sign al ou tpu t or DC
ou tpu t (VDD an d VSS bin ary ou tpu t). Wh en DC ou tpu t
is selected, th e data correspon din g to COM0 of each
segm en t pin is ou tpu t.
➀ Wh en DC ou tpu t is selected, eith er com plem en tary
ou tpu t or Pch open drain ou tpu t can be selected for
each pin by m ask option .
Note The pin pairs are the combination of SEG (2*n) and SEG (2*n + 1)
(where n is an integer from 0 to 12).
S1C62N51 TECHNICAL HARDWARE
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver)
Table 4.6.2 sh ows th e con trol bits of th e LCD driver an d
Control of LCD
d rive r
th eir addresses. Figu re 4.6.6 sh ows th e display m em ory
m ap.
Table 4.6.2 Control bits of LCD driver
Register
Address
Comment
*1
D3
D2
D1
D0
0
Name
Init
0
1
0
Static
Dynamic LCD drive switch
CSDC
CSDC
0
0
*5
*5
*5
0
0
0
0FBH
R/W
R
*1 In itial valu e followin g in itial reset
*2 Not set in th e circu it
*3 Un defin ed
*4 Reset (0) im m ediately after bein g read
*5 Always "0" wh en bein g read
*6 Refer to m ain m an u al
Address
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
Fig. 4.6.6
Display
090
0A0
Display memory (Write only)
32 words x 4 bits
memory map
LCD drive switch (0FBH D3)
CSDC
Th e LCD drive form at can be selected with th is switch .
Wh en "1" is written :
Wh en "0" is written :
Readin g:
Static drive
Dyn am ic drive
Valid
After an in itial reset, dyn am ic drive (CSDC = "0") is selected.
Display memory (090H–0AFH)
Th e LCD segm en ts are tu rn ed on or off accordin g to th is
data.
Wh en "1" is written :
Wh en "0" is written :
Readin g:
On
Off
In valid
By writin g data in to th e display m em ory allocated to th e
LCD segm en t (on th e pan el), th e segm en t can be tu rn ed on
or off. After an in itial reset, th e con ten ts of th e display
m em ory are u n defin ed.
I-36
EPSON
S1C62N51 TECHNICAL HARDWARE
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Clock Timer)
4.7 Cloc k Tim e r
Th e S1C62N51 Series h ave a bu ilt-in clock tim er driven by
th e sou rce oscillator. Th e clock tim er is con figu red as a
seven -bit bin ary cou n ter th at serves as a frequ en cy divider
takin g a 256 Hz sou rce clock from a prescaler. Th e fou r
h igh -order bits (16 Hz–2 Hz) can be read by th e software.
Figu re 4.7.1 is th e block diagram of th e clock tim er.
Config ura tion of
c loc k tim e r
Data bus
OSC
(oscillation
circuit)
256 Hz
128 Hz–32 Hz
16 Hz–2 Hz
32 Hz, 8 Hz, 2 Hz
Fig. 4.7.1
Clock timer reset signal
Block diagram of
clock timer
Interrupt
request
Interrupt
control
Norm ally, th is clock tim er is u sed for all kin ds of tim in g
pu rpose, su ch as clocks.
S1C62N51 TECHNICAL HARDWARE
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Clock Timer)
Th e clock tim er can in terru pt on th e fallin g edge of th e 32
Inte rrup t func tion
Hz, 8 Hz, an d 2 Hz sign als. Th e software can m ask an y of
th ese in terru pt sign als.
Figu re 4.7.2 is th e tim in g ch art of th e clock tim er.
Register
bits
Address
Frequency
Clock timer timing chart
D0
16 Hz
8 Hz
4 Hz
2 Hz
D1
D2
D3
0E3H
Occurrence of
32 Hz interrupt request
Occurrence of
8 Hz interrupt request
Occurrence of
2 Hz interrupt request
Fig. 4.7.2 Timing chart of the clock timer
As sh own in Figu re 4.7.2, an in terru pt is gen erated on th e
fallin g edge of th e 32 Hz, 8 Hz, an d 2 Hz frequ en cies. Wh en
th is h appen s, th e correspon din g in terru pt even t flag (IT32,
IT8, IT2) is set to "1". Maskin g th e separate in terru pts can
be don e with th e in terru pt m ask register (EIT32, EIT8,
EIT2). However, regardless of th e in terru pt m ask register
settin g, th e in terru pt even t flags will be set to "1" on th e
fallin g edge of th eir correspon din g sign al (e.g. th e fallin g
edge of th e 2 Hz sign al sets th e 2 Hz in terru pt factor flag to
"1").
Note Write to the interrupt mask register (EIT32, EIT8, EIT2) only in the
DI status (interrupt flag = "0"). Otherwise, it causes malfunction.
I-38
EPSON
S1C62N51 TECHNICAL HARDWARE
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Clock Timer)
Table 4.7.1 sh ows th e clock tim er con trol bits an d th eir
addresses.
Control of c loc k
tim e r
Table 4.7.1 Control bits of clock timer
Register
Address
0E3H
Comment
Clock timer data 2 Hz
*1
D3
D2
D1
D0
Name
TM3
TM2
TM1
TM0
0
Init
–
1
0
*3
*3
*3
*3
High
High
High
High
Low
Low
Low
Low
TM3
TM2
EIT2
IT2
TM1
TM0
Clock timer data 4 Hz
Clock timer data 8 Hz
Clock timer data 16 Hz
–
–
R
–
*5
0
R
0
EIT8
R/W
IT8
EIT32
IT32
Enable
Enable
Enable
Mask
Mask
Mask
Interrupt mask register (clock timer) 2 Hz
Interrupt mask register (clock timer) 8 Hz
Interrupt mask register (clock timer) 32 Hz
EIT2
EIT8
EIT32
0
0
0
0
0EBH
0EFH
0F9H
*5
*4
*4
*4
*5
*5
*5
*5
Yes
Yes
Yes
No
No
No
Interrupt factor flag (clock timer) 2 Hz
Interrupt factor flag (clock timer) 8 Hz
Interrupt factor flag (clock timer) 32 Hz
IT2
0
0
0
IT8
R
IT32
0
0
0
0
TMRST
W
0
0
R
Reset
–
Clock timer reset
TMRST
Reset
*1 In itial valu e followin g in itial reset
*2 Not set in th e circu it
*3 Un defin ed
*4 Reset (0) im m ediately after bein g read
*5 Always "0" wh en bein g read
*6 Refer to m ain m an u al
TM0–TM3 Timer data (0E3H)
Th e l6 Hz to 2 Hz tim er data of th e clock tim er can be read
from th is register. Th ese fou r bits are read-on ly, an d write
operation s are in valid.
After an in itial reset, th e tim er data is in itialized to "0H".
Interrupt mask registers (0EBH D0–D2)
EIT32, EIT8, EIT2
Th ese registers are u sed to m ask th e clock tim er in terru pt.
Wh en "1" is written :
Wh en "0" is written :
Readin g:
En abled
Masked
Valid
Th e in terru pt m ask register bits (EIT32, EIT8, EIT2) m ask
th e correspon din g in terru pt frequ en cies (32 Hz, 8 Hz, 2 Hz).
After an in itial reset, th ese registers are all set to "0".
S1C62N51 TECHNICAL HARDWARE
EPSON
I-39
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Clock Timer)
IT32, IT8, IT2 Interrupt factor flags (0EFH D0–D2)
Th ese flags in dicate th e statu s of th e clock tim er in terru pt.
Wh en "1" is read:
Wh en "0" is read:
Writin g:
In terru pt h as occu rred
In terru pt h as n ot occu rred
In valid
Th e in terru pt factor flags (IT32, IT8, IT2) correspon d to th e
clock tim er in terru pts (32 Hz, 8 Hz, 2 Hz). Th e software can
determ in e from th ese flags wh eth er th ere is a clock tim er
in terru pt. However, even if th e in terru pt is m asked, th e
flags are set to "1" on th e fallin g edge of th e sign al. Th ese
flags can be reset wh en th e register is read by th e software.
Readin g of in terru pt factor flags is available at EI, bu t be
carefu l in th e followin g cases.
If th e in terru pt m ask register valu e correspon din g to th e
in terru pt factor flags to be read is set to "1", an in terru pt
requ est will be gen erated by th e in terru pt factor flags set
tim in g, or an in terru pt requ est will n ot be gen erated. Be
very carefu l wh en in terru pt factor flags are in th e sam e
address.
After an in itial reset, th ese flags are set to "0".
TMRST Clock timer reset (0F9H D0)
Th is bit resets th e clock tim er.
Wh en "1" is written :
Wh en "0" is written :
Readin g:
Clock tim er reset
No operation
Always "0"
Th e clock tim er is reset by writin g "1" to TMRST. Th e clock
tim er starts im m ediately after th is. No operation resu lts
wh en "0" is written to TMRST.
Th is bit is write-on ly, an d so is always "0" wh en read.
I-40
EPSON
S1C62N51 TECHNICAL HARDWARE
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (A/D Converter)
4.8 A/ D Conve rte r
Th e S1C62N51 Series h ave a CR oscillation type A/ D con -
verter. Th is A/ D con verter is equ ipped with two CR oscilla-
tion circu it system s an d a cou n ter th at m easu res th eir
oscillation frequ en cy. Cou n ted valu es represen t con n ected
resistan ce valu es con verted in to digital valu es. Con n ect a
referen ce resistan ce th at does n ot ch an ge oscillation fre-
qu en cy accordin g to tem peratu re between th e RS an d CS
term in als an d a sen sor th at does ch an ge resistan ce valu es
accordin g to tem peratu re between th e TH an d CS term in als.
Th en , oscillate th em altern ately. Th e differen ce in th e
cou n ted valu e can be evalu ated as th e differen ce between
th e respective oscillation frequ en cies. Th erefore, variou s
sen sor circu it su ch as a tem peratu re-m easu rin g circu it
u sin g a th erm istor can be easily created, for exam ple.
Th e con figu ration of th e A/ D con verter is sh own in Figu re
4.8.1.
Config ura tion of A/ D
c onve rte r
Up/down counter
32 kHz or 65 kHz
OSC1
clock
Multiplying
circuit
TC15 TC11 TC7
–TC12 –TC8 –TC4 –TC0
TC3
Up/Down
control
Start/Stop
control
ADCLK
Data bus
ADRUN
Start/Stop
IAD EIAD
Interrupt
request
C15
–C12 –C8
C11
C7
–C4
C3
–C0
Interrupt
controller
Up-counter
Start/Stop
control
Controller
V
SS
VDD
Tr3
Tr1
Tr2
V
SS
CS
RS
TH
ADOUT
Fig. 4.8.1
CAD
R1
Configuration of
A/D converter
R2
S1C62N51 TECHNICAL HARDWARE
EPSON
I-41
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (A/D Converter)
Con n ect a referen ce resistan ce th at on ly sligh tly ch an ges
resistan ce valu es accordin g to en viron m en tal con dition s
between th e oscillatin g I/ O term in als RS an d CS. Con n ect a
sen sor th at ch an ges resistan ce valu es between th e TH an d
CS term in als. Fu rth erm ore, by con n ectin g a con den ser
between th e CS an d VSS, a CR oscillation circu it is com -
pleted.
Th is A/ D con verter perform s CR oscillation u sin g on e of th e
two resistan ces con n ected to extern al devices. Th eir oscilla-
tion frequ en cy serves as a clock from wh ich th e oscillation
frequ en cy is cou n ted. Differen ce in cou n ted oscillation
frequ en cy can be evalu ated in term s of th e differen ce be-
tween th e respective resistan ce valu es. Measu rem en t resu lts
can be obtain ed from th e ch an ges in resistan ce valu es after
correctin g th e differen ce accordin g to th e program .
Op e ra tion of A/ D
c onve rte r
(1) External resistances and condenser
Con n ect a sen sor (a variable resistan ce elem en t su ch as a
th erm istor) between th e TH an d CS term in als.
Next, set th e referen ce valu e of th e item to be m easu red
(e.g. referen ce tem peratu re in th e case of tem peratu re
m easu rem en t) an d con n ect th e referen ce resistan ce
equ ivalen t to th e sen sor resistan ce valu e at th e above
referen ce valu e between th e RS an d CS term in als. An
elem en t th at does n ot ch an ge du e to tem peratu re or oth er
en viron m en tal con dition s m u st be u sed as th e referen ce
resistan ce.
Con n ect an oscillatin g con den ser th at is u sed for CR
oscillation of both th e referen ce resistan ce an d th e sen sor
between th e CS an d VSS term in als.
I-42
EPSON
S1C62N51 TECHNICAL HARDWARE
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (A/D Converter)
(2) Oscillation circuit
Th e CR oscillation circu it is design ed so th at eith er th e
referen ce resistan ce side or th e sen sor side can be oper-
ated in depen den tly by th e oscillation con trol circu it.
A/ D con version begin s wh en "1" is written in th e ADRUN
register (0F1H D0). At th e sam e tim e, th e oscillation
circu it also tu rn s on . At first, th e circu it of th e referen ce
resistan ce side (RS) is operated by th e oscillation con trol
circu it. Th en , th e circu it of th e sen sor side (TH) tu rn s on
wh en cou n tin g by th e oscillation clock of th e referen ce
resistan ce is term in ated.
Each circu it perform s th e sam e oscillatin g operation as
follows:
Th e Tr1 (Tr2) tu rn s on first, an d th e con den ser con n ected
between th e CS an d VSS term in als is ch arged th rou gh th e
referen ce resistan ce (sen sor). If th e voltage level of th e CS
term in al decreases, th e Tr1 (Tr2) tu rn s off an d th e Tr3
tu rn s on . As a resu lt, th e con den ser becom es disch arged,
an d oscillation is perform ed accordin g to CR tim e con -
stan t. Th e tim e con stan t ch an ges as th e sen sor resist-
an ce valu e flu ctu ates, produ cin g a differen ce from th e
oscillation frequ en cy of th e referen ce resistan ce.
Oscillation waveform s are sh aped by th e Sch m itt trigger
an d tran sm itted to cou n ter. Th e clock tran sm itted to th e
cou n ter is also ou tpu t from th e ADOUT term in al. As a
resu lt, oscillation frequ en cy can be iden tified by th e
oscilloscope. Sin ce th is m on itor h as n o effect on oscilla-
tion frequ en cy, it can be u sed to adju st CR oscillation
frequ en cy.
Oscillation waveform s an d waveform s ou tpu t from th e
ADOUT term in al are sh own in Figu re 4.8.2.
VDD
CS terminal
VSS
VDD
Fig. 4.8.2
ADOUT
Oscillation waveforms
VSS
S1C62N51 TECHNICAL HARDWARE
EPSON
I-43
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (A/D Converter)
(3) Counter
Th e A/ D con verter in corporates two types of 16-bit
cou n ters. On e is th e u p-cou n ter C0–C15 th at cou n ts th e
aforem en tion ed oscillation clock, an d th e oth er is u p/
down cou n ter TC0–TC15 th at cou n ts th e in tern al clock
for referen ce cou n tin g. Each cou n ter perm its readin g an d
writin g on a 4-bit basis.
Th e in pu t u n it of th e u p/ down cou n ter TC0–TC15 in cor-
porates a m u ltiplyin g circu it so th at eith er th e OSC1
clock (Typ. 32.768 kHz) or its m u ltiplication clock (Typ.
65.536 kHz) can be selected as an in pu t clock.
Wh en A/ D con version is in itiated by th e ADRUN register,
oscillation by th e referen ce resistan ce begin s first, an d
th e u p-cou n ter C0–C15 starts cou n tin g u p accordin g to
th e oscillation clock. At th e sam e tim e, th e u p/ down
cou n ter TC0–TC15 starts cou n tin g u p.
Tim in g in startin g oscillation an d startin g cou n tin g u p
are sh own in Figu re 4.8.3.
Th e u p-cou n ter becom es ENABLE at th e fallin g edge of
th e first clock after CR oscillation is in itiated an d starts
cou n tin g u p from th e fallin g edge of th e n ext clock.
Th e u p/ down cou n ter becom es ENABLE at th e fallin g
edge of th e in tern al clock wh ich is in pu t im m ediately
after th e first CR oscillation clock h as fallen . Th en , it
starts cou n tin g u p from th e fallin g edge of th e n ext in ter-
n al clock.
ADRUN register
CS terminal
ADOUT
Up-counter enable
Up-counter (C0)
Start
Start
Clock (Up/down counter)
Up/down counter enable
Up/down counter (TC0)
Fig. 4.8.3
Counting up start
timing
I-44
EPSON
S1C62N51 TECHNICAL HARDWARE
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (A/D Converter)
If th e u p-cou n ter C0–C15 becom es "0000H" du e to over-
flow, th e sen sor side of th e oscillation circu it tu rn s on ,
an d th e u p-cou n ter starts cou n tin g u p accordin g to th e
oscillation clock on th e sen sor side.
Th e u p/ down cou n ter TC0–TC15 sh ifts to th e cou n tin g-
down m ode at th is poin t an d starts cou n tin g down from
th e valu e m easu red as a resu lt of oscillation by th e
referen ce resistan ce.
Tim in g in startin g cou n tin g wh en oscillation is switch ed,
is sam e as Figu re 4.8.3.
Wh en th e u p/ down cou n ter TC0–TC15 h as cou n ted down
to "0000H", th e cou n tin g operation of both cou n ters an d
CR oscillation stops, an d an in terru pt occu rs. At th e
sam e tim e, th e ADRUN register is set to "0", an d th e A/ D
con verter circu it stops operation com pletely.
Th e sen sor is oscillated for th e sam e period of tim e as th e
referen ce resistan ce is oscillated after th e u p/ down
cou n ter TC0–TC15 is set to "0000H" prior to A/ D con ver-
sion . Th erefore, th e differen ce in oscillation frequ en cy can
be m easu red from th e valu es cou n ted by th e u p-cou n ter
C0–C15.
Sin ce th e referen ce resistan ce is oscillated u n til th e u p-
cou n ter C0–C15 overflows, an appropriate in itial valu e
n eeds to be set before A/ D con version is started. If a
sm aller in itial valu e is set, a lon ger cou n tin g period is
possible, th ereby en su rin g m ore accu rate detection .
Likewise, if th e in pu t clock of th e u p/ down cou n ter TC0–
TC15 is set at 65 kHz, th e degree of precision is redu ced.
However, sin ce CR oscillation frequ en cy is n orm ally set
lower th an th e clock frequ en cy of th e u p/ down cou n ter
TC0–TC15 to en su re accu rate m easu rem en t, th e u p/
down cou n ter TC0–TC15 m ay overflow wh ile cou n tin g th e
oscillation frequ en cy of th e referen ce resistan ce.
If an overflow occu rs, CR oscillation an d A/ D con version
is term in ated im m ediately. Also in su ch cases, th e u p/
down cou n ter in dicates "0000H", an d in terru pt occu rs.
However, it is im possible to ju dge wh eth er th e in terru pt
h as occu rred du e to an overflow or n orm al term in ation .
S1C62N51 TECHNICAL HARDWARE
EPSON
I-45
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (A/D Converter)
Note th at correct m easu rem en t is im possible if an over-
flow occu rs. Th e in itial valu e to be set depen ds on th e
m easu rable ran ge by th e sen sor or wh ere to set th e
referen ce resistan ce valu e with in th at ran ge.
Th e in itial valu e m u st be set takin g th e above in to con -
sideration .
Con vert th e in itial valu e in to a com plem en t (valu e su b-
tracted from 0000H) before settin g it on th e u p-cou n ter
C0–C15. Sin ce th e data ou tpu t from th e u p-cou n ter C0–
C15 after A/ D con version m atch es data detected by th e
sen sor, process th e differen ce between th at valu e an d th e
in itial valu e before it is con verted in to a com plem en t
accordin g to th e program an d calcu late th e target valu e.
Th e above operation s are sh own in Figu re 4.8.4.
Setting by software
Up-counter
(C0–C15)
Up/down counter
(TC0–TC15)
Set the complement of the initial
value n on the up-counter
Set "0000H" on the up /down
counter
(1) Set the initial value (0000H-n)
(0000H-n)
0000H
0000H
(2) Start A/D conversion
(Set "1" on the ADRUN)
Count up
Count up
Oscillation by
reference resistance
FFFFH
:
x
0
Switch CR oscillation when
the up-counter overflows and
shift the up/down counter to
the counting-down mode
0
x
Count up
Count down
0001H
0000H
Oscillation by
sensor
:
m
When the value of the up/down
counter reaches 0000H, oscillation
and conting stops, and
(3) Read the up-counter and process the m–n value acoording to the program
an interruption occurs.
Fig. 4.8.4
Sequence of A/D conversion
-
-
Set the initial value of the up-counter C0–C15 taking into
Note
account the measurable range and the overflow of the up/down
counter TC0–TC15.
If the up/down counter TC0–TC15 is measured after A/D
conversion, it may not indicate "0000H". This is not due to
incorrect timing in terminating A/D conversion but because the
counting down clock is input after the control signal is output to
the up-counter to terminate counting.
I-46
EPSON
S1C62N51 TECHNICAL HARDWARE
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (A/D Converter)
Th e A/ D con verter h as a fu n ction wh ich allows in terru pt to
occu r after A/ D con version .
Inte rrup t func tion
Wh en th e u p/ down cou n ter TC0–TC15 is cou n ted down to
"0000H", both cou n ters stop cou n tin g. Th e in terru pt factor
flag IAD is set to "1" at th e fallin g edge of th e n ext clock. If
th e u p/ down cou n ter TC0–TC15 overflow du rin g cou n tin g-
u p operation , th e in terru pt factor flag is set to "1" at th e
risin g edge of th e clock im m ediately after th e cou n ter
reach es "0000H".
Th is in terru pt factor allows m askin g by th e in terru pt m ask
register EIAD. If th e EIAD is set at "1", an in terru pt occu rs
in th e CPU. If th e EIAD is set at "0", th e in terru pt factor flag
is set to "1". However, n o in terru pt will occu r in th e CPU.
Th e in terru pt factor flag is reset to "0" by a readin g opera-
tion .
Tim in g of in terru pt by th e A/ D con verter is sh own in Figu re
4.8.5.
ADRUN register
ADOUT
n
0
n+1 n+2
FFFE FFFF
x-3 x-2 x-1
0
1
2
m-1
m
Up-counter data
Up/down counter clock
Up/down counter data
Interrupt
1
2
3
x
x-1 x-2 x-3
3 2 1 0
Oscillation with reference resistor
Oscillation with sensor
Fig. 4.8.5
Timing of A/D
converter interrupt
Tem peratu re m easu rem en t is possible with th e A/ D con -
verter in wh ich a th erm istor is u sed as a sen sor. Elem en ts
Usa g e e xa m p le of
the A/ D c onve rte r
to be con n ected an d cou n ter settin g in th e case of tem pera-
tu re m easu rem en t are as follows:
Example: Temperature measurement at -20°C to 70°C
Referen ce resistan ce ....... 49.8 kΩ
th erm istor ....................... 50 kΩ
Oscillatin g con den ser ...... 2,200 pF
S1C62N51 TECHNICAL HARDWARE
EPSON
I-47
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (A/D Converter)
Wh en th e above elem en ts are con n ected, th e oscillation
frequ en cy of th e referen ce resistan ce becom es abou t 10 kHz,
an d th e oscillation frequ en cy of th e th erm istor varies with in
th e ran ge of abou t 1 kHz to 50 kHz at -20°C to 70°C.
Referen ce resistan ce is adju sted to th e th erm istor resistan ce
valu e at 25°C.
In addition , Figu re 4.8.6 in dicates th e resistan ce an d oscil-
lation frequ en cy ratio TYP at th e tim e of A/ D con version .
5.0
Resistance and oscillation frequency ratio
of A/D conversion circuit
For 50 kΩ , set the oscillation frequency to 1.
1.0
0.1
10 k
50 k
100 k
500 k
(
)
Ω
Fig. 4.8.6
Resistance and oscillation
frequency ratio
Resistance value
I-48
EPSON
S1C62N51 TECHNICAL HARDWARE
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (A/D Converter)
Table 4.8.2 sh ows th e A/ D con verter con trol bits an d th eir
addresses.
Control of A/ D
c onve rte r
Table 4.8.2 Control bits of clock timer
Register
Address
0E4H
Comment
*1
D3
D2
D1
D0
Name
TC3
TC2
TC1
TC0
TC7
TC6
TC5
TC4
TC11
TC10
TC9
TC8
TC15
TC14
TC13
TC12
C3
Init
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
*3
*3
*3
*3
*3
*3
*3
*3
*3
*3
*3
*3
*3
*3
*3
*3
*3
*3
*3
*3
*3
*3
*3
*3
*3
*3
*3
*3
*3
*3
*3
*3
Up/down counter data TC3
Up/down counter data TC2
Up/down counter data TC1
Up/down counter data TC0 (LSB)
Up/down counter data TC7
Up/down counter data TC6
Up/down counter data TC5
Up/down counter data TC4
Up/down counter data TC11
Up/down counter data TC10
Up/down counter data TC9
Up/down counter data TC8
Up/down counter data TC15 (MSB)
Up/down counter data TC14
Up/down counter data TC13
Up/down counter data TC12
Up-counter data C3
TC3
TC2
TC6
TC10
TC14
C2
TC1
TC0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
TC7
TC11
TC15
C3
TC5
TC9
TC13
C1
C5
C9
C13
0
TC4
TC8
TC12
C0
0E5H
0E6H
0E7H
0F5H
0F6H
0F7H
0F8H
0F1H
0FEH
0ECH
0F0H
Up-counter data C2
C2
Up-counter data C1
C1
Up-counter data C0 (LSB)
Up-counter data C7
C0
C7
C7
C6
C4
Up-counter data C6
C6
Up-counter data C5
C5
Up-counter data C4
C4
Up-counter data C11
C11
C10
C9
C11
C15
0
C10
C14
C8
Up-counter data C10
Up-counter data C9
Up-counter data C8
C8
Up-counter data C15 (MSB)
Up-counter data C14
C15
C14
C13
C12
0
C12
Up-counter data C13
Up-counter data C12
*5
*5
*5
0
R
0
ADRUN
R/W
0
0
Start
65 kHz
Enable
Yes
Stop
32 kHz
Mask
No
A/D conversion Start/Stop
ADRUN
0
0
0
0
0
*5
*5
*5
0
0
ADCLK
R/W
0
0
R
0
A/D clock selection 65 kHz/32 kHz
Interrupt mask register (A/D)
Interrupt factor flag (A/D)
ADCLK
0
*5
*5
*5
0
0
EIAD
R/W
0
0
R
0
EIAD
0
*5
*5
*5
*4
0
0
IAD
0
0
R
IAD
*1 In itial valu e followin g in itial reset
*2 Not set in th e circu it
*3 Un defin ed
*4 Reset (0) im m ediately after bein g read
*5 Always "0" wh en bein g read
*6 Refer to m ain m an u al
S1C62N51 TECHNICAL HARDWARE
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (A/D Converter)
TC0–TC15 Up/down counter (0E4H–0E7H)
Writin g an d readin g is possible on a 4-bit basis by th e u p/
down cou n ter th at is u sed to adju st th e CR oscillation tim e
between th e referen ce resistan ce an d th e variable resistan ce
elem en ts.
Th e u p/ down cou n ter cou n ts u p du rin g oscillation of th e
referen ce resistan ce an d cou n ts down from th e valu e it
reach ed wh en cou n tin g u p to "0000H" du rin g oscillation of
th e sen sor.
"0000H" n eeds to be en tered in th e cou n ter prior to A/ D
con version in order to adju st th e cou n tin g tim e of both
cou n ts.
After an in itial reset, data in th is cou n ter becom e in defin ite.
C0–C15
Up-counter (0F5H–0F8H)
Th is cou n ter cou n ts u p accordin g to th e CR oscillation
clock. It perm its writin g an d readin g on a 4-bit basis.
Th e com plem en t of th e n u m ber of clocks to be cou n ted by
th e oscillation of th e referen ce resistan ce, m u st be en tered
in th is cou n ter prior to A/ D con version .
If A/ D con version is in itiated, th e cou n ter cou n ts u p from
th e set in itial valu e, first accordin g to th e oscillation clock of
th e referen ce resistan ce. Wh en th e cou n ter reach es "0000H"
du e to overflow, th e oscillation of th e referen ce resistan ce
stops, an d th e sen sor starts oscillatin g. Th e cou n ter con tin -
u es cou n tin g accordin g to th e sen sor oscillation clock.
Cou n tin g tim e du rin g th e oscillation of th e referen ce resist-
an ce is calcu lated by th e u p/ down cou n ter TC0–TC15. Up-
cou n ter C0–C15 stops cou n tin g wh en th e sam e period of
tim e elapses. Differen ce from th e referen ce resistan ce can be
evalu ated from th e valu e in dicated by th e cou n ter wh en it
stops. Calcu late th e target valu e by processin g th e above
differen ce accordin g to th e program .
Measu rable ran ge an d th e overflow of th e u p/ down cou n ter
TC0–TC15 m u st be taken in to accou n t wh en settin g an
in itial valu e to be en tered prior to A/ D con version .
After an in itial reset, data in th is cou n ter becom e in defin ite.
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S1C62N51 TECHNICAL HARDWARE
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (A/D Converter)
ADCLK Input clock selection (0FEH D0)
Select th e in pu t clock of th e u p/ down cou n ter TC0–TC15.
Wh en "1" is written :
Wh en "0" is written :
Readin g:
65 kHz
32 kHz
Valid
Select th e ou tpu t clock of th e m u ltiplyin g circu it for th e
cou n tin g operation of th e u p/ down cou n ter TC0–TC15.
Wh en "1" is written in th e ADCLK, 65 kHz, a m u ltitu de of
th e OSC1 clock is selected. Wh en "0" is written , th e OSC1
clock is selected at 32 kHz.
If 65 kHz is selected, A/ D con version becom es m ore accu -
rate. However, th e in itial valu e m u st be set on th e u p-
cou n ter C0–C15 so th at th e u p/ down cou n ter TC0–TC15
will n ot overflow wh ile CR oscillation is bein g cou n ted.
After an in itial reset, ADCLK is set to "0".
ADRUN
A/D conversion START/STOP (0F1H D0)
Start A/ D con version .
Wh en "1" is written :
Wh en "0" is written :
Readin g:
A/ D con version starts
A/ D con version stops
Valid
Wh en "1" is written in th e ADRUN, A/ D con version begin s.
Th e register rem ain s at "1" du rin g A/ D con version an d is set
to "0" wh en A/ D con version is term in ated.
Wh en "0" is written in th e ADRUN du rin g A/ D con version ,
A/ D con version is pau sed.
ADRUN is set to "0" at in itial reset, wh en th e u p/ down
cou n ter overflows or wh en m easu rem en t is fin ish ed.
Interrupt mask register (0ECH D0)
EIAD
Select wh eth er to m ask in terru pt with th e A/ D con verter.
Wh en "1" is written :
Wh en "0" is written :
Readin g:
En able
Mask
Valid
Th e A/ D con verter in terru pt is perm itted wh en "1" is written
in th e EIAD. Wh en "0" is written , in terru pt is m asked.
After an in itial reset, th is register is set to "0".
S1C62N51 TECHNICAL HARDWARE
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (A/D Converter)
IAD Interrupt factor flag (0F0H D0)
Th is flag in dicates in terru pt cau sed by th e A/ D con verter.
Wh en "1" is read:
Wh en "0" is read:
Writin g:
In terru pt h as occu rred
In terru pt h as n ot occu rred
In valid
IAD is set to "1" wh en A/ D con version is term in ated (wh en
th e u p/ down cou n ter cou n ted u p or down to "0000H"). From
th e statu s of th is flag, th e software can decide wh eth er an
A/ D con verter in terru pt h as occu rred.
Th is flag is reset wh en th e software h as read it.
Readin g of in terru pt factor flag is available at EI, bu t be
carefu l in th e followin g cases.
If th e in terru pt m ask register valu e correspon din g to th e
in terru pt factor flag to be read is set to "1", an in terru pt
requ est will be gen erated by th e in terru pt factor flag set
tim in g, or an in terru pt requ est will n ot be gen erated.
After an in itial reset, th is flag is set to "0".
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S1C62N51 TECHNICAL HARDWARE
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (SVD Circuit and Heavy Load Protection Function)
4.9 Sup p ly Volta g e De te c tion (SVD) Circ uit a nd
He a vy Loa d Prote c tion Func tion
Th e S1C62N51 Series h ave a bu ilt-in su pply voltage detec-
Config ura tion of SVD
tion (SVD) circu it an d a h eavy load protection fu n ction .
c irc uit a nd he a vy
Figu re 4.9.1 sh ows th e con figu ration of th e circu it.
loa d p rote c tion
SVD circuit
func tion
Th e SVD circu it m on itors th e con dition s of th e su pply
voltage (battery voltage), an d software can ch eck wh eth er
th e su pply voltage h as dropped below th e detectin g voltage
level of th e SVD circu it: 2.4 V wh en su pply voltage is 3.0 V
(S1C62N51), or 1.2 V wh en su pply voltage is 1.5 V
(S1C62L51). Registers SVDON (SVD con trol on / off) an d
SVDDT (SVD data) are u sed for th e SVD circu it. Th e soft-
ware can tu rn SVD operation on an d off. Wh en SVD is on ,
th e IC draws a large cu rren t, so keep SVD off u n less it is.
Sin ce su pply voltage detection is au tom atically perform ed by
th e h ardware every 2 Hz (0.5 sec) wh en th e h eavy load
protection fu n ction operates, do n ot perm it th e operation of
th e SVD circu it by th e software in order to m in im ize power
cu rren t con su m ption .
Heavy load protection function
Note th at th e h eavy load protection fu n ction on th e
S1C62L51 is differen t from th e S1C62N51.
(1) In case of S1C62L51
Th e S1C62L51 h as th e h eavy load protection fu n ction for
wh en th e battery load becom es h eavy an d th e sou rce
voltage drops, su ch as wh en an extern al bu zzer sou n ds
or an extern al lam p ligh ts. Th e state wh ere th e h eavy
load protection fu n ction is in effect is called th e h eavy
load protection m ode. In th is m ode, operation with a
lower voltage th an n orm al is possible.
Th e n orm al m ode ch an ges to th e h eavy load protection
m ode in th e followin g two cases:
➀ Wh en th e software ch an ges th e m ode to th e h eavy load
protection m ode (HLMOD = "1")
➀ Wh en su pply voltage drop (SVDDT = "1") in th e SVD
circu it is detected, th e m ode will au tom atically sh ift to
th e h eavy load protection m ode u n til th e su pply volt-
age is recovered (SVTDT = "0")
S1C62N51 TECHNICAL HARDWARE
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (SVD Circuit and Heavy Load Protection Function)
In th e h eavy load protection m ode, th e in tern ally regu -
lated voltage is gen erated by th e liqu id crystal driver
sou rce ou tpu t VL2 so as to operate th e in tern al circu it.
Con sequ en tly, m ore cu rren t is con su m ed in th e h eavy
load protection m ode th an in th e n orm al m ode. Un less it
is n ecessary, be carefu l n ot to set th e h eavy load protec-
tion m ode with th e software. Also, to redu ce cu rren t
con su m ption , do n ot set th e SVDON to ON in th e h eavy
load protection m ode.
(2) In case of S1C62N51
Th e S1C62N51 h as th e h eavy load protection fu n ction for
wh en th e battery load becom es h eavy an d th e sou rce
voltage ch an ges, su ch as wh en an extern al bu zzer sou n ds
or an extern al lam p ligh ts. Th e state wh ere th e h eavy
load protection fu n ction is in effect is called th e h eavy
load protection m ode. Com pared with th e n orm al opera-
tion m ode, th is m ode can redu ce th e ou tpu t voltage
variation of th e con stan t voltage/ booster voltage circu it of
th e LCD system .
Th e n orm al m ode ch an ges to th e h eavy load protection
m ode in th e followin g case:
•
Wh en th e software ch an ges th e m ode to th e h eavy load
protection m ode (HLMOD = "1")
Th e h eavy load protection m ode switch es th e con stan t
voltage circu it of th e LCD system to th e h igh -stability
m ode from th e low cu rren t con su m ption m ode. Con se-
qu en tly, m ore cu rren t is con su m ed in th e h eavy load
protection m ode th an in th e n orm al m ode. Un less it is
n ecessary, be carefu l n ot to set th e h eavy load protection
m ode with th e software.
Note th at in S1C62L51, th e ran ge of operatin g pressu re
differs du rin g CR oscillation an d du rin g crystal oscilla-
tion .
Regurated
voltage circuit
SVD circuit
V
S1
L1
V
Vss
Address 0FAH
HLMOD
D3
D1
SVD sampling
control
Fig. 4.9.1
Configuration of SVD and
heavy load protection circuits
SVDDT
Vss
D0
SVDON
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (SVD Circuit and Heavy Load Protection Function)
Th e followin g explain s th e tim in g wh en th e SVD circu it
Op e ra tion of SVD
writes th e resu lt of su pply voltage detection to th e SVDDT
d e te c tion tim ing
register.
Th e resu lt of su pply voltage detection is written to th e
SVDDT register by th e SVD circu it, an d th is data can be
read by th e software to determ in e th e su pply voltage.
Th ere are two m eth ods, explain ed below, for execu tin g th e
detection by th e SVD circu it.
(1) Sampling with HLMOD set to "1"
Wh en HLMOD is set to "1" an d SVD sam plin g is ex-
ecu ted, th e detection resu lts can be written to th e SVDDT
register with th e followin g tim in g:
Im m ediately after sam plin g with th e 2 Hz cycle ou tpu t by
th e oscillation circu it wh ile HLMOD = "1" (sam plin g tim e
is 122 µs in th e case of fosc = 32,768 Hz).
Con sequ en tly, after HLMOD h as been set to "1", th e n ew
detection resu lt is written in a 2 Hz.
(2) Sampling with SVDON set to "1"
Wh en SVDON is set to "1", SVD detection is execu ted. As
soon as SVDON is reset to "0", th e resu lt is loaded to in
th e SVDDT register. To obtain a stable SVD detection
resu lt, th e SVD circu it m u st be on for at least 100 µs.
So, to obtain th e SVD detection resu lt, follow th e pro-
gram m in g sequ en ce below.
➀ Set SVDON to "1"
➀ Main tain for 100 µs m in im u m
➀ Set SVDON to "0"
➀ Read SVDDT
However, at 32 kHz for th e S1C62N51 an d S1C62L51,
th e in stru ction cycles are lon g en ou gh , so th ere is n o
n eed to worry abou t m ain tain in g 100 µs for SVDON = "1"
in th e software.
Notice th at even if th e SVD circu it detects a drop in th e
su pply voltage (1.2 V/ 2.4 V or less) an d in vokes th e h eavy
load protection m ode, th is will be th e sam e as wh en th e
software in vokes th e h eavy load protection m ode, in th at th e
SVD circu it will be sam pled with a tim in g syn ch ron ized to
th e 2 Hz ou tpu t from th e prescaler. If th e SVD circu it
detects a voltage drop an d en ters th e h eavy load protection
m ode, it will retu rn to th e n orm al m ode on ce th e su pply
voltage recovers an d th e SVD circu it determ in es th at th e
su pply voltage is 1.2 V/ 2.4 V or m ore.
S1C62N51 TECHNICAL HARDWARE
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (SVD Circuit and Heavy Load Protection Function)
Th e S1C62N51 h as a h eavy load protection fu n ction for
Op e ra tion of he a vy
wh en th e battery load becom es h eavy an d th e su pply voltage
loa d p rote c tion
drops, su ch as wh en a m elody is played or an extern al lam p
func tion
ligh ts. Th is fu n ction s works in th e h eavy load protection
m ode.
(1) In cace of S1C62L51
Th e n orm al m ode ch an ges to th e h eavy load protection
m ode in th e followin g two cases:
➀ Wh en th e software ch an ges th e m ode to th e h eavy load
protection m ode
➀ Wh en th e SVD circu it detects a su pply voltage less
th an 1.2 V, in wh ich case th e m ode is au tom atically
ch an ged to th e h eavy load protection m ode
(2) In case of S1C62N51
Th e n orm al m ode ch an ges to th e h eavy load protection
m ode in th e followin g case:
•
Wh en th e software ch an ges th e m ode to th e h eavy load
protection m ode (HLMOD = "1")
Based on th e operation of th e SVD circu it an d th e h eavy
load protection fu n ction , th e S1C62L51 obtain s an opera-
tion su pply voltage as low as 0.9 V. See th e electrical ch ar-
acteristics for th e precision of voltage detection by th e SVD
circu it.
In th e h eavy load protection m ode, th e in tern ally regu lated
voltage is gen erated by th e liqu id crystal driver su pply
ou tpu t, VL2, in order to operate th e in tern al circu it
(S1C62L51). Con sequ en tly, m ore cu rren t is con su m ed in
th e h eavy load protection m ode th an in th e n orm al m ode.
Un less n ecessary, do n ot select th e h eavy load protection
m ode with th e software.
Note Activation of the SVD circuit by software in the heavy load protec-
tion mode causes a malfunction. Avoid such activation if possible.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (SVD Circuit and Heavy Load Protection Function)
Table 4.9.1 sh ows th e con trol bits an d th eir addresses for
Control of SVD c ir-
th e SVD circu it an d th e h eavy load protection fu n ction .
c uit a nd he a vy loa d
p rote c tion func tion
Table 4.9.1 Control bits for SVD circuit and heavy load protection function
Register
Address
Comment
*1
D3
D2
D1
D0
Name
HLMOD
0
Init
0
1
0
Heavy
Normal Heavy load protection mode register
HLMOD
0
SVDDT SVDON
*5
0FAH
Low
On
Normal Supply voltage detection data
SVDDT
SVDON
0
0
R/W
R/W
R
Off
Supply voltage detection circuit On/Off
*1 In itial valu e followin g in itial reset
*2 Not set in th e circu it
*3 Un defin ed
*4 Reset (0) im m ediately after bein g read
*5 Always "0" wh en bein g read
*6 Refer to m ain m an u al
HLMOD Heavy load protection mode on/off (0FAH D3)
Wh en "1" is written :
Wh en "0" is written :
Readin g:
Heavy load protection m ode on
Heavy load protection m ode off
Valid
Wh en HLMOD is set to "1", th e IC en ters th e h eavy load
protection m ode, an d sam plin g con trol is execu ted for th e
tim e th e SVD circu it is on . Th e sam plin g tim in g is as fol-
lows:
Sam plin g in cycles of 2 Hz ou tpu t by th e oscillation circu it
wh ile HLMOD = "1" (sam plin g tim e is 122 µs in th e case of
fosc = 32,768 Hz).
Wh en SVD sam plin g is don e with HLMOD set to "1", th e
resu lts are written to th e SVDDT register with th e as follow-
in g tim in g:
Im m ediately on com pletion of sam plin g in cycles of 2 Hz
ou tpu t by th e oscillation circu it wh ile HLMOD = "1".
Con sequ en tly, after HLMOD is set to "1", th e n ew detected
resu lt is written in 2 Hz.
In th e h eavy load protection m ode, th e con su m ed cu rren t
becom es larger. Un less n ecessary, do n ot select th e h eavy
load protection m ode with th e software.
S1C62N51 TECHNICAL HARDWARE
EPSON
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (SVD Circuit and Heavy Load Protection Function)
SVDON SVD control on/off (0FAH D0)
Wh en "0" is written :
Wh en "1" is written :
Readin g:
SVD detection off
SVD detection on
Valid
Wh en th is bit is written , th e SVD detection on / off operation
is con trolled. Large cu rren t is drawn du rin g SVD detection ,
so keep SVD detection off except wh en n ecessary. Wh en
SVDON is set to "1", SVD detection is execu ted. As soon as
SVDON is reset to "0", th e detected resu lt is loaded in to th e
SVDDT register.
SVDDT SVD data (0FAH D1)
Wh en "0" is read:
Wh en "1" is read:
Su pply voltage ≥ Criteria voltage
Su pply voltage < Criteria voltage
Wh en SVDDT is "1", th e S1C62N51 en ters th e h eavy load
protection m ode. In th is m ode, th e detection operation of
th e SVD circu it is sam pled in 2 Hz cycles an d th e respective
detection resu lts are written to th e SVDDT register.
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S1C62N51 TECHNICAL HARDWARE
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Interrupt and HALT)
4.10 Inte rrup t a nd HALT
Th e S1C62N51 Series provide th e followin g in terru pt set-
tin gs, each of wh ich is m askable.
Extern al in terru pt:
In tern al in terru pt:
In pu t in terru pt (on e)
Tim er in terru pt (on e)
A/ D con verter in terru pt (on e)
To en able in terru pts, th e in terru pt flag m u st be set to "1"
(EI) an d th e n ecessary related in terru pt m ask registers m u st
be set to "1" (en able). Wh en an in terru pt occu rs, th e in ter-
ru pt flag is au tom atically reset to "0" (DI) an d in terru pts
after th at are in h ibited.
Wh en a HALT in stru ction is in pu t, th e CPU operatin g clock
stops an d th e CPU en ters th e h alt state. Th e CPU is reacti-
vated from th e h alt state wh en an in terru pt requ est occu rs.
Figu re 4.10.1 sh ows th e con figu ration of th e in terru pt
circu it.
Interrupt vector
(MSB)
K00
:
EIK00
Program counter of CPU
:
(three low-order bits)
(LSB)
K01
EIK01
IK0
INT
K02
(Interrupt request)
EIK02
K03
EIK03
IAD
EIAD
IT2
Interrupt factor flag
EIT2
IT8
Interrupt mask register
EIT8
IT32
EIT32
Fig. 4.10.1
Configuration of
interrupt circuit
S1C62N51 TECHNICAL HARDWARE
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Interrupt and HALT)
Table 4.10.1 sh ows th e factors th at gen erate in terru pt
Inte rrup t fa c tors
requ ests.
Th e in terru pt factor flags are set to "1" depen din g on th e
correspon din g in terru pt factors.
Th e CPU is in terru pted wh en th e followin g two con dition s
occu r an d an in terru pt factor flag is set to "1".
• Th e correspon din g m ask register is "1" (en abled)
• Th e in terru pt flag is "1" (EI)
Th e in terru pt factor flag is a read-on ly register, bu t can be
reset to "0" wh en th e register data is read.
After an in itial reset, th e in terru pt factor flags are reset to
"0".
Note Reading of interrupt factor flags is available at EI, but be careful in
the following cases.
If the interrupt mask register value corresponding to the interrupt
factor flags to be read is set to "1", an interrupt request will be
generated by the interrupt factor flags set timing, or an interrupt
request will not be generated. Be very careful when interrupt factor
flags are in the same address.
Table 4.10.1
Interrupt factors
Interrupt factor
Colck timer 2 Hz falling edge
Colck timer 8 Hz falling edge
Colck timer 32 Hz falling edge
A/D converter
Interrrupt factor flag
IT2
(0EFH D2)
(0EFH D1)
(0EFH D0)
IT8
IT32
IAD
IK0
(0F0H D0)
(0EDH D0)
A/D conversion completion
Input data (K00–K03)
Rising edge
I-60
EPSON
S1C62N51 TECHNICAL HARDWARE
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Interrupt and HALT)
Th e in terru pt factor flags can be m asked by th e correspon d-
in g in terru pt m ask registers. Th e in terru pt m ask registers
are read/ write registers. Th ey are en abled (in terru pt en -
abled) wh en "1" is written to th em , an d m asked (in terru pt
disabled) wh en "0" is written to th em . After an in itial reset,
th e in terru pt m ask register is set to "0".
Sp e c ific m a sks a nd
fa c tor fla g s for inte r-
rup t
Table 4.10.2 sh ows th e correspon den ce between in terru pt
m ask registers an d in terru pt factor flags.
Table 4.10.2
Interrupt mask registers and
interrupt factor flags
Interrupt mask register
Interrrupt factor flag
EIT2
(0EBH D2)
(0EBH D1)
(0EBH D0)
(0ECH D0)
(0E8H D3)
(0E8H D2)
(0E8H D1)
(0E8H D0)
IT2
(0EFH D2)
(0EFH D1)
(0EFH D0)
(0F0H D0)
EIT8
IT8
EIT32
EIAD
IT32
IAD
EIK03*
EIK02*
EIK01*
EIK00*
IK0
(0EDH D0)
* Th ere is an in terru pt m ask register for each in pu t port pin .
Wh en an in terru pt requ est is in pu t to th e CPU, th e CPU
begin s in terru pt processin g. After th e program bein g exe-
cu ted is su spen ded, in terru pt processin g is execu ted in th e
followin g order:
Inte rrup t ve c tors
➀ Th e address data (valu e of th e program cou n ter) of th e
program step to be execu ted n ext is saved on th e stack
(RAM).
➀ Th e in terru pt requ est cau ses th e valu e of th e in terru pt
vector (page 1, 01H–07H) to be loaded in to th e program
cou n ter.
➀ Th e program at th e specified address is execu ted (execu -
tion of in terru pt processin g rou tin e).
Note The processing in steps 1 and 2, above, takes 12 cycles of the
CPU system clock.
S1C62N51 TECHNICAL HARDWARE
EPSON
I-61
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Interrupt and HALT)
Table 4.10.4 sh ows th e in terru pt con trol bits an d th eir
addresses.
Control of inte rrup t
Table 4.10.4 Interrupt control bits
Register
Address
Comment
*1
D3
D2
D1
D0
Name
EIK03
EIK02
EIK01
EIK00
0
Init
0
1
0
Enable
Enable
Enable
Enable
Mask
Mask
Mask
Mask
Interrupt mask register K03
Interrupt mask register K02
Interrupt mask register K01
Interrupt mask register K00
EIK03
EIK02
EIK01
EIK00
0
0E8H
0EBH
0ECH
0EDH
0EFH
0F0H
0
R/W
0
*5
0
R
0
EIT2
EIT8
R/W
0
EIT32
Enable
Enable
Enable
Mask
Mask
Mask
Interrupt mask register (clock timer) 2 Hz
Interrupt mask register (clock timer) 8 Hz
Interrupt mask register (clock timer) 32 Hz
EIT2
EIT8
EIT32
0
0
0
0
*5
*5
*5
0
R
0
EIAD
R/W
IK0
0
0
Enable
Mask
Interrupt mask register (A/D)
EIAD
0
0
*5
*5
*5
*4
*5
*4
*4
*4
*5
*5
*5
*4
0
0
0
0
IT8
0
0
0
R
R
R
Yes
No
Interrupt factor flag (K00–K03)
IK0
0
0
IT2
0
IT32
IAD
Yes
Yes
Yes
No
No
No
Interrupt factor flag (clock timer) 2 Hz
Interrupt factor flag (clock timer) 8 Hz
Interrupt factor flag (clock timer) 32 Hz
IT2
IT8
IT32
0
0
0
0
0
0
Yes
No
Interrupt factor flag (A/D)
IAD
0
*1 In itial valu e followin g in itial reset
*2 Not set in th e circu it
*3 Un defin ed
*4 Reset (0) im m ediately after bein g read
*5 Always "0" wh en bein g read
*6 Refer to m ain m an u al
EIT32, EIT8, EIT2 Interrupt mask registers (0EBH D0–D2)
IT32, IT8, IT2 Interrupt factor flags (0EFH D0–D2)
See 4.7, "Clock Tim er".
EIAD Interrupt mask register (0ECH D0)
IAD Interrupt factor flag (0F0H D0)
See 4.8, "A/ D Con verter".
EIK00–EIK03 Interrupt mask registers (0E8H)
IK0 Interrupt factor flag (0EDH D0)
See 4.3, "In pu t Ports".
I-62
EPSON
S1C62N51 TECHNICAL HARDWARE
CHAPTER 5: BASIC EXTERNAL WIRING DIAGRAM
CHAPTER 5
BASIC EXTERNAL WIRING DIAGRAM
(1) Pie zo Buzze r Sing le Te rm ina l Driving
LCD
PANEL
K00
K03
P00
P03
CA
CB
CC
C
C
C
C
C
1
2
3
4
5
I
V
L1
L2
L3
DD
V
V
V
I/O
C
G
S1C62N51/62L51 OSC1
X'tal
OSC2
C6
1.5V
or
3.0V
V
S1
RESET
TEST
Vss
R00
R02
R03
O
Cp
Piezo
Buzzer
R1 R2
C
AD
Coil
X'tal
Crystal oscillator
Trimmer capacitor
Capacitor
32,768 Hz CI(MAX) = 35 kΩ
CG
5–25 pF
0.1 µF
C1–C6
Cp
Capacitor
3.3 µF
R
R
C
2
Thermistor
Resistor
50 kΩ
1
49.8 kΩ
2,200 pF
AD
Capacitor
S1C62N51 TECHNICAL HARDWARE
EPSON
I-63
CHAPTER 5: BASIC EXTERNAL WIRING DIAGRAM
(2) Pie zo Buzze r Dire c t Driving
LCD
PANEL
K00
K03
P00
P03
CA
CB
CC
C
C
C
C
C
1
2
3
4
5
I
V
L1
L2
L3
DD
V
V
V
I/O
C
G
S1C62N51/62L51 OSC1
X'tal
OSC2
C6
1.5V
or
3.0V
V
S1
RESET
TEST
Vss
R02
R03
O
Cp
R1 R2
Piezo
Buzzer
C
AD
X'tal
Crystal oscillator
32,768 Hz CI(MAX) = 35 kΩ
C
G
Trimmer capacitor
Capacitor
5–25 pF
0.1 µF
C1
–C6
Cp
Capacitor
3.3 µF
R
R
C
2
Thermistor
Resistor
50 kΩ
1
49.8 kΩ
2,200 pF
AD
Capacitor
I-64
EPSON
S1C62N51 TECHNICAL HARDWARE
CHAPTER 6: ELECTRICAL CHARACTERISTICS
CHAPTER 6
ELECTRICAL CHARACTERISTICS
6.1 Ab solute Ma xim um Ra ting
S1 C6 2 N5 1
(VDD =0V)
Item
Power voltage
Symbol
Rated value
-5.0 to 0.5
Unit
V
V
V
V
SS
Input voltage (1)
I
Vss-0.3 to 0.5
Vss-0.3 to 0.5
-20 to 70
V
Input voltage (2)
IOSC
V
Operating temperature
Storage temperature
Soldering temperature / Time
Allowable dissipation*1
Topr
Tstg
Tsol
°C
°C
–
-65 to 150
260°C, 10sec (lead section)
250
PD
mW
*1 In case of QFP6-64 pin plastic package
S1 C6 2 L5 1
(VDD =0V)
Item
Power voltage
Symbol
Rated value
-5.0 to 0.5
Unit
V
V
V
V
SS
Input voltage (1)
I
Vss-0.3 to 0.5
Vss-0.3 to 0.5
-20 to 70
V
Input voltage (2)
IOSC
V
Operating temperature
Storage temperature
Soldering temperature / Time
Allowable dissipation*1
Topr
Tstg
Tsol
°C
°C
–
-65 to 150
260°C, 10sec (lead section)
250
PD
mW
*1 In case of QFP6-64 pin plastic package
S1C62N51 TECHNICAL HARDWARE
EPSON
I-65
CHAPTER 6: ELECTRICAL CHARACTERISTICS
6.2 Re c om m e nd e d Op e ra ting Cond itions
S1 C6 2 N5 1
(Ta=-20 to 70°C)
Item
Symbol
Condition
DD=0V
Min
-3.5
Typ
-3.0
Max
-1.8
Unit
V
Power voltage
VSS
V
Oscillation frequency
Oscillation frequency
f
f
f
OSC1 Crystal oscillation
OSC1 Crystal oscillation
OSC2 CR oscillation, R=420kΩ
32,768
32,768
65
Hz
Hz
kHz
µF
µF
µF
µF
µF
µF
80
Booster capacitor (1)
Booster capacitor (2)
Capacitor between VDD and VL1
Capacitor between VDD and VL2
Capacitor between VDD and VL3
Capacitor between VDD and VS1
C
C
C
C
C
C
1
2
3
4
5
6
0.1
0.1
0.1
0.1
0.1
0.1
S1 C6 2 L5 1
(Ta=-20 to 70°C)
Item
Symbol
Condition
DD=0V *3
DD=0V, With software
Min
-2.0
-2.0
Typ
-1.5
-1.5
Max
-1.1
-0.9 *2
Unit
V
V
Power voltage
VSS
V
V
correspondence*1
Oscillation frequency
Oscillation frequency
f
f
f
OSC1 Crystal oscillation
OSC1 Crystal oscillation
OSC2 CR oscillation, R=420kΩ
32,768
32,768
65
Hz
Hz
kHz
µF
µF
µF
µF
µF
µF
80
Booster capacitor (1)
Booster capacitor (2)
Capacitor between VDD and VL1
Capacitor between VDD and VL2
Capacitor between VDD and VL3
Capacitor between VDD and VS1
C
C
C
C
C
C
1
2
3
4
5
6
0.1
0.1
0.1
0.1
0.1
0.1
*1 Wh en switch in g to th e h eavy load protection m ode.
Th e SVD circu it is tu rn ed OFF.
(For details, refer to Section 4.9).
*2 Th e voltage wh ich can be displayed on th e LCD pan el will differ accordin g to th e
ch aracteristics of th e LCD pan el.
*3 Wh en th ere is n o software correspon den ce du rin g CR oscillation or crystal oscilla-
tion .
I-66
EPSON
S1C62N51 TECHNICAL HARDWARE
CHAPTER 6: ELECTRICAL CHARACTERISTICS
6.3 DC Cha ra c te ristic s
S1 C6 2 N5 1
Un less oth erwise specified
VDD=0 V, VSS=-3.0 V, fosc=32,768 Hz, Ta=25°C, VS1, VL1, VL2 an d VL3 are in tern al
voltages, an d C1=C2=C3=C4=C5=C6=0.1 µF
Item
Symbol
Condition
Min
0.2•Vss
0.15•Vss
Vss
Vss
0
Typ
Max
0
0
0.8•Vss
0.85•Vss
0.5
Unit
V
V
V
V
High level input voltage (1)
High level input voltage (2)
Low level input voltage (1)
Low level input voltage (2)
High level input current (1)
VIH1
VIH2
VIL1
VIL2
K00–K03, P00–P03
RESET, TEST
K00~K03, P00–P03
RESET, TEST
I
I
I
I
IH1
V
IH1=0V
Without pull down resistor
IH2=0V
With pull down resistor
IH3=0V
With pull down resistor
K00–K03, P00–P03
µA
High level input current (2)
High level input current (3)
Low level input current
IH2
V
K00–K03
5
16
100
0
µA
µA
µA
IH3
IL
V
P00–P03
30
RESET, TEST
K00–K03, P00–P03
RESET, TEST
R02, R03, P00–P03
R00, R01
VIL=VSS
-0.5
High level output current (1)
High level output current (2)
I
I
OH1
OH2
V
V
OH1=0.1•VSS
OH2=0.1•VSS
-1.0
-1.0
mA
mA
(built-in protection resistance)
High level output current (3)
Low level output current (1)
Low level output current (2)
I
I
I
OH3
OL1
OL2
V
V
V
OH3=-1.0V
ADOUT
R02, R03, P00–P03
R00, R01
-100
3.0
3.0
-10
µA
mA
mA
OL1=0.9•VSS
OL2=0.9•VSS
(built-in protection resistance)
Low level output current (3)
Common output current
I
I
I
I
I
I
I
OL3
OH4
OL4
OH5
OL5
OH6
OL6
V
V
V
V
V
V
V
OL3=-2.0V
ADOUT
COM0–COM3
10
3
100
-3
µA
µA
µA
µA
µA
µA
µA
OH4=-0.05V
OL4=VL3+0.05V
OH5=-0.05V
Segment output current
(during LCD output)
Segment output current
(during DC output)
SEG0–SEG25
SEG0–SEG25
-3
OL5=VL3+0.05V
OH6=0.1•VSS
OL6=0.9•VSS
3
-300
300
S1C62N51 TECHNICAL HARDWARE
EPSON
I-67
CHAPTER 6: ELECTRICAL CHARACTERISTICS
S1 C6 2 L5 1
Un less oth erwise specified
VDD=0 V, VSS=-1.5 V, fosc=32,768 Hz, Ta=25°C, VS1, VL1, VL2 an d VL3 are in tern al
voltages, an d C1=C2=C3=C4=C5=C6=0.1 µF
Item
Symbol
Condition
Min
0.2•Vss
0.15•Vss
Vss
Vss
0
Typ
Max
0
0
0.8•Vss
0.85•Vss
0.5
Unit
V
V
V
V
High level input voltage (1)
High level input voltage (2)
Low level input voltage (1)
Low level input voltage (2)
High level input current (1)
VIH1
VIH2
VIL1
VIL2
K00–K03, P00–P03
RESET, TEST
K00~K03, P00–P03
RESET, TEST
I
I
I
I
IH1
V
IH1=0V
Without pull down resistor
IH2=0V
With pull down resistor
IH3=0V
With pull down resistor
K00–K03, P00–P03
µA
High level input current (2)
High level input current (3)
Low level input current
IH2
V
K00–K03
2.0
9.0
16
100
0
µA
µA
µA
IH3
IL
V
P00–P03
RESET, TEST
K00–K03, P00–P03
RESET, TEST
R02, R03, P00–P03
R00, R01
VIL=VSS
-0.5
High level output current (1)
High level output current (2)
I
I
OH1
OH2
V
V
OH1=0.1•VSS
OH2=0.1•VSS
-200
-200
µA
µA
(built-in protection resistance)
High level output current (3)
Low level output current (1)
Low level output current (2)
I
I
I
OH3
OL1
OL2
V
V
V
OH3=-1.5V
ADOUT
R02, R03, P00–P03
R00, R01
-100
700
700
-10
µA
µA
µA
OL1=0.9•VSS
OL2=0.9•VSS
(built-in protection resistance)
Low level output current (3)
Common output current
I
I
I
I
I
I
I
OL3
OH4
OL4
OH5
OL5
OH6
OL6
V
V
V
V
V
V
V
OL3=-1.0V
ADOUT
COM0–COM3
10
3
100
-3
µA
µA
µA
µA
µA
µA
µA
OH4=-0.05V
OL4=VL3+0.05V
OH5=-0.05V
Segment output current
(during LCD output)
Segment output current
(during DC output)
SEG0–SEG25
SEG0–SEG25
-3
OL5=VL3+0.05V
OH6=0.1•VSS
OL6=0.9•VSS
3
-100
130
I-68
EPSON
S1C62N51 TECHNICAL HARDWARE
CHAPTER 6: ELECTRICAL CHARACTERISTICS
6.4 Ana log Circ uit Cha ra c te ristic s a nd Powe r Curre nt Con-
sum p tion
S1 C6 2 N5 1 (Norm al Operat in g Mode)
Un less oth erwise specified
VDD=0 V, VSS=-3.0 V, fosc=32,768 Hz, Ta=25°C, CG=25 pF, VS1, VL1, VL2 an d VL3
are in tern al voltages, an d C1=C2=C3=C4=C5=C6=0.1 µF
(Du rin g A/ D con version : R1=49.8 kΩ, R2=50 kΩ, CAD=2,200 pF)
Item
Symbol
Condition
Min
Typ Max Unit
Internal voltage
V
V
V
V
L1
Connect 1MΩ load resistor between VDD and VL1 -1.15 -1.05 -0.95
(without panel load)
V
V
V
L2
Connect 1MΩ load resistor between VDD and VL2 2•VL1
(without panel load) -0.1
Connect 1MΩ load resistor between VDD and VL3 3•VL1
2•VL1
0.9
3•VL1
0.9
×
L3
(without panel load)
-0.1
×
SVD voltage
SVD circuit response time
Current consumption
SVD
-2.55 -2.40 -2.25
100
V
µs
µA
µA
µA
t
SVD
I
OP
During HALT
During execution *1
During A/D conversion (HALT)
1.0
2.5
30
2.5
5.0
40
Without panel load
*1 Th e SVD circu it is tu rn ed OFF.
S1 C6 2 N5 1 (Heavy Load Prot ect ion Mode)
Un less oth erwise specified
VDD=0 V, VSS=-3.0 V, fosc=32,768 Hz, Ta=25°C, CG=25 pF, VS1, VL1, VL2 an d VL3
are in tern al voltages, an d C1=C2=C3=C4=C5=C6=0.1 µF
(Du rin g A/ D con version : R1=49.8 kΩ, R2=50 kΩ, CAD=2,200 pF)
Item
Symbol
Condition
Min
Typ Max Unit
Internal voltage
V
V
V
V
L1
Connect 1MΩ load resistor between VDD and VL1 -1.15 -1.05 -0.95
(without panel load)
V
V
V
L2
Connect 1MΩ load resistor between VDD and VL2 2•VL1
(without panel load) -0.1
Connect 1MΩ load resistor between VDD and VL3 3•VL1
2•VL1
0.85
3•VL1
0.85
×
L3
(without panel load)
-0.1
×
SVD voltage
SVD circuit response time
Current consumption
SVD
-2.55 -2.40 -2.25
100
V
µs
µA
µA
µA
t
SVD
I
OP
During HALT
During execution *1
During A/D conversion (HALT)
2.0
5.5
31
5.5
10.0
41.5
Without panel load
*1 Th e SVD circu it is tu rn ed OFF.
S1C62N51 TECHNICAL HARDWARE
EPSON
I-69
CHAPTER 6: ELECTRICAL CHARACTERISTICS
S1 C6 2 L5 1 (Norm al Operat in g Mode)
Un less oth erwise specified
VDD=0 V, VSS=-1.5 V, fosc=32,768 Hz, Ta=25°C, CG=25 pF, VS1, VL1, VL2 an d VL3
are in tern al voltages, an d C1=C2=C3=C4=C5=C6=0.1 µF
(Du rin g A/ D con version : R1=49.8 kΩ, R2=50 kΩ, CAD=2,200 pF)
Item
Symbol
Condition
Min
Typ Max Unit
Internal voltage
V
V
V
V
L1
Connect 1MΩ load resistor between VDD and VL1 -1.15 -1.05 -0.95
(without panel load)
V
V
V
L2
Connect 1MΩ load resistor between VDD and VL2 2•VL1
(without panel load) -0.1
Connect 1MΩ load resistor between VDD and VL3 3•VL1
2•VL1
0.9
3•VL1
0.9
×
L3
(without panel load)
-0.1
×
SVD voltage
SVD circuit response time
Current consumption
SVD
-1.30 -1.20 -1.10
100
V
µs
µA
µA
µA
t
SVD
I
OP
During HALT
During execution *1
During A/D conversion (HALT)
1.0
2.5
30
2.5
5.0
40
Without panel load
*1 Th e SVD circu it is tu rn ed OFF.
S1 C6 2 L5 1 (Heavy Load Prot ect ion Mode)
Un less oth erwise specified
VDD=0 V, VSS=-1.5 V, fosc=32,768 Hz, Ta=25°C, CG=25 pF, VS1, VL1, VL2 an d VL3
are in tern al voltages, an d C1=C2=C3=C4=C5=C6=0.1 µF
(Du rin g A/ D con version : R1=49.8 kΩ, R2=50 kΩ, CAD=2,200 pF)
Item
Symbol
Condition
Min
Typ Max Unit
Internal voltage
V
V
V
V
L1
Connect 1MΩ load resistor between VDD and VL1 -1.15 -1.05 -0.95
(without panel load)
V
V
V
L2
Connect 1MΩ load resistor between VDD and VL2 2•VL1
(without panel load) -0.1
Connect 1MΩ load resistor between VDD and VL3 3•VL1
2•VL1
0.85
3•VL1
0.85
×
L3
(without panel load)
-0.1
×
SVD voltage
SVD circuit response time
Current consumption
SVD
-1.30 -1.20 -1.10
100
V
µs
µA
µA
µA
t
SVD
I
OP
During HALT
During execution *1
During A/D conversion (HALT)
2.0
5.5
31
5.5
10.0
41.5
Without panel load
*1 Th e SVD circu it is tu rn ed OFF.
I-70
EPSON
S1C62N51 TECHNICAL HARDWARE
CHAPTER 6: ELECTRICAL CHARACTERISTICS
S1 C6 2 N5 1 (CR, Norm al Operat in g Mode)
Un less oth erwise specified
VDD=0 V, VSS=-3.0 V, fosc=65 kHz, Ta=25°C, CG=25 pF, VS1, VL1, VL2 an d VL3 are
in tern al voltages, an d C1=C2=C3=C4=C5=C6=0.1 µF, Recom m en ded extern al resis-
tan ce for CR oscillation = 420 kΩ
(Du rin g A/ D con version : R1=49.8 kΩ, R2=50 kΩ, CAD=2,200 pF)
Item
Symbol
Condition
Min
Typ Max Unit
Internal voltage
V
V
V
V
L1
Connect 1MΩ load resistor between VDD and VL1 -1.15 -1.05 -0.95
(without panel load)
V
V
V
L2
Connect 1MΩ load resistor between VDD and VL2 2•VL1
(without panel load) -0.1
Connect 1MΩ load resistor between VDD and VL3 3•VL1
2•VL1
0.9
3•VL1
0.9
×
L3
(without panel load)
-0.1
×
SVD voltage
SVD circuit response time
Current consumption
SVD
-2.55 -2.40 -2.25
100
V
µs
µA
µA
µA
t
SVD
I
OP
During HALT
During execution *1
During A/D conversion (HALT)
8.0
15.0 20.0
37 52.5
15.0
Without panel load
*1 Th e SVD circu it is tu rn ed OFF.
S1 C6 2 N5 1 (CR, Heavy Load Prot ect ion Mode)
Un less oth erwise specified
VDD=0 V, VSS=-3.0 V, fosc=65 kHz, Ta=25°C, CG=25 pF, VS1, VL1, VL2 an d VL3 are
in tern al voltages, an d C1=C2=C3=C4=C5=C6=0.1 µF, Recom m en ded extern al resis-
tan ce for CR oscillation = 420 kΩ
(Du rin g A/ D con version : R1=49.8 kΩ, R2=50 kΩ, CAD=2,200 pF)
Item
Symbol
Condition
Min
Typ Max Unit
Internal voltage
V
V
V
V
L1
Connect 1MΩ load resistor between VDD and VL1 -1.15 -1.05 -0.95
(without panel load)
V
V
V
L2
Connect 1MΩ load resistor between VDD and VL2 2•VL1
(without panel load) -0.1
Connect 1MΩ load resistor between VDD and VL3 3•VL1
2•VL1
0.85
3•VL1
0.85
×
L3
(without panel load)
-0.1
×
SVD voltage
SVD circuit response time
Current consumption
SVD
-2.55 -2.40 -2.25
100
V
µs
µA
µA
µA
t
SVD
I
OP
During HALT
During execution *1
16.0 30.0
30.0 40.0
Without panel load
During A/D conversion (HALT)
45
57.5
*1 Th e SVD circu it is tu rn ed OFF.
S1C62N51 TECHNICAL HARDWARE
EPSON
I-71
CHAPTER 6: ELECTRICAL CHARACTERISTICS
S1 C6 2 L5 1 (CR, Norm al Operat in g Mode)
Un less oth erwise specified
VDD=0 V, VSS=-1.5 V, fosc=65 kHz, Ta=25°C, CG=25 pF, VS1, VL1, VL2 an d VL3 are
in tern al voltages, an d C1=C2=C3=C4=C5=C6=0.1 µF, Recom m en ded extern al resis-
tan ce for CR oscillation = 420 kΩ
(Du rin g A/ D con version : R1=49.8 kΩ, R2=50 kΩ, CAD=2,200 pF)
Item
Symbol
Condition
Min
Typ Max Unit
Internal voltage
V
V
V
V
L1
Connect 1MΩ load resistor between VDD and VL1 -1.15 -1.05 -0.95
(without panel load)
V
V
V
L2
Connect 1MΩ load resistor between VDD and VL2 2•VL1
(without panel load) -0.1
Connect 1MΩ load resistor between VDD and VL3 3•VL1
2•VL1
0.9
3•VL1
0.9
×
L3
(without panel load)
-0.1
×
SVD voltage
SVD circuit response time
Current consumption
SVD
-1.30 -1.20 -1.10
100
V
µs
µA
µA
µA
t
SVD
I
OP
During HALT
During execution *1
During A/D conversion (HALT)
8.0
15.0 20.0
37 52.5
15.0
Without panel load
*1 Th e SVD circu it is tu rn ed OFF.
S1 C6 2 L5 1 (CR, Heavy Load Prot ect ion Mode)
Un less oth erwise specified
VDD=0 V, VSS=-1.5 V, fosc=65 kHz, Ta=25°C, CG=25 pF, VS1, VL1, VL2 an d VL3 are
in tern al voltages, an d C1=C2=C3=C4=C5=C6=0.1 µF, Recom m en ded extern al resis-
tan ce for CR oscillation = 420 kΩ
(Du rin g A/ D con version : R1=49.8 kΩ, R2=50 kΩ, CAD=2,200 pF)
Item
Symbol
Condition
Min
Typ Max Unit
Internal voltage
V
V
V
V
L1
Connect 1MΩ load resistor between VDD and VL1 -1.15 -1.05 -0.95
(without panel load)
V
V
V
L2
Connect 1MΩ load resistor between VDD and VL2 2•VL1
(without panel load) -0.1
Connect 1MΩ load resistor between VDD and VL3 3•VL1
2•VL1
0.85
3•VL1
0.85
×
L3
(without panel load)
-0.1
×
SVD voltage
SVD circuit response time
Current consumption
SVD
-1.30 -1.20 -1.10
100
V
µs
µA
µA
µA
t
SVD
I
OP
During HALT
During execution *1
16.0 30.0
30.0 40.0
Without panel load
During A/D conversion (HALT)
45
57.5
*1 Th e SVD circu it is tu rn ed OFF.
I-72
EPSON
S1C62N51 TECHNICAL HARDWARE
CHAPTER 6: ELECTRICAL CHARACTERISTICS
6.5 Osc illa tion Cha ra c te ristic s
Oscillation ch aracteristics will vary accordin g to differen t con dition s. Use th e
followin g ch aracteristics are as referen ce valu es.
S1 C6 2 N5 1
Un less oth erwise specified
VDD=0 V, VSS=-3.0 V, Crystal : Q13MC146, CG=25 pF, CD=bu ilt-in , Ta=25°C
Item
Symbol
Vsta
(Vss)
Vstp
Condition
Min
-1.8
Typ Max Unit
Oscillation start voltage
t
t
sta≤5sec
V
Oscillation stop voltage
stp≤10sec
-1.8
V
(Vss)
Built-in capacity (drain)
C
D
Including the parasitic capacity inside the IC
Vss=-1.8 to -3.5V
20
pF
ppm
ppm
ppm
V
Frequency voltage deviation f/V
Frequency IC deviation f/IC
Frequency adjustment range f/C
Higher harmonic oscillation
start voltage
5
10
-10
40
G
C
C
G
=5–25pF
V
hho
G=5pF
-3.5
(Vss)
leak Between OSC1 and VDD
and between VSS and OSC1
Allowable leak resistance
R
,
200
MΩ
S1 C6 2 L5 1
Un less oth erwise specified
VDD=0 V, VSS=-1.5 V, Crystal : Q13MC146, CG=25 pF, CD=bu ilt-in , Ta=25°C
Item
Symbol
Vsta
(Vss)
Vstp
Condition
Min
-1.1
Typ Max Unit
Oscillation start voltage
t
t
sta≤5sec
V
Oscillation stop voltage
stp≤10sec
-1.1
(-0.9)*1
V
(Vss)
Built-in capacity (drain)
C
D
Including the parasitic capacity inside the IC
Vss=-1.1 to -2.0V (-0.9)*1
20
pF
ppm
ppm
ppm
V
Frequency voltage deviation f/V
Frequency IC deviation f/IC
Frequency adjustment range f/C
Higher harmonic oscillation
start voltage
5
10
-10
40
G
C
C
G
=5–25pF
V
hho
G=5pF
-2.0
(Vss)
leak Between OSC1 and VDD
and between VSS and OSC1
Allowable leak resistance
R
,
200
MΩ
*1 Item s en closed in paren th eses ( ) are th ose u sed wh en operatin g at h eavy load
protection m ode.
S1C62N51 TECHNICAL HARDWARE
EPSON
I-73
CHAPTER 6: ELECTRICAL CHARACTERISTICS
S1 C6 2 N5 1 (CR)
Un less oth erwise specified
VDD=0 V, VSS=-3.0 V, RCR=420 kΩ, Ta=25°C
Item
Symbol
fosc
Vsta
Condition
Min
-20
-1.8
Typ
65kHz
Max
20
Unit
%
V
ms
V
Oscillation frequency dispersion
Oscillation start voltage
Oscillation start time
t
sta Vss=-1.8 to -3.5V
Vstp
3
Oscillation stop voltage
-1.8
S1 C6 2 L5 1 (CR)
Un less oth erwise specified
VDD=0 V, VSS=-1.5 V, RCR=420 kΩ, Ta=25°C
Item
Symbol
fosc
Vsta
Condition
Min
-20
-1.1
Typ
65kHz
Max
20
Unit
%
V
ms
V
Oscillation frequency dispersion
Oscillation start voltage
Oscillation start time
t
sta Vss=-1.1 to -2.0V
Vstp
3
Oscillation stop voltage
-1.1
I-74
EPSON
S1C62N51 TECHNICAL HARDWARE
CHAPTER 7: PACKAGE
CHAPTER 7
PACKAGE
7.1 Pla stic Pa c ka g e
QFP6-64 pin
±0.4
±0.2
16.8
14.0
48
33
49
32
Index
64
17
1
16
±0.15
±0.15
0.8
0.35
0~12°
0.6 ±0.3
1.4
S1C62N51 TECHNICAL HARDWARE
EPSON
I-75
CHAPTER 7: PACKAGE
Ce ra m ic Pa c ka g e for Te st Sa m p le s
7.2
QFP6-60 pin
±0.3
17.6
±0.2
14.0
45
31
46
30
60
16
1
15
±0.15
±0.15
0.8
0.35
1.0
5° ±5°
±0.2
0.7
1.8
I-76
EPSON
S1C62N51 TECHNICAL HARDWARE
CHAPTER 8: PAD LAYOUT
CHAPTER 8
PAD LAYOUT
8.1 Dia g ra m of Pa d La yout
DIE No.
60
14 13 12 11 10
9
8
7
6
5
4
3
2
1
15
59
58
57
56
55
16
17
18
19
20
21
22
23
24
Y
54
53
52
X
(0, 0)
25
26
27
28
51
50
49
29
30
48
47
46
45
44
31 32 33 34 35 36 37 38 39
40
41 42 43
3.58 mm
S1C62N51 TECHNICAL HARDWARE
EPSON
I-77
CHAPTER 8: PAD LAYOUT
8.2 Pa d Coord ina te s
Pad No Pad name
X
Y
Pad No Pad name
X
Y
1
COM3 1,340.4 1,808.4
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
P00 -1,584.8 -1,808.0
P01 -1,424.0 -1,808.0
P02 -1,260.8 -1,808.0
P03 -1,100.0 -1,808.0
RESET -904.4 -1,808.0
2
SEG0
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
SEG10
745.2 1,808.4
585.2 1,808.4
425.2 1,808.4
265.2 1,808.4
105.2 1,808.4
-54.8 1,808.4
-214.8 1,808.4
-374.8 1,808.4
-534.8 1,808.4
-694.8 1,808.4
-854.8 1,808.4
3
4
5
6
K00
K01
K02
K03
R00
R01
R02
R03
CS
-744.8 -1,808.0
-579.2 -1,808.0
-418.4 -1,808.0
-252.8 -1,808.0
-17.2 -1,808.0
282.8 -1,808.0
508.8 -1,808.0
668.4 -1,808.0
1,630.4 -1,784.8
1,630.4 -1,624.8
1,630.4 -1,464.8
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
SEG11 -1,014.8 1,808.4
SEG12 -1,174.8 1,808.4
TEST -1,630.8 1,612.4
SEG13 -1,630.8 1,367.6
SEG14 -1,630.8 1,207.6
SEG15 -1,630.8 1,047.6
RS
TH
ADOUT 1,630.4 -1,264.8
1,630.4 -1,014.8
V
DD
SEG16 -1,630.8
SEG17 -1,630.8
SEG18 -1,630.8
SEG19 -1,630.8
SEG20 -1,630.8
SEG21 -1,630.8
887.6
727.6
567.6
407.6
247.6
87.6
OSC1 1,630.4 -787.2
OSC2 1,630.4 -627.6
V
SS
1,630.4 -467.6
CA
CB
CC
1,630.4
1,630.4
1,630.4
1,630.4
175.6
335.6
495.6
954.4
SEG22 -1,630.8 -152.8
SEG23 -1,630.8 -312.8
SEG24 -1,630.8 -472.8
SEG25 -1,630.8 -632.8
V
V
V
L1
L2
L3
1,630.4 1,114.4
1,630.4 1,274.4
COM0 1,630.4 1,434.0
COM1 1,630.4 1,595.6
COM2 1,630.4 1,755.2
V
V
DD -1,630.8 -933.6
S1
-1,630.8 -1,093.2
Chip size X: 3.58 (mm)
Y: 3.93 (mm)
I-78
EPSON
S1C62N51 TECHNICAL HARDWARE
S1C62N51
II. Technical Software
CONTENTS
CONTENTS
CHAPTER 1
CONFIGURATION ........................................................... II-1
1.1 S1C62N51 Block Diagram ............................................. II-1
1.2 ROM Map ....................................................................... II-2
1.3 Interrupt Vectors ............................................................. II-3
1.4 Data Memory Map .......................................................... II-4
CHAPTER 2
CHAPTER 3
INITIAL RESET ................................................................... II-7
2.1 Internal Register Status on Initial Reset ......................... II-7
2.2 Initialize Program Example............................................. II-9
PERIPHERAL CIRCUITS .................................................... II-11
3.1 Input Ports ..................................................................... II-11
In pu t port m em ory m ap .......................................... II-11
Con trol of th e in pu t port ......................................... II-12
Exam ples of in pu t port con trol program .................. II-12
3.2 Output Ports .................................................................. II-14
Ou tpu t port m em ory m ap ........................................ II-14
Con trol of th e ou tpu t port ....................................... II-14
Exam ples of ou tpu t port con trol program ................ II-14
3.3 Special Use Output Ports .............................................. II-16
Special u se ou tpu t port m em ory m ap ...................... II-16
Con trol of th e special u se ou tpu t port ..................... II-16
Examples of special u se ou tpu t port control program . II-17
S1C62N51 TECHNICAL SOFTWARE
EPSON
II-i
CONTENTS
3.4 I/O Ports ........................................................................ II-19
I/ O port m em ory m ap ............................................. II-19
Con trol of th e I/ O port ............................................ II-19
Exam ples of I/ O port con trol program ..................... II-20
3.5 LCD Driver..................................................................... II-23
LCD driver m em ory m ap ......................................... II-23
Con trol of th e LCD driver ........................................ II-23
Exam ples of LCD driver con trol program ................. II-25
3.6 Timer ............................................................................. II-27
Tim er m em ory m ap ................................................. II-27
Con trol of th e tim er ................................................. II-28
Exam ples of tim er con trol program .......................... II-29
3.7 A/D Converter................................................................ II-31
A/ D con verter m em ory m ap .................................... II-31
Con trol of th e A/ D con verter ................................... II-32
Exam ples of A/ D con verter con trol program ............ II-35
3.8 Supply Voltage Detection (SVD) Circuit
and Heavy Load Protection Function ............................ II-48
SVD circu it an d h eavy load protection
fu n ction m em ory m ap ............................................. II-48
Con trol of th e SVD circu it ....................................... II-49
Exam ple of SVD circu it con trol program .................. II-49
Heavy load protection fu n ction ................................ II-50
Exam ples of h eavy load protection
fu n ction con trol program ......................................... II-52
3.9 Interrupt and Halt........................................................... II-55
In terru pt m em ory m ap ............................................ II-55
Con trol of in terru pts an d h alt ................................. II-56
Exam ples of in terru pt an d h alt con trol program ...... II-63
II-ii
EPSON
S1C62N51 TECHNICAL SOFTWARE
CONTENTS
CHAPTER 4
APPENDIX
SUMMARY OF PROGRAMMING POINTS....................... II-66
A
B
C
D
Table of Instructions ...................................................... II-70
RAM Map ...................................................................... II-75
Table of the ICE Commands ......................................... II-77
Cross-assembler Pseudo-instruction List ...................... II-79
S1C62N51 TECHNICAL SOFTWARE
EPSON
II-iii
CHAPTER 1: CONFIGURATION
CHAPTER 1
CONFIGURATION
1.1 S1C62N51 Bloc k Dia g ra m
ROM
System Reset
Control
OSC
1,024 words x 12 bits
Core CPU S1C6200A
RAM
80 words x 4 bits
Interrupt
Generator
COM0–3
SEG0–25
K00–03
TEST
Input Port
Test Port
LCD Driver
VDD
V
L1–3
I/O Port
Output Port
Timer
P00–03
R00–03
Power
Controller
CA–CC
VS1
VSS
SVD
ADOUT
RS
TH
FOUT / BUZZER
BUZZER
Fout & Buzzer
A/D Converter
CS
Fig. 1.1.1
S1C62N51 block diagram
S1C62N51 TECHNICAL SOFTWARE
EPSON
II-1
CHAPTER 1: CONFIGURATION
1.2 ROM Ma p
Th e S1C62N51 h as a bu ilt-in m ask ROM with a capacity of
1,024 steps × 12 bits for program storage. Th e con figu ration
of th e ROM is sh own in Figu re 1.2.1.
Bank 0
00H step
01H step
Program start address
Interrupt vector area
0 page
1 page
2 page
3 page
07H step
08H step
Program area
FFH step
12 bits
Fig. 1.2.1
Configuration of built-in ROM
II-2
EPSON
S1C62N51 TECHNICAL SOFTWARE
CHAPTER 1: CONFIGURATION
1.3 Inte rrup t Ve c tors
Wh en an in terru pt requ est is received by th e CPU, th e CPU
in itiates th e followin g in terru pt processin g after com pletin g
th e in stru ction bein g execu ted.
(1) Th e address of th e n ext in stru ction to be execu ted (th e
valu e of th e program cou n ter) is saved on th e stack
(RAM).
(2) Th e in terru pt vector address correspon din g to th e in ter-
ru pt requ est is loaded in to th e program cou n ter.
(3) Th e bran ch in stru ction written in th e vector is execu ted
to bran ch to th e software in terru pt processin g rou tin e.
Steps 1 and 2 require 12 cycles of the CPU system clock.
Note
Th e in terru pt vectors are sh own in Table 1.3.1.
Table 1.3.1
Page
Step
00H
01H
02H
03H
04H
05H
06H
07H
Interrupt vector
Interrupt requests and vectors
Initial reset
Clock timer interrupt
A/D interrupt
Clock timer interrupt and A/D interrupt
Input (K00–K03) interrupt
Input interrupt and clock timer interrupt
Input interrupt and A/D interrupt
Generation of all interrupt
1
Addresses (start address of in terru pt processin g rou tin es) to
ju m p to are written in to th e addresses available for in terru pt
vector allocation .
S1C62N51 TECHNICAL SOFTWARE
EPSON
II-3
CHAPTER 1: CONFIGURATION
1.4 Da ta Me m ory Ma p
Th e S1C62N51 bu ilt-in RAM h as 80 words of data m em ory,
32 words of display m em ory for th e LCD, an d I/ O m em ory
for con trollin g th e periph eral circu it. Wh en writin g pro-
gram s, n ote th e followin g:
(1) Sin ce th e stack area is in th e data m em ory area, take
care n ot to overwrite th e stack with data. Su brou tin e
calls or in terru pts u se 3 words on th e stack.
(2) Data m em ory addresses 000H–00FH are m em ory register
areas th at are addressed with register poin ter RP.
Address
Low
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
Page
High
0
M0 M1 M2 M3 M4 M5 M6 M7 M8 M9 MA MB MC MD ME MF
1
2
RAM area (000H–04FH)
80 words x 4 bits (R/W)
3
4
5
6
7
0
8
9
Display memory area (090H–0AFH)
32 words x 4 bits (Write only)
A
B
C
D
E
F
I/O memory area Table 4.1.1(a), (b)
Unused area
Fig. 1.4.1
Data memory map
Note Memory is not mounted in unused area within the memory map
and in memory area not indicated in this chapter. For this reason,
normal operation cannot be assured for programs that have been
prepared with access to these areas.
II-4
EPSON
S1C62N51 TECHNICAL SOFTWARE
CHAPTER 1: CONFIGURATION
Table 1.4.1(a) I/O memory map 1
Register
Address
Comment
*1
D3
D2
D1
D0
Name
K03
K02
K01
K00
TM3
TM2
TM1
TM0
TC3
TC2
TC1
TC0
TC7
TC6
TC5
TC4
TC11
TC10
TC9
TC8
TC15
TC14
TC13
TC12
EIK03
EIK02
EIK01
EIK00
0
Init
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
0
0
0
0
1
0
Low
Low
Low
Low
Low
Low
Low
Low
0
*2
*2
*2
*2
*3
*3
*3
*3
*3
*3
*3
*3
*3
*3
*3
*3
*3
*3
*3
*3
*3
*3
*3
*3
High
Input port data K03
K03
K02
K01
K00
High
Input port data K02
0E0H
0E3H
0E4H
0E5H
0E6H
0E7H
0E8H
0EBH
0ECH
0EDH
0EFH
High
Input port data K01
R
High
Input port data K00
High
Clock timer data 2 Hz
TM3
TC3
TM2
TC2
TM1
TC1
TM0
TC0
High
Clock timer data 4 Hz
High
Clock timer data 8 Hz
R
High
Clock timer data 16 Hz
1
Up/down counter data TC3
Up/down counter data TC2
Up/down counter data TC1
Up/down counter data TC0 (LSB)
Up/down counter data TC7
Up/down counter data TC6
Up/down counter data TC5
Up/down counter data TC4
Up/down counter data TC11
Up/down counter data TC10
Up/down counter data TC9
Up/down counter data TC8
Up/down counter data TC15 (MSB)
Up/down counter data TC14
Up/down counter data TC13
Up/down counter data TC12
Interrupt mask register K03
Interrupt mask register K02
Interrupt mask register K01
Interrupt mask register K00
1
0
1
0
R/W
R/W
R/W
R/W
R/W
1
0
1
0
TC7
TC6
TC5
TC4
1
0
1
0
1
0
1
0
TC11
TC15
EIK03
TC10
TC14
EIK02
EIT2
TC9
TC8
1
0
1
0
1
0
1
1
0
TC13
EIK01
TC12
EIK00
EIT32
0
1
0
1
0
Enable
Enable
Enable
Enable
Mask
Mask
Mask
Mask
*5
0
R
0
EIT8
R/W
0
Enable
Enable
Enable
Mask
Mask
Mask
Interrupt mask register (clock timer) 2 Hz
Interrupt mask register (clock timer) 8 Hz
Interrupt mask register (clock timer) 32 Hz
EIT2
EIT8
EIT32
0
0
0
0
*5
*5
*5
0
R
0
EIAD
R/W
IK0
0
0
Enable
Mask
Interrupt mask register (A/D)
EIAD
0
0
*5
*5
*5
*4
*5
*4
*4
*4
0
0
0
0
0
R
R
Yes
No
Interrupt factor flag (K00–K03)
IK0
0
0
IT2
IT8
IT32
Yes
Yes
Yes
No
No
No
Interrupt factor flag (clock timer) 2 Hz
Interrupt factor flag (clock timer) 8 Hz
Interrupt factor flag (clock timer) 32 Hz
IT2
0
0
0
IT8
IT32
*1 In itial valu e followin g in itial reset
*2 Not set in th e circu it
*3 Un defin ed
*4 Reset (0) im m ediately after bein g read
*5 Always "0" wh en bein g read
*6 Refer to m ain m an u al
S1C62N51 TECHNICAL SOFTWARE
EPSON
II-5
CHAPTER 1: CONFIGURATION
Table 1.4.1(b) I/O memory map 2
Register
Address
Comment
*1
D3
D2
D1
D0
IAD
Name
Init
0
1
0
*5
*5
*5
*4
*5
*5
*5
0
0
0
0
0
0F0H
0F1H
0
R
Yes
No
Interrupt factor flag (A/D)
IAD
0
0
0
0
ADRUN
R/W
0
0
R
Start
High
High
High
On
High
On
High
High
High
High
1
Stop
Low
Low
Low
Off
Low
Off
Low
Low
Low
Low
0
A/D conversion Start/Stop
Output port data R03
Output port data R02
Output port data R01
Buzzer On/Off control register
Output port data R00
Frequency output control register
I/O port data P03
ADRUN
R03
R02
R01
BUZZER
R00
FOUT
P03
P02
P01
P00
C3
0
0
0
0
0
0
0
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
R01
R00
R03
R02
BUZZER
FOUT
0F3H
R/W
*2
*2
*2
*2
*3
*3
*3
*3
*3
*3
*3
*3
*3
*3
*3
*3
*3
*3
*3
*3
P03
C3
P02
C2
P01
C1
C5
C9
C13
0
P00
C0
I/O port data P02
0F4H
0F5H
0F6H
0F7H
0F8H
0F9H
0FAH
0FBH
0FCH
0FDH
0FEH
I/O port data P01
R/W
R/W
R/W
R/W
R/W
I/O port data P00
Up-counter data C3
Up-counter data C2
Up-counter data C1
Up-counter data C0 (LSB)
Up-counter data C7
Up-counter data C6
Up-counter data C5
Up-counter data C4
Up-counter data C11
Up-counter data C10
Up-counter data C9
Up-counter data C8
Up-counter data C15 (MSB)
Up-counter data C14
Up-counter data C13
Up-counter data C12
1
0
C2
1
0
C1
1
0
C0
1
0
C7
C7
C6
C4
1
0
C6
1
0
C5
1
0
C4
1
0
C11
C10
C9
C11
C15
0
C10
C14
C8
1
0
1
0
1
0
C8
1
0
C15
C14
C13
C12
0
C12
1
0
1
0
1
0
*5
*5
*5
*5
0
R
0
TMRST
W
0
0
Reset
Heavy
–
Clock timer reset
TMRST
HLMOD
0
Reset
0
Normal Heavy load protection mode register
HLMOD
R/W
SVDDT SVDON
R/W
*5
Low
On
Normal Supply voltage detection data
SVDDT
SVDON
CSDC
0
0
0
0
R
Off
Supply voltage detection circuit On/Off
Static
Dynamic LCD drive switch
CSDC
R/W
0
0
R
0
0
*5
*5
*5
*5
*5
*5
0
0
0
0
0
R
0
IOC
R/W
0
0
Out
In
I/O port I/O control register
IOC
XBZR
0
0
0
2 kHz
4 kHz
Buzzer frequency control
XBZR
R/W
0
XFOUT1 XFOUT0
R/W
*5
*6
*6
FOUT frequency control
FOUT frequency control
XFOUT1
XFOUT0
0
0
0
R
0
*5
*5
*5
0
ADCLK
R/W
0
0
R
65 kHz
32 kHz
A/D clock selection 65 kHz/32 kHz
ADCLK
0
II-6
EPSON
S1C62N51 TECHNICAL SOFTWARE
CHAPTER 2: INITIAL RESET
CHAPTER 2
INITIAL RESET
2.1 Inte rna l Re g iste r Sta tus on Initia l Re se t
Followin g an in itial reset, th e in tern al registers an d in tern al
data m em ory area are in itialized to th e valu es sh own in
Tables 2.1.1 an d 2.1.2.
Table 2.1.1
Internal register
Bit length
Initial value following reset
Initial values of internal
registers
Program counter step PCS
Program counter page PCP
8
4
4
8
8
8
4
4
4
1
1
1
1
00H
1H
New page pointer
Stack pointer
Index register
Index register
Register pointer
General register
General register
Interrupt flag
Decimal flag
Zero flag
NPP
SP
X
1H
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
0
Y
RP
A
B
I
D
0
Z
Undefined
Undefined
Carry flag
C
Table 2.1.2
Initial values of internal data
memory area
Internal data
memory area
RAM data
Initial value
following reset
Bit length
Address
4 × 80
4 × 32
Undefined
Undefined
000H–04FH
090H–0AFH
0E0H–0FEH
Display memory
Internal I/O register
See Tables 1.4.1(a) and (b)
S1C62N51 TECHNICAL SOFTWARE
EPSON
II-7
CHAPTER 2: INITIAL RESET
After an in itial reset, th e program cou n ter page (PCP) is
in itialized to 1H, an d th e program cou n ter step (PCS), to
00H. Th is is wh y th e program is execu ted from step 00H of
th e first page.
Th e in itial valu es of som e in tern al registers an d in tern al
data m em ory area location s are u n defin ed after a reset. Set
th em as n ecessary to th e proper in itial valu es in th e pro-
gram .
Th e periph eral I/ O fu n ction s (m em ory-m apped I/ O) are
assign ed to in tern al data m em ory area addresses 0E0H to
0FEH. Each address represen ts a 4-bit in tern al I/ O register,
allowin g access to th e periph eral fu n ction s in 1-word (4-bit)
read/ write u n its.
II-8
EPSON
S1C62N51 TECHNICAL SOFTWARE
CHAPTER 2: INITIAL RESET
2.2 Initia lize Prog ra m Exa m p le
Th e followin g is a program th at clears th e RAM, LCD, Up/
down cou n ter an d Up-cou n ter, resets th e flags, registers an d
tim er, an d sets th e stack poin ter im m ediately after resettin g
th e system .
Label
Mnemonic/operand
Comment
ORG
JP
100H
INIT
;Jump to "INIT"
;
ORG
RST
110H
F,0011B
INIT
;
;Interrupt mask, decimal
;adjustment off
LD
LDPX
CP
X,0
MX,0
XH,5H
;
;
;
RAMCLR
Clear RAM (00H–4FH)
JP
LD
NZ,RAMCLR
X,90H
;
;
LCDCLR
;
LDPX
CP
JP
MX,0
XH,0BH
NZ,LCDCLR
;
;
;
Clear LCD (90H–AFH)
LD
LD
LD
LD
A,0
B,4
SPL,A
SPH,B
;
;
;
;
Set stack pointer to 40H
;
;
LD
OR
X,0F9H
MX,0001B
;
;
Reset clock timer
LD
X,0E4H
MX,0
;
;
Clear Up/down counter
UDCNTCLR LDPX
CP
JP
LD
LDPX
CP
XL,8H
NZ,UDCNTCLR ;
X,0F5H
MX,0
XL,9H
;
(0E4H–0E7H)
;
;
;
;
Clear Up-counter
(0F5H–0F8H)
UCLR
JP
NZ,UCLR
;
;
;
LD
OR
X,0EBH
MX,0111B
;
;
Enable timer interrupt
LD
OR
X,0E8H
MX,1111B
;
;
Enable input interrupt
(K03–K00)
LD
LD
LD
LD
RST
EI
X,0
Y,0
A,0
B,0
F,0
;
;
;
;
;
Reset register flags
;Enable interrupt
S1C62N51 TECHNICAL SOFTWARE
EPSON
II-9
CHAPTER 2: INITIAL RESET
Th e above program is a basic in itialization program for th e
S1C62N51. Figu re 2.2.1 is th e flow ch art for th is program .
Th e settin g data are all in itialized as sh own in th e flow ch art
by execu tin g th is program . Wh en u sin g th is program , add
settin g item s n ecessary for each specific application .
Initialization
Reset
I : Interrupt flag
I (Interrupt flag)
D : Decimal adjustment flag
D (Decimal adjustment flag)
Clear data RAM (00H to 04FH)
Clear segment RAM (90H to 0AFH)
Clear RAM
Set SP
Set stack pointer to 40H
Reset clock timer
Clear Up/down counter,
Up-counter
Enable timer interrupt 2 Hz, 8 Hz, 32 Hz
Enable K03–K00 input port interrupt
Enable timer interrupt
Enable input interrupt
Reset registers (X, Y, A, B)
flags (I, Z, D, C)
EI (enable interrupt)
Fig. 2.2.1
Flow chart of the initialization
program
To next process
II-10
EPSON
S1C62N51 TECHNICAL SOFTWARE
CHAPTER 3: PERIPHERAL CIRCUITS (Input Ports)
CHAPTER 3
PERIPHERAL CIRCUITS
Details on h ow to con trol th e S1C62N51 periph eral circu it is
given in th is ch apter.
3.1
Inp ut Ports
Inp ut p ort m e m ory
m a p
Table 3.1.1 I/O memory map
Register
Address
Comment
Input port data K03
*1
D3
D2
D1
D0
Name
K03
K02
K01
K00
EIK03
EIK02
EIK01
EIK00
0
Init
–
1
0
*2
*2
*2
*2
High
Low
K03
K02
K01
K00
High
Low
Input port data K02
–
0E0H
0E8H
0EDH
High
Low
Input port data K01
–
R
R/W
R
High
Low
Input port data K00
–
Enable
Enable
Enable
Enable
Mask
Mask
Mask
Mask
Interrupt mask register K03
Interrupt mask register K02
Interrupt mask register K01
Interrupt mask register K00
0
EIK03
EIK02
EIK01
EIK00
IK0
0
0
0
*5
*5
*5
*4
0
0
0
0
0
Yes
No
Interrupt factor flag (K00–K03)
IK0
0
*1 In itial valu e followin g in itial reset
*2 Not set in th e circu it
*3 Un defin ed
*4 Reset (0) im m ediately after bein g read
*5 Always "0" wh en bein g read
*6 Refer to m ain m an u al
S1C62N51 TECHNICAL SOFTWARE
EPSON
II-11
CHAPTER 3: PERIPHERAL CIRCUITS (Input Ports)
Th e S1C62N51 h as on e 4-bit in pu t port (K00–K03). In pu t
Control of
port data can be read as a 4-bit u n it (K00–K03).
the inp ut p ort
Th e state of th e in pu t ports can be obtain ed by readin g th e
data (bits D3, D2, D1, D0) of address 0E0H. Th e in pu t ports
can be u sed to sen d an in terru pt requ est to th e CPU via th e
in pu t in terru pt con dition flag. See Section 3.9 "In terru pt
an d Halt", for details.
• Loadin g K0 0 –K0 3 in t o t h e A regist er
Exa m p le s of inp ut
p ort c ontrol
p rog ra m
Label
Mnemonic/operand
Comment
LD
LD
Y,0E0H
A,MY
;Set address of port
;A register ← K00–K03
As sh own in Figu re 3.1.1, th e two in stru ction steps above
load th e data of th e in pu t port in to th e A register.
D3
D2
D1
D0
A register
K03 K02 K01 K00
Fig. 3.1.1
Loading the A register
Th e data of th e in pu t port can be loaded in to th e B register
or MX in stead of th e A register.
II-12
EPSON
S1C62N51 TECHNICAL SOFTWARE
CHAPTER 3: PERIPHERAL CIRCUITS (Input Ports)
• Bit -u n it ch eck in g of in pu t port s
Label
Mnemonic/operand
Comment
DI
;Disable interrupt
LD
Y,0E0H
;Set address of port
INPUT1: FAN
MY,0010B
NZ,INPUT1
MY,0010B
Z,INPUT2
;
JP
INPUT2: FAN
JP
;Loop until K01 becomes "0"
;
;Loop until K01 becomes "1"
Th is program loopes u n til a risin g edge is in pu t to in pu t port
K01.
Th e in pu t port can be addressed u sin g th e X register in stead
of th e Y register.
Note When the input port is changed from high level to low level with a
pull-down resistor, the signal falls following a certain delay caused
by the time constants of the pull-down resistance and the input
gate capacitance. It is therefore necessary to observe a proper
wait time before the input port data is read.
S1C62N51 TECHNICAL SOFTWARE
EPSON
II-13
CHAPTER 3: PERIPHERAL CIRCUITS (Output Ports)
3.2 Outp ut Ports
Outp ut p ort
m e m ory m a p
Table 3.2.1 I/O memory map
Register
Address
Comment
Output port data R03
*1
D3
D2
D1
D0
Name
R03
Init
0
1
0
High
High
High
On
Low
Low
Low
Off
R01
R00
R03
R02
Output port data R02
R02
0
BUZZER
FOUT
Output port data R01
R01
0
0F3H
Buzzer On/Off control register
Output port data R00
BUZZER
R00
0
R/W
High
On
Low
Off
0
Frequency output control register
FOUT
0
*1 In itial valu e followin g in itial reset
*2 Not set in th e circu it
*3 Un defin ed
*4 Reset (0) im m ediately after bein g read
*5 Always "0" wh en bein g read
*6 Refer to m ain m an u al
Th e S1C62N51 h as 4 bits for gen eral ou tpu t ports (R00–
R03). R00 an d R01 alth ou gh can be u se for special u se
ou tpu t port as sh own in later of th is section . Th e ou tpu t
port is a read/ write register, ou tpu t pin s provide th e con -
ten ts of th e register. Th e states of th e ou tpu t ports (R00–
R03) are decided by th e data of address 0F3H. Ou tpu t ports
can also be read, an d ou tpu t con trol is possible u sin g th e
operation in stru ction s (AND, OR, etc.). Th e ou tpu t ports are
all in itialized to low level (0) after an in itial reset.
Control of
the outp ut p ort
• Loadin g B regist er dat a in t o R0 0 –R0 3
Exa m p le s of outp ut
p ort c ontrol
Label
Mnemonic/operand
Comment
p rog ra m
LD
LD
Y,0F3H
MY,B
;Set address of port
;R00–R03 ← B register
As sh own in Figu re 3.2.1, th e two in stru ction steps above
load th e data of th e B register in to th e ou tpu t ports.
II-14
EPSON
S1C62N51 TECHNICAL SOFTWARE
CHAPTER 3: PERIPHERAL CIRCUITS (Output Ports)
D3
D2
D1
D0
B register
R00
R01
R02
R03
Data register
Data register
Data register
Data register
Fig. 3.2.1
Control of the output port
Th e ou tpu t data can be taken from th e A register, MX, or
im m ediate data in stead of th e B register.
• Bit -u n it operat ion of ou t pu t port s
Label
Mnemonic/operand
Comment
LD
OR
AND
Y,0F3H
MY,0010B
MY,1011B
;Set address of port
;Set R01 to 1
;Set R02 to 0
Th e th ree in stru ction steps above cau se th e ou tpu t port to
be set, as sh own in Figu re 3.2.2.
D3
D2
D1
D0
Address 0F3H
R03 R02 R01 R00
No change
Sets "1"
Sets "0"
No change
Fig. 3.2.2
Setting of the output port
S1C62N51 TECHNICAL SOFTWARE
EPSON
II-15
CHAPTER 3: PERIPHERAL CIRCUITS (Special Use Output Ports)
3.3 Sp e c ia l Use Outp ut Ports
Sp e c ia l use outp ut
p ort m e m ory m a p
Table 3.3.1 I/O memory map
Register
Address
Comment
Output port data R03
*1
D3
D2
D1
D0
Name
R03
Init
0
1
0
Low
Low
Low
Off
High
High
High
On
R01
R00
R03
R02
Output port data R02
R02
0
BUZZER
FOUT
Output port data R01
R01
0
0F3H
Buzzer On/Off control register
Output port data R00
BUZZER
R00
0
R/W
High
On
Low
Off
0
Frequency output control register
Buzzer frequency control
FOUT
XBZR
0
0
2 kHz
4 kHz
0
XBZR
R/W
0
XFOUT1 XFOUT0
R/W
*5
*6
*6
0FDH
FOUT frequency control
FOUT frequency control
XFOUT1
XFOUT0
0
0
R
*1 In itial valu e followin g in itial reset
*2 Not set in th e circu it
*3 Un defin ed
*4 Reset (0) im m ediately after bein g read
*5 Always "0" wh en bein g read
*6 Refer to m ain m an u al
In addition to th e regu lar DC, special ou tpu t can be selected
for ou tpu t ports R00 an d R01, as sh own in Table 3.3.2.
Figu re 3.3.1 sh ows th e stru ctu re of ou tpu t ports R00–R03.
Control of the sp e -
c ia l use outp ut p ort
Table 3.3.2
Pin name
R00
When special output is selected
FOUT or BUZZER
BUZZER
Special output
R01
II-16
EPSON
S1C62N51 TECHNICAL SOFTWARE
CHAPTER 3: PERIPHERAL CIRCUITS (Special Use Output Ports)
Register
(R03)
R03
Register
(R02)
R02
R01
BUZZER
Register
(R01)
BUZZER
FOUT
Register
(R00)
R00
Fig. 3.3.1
Structure of output ports
R00–R03
Address
(0F3H)
Mask option
• Bu zzer driver ou t pu t (BUZZER)
Exa m p le s of sp e c ia l
use outp ut p ort
Wh en ou tpu t port R01 is set for BUZZER an d R00 is set for
BUZZER, it perform s 2,048 Hz or 4,096 Hz selected by
register XBZR (0FDH D3).
c ontrol p rog ra m
Label
Mnemonic/operand
Comment
LD
Y,0FDH
;Set address of BUZZER
;frequency control register
;Select 2,048 Hz
;Set address of output port
;Turn on BUZZER
LD
LD
OR
:
MY,1000B
Y,0F3H
MY,0010B
:
AND
MY,1101B
;Turn off BUZZER
S1C62N51 TECHNICAL SOFTWARE
EPSON
II-17
CHAPTER 3: PERIPHERAL CIRCUITS (Special Use Output Ports)
• In t ern al divided frequ en cy ou t pu t (FOUT)
Wh en ou tpu t port R00 is set to FOUT ou tpu t, fosc or clock
frequ en cy divided in to fosc is gen erated. Clock frequ en cy
m ay be selected in dividu ally for F1–F4, from am on g 5 types
by m ask option ; a clock frequ en cy is th en selected from 4
types (i.e., F1–F4) th rou gh XFOUT0 an d XFOUT1 (0FDH D0
an d D1) registers an d is gen erated.
Th e clock frequ en cy types are sh own in Table 3.3.3.
Table 3.3.3
Mask option and register
selection
Clock frequency (Hz)
F2 F3
fosc = 32,768
F4
Mask
option
sets
F1
(D1,D0)=(0,0) (D1,D0)=(0,1) (D1,D0)=(1,0) (D1,D0)=(1,1)
256
(fosc/128)
512
(fosc/64)
1,024
(fosc/32)
2,048
(fosc/16)
Set 1
Set 2
Set 3
Set 4
Set 5
4,096
(fosc/8)
512
(fosc/64)
1,024
(fosc/32)
2,048
(fosc/16)
8,192
(fosc/4)
1,024
(fosc/32)
2,048
(fosc/16)
4,096
(fosc/8)
2,048
(fosc/16)
4,096
(fosc/8)
8,192
(fosc/4)
16,384
(fosc/2)
4,096
(fosc/8)
8,192
(fosc/4)
16,384
(fosc/2)
32,768
(fosc/1)
For exam ple m ask option is set to Set 4:
Label
Mnemonic/operand
Comment
LD
Y,0FDH
;Set address of FOUT
;frequency control register
;Select 16,384 Hz
;Set address of output port
;Turn on FOUT
LD
LD
OR
:
MY,0011B
Y,0F3H
MY,0001B
:
AND
MY,1110B
;Turn off FOUT
II-18
EPSON
S1C62N51 TECHNICAL SOFTWARE
CHAPTER 3: PERIPHERAL CIRCUITS (I/O Ports)
3.4 I/ O Ports
I/ O p ort m e m ory
m a p
Table 3.4.1 I/O memory map
Register
D2 D1
Address
Comment
*1
D3
D0
Name
P03
P02
P01
P00
0
Init
–
1
0
*2
*2
*2
*2
High
High
High
High
Low
Low
Low
Low
I/O port data P03
I/O port data P02
I/O port data P01
I/O port data P00
P03
P02
P01
P00
–
0F4H
0FCH
–
R/W
–
*5
*5
*5
0
0
0
IOC
R/W
0
0
R
Out
In
I/O port I/O control register
IOC
0
*1 In itial valu e followin g in itial reset
*2 Not set in th e circu it
*3 Un defin ed
*4 Reset (0) im m ediately after bein g read
*5 Always "0" wh en bein g read
*6 Refer to m ain m an u al
Th e S1C62N51 con tain s a 4-bit gen eral I/ O port (4 bits × 1).
Th is port can be u sed as an in pu t port or an ou tpu t port,
accordin g to I/ O port con trol register IOC. Wh en IOC is "0",
th e port is set for in pu t, wh en it is "1", th e port is set for
ou tpu t.
Control of
the I/ O p ort
• How t o set an in pu t port
Set "0" in th e I/ O port con trol register (D0 of address 0FCH),
an d th e I/ O port is set as an in pu t port. Th e state of th e I/ O
port (P00–P03) is decided by th e data of address 0F4H. (In
th e in pu t m ode, th e port level is read directly.)
S1C62N51 TECHNICAL SOFTWARE
EPSON
II-19
CHAPTER 3: PERIPHERAL CIRCUITS (I/O Ports)
• How t o set an ou t pu t port
Set "1" in th e I/ O port con trol register, an d th e I/ O port is
set as an ou tpu t port. Th e state of th e I/ O port is decided by
th e data of address 0F4H. Th is data is h eld by th e register,
an d can be set regardless of th e con ten ts of th e I/ O con trol
register. (Th e data can be set wh eth er P00 to P03 ports are
in pu t ports or ou tpu t ports.)
Th e I/ O con trol registers are cleared to "0" (in pu t/ ou tpu t
ports are set as in pu t ports), an d th e data registers are also
cleared to "0" after an in itial reset.
• Loadin g P0 0 –P0 3 in pu t dat a in t o A regist er
Exa m p le s of I/ O p ort
c ontrol p rog ra m
Label
Mnemonic/operand
Comment
LD
AND
LD
Y,0FCH
MY,1110B
Y,0F4H
A,MY
;Set address of I/O control port
;Set port as input port
;Set address of port
;A regiser ← P00–P03
LD
As sh own in Figu re 3.4.1, th e fou r in stru ction steps above
load th e data of th e I/ O ports in to th e A register.
D3
D2
D1
D0
A register
P03 P02 P01 P00
Fig. 3.4.1
Loading into the A register
II-20
EPSON
S1C62N51 TECHNICAL SOFTWARE
CHAPTER 3: PERIPHERAL CIRCUITS (I/O Ports)
• Loadin g P0 0 –P0 3 ou t pu t dat a in t o A regist er
Label
Mnemonic/operand
Comment
LD
Y,0FCH
;Set the address of input/output
;port control register
;Set as output port
;Set the address of port
;A register ← P00–P03
OR
LD
LD
MY,0001B
Y,0F4H
A,MY
As sh own in Figu re 3.4.2, th e fou r in stru ction steps above
load th e data of th e I/ O ports in to th e A register.
D3
D2
D1
D0
P03 P02 P01 P00
A register
P00
P01
P02
P03
Data register
Data register
Data register
Data register
Fig. 3.4.2
Control of I/O port (input)
Data can be loaded from th e I/ O port in to th e B register or
MX in stead of th e A register.
S1C62N51 TECHNICAL SOFTWARE
EPSON
II-21
CHAPTER 3: PERIPHERAL CIRCUITS (I/O Ports)
• Loadin g con t en t s of B regist er in t o P0 0 –P0 3
Label
Mnemonic/operand
Comment
LD
Y,0FCH
;Set the address of input/output
;port control register
;Set port as output port
;Set the address of port
;P00–P03 ← B register
OR
LD
LD
MY,0001B
Y,0F4H
MY,B
As sh own in Figu re 3.4.3, th e fou r in stru ction steps above
load th e data of th e B register in to th e I/ O ports.
D3
D2
D1
D0
B register
P00
P01
P02
P03
Data register
Data register
Data register
Data register
Fig. 3.4.3
Control of the I/O port (output)
Th e ou tpu t data can be taken from th e A register, MX, or
im m ediate data in stead of th e B register.
Bit-u n it operation for th e I/ O port is iden tical to th at for th e
in pu t ports (K00–K03) or ou tpu t ports (R00–R03).
II-22
EPSON
S1C62N51 TECHNICAL SOFTWARE
CHAPTER 3: PERIPHERAL CIRCUITS (LCD Driver)
3.5 LCD Drive r
LCD d rive r m e m ory
m a p
Table 3.5.1 I/O memory map
Register
Address
Comment
*1
D3
D2
D1
D0
0
Name
Init
0
1
0
Static
Dynamic LCD drive switch
CSDC
CSDC
0
0
*5
*5
*5
0
0
0
0FBH
R/W
R
*1 In itial valu e followin g in itial reset
*2 Not set in th e circu it
*3 Un defin ed
*4 Reset (0) im m ediately after bein g read
*5 Always "0" wh en bein g read
*6 Refer to m ain m an u al
Address
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
Fig. 3.5.1
090
0A0
Display memory (write only)
32 words x 4 bits
Display memory map
Th e S1C62N51 con tain s 128 bits of display m em ory in
Control of the LCD
d rive r
addresses 090H to 0AFH of th e data m em ory. Each display
m em ory can be assign ed to an y 104 bits of th e 128 bits for
th e LCD driver (26 SEG × 4 COM), 78 bits of th e 128 bits (26
SEG × 3 COM) or 52 bits of th e 128 bits (26 SEG × 2 COM)
by u sin g a m ask option . Th e rem ain in g 24 bits, 50 bits or 76
bits of display m em ory are n ot con n ected to th e LCD driver,
an d are n ot ou tpu t even wh en data is written . An LCD
segm en t is on with "1" set in th e display m em ory, an d off
with "0" set in th e display m em ory. Note th at th e display
m em ory is a write-on ly.
S1C62N51 TECHNICAL SOFTWARE
EPSON
II-23
CHAPTER 3: PERIPHERAL CIRCUITS (LCD Driver)
• LCD drive con t rol regist er (CSDC)
Th e LCD drive con trol register (CSDC: address 0FBH, D3)
can be set eith er for dyn am ic drive or for static drive. Set "0"
in CSDC for 1/ 2, 1/ 3 or 1/ 4 du ty (tim e-sh ared) dyn am ic
drive. Set "1" in CSDC an d th e sam e valu e in th e registers
correspon din g to COM0 to COM1 (1/ 2), COM0 to COM2 (1/
3) or COM0 to COM3 (1/ 4) for static drive. Figu re 3.5.2 is
th e static drive con trol of th e LCD, an d Figu re 3.5.3 is an
exam ple of th e 7-segm en t LCD assign m en t.
LCD lighting status
COM0
COM1
COM2
COM3
–VDD
–VL1
–VL2
–VL3
COM
0–3
SEG0–25
Not lit
Frame frequency
Lit
–VDD
–VL1
–VL2
–VL3
SEG
0–25
–VDD
–VL1
–VL2
–VL3
Fig. 3.5.2
LCD static drive control
a
f
b
Register
Address
D3
D2
c
D1
b
D0
a
g
d
090H
091H
g
f
e
e
c
Fig. 3.5.3
7-segment LCD assignment
d
In th e assign m en t sh own in Figu re 3.5.3, th e 7-segm en t
display pattern is con trolled by writin g data to display
m em ory addresses 090H an d 091H.
II-24
EPSON
S1C62N51 TECHNICAL SOFTWARE
CHAPTER 3: PERIPHERAL CIRCUITS (LCD Driver)
• Displayin g 7 -segm en t
Exa m p le s of
LCD d rive r c ontrol
p rog ra m
Th e LCD display rou tin e u sin g th e assign m en t of Figu re
3.5.3 can be program m ed as follows.
Label
Mnemonic/operand
Comment
ORG
000H
3FH
06H
5BH
4FH
66H
6DH
7DH
27H
7FH
6FH
RETD
RETD
RETD
RETD
RETD
RETD
RETD
RETD
RETD
RETD
;0 is displayed
;1 is displayed
;2 is displayed
;3 is displayed
;4 is displayed
;5 is displayed
;6 is displayed
;7 is displayed
;8 is displayed
;9 is displayed
SEVENS: LD
LD
B,0
X,090H
;Set the address of jump
;Set address of display memory
JPBA
Wh en th e above rou tin e is called (by th e CALL or CALZ
in stru ction ) with an y n u m ber from "0" to "9" set in th e A
register for th e assign m en t of Figu re 3.5.4, seven segm en ts
are displayed accordin g to th e con ten ts of th e A register.
Fig. 3.5.4
A register Display A register Display A register Display A register Display A register Display
0
1
2
3
4
5
6
7
8
9
Data set in A register and
displayed patterns
Th e RETD in stru ction can be u sed to write data to th e
display m em ory on ly if it is addressed u sin g th e X register.
(Addressin g u sin g th e Y register is in valid.)
Note th at th e stack poin ter m u st be set to a proper valu e
before th e CALL (CALZ) in stru ction is execu ted.
S1C62N51 TECHNICAL SOFTWARE
EPSON
II-25
CHAPTER 3: PERIPHERAL CIRCUITS (LCD Driver)
• Bit -u n it operat ion of t h e display m em ory
Data
Address
090H
Fig. 3.5.5
Example of segment
assignment
D3
D2
D1
D0
▲
▲
▲ : SEG-A
▲ : SEG-B
Label
Mnemonic/operand
Comment
LD
X,SEGBUF
;Set address display
;memory buffer
LD
LD
Y,090H
MX,3
;Set address display memory
;Set buffer data
LD
AND
LD
AND
LD
MY,MX
MX,1110B
MY,MX
MX,1101B
MY,MX
;SEG-A, B ON (▲,▲)
;Change buffer data
;SEG-B OFF (▲,▲)
;Change buffer data
;SEG-A OFF (▲,▲)
For m an ipu lation of th e display m em ory in bit-u n its for th e
assign m en t of Figu re 3.5.5, a bu ffer m u st be provided in
RAM to h old data. Note th at, sin ce th e display m em ory is
write-on ly, data can n ot be ch an ged directly u sin g an ALU
in stru ction (for exam ple, AND or OR).
After m an ipu latin g th e data in th e bu ffer, write it in to th e
correspon din g display m em ory u sin g th e tran sfer com m an d.
II-26
EPSON
S1C62N51 TECHNICAL SOFTWARE
CHAPTER 3: PERIPHERAL CIRCUITS (Timer)
3.6 Tim e r
Tim e r m e m ory m a p
Table 3.6.1 I/O memory map
Register
Address
Comment
*1
D3
D2
D1
D0
Name
TM3
TM2
TM1
TM0
0
Init
–
1
0
*3
*3
*3
*3
High
High
High
High
Low
Low
Low
Low
Clock timer data 2 Hz
Clock timer data 4 Hz
Clock timer data 8 Hz
Clock timer data 16 Hz
TM3
TM2
TM1
TM0
–
0E3H
0EBH
0EFH
0F9H
–
R
–
*5
0
R
0
EIT2
IT2
EIT8
R/W
IT8
EIT32
IT32
Enable
Enable
Enable
Mask
Mask
Mask
Interrupt mask register (clock timer) 2 Hz
Interrupt mask register (clock timer) 8 Hz
Interrupt mask register (clock timer) 32 Hz
EIT2
EIT8
EIT32
0
0
0
0
*5
*4
*4
*4
*5
*5
*5
*5
Yes
Yes
Yes
No
No
No
Interrupt factor flag (clock timer) 2 Hz
Interrupt factor flag (clock timer) 8 Hz
Interrupt factor flag (clock timer) 32 Hz
IT2
0
0
0
IT8
R
IT32
0
0
0
0
TMRST
W
0
0
R
Reset
–
Clock timer reset
TMRST
Reset
*1 In itial valu e followin g in itial reset
*2 Not set in th e circu it
*3 Un defin ed
*4 Reset (0) im m ediately after bein g read
*5 Always "0" wh en bein g read
*6 Refer to m ain m an u al
S1C62N51 TECHNICAL SOFTWARE
EPSON
II-27
CHAPTER 3: PERIPHERAL CIRCUITS (Timer)
Th e S1C62N51 con tain s a tim er with a basic oscillation of
Control of the tim e r
32.768 kHz (typical). Th is tim er is a 4-bit bin ary cou n ter,
an d th e cou n ter data can be read as n ecessary. Th e cou n ter
data of th e 16 Hz clock can be read by readin g TM3 to TM0
(address 0E3H, D3 to D0). ("1" to "0" are set in TM3 to TM0,
correspon din g to th e h igh -low levels of th e 2 Hz, 4 Hz, 8 Hz,
an d 16 Hz 50 % du ty waveform . See Figu re 3.6.1.) Th e tim er
can also in terru pt th e CPU on th e fallin g edges of th e 32 Hz,
8 Hz, an d 2 Hz sign als. For details, see Section 3.9, "In ter-
ru pt an d Halt".
Register
Address
Frequency
16 Hz
8 Hz
Clock timer timing chart
bits
D0
D1
D2
D3
0E3H
4 Hz
2 Hz
Occurrence of
32 Hz interrupt request
Occurrence of
8 Hz interrupt request
Occurrence of
2 Hz interrupt request
Fig. 3.6.1 Output waveform of timer and interrupt timing
Th e tim er is reset by settin g "1" in TMRST (address 0F9H,
D0).
The 128 Hz to 2 Hz of the internal divider is initialized by resetting
the clock timer.
Note
II-28
EPSON
S1C62N51 TECHNICAL SOFTWARE
CHAPTER 3: PERIPHERAL CIRCUITS (Timer)
• In it ializin g t h e t im er
Exa m p le s of tim e r
c ontrol p rog ra m
Label
Mnemonic/operand
Comment
LD
Y,0F9H
;Set address of the timer
;reset register
OR
MY,0001B
;Reset the timer
Th e two in stru ction steps above are u sed to reset (clear
TM0–TM3 to "0") an d restart th e tim er. Th e TMRST register
is cleared to "0" by h ardware 1 clock after it is set to "1".
• Loadin g t h e t im er
Label
Mnemonic/operand
Comment
LD
Y,0E3H
;Set address of
;the timer data (TM0 to TM3)
;Load the data of
LD
A,MY
;TM0 to TM3 into A register
As sh own in Table 3.6.2, th e two in stru ction steps load th e
data of TM0 to TM3 in to th e A register.
Table 3.6.2
D3
D2
D1
D0
A register
Loading the timer data
TM3 (2 Hz) TM2 (4 Hz) TM1 (8 Hz) TM0 (16 Hz)
S1C62N51 TECHNICAL SOFTWARE
EPSON
II-29
CHAPTER 3: PERIPHERAL CIRCUITS (Timer)
• Ch eck in g t im er edge
Label
Mnemonic/operand
Comment
LD
CP
X,TMSTAT
MX,0
;Set address of the timer edge counter
;Check whether the timer edge
;counter is "0"
JP
LD
LD
Z,RETURN
Y,0E3H
A,MY
;Jump if "0" (Z-flag is "1")
;Set address of the timer
;Read the data of TM0 to TM3
;into A register
LD
XOR
Y,TMDTBF
MY,A
;Set address of the timer data buffer
;Did the count on the timer
;change?
FAN
LD
MX,0100B
MY,A
;Check bit D2 of the timer data buffer
;Set the data of A register into
;the timer data buffer
JP
ADD
Z,RETURN
MX,0FH
;Jump, if the Z-flag is "1"
;Decrement the timer edge counter
;
RETURN: RET
;Return
Th is program takes a su brou tin e form . It is called at sh ort
in tervals, an d decrem en ts th e data at address TMSTAT every
125 m s u n til th e data reach es "0". Th e tim in g ch art is
sh own in Figu re 3.6.2. Th e tim er can be addressed u sin g
th e X register in stead of th e Y register.
TMSTAT and TMDTBF may be any address in RAM and not
involve a hardware function.
Note
TM2
125 ms
Fig. 3.6.2
Timing of the timer
edge counter
Timer edge counter (TMSTAT) decrementing timing
II-30
EPSON
S1C62N51 TECHNICAL SOFTWARE
CHAPTER 3: PERIPHERAL CIRCUITS (A/D Converter)
3.7 A/ D Conve rte r
A/ D c onve rte r m e m -
ory m a p
Table 3.7.1 I/O memory map
Register
Address
Comment
*1
D3
D2
D1
D0
Name
TC3
TC2
TC1
TC0
TC7
TC6
TC5
TC4
TC11
TC10
TC9
TC8
TC15
TC14
TC13
TC12
C3
Init
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
*3
*3
*3
*3
*3
*3
*3
*3
*3
*3
*3
*3
*3
*3
*3
*3
*3
*3
*3
*3
*3
*3
*3
*3
*3
*3
*3
*3
*3
*3
*3
*3
Up/down counter data TC3
Up/down counter data TC2
Up/down counter data TC1
Up/down counter data TC0 (LSB)
Up/down counter data TC7
Up/down counter data TC6
Up/down counter data TC5
Up/down counter data TC4
Up/down counter data TC11
Up/down counter data TC10
Up/down counter data TC9
Up/down counter data TC8
Up/down counter data TC15 (MSB)
Up/down counter data TC14
Up/down counter data TC13
Up/down counter data TC12
Up-counter data C3
TC3
TC2
TC6
TC10
TC14
C2
TC1
TC0
0E4H
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
TC7
TC11
TC15
C3
TC5
TC9
TC13
C1
C5
C9
C13
0
TC4
TC8
TC12
C0
0E5H
0E6H
0E7H
0F5H
0F6H
0F7H
0F8H
0F1H
0FEH
0ECH
0F0H
Up-counter data C2
C2
Up-counter data C1
C1
Up-counter data C0 (LSB)
Up-counter data C7
C0
C7
C7
C6
C4
Up-counter data C6
C6
Up-counter data C5
C5
Up-counter data C4
C4
Up-counter data C11
C11
C10
C9
C11
C15
0
C10
C14
C8
Up-counter data C10
Up-counter data C9
Up-counter data C8
C8
Up-counter data C15 (MSB)
Up-counter data C14
C15
C14
C13
C12
0
C12
Up-counter data C13
Up-counter data C12
*5
*5
*5
0
R
0
ADRUN
R/W
0
0
Start
65 kHz
Enable
Yes
Stop
32 kHz
Mask
No
A/D conversion Start/Stop
ADRUN
0
0
0
0
0
*5
*5
*5
0
0
ADCLK
R/W
0
0
R
0
A/D clock selection 65 kHz/32 kHz
Interrupt mask register (A/D)
Interrupt factor flag (A/D)
ADCLK
0
*5
*5
*5
0
0
EIAD
R/W
0
0
R
0
EIAD
0
*5
*5
*5
*4
0
0
IAD
0
0
R
IAD
*1 In itial valu e followin g in itial reset
*2 Not set in th e circu it
*3 Un defin ed
*4 Reset (0) im m ediately after bein g read
*5 Always "0" wh en bein g read
*6 Refer to m ain m an u al
S1C62N51 TECHNICAL SOFTWARE
EPSON
II-31
CHAPTER 3: PERIPHERAL CIRCUITS (A/D Converter)
Th e S1C62N51 h as a CR oscillation type A/ D con verter.
Control of the A/ D
c onve rte r
Th is A/ D con verter is equ ipped with two CR oscillation
circu it system s an d a cou n ter th at m easu res th eir
oscillation frequ en cy. Cou n ted valu es represen t con n ected
resistan ce valu es con verted in to digital valu es.
Th e A/ D con verter in corporates two types of 16-bit cou n t-
ers. On e is th e u p-cou n ter C0–C15 th at cou n ts th e afore-
m en tion ed oscillation clock, an d th e oth er is u p/ down
cou n ter TC0–TC15 th at cou n ts th e in tern al clock for refer-
en ce cou n t. Each cou n ter perm its readin g an d writin g on a
4-bit basis.
Figu re 3.7.1 sh ows th e operation an d con trol flow of A/ D
con verter. Figu re 3.7.2 sh ows th e Tim in g ch art of th e A/ D
con version .
A/D conversion
Reset the two
Reset the up/down counter TC0–TC15 (0E4H–0E7H)
and the up-counter C0–C15 (0F5H–0F8H) to "0000H"
counter memories
A
Reset I (Interrupt) flag
Up/down counter TC
NO
A/D interrupt
necessary ?
counts down
YES
Up-counter C counts up
Set the interrupt mask
register to ENABLE
Set the EIAD
(0ECH D0) to "1"
NO
Counter TC : 0
YES
Set an initial value
(complement) in
the C0–C15 (0F5H–0F8H)
Set an initial value
in the up-counter C
Both counter
finish counting
Set "1" in
the ADRUN (0F1H D0)
Start A/D conversion
Set the interrupt factor
flag IAD to "1"
Up-counter C counts up
Up/down counter TC
counts up
NO
Is A/D interrupt
set to ENABLE ?
YES
Read the C0–C15
(0F5H–0F8H)
and process the
NO
Counter C : 0
Interrupt process
measurement results
YES
A
END
Fig. 3.7.1
Control flow of A/D
converter
II-32
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S1C62N51 TECHNICAL SOFTWARE
CHAPTER 3: PERIPHERAL CIRCUITS (A/D Converter)
ADRUN register
ADOUT
n
0
n+1 n+2
FFFE FFFF
x-3 x-2 x-1
0
1
2
m-1
m
Up-counter data
Up/down counter clock
Up/down counter data
Interrupt
1
2
3
x
x-1 x-2 x-3
3 2 1 0
Oscillation with reference resistor
Oscillation with sensor
Fig. 3.7.2
Timing of A/D conversion
Basic con trol an d operation of th e A/ D con verter are de-
scribed in th e flowch art in Figu re 3.7.1. In order to prepare
a program , add item s requ ired accordin g to application .
After A/ D con version , th e valu e cou n ted du rin g oscillation of
th e sen sor con n ected between th e TH an d CS term in als is
set on th e u p-cou n ter C0–C15. Th is valu e is th e sen sor
oscillation clock n u m ber du rin g a tim e period equ al to th at
du rin g wh ich th e referen ce resistan ce con n ected between
th e RS an d CS term in als is oscillated accordin g to th e in itial
valu e set on th e u p-cou n ter. Th e differen ce between th e
referen ce resistan ce an d th e sen sor resistan ce valu e can be
obtain ed in directly from th e in itial valu e an d resu lts. Correct
it accordin g to th e ch aracteristics of th e con n ected elem en ts
an d calcu late th e target m easu rem en t resu lts.
Note
Depending on the initial value of the up-counter C0–C15, the up/
down counter TC0–TC15 may overflow while the CR oscillation
clock is being counted. When setting the initial value, pay attention
to CR oscillation frequency, its fluctuation range and the input clock
frequency of the up/down counter. If the up/down counter over-
flows, A/D conversion is terminated immediately, and correct
measurement is impossible.
S1C62N51 TECHNICAL SOFTWARE
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CHAPTER 3: PERIPHERAL CIRCUITS (A/D Converter)
Set "0000H" on th e u p/ down cou n ter prior to A/ D con ver-
sion . No oth er readin g or writin g operation is n ecessary.
Th is cou n ter is provided in order to adju st th e oscillation
tim e of th e two extern al resistan ce.
Note If the up/down counter TC0–TC15 is measured after A/D conver-
sion, it may not indicate "0000H". This is not due to incorrect timing
in terminating A/D conversion but because the counting down clock
is input after the control signal is output to the up-counter to termi-
nate counting.
Sin ce in terru ption is possible after A/ D con version , readin g
of th e u p-cou n ter an d data processin g are basically per-
form ed u sin g th e in terru pt fu n ction .
If in terru pt is n ot u sed, A/ D con verter operation can be
ch ecked by readin g th e ADRUN register. After "1" is en tered
in th is register to start A/ D con version , th e register rem ain s
at "1" du rin g A/ D con version an d is reset to "0" wh en A/ D
con version is fin ish ed.
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EPSON
S1C62N51 TECHNICAL SOFTWARE
CHAPTER 3: PERIPHERAL CIRCUITS (A/D Converter)
In th is section , we will explain , for an exam ple of an A/ D
con verter, a m eth od of tem peratu re m easu rem en t an d its
program .
Exa m p le s of A/ D
c onve rte r c ontrol
p rog ra m
Wh en perform in g tem peratu re m easu rem en t, con n ect a
referen ce resistan ce to th e RS term in al, a th erm istor to th e
TH term in al an d a con den ser to th e CS term in al, respec-
tively. Th e ideal referen ce resistan ce to be con n ected to th e
RS term in al sh ou ld be on e wh ich sh ows n o ch an ge in its
resistan ce valu e as a resu lt of flu ctu ation s in tem peratu re.
Th e th erm istor h as a ch aracteristic again st tem peratu re
resistan ce an d th e resistan ce valu e Rγ at a certain tem pera-
tu re T (°K) can be represen ted by th e followin g form u la:
Rγ = R0 EXP{ B (1/T - 1/T0) }
R0: Resistance value of the thermistor at the reference temperature (T
0°K)
B: Constant of the thermistor
By u sin g th e referen ce resistan ce an d th e tem peratu re
resistan ce ch aracteristic of th e th erm istor, tem peratu re
m easu rem en t is perform ed.
On e m eth od sets th e referen ce resistan ce an d th e th erm istor
in an altern atin g state of CR oscillation , u sin g th e sam e
con den ser on ly in th e sam e tim e in terval. A n u m erical
com parison of each oscillatin g frequ en cy is perform ed by a
cou n ter, an d th e cou n ter valu es are con verted to th e tem -
peratu re by way of th e ch aracteristics of th e th erm istor.
After th e A/ D con version , th e cou n ter valu e of 16 bits will
h ave been set in th e u p-cou n ter from C15 (0F8H, MSB) to
C0 (0F5H, LSB). Th is cou n ter valu e represen ts th e am ou n t
of CR oscillation of th e th erm istor again st du ration wh en it
is oscillated with CR of th e referen ce resistan ce for a speci-
fied n u m ber of tim es.
Th e relation sh ip between th e am ou n t of oscillation of th e
th erm istor an d th e tem peratu re is sh own in Figu re 3.7.3.
S1C62N51 TECHNICAL SOFTWARE
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CHAPTER 3: PERIPHERAL CIRCUITS (A/D Converter)
60
50
40
30
20
10
0
-10
-20
Fig. 3.7.3
Counter value characteristics
of the temperature and the up-
counter
-30
1000 2000 3000 4000 5000 6000 7000 8000
Counter value of up-counter
As sh own in Figu re 3.7.3, th e tem peratu re an d th e cou n ter
valu es do n ot form a straigh t lin e. Th erefore, it is n ecessary
to drive th e ran ge of m easu rem en t tem peratu re in to several
section s an d to calcu late in advan ce th e cou n ter valu es at
th e tem peratu re of its division poin ts, accordin g to th e
ch aracteristics of th e th erm istor. As for th e divided section s,
th e tem peratu re coefficien t (flu ctu ation in tem peratu re by
u n it cou n ter) wh ich approxim ates to a straigh t lin e between
th e section s is calcu lated an d stored in to th e ROM in con -
ju n ction with th e cou n ter valu e of su ch division poin t. With
th is valu e an d th e cou n ter valu e calcu lated, th e tem peratu re
can th en be calcu lated.
Th e followin g is a sam ple program wh ich con trols th e A/ D
con verter an d con verts th e cou n ter valu e to th e tem peratu re
wh en perform in g tem peratu re m easu rem en t with th is
m eth od.
In th is program , 49.9 kΩ are u sed for th e extern al referen ce
resistan ce, 2,200 pF for th e con den ser an d on e with a
tem peratu re ch aracteristic as sh own in Table 3.7.2 for th e
th erm istor.
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EPSON
S1C62N51 TECHNICAL SOFTWARE
CHAPTER 3: PERIPHERAL CIRCUITS (A/D Converter)
Table 3.7.2
Temperature characteristics
of the thermistor in the
sample program
Temperature [°C] TH resistance [kΩ]
Up-counter value
-30
-20
-10
0
872.20
484.00
277.40
164.00
99.97
62.56
40.20
26.43
17.75
12.16
006B[HEX]
107[DEC]
205[DEC]
358[DEC]
606[DEC]
993[DEC]
1565[DEC]
2383[DEC]
3532[DEC]
5138[DEC]
7958[DEC]
00CD[HEX]
0166[HEX]
025E[HEX]
03E1[HEX]
061D[HEX]
094F[HEX]
0DCC[HEX]
1412[HEX]
1F16[HEX]
10
20
30
40
50
60
Th e cou n ter valu e of th e u p-cou n ter sh ows th e am ou n t of CR
oscillation of th e th erm istor wh en th e referen ce resistan ce is
oscillated with CR 2,000 tim es.
Label
Mnemonic/operand
Comment
HEXDEC MACROARG1, ARG2, ARG3
LOCALHXDC1, HXDC2
;*******************************************************
;*
*
*
*
;* HEX --> DEC
;*
1 -- 13 DIGIT
;*******************************************************
RST F,8
;Reset D, Z and C flags
;Digit ← Digit + 1
LD
A,ARG3
ADD A,1
;***** ARG2 ZERO CLEAR *****
;***** ARG2 DATA <-- ARG1 TOP DATA *****
LD
LD
LD
CP
JP
X,ARG1+ARG3-1
Y,ARG2
MY,MX
MY,0AH
C,$+5
;ARG2 data ← ARG1 data
;If ARG2 data < 0AH
ADD MY,6
INC
LDPY MY,1
;ARG2 data ← ARG2 data + 6
;ARG2 address increment
;ARG2 data 1 increment
Y
JP
INC
$+3
Y
LDPY MY,0
;Zero clear
ADD A,0FH
;Digit counter decrement
;If digit counter not = 0
;B-reg. ← Digit - 1
JP
LD
CP
JP
NZ,$-2
B,ARG3-1
B,0
Z,HXDC2
;If Digit = 1
S1C62N51 TECHNICAL SOFTWARE
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CHAPTER 3: PERIPHERAL CIRCUITS (A/D Converter)
HXDC1
PUSH B
;***** ARG2 DATA <-- ARG2 DATA * 16D *****
LD
B,4
;Loop counter setting
LD
LD
Y,ARG2
A,ARG3+2
;A-reg. ← Digit + 2
;Reset C flag
;Set D flag
RCF
SDF
ACPY MY,MY
PUSH F
;ARG2 data ← 2 * ARG2 data
ADD A,9
;A-reg. decrement
;If A-reg. not = 0
JP
Z,$+3
POP
JP
POP
F
$-5
F
ADD B,9
JP NZ,$-12
;Loop counter decrement
;If loop counter not = 0
;*** ARG2 DATA <-- ARG2 DATA + ARG1 1 DIGIT DATA ****
RST F,8
ADC XL,0FH
ADC XH,0FH
;Reset D, Z and C Flags
;ARG1 address decrement
;Digit counter setting
LD
LD
CP
JP
Y,ARG2
B,ARG3+1
MX,0AH
C,$+7
;If ARG1 1 digit data < 0AH
;ARG1 1 digit data + 6
;Set D flag
ADD MX,6
SDF
RCF
;Reset C flag
ACPY MY,MX
ADC MY,1
;ARG2 data ← ARG1 1 digit data
JP
$+5
RCF
SDF
;Reset C flag
;Set D flag
ACPY MY,MX
ADC MY,0
;ARG2 data ← ARG1 1 digit data
;If C = 1 then 1 increment
INC
Y
PUSH F
ADD B,9
;Digit counter decrement
;If digit counter not = 0
JP
Z,$+3
POP
JP
POP
F
$-6
F
;***** DIGIT DECREMENT *****
POP
B
ADD B,9
;Digit decrement
;If digit counter not = 0
;Reset D flag
JP
NZ,HXDC1
HXDC2
RDF
ENDM
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EPSON
S1C62N51 TECHNICAL SOFTWARE
CHAPTER 3: PERIPHERAL CIRCUITS (A/D Converter)
ORG 100H
JP
HALT
JP
INIT
INAD
;Initialize and mode selection
;(101H)
;A/D converter interrupt (102H)
HALT
HALT
HALT
HALT
HALT
;(103H)
;(104H)
;(105H)
;(106H)
;(107H)
DI
INIT
LD
LD
LD
LD
LD
A,05H
SPH,A
A,0
SPL,A
X,0
;Set stack pointer to 05H
;Clear RAM area (00H–4FH)
CLRRAM
LDPX MX,0
CP
JP
XH,5H
C,CLRRAM
LD
LD
X,0ECH
MX,1
;Set A/D interrupt to Enable
;Clear up/down counter
LD
X,0E4H
UDCCL
LDPX MX,0
CP
JP
XL,8
NZ,UDCCL
LD
X,0F5H
;Set complement of 2,000 to up-counter
LDPX MX,0H
LDPX MX,3H
LDPX MX,8H
LDPX MX,0FH
EI
;Set interrupt to Enable
;Start A/D conversion
LD
X,0F1H
MX,1
LD
HALT
INAD
RST F,8
LD
LD
A,0
B,0
READKN
CALL $+2
JP
LD
READEND
X,10H
PSET 2
JPBA
S1C62N51 TECHNICAL SOFTWARE
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CHAPTER 3: PERIPHERAL CIRCUITS (A/D Converter)
READEND
PUSH B
LD
LD
LD
B,4
X,0F8H
Y,13H
COMP
CP
MX,MY
JP
JP
C,MULTI
Z,$+2
JP
NC,NEXTREAD
RCF
ADC XL,15
RCF
ADC YL,15
ADD B,15
JP
JP
NZ,COMP
MULTI
NEXTREAD
POP
B
ADD A,6
ADC B,0
;Set address of next setting value stored
JP
READKN
MULTI
POP
RCF
B
SBC A,6
SBC B,0
CALL $+2
JP
LD
$+4
X,10H
PSET 2
JPBA
LD
LD
LD
X,0F5H
Y,00H
B,4
LDPX MY,MX
INC
ADD B,15
Y
JP
NZ,$-3
RCF
LD
LD
X,10H
Y,0H
SCPY MY,MX
INC
SCPY MY,MX
INC
SCPY MY,MX
INC
SCPY MY,MX
X
X
X
II-40
EPSON
S1C62N51 TECHNICAL SOFTWARE
CHAPTER 3: PERIPHERAL CIRCUITS (A/D Converter)
;***** INITIALIZE WORK MEMORY *****
LD
LD
X,24H
B,4
WMCLR
LBPX MX,00
ADD B,15
JP
NZ,WMCLR
;***** CALCURATE An X K *****
LD
LD
LD
X,0H
Y,04H
B,4
LDPX MY,MX
INC
ADD B,15
Y
JP
LD
LD
NZ,$-3
MY,0
B,1
MULTI00
MULTI01
LD
Y,14H
FAN MY,B
LD X,00H
PUSH YL
JP
LD
LD
LD
Z,MULTI02
X,04H
A,2
YH,A
CALL SUBROUTADD
LD
LD
A,1
YH,A
MULTI02
POP YL
INC
CP
Y
YL,7
JP
NZ,MULTI01
RCF
RLC
JP
B
C,SUBTRA
;***** WORK MEMORY X 2 *****
LD
X,04H
RCF
ACPX MX,MX
ACPX MX,MX
ACPX MX,MX
ACPX MX,MX
ACPX MX,MX
JP
MULTI00
;***** ADD Bn *****
S1C62N51 TECHNICAL SOFTWARE
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CHAPTER 3: PERIPHERAL CIRCUITS (A/D Converter)
SUBTRA
HEXDEC 24H,30H,10 ;Decimal ← 8 digit HEX
LD
LD
X,17H
A,MX
;Set decimal point
SDF
LD
CP
JP
X,1BH
MX,1
Z,MINUS
PLUS
RCF
LD
LD
X,18H
Y,30H
YL,A
LD
PLUS1
ACPY MY,MX
INC
PUSH F
X
CP
XL,0BH
JP
Z,$+3
POP
JP
POP
RDF
JP
F
PLUS1
F
ENDPROG+1
MINUS
RCF
LD
X,18H
Y,30H
LD
MINUS1
PUSH F
LD
B,YL
CP
B,A
JP
Z,MINUS2
LD
POP
B,0
F
SBC B,MY
LD
INC
JP
MY,B
Y
MINUS1
MINUS2
POP
F
SBC MX,MY
LD
MY,MX
INC
INC
X
Y
PUSH F
CP
XL,0BH
JP
JP
POP
RDF
Z,$+2
MINUS2
F
JP
ENDPROG+1
II-42
EPSON
S1C62N51 TECHNICAL SOFTWARE
CHAPTER 3: PERIPHERAL CIRCUITS (A/D Converter)
;***** 16-BIT ADDITION *****
SUBROUTADD
RCF
ACPY MY,MX
INC
ACPY MY,MX
INC
ACPY MY,MX
INC
ACPY MY,MX
INC
X
X
X
X
ACPY MY,MX
RET
ENDPROG
ORG 200H
;*************************
;*
*
*
*
;* Kn, An, Bn SETTINGS
;*
;*************************
SETCON
;-30°C TO -20°C
LBPX MX,6BH
LBPX MX,00H
LBPX MX,66H
LBPX MX,30H
LBPX MX,30H
RETD 10H
;K1 = 06BH (107)
;A1 = 3066H (0.102)
;B1 = 1030 (-30°C)
;-20°C TO -10°C
LBPX MX,0CDH
LBPX MX,00H
LBPX MX,8DH
LBPX MX,42H
LBPX MX,20H
RETD 10H
;K1 = 0CDH (205)
;A1 = 428DH (0.0653)
;B1 = 1020 (-20°C)
;-10°C TO 0°C
LBPX MX,66H
LBPX MX,01H
LBPX MX,93H
LBPX MX,41H
LBPX MX,10H
RETD 10H
;K1 = 166H (358)
;A1 = 4193H (0.0403)
;B1 = 1010 (-10°C)
;0°C TO 10°C
LBPX MX,5EH
LBPX MX,02H
LBPX MX,02H
LBPX MX,41H
;K2 = 25EH (606)
;A2 = 4102H (0.0258)
S1C62N51 TECHNICAL SOFTWARE
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CHAPTER 3: PERIPHERAL CIRCUITS (A/D Converter)
LBPX MX,00H
RETD 00H
;B2 = 0000 (0°C)
;10°C TO 20°C
LBPX MX,0E1H
LBPX MX,03H
LBPX MX,0AFH
LBPX MX,40H
LBPX MX,10H
RETD 00H
;K2 = 3E1H (993)
;A2 = 40AFH (0.0175)
;B2 = 0010 (10°C)
;20°C TO 30°C
LBPX MX,1DH
LBPX MX,06H
LBPX MX,7AH
LBPX MX,40H
LBPX MX,20H
RETD 00H
;K2 = 61DH (1565)
;A2 = 407AH (0.0122)
;B2 = 0020 (20°C)
;30°C TO 40°C
LBPX MX,4FH
LBPX MX,09H
LBPX MX,66H
LBPX MX,53H
LBPX MX,30H
RETD 00H
;K2 = 94FH (2383)
;A2 = 5366H (0.00870)
;B2 = 0030 (30°C)
;40°C TO 50°C
LBPX MX,0CCH
LBPX MX,0DH
LBPX MX,6FH
LBPX MX,52H
LBPX MX,40H
RETD 00H
;K2 = 0DCCH (3532)
;A2 = 526FH (0.00623)
;B2 = 0040 (40°C)
;50°C TO 60°C
LBPX MX,12H
LBPX MX,14H
LBPX MX,63H
LBPX MX,51H
LBPX MX,50H
RETD 00H
;K2 = 1412H (5138)
;A2 = 5163H (0.00355)
;B2 = 0050 (50°C)
;60°C
LBPX MX,16H
LBPX MX,1FH
;K2 = 1F16H (7958)
RET
II-44
EPSON
S1C62N51 TECHNICAL SOFTWARE
CHAPTER 3: PERIPHERAL CIRCUITS (A/D Converter)
Figu re 3.7.4 in dicates a flowch art for th e sam ple program .
Th is sam ple program sets th e am ou n t of oscillation , as th e
referen ce of th e cou n ter valu e, to 2,000 tim es (decim al), bu t
determ in es th e am ou n t of oscillation in accordan ce with th e
m easu rem en t ran ge an d pu rposes.
in addition , as th is program on ly aim s at con version of
tem peratu re, on ly th e A/ D in terru pt is set. Wh en u sin g th is
program , set th e oth er in terru pts accordin g to desired
application .
Start
1
Set the data of the previous
Set the stack pointer to 50H
sector, to 10H–1BH
Clear RAM area (00H–4FH)
Set the difference between the
the up-counter value and the
count number, to 00H–03H
Set the A/D interrupt mask
register to "Enable"
Clear 24H–2BH
Clear the up/down counter
(E4H–E7H)
Calculate the product of the
difference between the count
numbers and the coefficient
of the linear approximation,
to 24H–2BH
Set the reference count in the
up-counter (F5H–F8H)
(set complement, F830H of
2,000 [DEC] times)
Set the hexadecimal number of
24H–2BH, converting it to the
decimal number, to 30H–39H
Interrupt admitted
Start of A/D conversion
HALT
The minimum
temperature of the
sector is minus
N
Y
N
Occurrence of
the interrupt
When adjusting the position of
the decimal point, reduce the
product calculated from the
absolute value of the minimum
temperature and then terminate
the conversion to the desired
temperature
When adjusting the position of
the decimal point, add the mini-
mum temperature and then
terminate the conversion to the
desired temperature
Y
Set the number for counting in
the range divided into 10H–1BH,
the coefficient of the linear
approximation of the sector
and the minimum temperature
Termination
The up-counter
value being within the
division range
Y
1
N
Set the address of the next
division sector data to a PC
Fig. 3.7.4
Flowchart
S1C62N51 TECHNICAL SOFTWARE
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CHAPTER 3: PERIPHERAL CIRCUITS (A/D Converter)
Th e followin g explain s th e ROM data in volved in th e tem -
peratu re division sector u sed in th is program .
Label
Mnemonic/operand
Comment
SETCON
;-30°C TO -20°C
LBPX MX,6BH
LBPX MX,00H
LBPX MX,66H
LBPX MX,30H
LBPX MX,30H
RETD 10H
;K1 = 06BH (107)
;A1 = 3066H (0.102)
;B1 = 1030 (-30°C)
;-20°C TO -10°C
LBPX MX,0CDH
LBPX MX,00H
LBPX MX,8DH
LBPX MX,42H
LBPX MX,20H
RETD 10H
;K1 = 0CDH (205)
;A1 = 428DH (0.0653)
;B1 = 1020 (-20°C)
:
:
Th e first 16-bit data (K1) is th e am ou n t of oscillation of th e
th erm istor again st th e n u m ber of oscillation (2,000 tim es) of
th e referen ce resistan ce in th e m in im u m tem peratu re be-
tween th e division sector, th at is, th e cou n ter valu e of th e
u p-cou n ter after th e A/ D con verter con trol. Th is valu e can
be calcu lated th rou gh th e ch aracteristics of th e extern al
referen ce resistan ce, th e th erm istor, th e con den ser an d th e
A/ D con verter. Th e sam ple program is 107 tim es (6BH) at -
30°C. Th e data are written in th e h exadecim al system .
Th e n ext 16-bit data (A1) is th e tem peratu re coefficien t
wh ich lin early approxim ates between th e division sector.
Th e tem peratu re coefficien t represen ts th e ch an gin g qu an -
tity of th e tem peratu re by on e cou n t. For exam ple, wh en th e
cou n ter valu e of -30°C an d -20°C are 107 (6BH) an d 205
(0CDH), respectively, th e tem peratu re coefficien t of th e
sector can be calcu lated u sin g th e followin g form u la:
{ (-20) - (-30) } / {205 - 107 } = 0.102 [°C/count]
Minimum counter number within the sector
Minimum counter number of the next sector
Minimum temperature within the sector
Minimum temperature of the next sector
II-46
EPSON
S1C62N51 TECHNICAL SOFTWARE
CHAPTER 3: PERIPHERAL CIRCUITS (A/D Converter)
Th is valu e is con verted to a h exadecim al n u m ber in clu din g
th e position of th e decim al poin t. Th e lower 12 bits repre-
sen t 066H wh ich in dicates 102 an d th e u pper 4 bits repre-
sen t th e n u m ber 3 for th e tim es th e position of th e decim al
poin t sh ifts to th e left (1/ 103). Th e tem peratu re coefficien t
at -30°C to -20°C will be 3066H after con version to a h exa-
decim al n u m ber. Th is sim ilarly applies to oth er coefficien ts
between th e tem peratu re sectors.
Th e last 16-bit data (B1) in dicates th e m in im u m tem pera-
tu re of th e sector con cern ed. Th e data at th e tem peratu re of
-30°C represen t 1030H.
Th e u pper 4 bits are m in u s flag, in dicatin g a m in u s n u m ber
if th ey are 1. Th e lower 12 bits represen t th e absolu te valu e
of th e tem peratu re. In ciden tally, as th e lower 12 bits operate
based on th e decim al arith m etic system , th ey are expressed
in th e decim al system .
Th u s far, we h ave explain ed an exam ple of tem peratu re
m easu rem en t wh ich calcu lates th e tem peratu re from th e
lin ear approxim ation u sin g an A/ D con verter. Wh en u sin g
th is program , you sh ou ld add item s n ecessary for th e de-
sired application s an d m odify as n ecessary th rou gh th e
ch aracteristics of th e extern al elem en t. In addition , on e
sh ou ld exercise cau tion wh en u sin g th e A/ D con verter for
oth er pu rposes.
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CHAPTER 3: PERIPHERAL CIRCUITS (SVD Circuit and Heavy Load Protection Function)
3.8 Sup p ly Volta g e De te c tion (SVD) Circ uit a nd
He a vy Loa d Prote c tion Func tion
Th e S1C62N51 Series h as bu ilt-in su pply voltage detection
circu it an d drop in su pply voltage m ay be detected by con -
trollin g th e register on th e I/ O m em ory. Criteria voltages are
as follows:
Model
Criteria Voltage
2.4 V ± 0.15 V
1.2 V ± 0.10 V
S1C62N51
S1C62L51
Moreover, wh en th e battery load becom es h eavy, su ch as
du rin g extern al piezo bu zzer drivin g or extern al lam p ligh t-
in g, h eavy load protection fu n ction is bu ilt-in in case th e
su pply voltage drops. S1C62L51 operates at 0.9 V (1.2 V
wh en th e A/ D con verter is operated) du e to th e SVD circu it
an d h eavy load protection fu n ction .
SVD c irc uit a nd
he a vy loa d p rote c -
tion func tion m e m -
ory m a p
Table 3.8.1 I/O memory map
Register
Address
Comment
*1
D3
D2
D1
D0
Name
HLMOD
0
Init
0
1
0
Heavy
Normal Heavy load protection mode register
HLMOD
0
SVDDT SVDON
R/W
*5
0FAH
Low
On
Normal Supply voltage detection data
SVDDT
SVDON
0
0
R/W
R
Off
Supply voltage detection circuit On/Off
*1 In itial valu e followin g in itial reset
*2 Not set in th e circu it
*3 Un defin ed
*4 Reset (0) im m ediately after bein g read
*5 Always 0 wh en bein g read
*6 Refer to m ain m an u al
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CHAPTER 3: PERIPHERAL CIRCUITS (SVD Circuit and Heavy Load Protection Function)
Th e SVD circu it will tu rn ON by writin g "1" on th e SVDON
Control of the SVD
c irc uit
register (address 0FAH, D0, R/ W) an d su pply voltage detec-
tion will be perform ed. By writin g "0" on th e SVDON register,
th e detection resu lt is stored in th e SVDDT register. How-
ever, in order to obtain a stable detection resu lt, it is n eces-
sary to tu rn th e SVD circu it ON for at least 100 µs. Accord-
in gly, readin g ou t th e detection resu lt from th e SVDDT
register is perform ed th rou gh th e followin g procedu res:
➀ Set th e SVDON register to "1".
➀ Provide at least 100 µs waitin g tim e.
➀ Set th e SVDON register to "0".
➀ Read-ou t from th e SVDDT register.
Note, h owever, th at wh en S1C62N51 is to be u sed with th e
n orm al system clock at fosc = 32.768 kHz, th ere is n o n eed
for th e waitin g tim e stated in th e above procedu re ➀ sin ce 1
in stru ction cycle will take lon ger th an 100 µs.
Becau se th e power cu rren t con su m ption of th e IC becom es
large wh en th e SVD circu it is operated, tu rn th e SVD circu it
OFF wh en n ot in u se. Th e operation tim in g ch art is sh own
in Figu re 3.8.1.
Supply voltage
Criteria voltage
100 µs or more
Fig. 3.8.1
SVDON register
SVD circuit
Timing chart of
supply voltage
detection operation
through the SVDON
register
SVDDT register
HLMOD register
Label
Mnemonic/operand
Comment
Exa m p le of SVD
c irc uit c ontrol
p rog ra m
LD
X,0FAH
MX,0001B
MX,1110B
A,MX
;Sets the address of SVDON
;Sets SVDON to "1"
;Sets SVDON to "0"
;Loads the detection result
;into the A register
OR
AND
LD
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CHAPTER 3: PERIPHERAL CIRCUITS (SVD Circuit and Heavy Load Protection Function)
Note th at th e h eavy load protection fu n ction on th e
He a vy loa d p rote c -
S1C62L51 is differen t from th e S1C62N51.
tion func tion
(1) In case of S1C62L51
Th e S1C62L51 h as th e h eavy load protection fu n ction for
wh en th e battery load becom es h eavy an d th e sou rce
voltage drops, su ch as wh en an extern al bu zzer sou n ds
or an extern al lam p ligh ts. Th e state wh ere th e h eavy
load protection fu n ction is in effect is called th e h eavy
load protection m ode. In th is m ode, operation with a
lower voltage th an n orm al is possible.
Th e n orm al m ode ch an ges to th e h eavy load protection
m ode in th e followin g two cases:
➀ Wh en th e software ch an ges th e m ode to th e h eavy load
protection m ode (HLMOD = "1")
➀ Wh en su pply voltage drop (SVDDT = "1") in th e SVD
circu it is detected, th e m ode will au tom atically sh ift to
th e h eavy load protection m ode u n til th e su pply volt-
age is recovered (SVTDT = "0")
In th e h eavy load protection m ode, th e in tern ally regu -
lated voltage is gen erated by th e liqu id crystal driver
sou rce ou tpu t VL2 so as to operate th e in tern al circu it.
Con sequ en tly, m ore cu rren t is con su m ed in th e h eavy
load protection m ode th an in th e n orm al m ode. Un less it
is n ecessary, be carefu l n ot to set th e h eavy load protec-
tion m ode with th e software. Also, to redu ce cu rren t
con su m ption , do n ot set th e SVDON to ON in th e h eavy
load protection m ode.
(2) In case of S1C62N51
Th e S1C62N51 h as th e h eavy load protection fu n ction for
wh en th e battery load becom es h eavy an d th e sou rce
voltage ch an ges, su ch as wh en an extern al bu zzer sou n ds
or an extern al lam p ligh ts. Th e state wh ere th e h eavy
load protection fu n ction is in effect is called th e h eavy
load protection m ode. Com pared with th e n orm al opera-
tion m ode, th is m ode can redu ce th e ou tpu t voltage
variation of th e con stan t voltage/ booster voltage circu it of
th e LCD system .
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S1C62N51 TECHNICAL SOFTWARE
CHAPTER 3: PERIPHERAL CIRCUITS (SVD Circuit and Heavy Load Protection Function)
Th e n orm al m ode ch an ges to th e h eavy load protection
m ode in th e followin g case:
•
Wh en th e software ch an ges th e m ode to th e h eavy load
protection m ode (HLMOD = "1")
Th e h eavy load protection m ode switch es th e con stan t
voltage circu it of th e LCD system to th e h igh -stability
m ode from th e low cu rren t con su m ption m ode. Con se-
qu en tly, m ore cu rren t is con su m ed in th e h eavy load
protection m ode th an in th e n orm al m ode. Un less it is
n ecessary, be carefu l n ot to set th e h eavy load protection
m ode with th e software.
Supply voltage
Criteria voltage
HLMOD register
Heavy load
protection mode
Fig. 3.8.2
Timing chart of
supply voltage
2 Hz clock
SVD circuit
detection operation
through the HLMOD
register
SVDDT register
SVDON register
Supply voltage
Criteria voltage
100 µs or more
SVDON register
2 Hz clock
Fig. 3.8.3
Timing chart of heavy
load protection
SVD circuit
SVDDT register
function operation
through the SVDON
register
Heavy load
protection mode
HLMOD register
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CHAPTER 3: PERIPHERAL CIRCUITS (SVD Circuit and Heavy Load Protection Function)
•
Operat ion t h rou gh t h e HLMOD regist er
Th is is a sam ple program wh en lam p is driven with th e
R00 term in al du rin g perform an ce of h eavy load protec-
tion .
Exa m p le s of he a vy
loa d p rote c tion
func tion c ontrol
p rog ra m
Label
Mnemonic/operand
Comment
LD
OR
LD
OR
X,0FAH
;Sets the address of HLMOD
MX,1000B ;Sets to the heavy load protection mode
Y,0F3H ;Sets the address of R0n port
MY,0001B ;Turns lamp ON
:
:
LD
Y,0F3H
;Sets the R0n port address
AND
MY,1110B ;Turns the lamp OFF
CALL WT1S
;1 second waiting time (software timer)
AND MX,0111B ;Cancels the heavy load protection mode
In th e above program , th e h eavy load protection m ode is
can celed after 1 sec waitin g tim e provided as th e tim e for
th e battery voltage to stabilize after th e lam p is tu rn ed
off; h owever, sin ce th is tim e varies accordin g to th e
n atu re of th e battery, tim e settin g m u st be don e in accor-
dan ce with th e actu al application .
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CHAPTER 3: PERIPHERAL CIRCUITS (SVD Circuit and Heavy Load Protection Function)
•
Operat ion t h rou gh t h e SVDON regist er
Label
Mnemonic/operand
Comment
LD
FAN
JP
X,0FAH
;Sets the HLMOD/SVDDT address
;Checks the HLMOD/SVDDT bits
;Heavy load protection mode
;Sets the SVDON to "1"
;Sets the SVDON to "0"
;Checks the SVDDT bit
;Shifts the mode to
MX,1010B
NZ,HLMOD
MX,0001B
MX,1110B
A,0010B
Z,HLMOD
OR
AND
FAN
JP
;the heavy load protection mode
LD
AND
RET
Y,FLAG
MY,0
;Resets the flag to "0"
;Sets the flag to "1"
;
HLMOD: LD
OR
Y,FLAG
MY,1
RET
Th e above program operates th e h eavy load protection
fu n ction by u sin g th e SVDON register. In th e n orm al
operation m ode, su pply voltage detection is don e from th e
SVDON register an d wh en th e su pply voltage drops below
th e criteria voltage, th e m ode sh ifts to th e h eavy load
protection m ode. In th e h eavy load protection m ode,
su pply voltage detection by th e h ardware is don e every 2
Hz an d th e detection resu lt is stored in th e SVDDT regis-
ter. Becau se of th is, th e SVDDT register will be "1" du rin g
th e h eavy load protection m ode. Moreover, in th e above
program , su pply voltage detection by th e SVDON is
h alted du rin g th e h eavy load protection m ode. If th e
su pply voltage becom e grater th an th e criteria voltage,
th e SVDDT register valu e will becom e "0" an d h en ce,
su pply voltage detection th rou gh th e SVDON register will
resu m e after ch eckin g th e SVDDT register valu e. Wh en
u sed as a su b-rou tin e, th e above program will en able th e
u ser to determ in e wh eth er th e presen t operation m ode is
th e n orm al operation m ode (flag = "0") or th e h eavy load
protection m ode (flag = "1").
Th e flowch art for th e above program is sh own in th e n ext
page.
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CHAPTER 3: PERIPHERAL CIRCUITS (SVD Circuit and Heavy Load Protection Function)
Start
=1
HLMOD?
=0
=1
SVDDT?
=0
SVDON
←
1
0
SVDON←
=1
SVDDT?
=0
FLAG←0
FLAG←1
Fig. 3.8.4
Flowchart of operation
RET
through the SVDON register
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S1C62N51 TECHNICAL SOFTWARE
CHAPTER 3: PERIPHERAL CIRCUITS (Interrupt and Halt)
3.9 Inte rrup t a nd Ha lt
Inte rrup t m e m ory
m a p
Table 3.9.1 I/O memory map
Register
Address
Comment
*1
D3
D2
D1
D0
Name
EIK03
EIK02
EIK01
EIK00
0
Init
0
1
0
Enable
Enable
Enable
Enable
Mask
Mask
Mask
Mask
Interrupt mask register K03
Interrupt mask register K02
Interrupt mask register K01
Interrupt mask register K00
EIK03
EIK02
EIK01
EIK00
0
0E8H
0EBH
0ECH
0EDH
0EFH
0F0H
0
R/W
0
*5
0
R
0
EIT2
EIT8
R/W
0
EIT32
Enable
Enable
Enable
Mask
Mask
Mask
Interrupt mask register (clock timer) 2 Hz
Interrupt mask register (clock timer) 8 Hz
Interrupt mask register (clock timer) 32 Hz
EIT2
EIT8
EIT32
0
0
0
0
*5
*5
*5
0
R
0
EIAD
R/W
IK0
0
0
Enable
Mask
Interrupt mask register (A/D)
Interrupt factor flag (K00–K03)
EIAD
0
0
0
*5
*5
*5
*4
*5
*4
*4
*4
*5
*5
*5
*4
0
0
0
0
IT8
0
0
0
R
R
R
Yes
No
IK0
0
IT2
0
IT32
IAD
Yes
Yes
Yes
No
No
No
Interrupt factor flag (clock timer) 2 Hz
Interrupt factor flag (clock timer) 8 Hz
Interrupt factor flag (clock timer) 32 Hz
IT2
IT8
IT32
0
0
0
0
0
0
Yes
No
Interrupt factor flag (A/D)
IAD
0
*1 In itial valu e followin g in itial reset
*2 Not set in th e circu it
*3 Un defin ed
*4 Reset (0) im m ediately after bein g read
*5 Always "0" wh en bein g read
*6 Refer to m ain m an u al
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CHAPTER 3: PERIPHERAL CIRCUITS (Interrupt and Halt)
Th e S1C62N51 su pports th ree types of a total of 8
Control of inte rrup ts
a nd ha lt
in terru pts. Th ere are th ree tim er in terru pts (2 Hz, 8 Hz, 32
Hz), on e A/ D in terru pt an d fou r in pu t in terru pts (K00–K03).
Th e 8 in terru pts are in dividu ally en abled or m asked (dis-
abled) by in terru pt m ask registers. Th e EI an d DI in stru c-
tion s can be u sed to set or reset th e in terru pt flag (I), wh ich
en ables or disables all th e in terru pts at th e sam e tim e.
Wh en an in terru pt is accepted, th e in terru pt flag (I) is reset,
an d can n ot accepts an y oth er in terru pts (DI state).
Restart from th e h alt state created by th e HALT in stru ction ,
is don e by in terru pt.
• In t erru pt fact or flags
Th is flag is set wh en an y of th e K00 to K03 in pu t in terru pts
occu rs. Th e in terru pt factor flag (IK0) is set to "1" wh en th e
con ten ts of th e in pu t (K00–K03) becom e "1" an d th e data of
th e correspon din g in terru pt m ask register (EIK00–EIK03) is
"1".
IK0
Th e con ten ts of th e IK0 flag can be loaded by software to
determ in e wh eth er th e K00–K03 in pu t in terru pts h ave
occu red.
Th e flag is reset wh en loaded by software. (See Figu re
3.9.1.)
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CHAPTER 3: PERIPHERAL CIRCUITS (Interrupt and Halt)
K00
K01
K02
K03
Address 0E0H
Input interrupt factor
flag register (IK0)
INT
(Interrupt request)
FF
Interrupt flag (I)
D0
D1
D2
D3
Input interrupt mask register
(EIK00–EIK03)
Address 0E8H
Fig. 3.9.1
K00–K03
Input interrupt circuit
IT32 Th is flag is set to "1" wh en a fallin g edge is detected in th e
tim er TM1 (32 Hz) sign al.
Th e con ten ts of th e IT32 flag can be loaded by software to
determ in e wh eth er a 32 Hz tim er in terru pt h as occu red.
Th e flag is reset, wh en it is loaded by software. (See Figu re
3.9.2.)
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CHAPTER 3: PERIPHERAL CIRCUITS (Interrupt and Halt)
IT8 Th is flag is set to "1" wh en a fallin g edge is detected in th e
tim er TM1 (8 Hz) sign al.
Th e con ten ts of th e IT8 flag can be loaded by software to
determ in e wh eth er an 8 Hz tim er in terru pt h as occu red.
Th e flag is reset, wh en it is loaded by software. (See Figu re
3.9.2.)
IT2 Th is flag is set to "1" wh en a fallin g edge is detected in th e
tim er TM1 (2 Hz) sign al.
Th e con ten ts of th e IT2 flag can be loaded by software to
determ in e wh eth er a 2 Hz tim er in terru pt h as occu red.
Th e flag is reset, wh en it is loaded by software. (See Figu re
3.9.2.)
Timer interrupt
factor flag (IT)
32 Hz
D0
8 Hz
2 Hz
D1
D2
Address 0EFH
Timer interrupt
mask register (EIT)
D0
INT
D1
D2
(Interrupt request)
Address 0EBH
Interrupt flag (I)
Fig. 3.9.2
Timer interrupt circuit
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CHAPTER 3: PERIPHERAL CIRCUITS (Interrupt and Halt)
IAD Wh en th e cou n ted valu e reach es "0" du rin g th e cou n tin g-
down or cou n tin g-u p operation of th e u p/ down cou n ter, th is
flag is set to "1" at th e fallin g edge of th e n ext sign al du rin g
cou n tin g-down operation an d at th e risin g edge of th e n ext
sign al du rin g cou n tin g-u p operation .
Th e con ten ts of th e IAD flag can be loaded by software to
determ in e wh eth er an A/ D in terru pt h as occu rred.
Th e flag is reset, wh en it is loaded by software.
A/D converter
factor flag (IAD)
D0
Address 0F0H
A/D converter
mask register (EIAD)
INT
D0
(Interrupt request)
Fig. 3.9.3
Address 0ECH
Interrupt flag (I)
A/D interrupt circuit
Reading of interrupt factor flags is available at EI, but be careful in
the following cases.
Note
If the interrupt mask register value corresponding to the interrupt
factor flags to be read is set to "1", an interrupt request will be
generated by the interrupt factor flags set timing, or an interrupt
request will not be generated. Be very careful when interrupt factor
flags are in the same address.
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CHAPTER 3: PERIPHERAL CIRCUITS (Interrupt and Halt)
• In t erru pt m ask regist ers
Th e in terru pt m ask registers are registers th at in dividu ally
specify wh eth er to en able or m ask th e tim er in terru pt (2 Hz,
8 Hz, 32 Hz), A/ D in terru pt, or in pu t in terru pt (K00–K03).
Th e followin g are description s of th e in terru pt m ask regis-
ters.
EIK00 to EIK03 Th is register en ables or m asks th e K00–K03 in pu t in terru pt.
Th e in terru pt factor flag (IK0) is set to "1" wh en th e con ten ts
of th e in pu t (K00–K03) becom e "1" an d th e data of th e
correspon din g in terru pt m ask register (EIK00–EIK03) is "1".
Th e CPU is in terru pted if it is in th e EI state (in terru pt flag
[I] = "1"). (See Figu re 3.9.1.)
EIT32 Th is register en ables or m asks th e 32 Hz tim er in terru pt.
Th e CPU is in terru pted if it is in th e EI state wh en th e
in terru pt m ask register (EIT32) is set to "1" an d th e in ter-
ru pt factor flag (IT32) is "1". (See Figu re 3.9.2.)
EIT8 Th is register en ables or m asks th e 8 Hz tim er in terru pt. Th e
CPU is in terru pted if it is in th e EI state wh en th e in terru pt
m ask register (EIT8) is set to "1" an d th e in terru pt factor flag
(IT8) is "1". (See Figu re 3.9.2.)
EIT2 Th is register en ables or m asks th e 2 Hz tim er in terru pt. Th e
CPU is in terru pted if it is in th e EI state wh en th e in terru pt
m ask register (EIT2) is set to "1" an d th e in terru pt factor flag
(IT2) is "1". (See Figu re 3.9.2.)
EIAD Th is register en ables or m asks th e A/ D in terru pt. Th e CPU
is in terru pted if it is in th e EI state wh en th e in terru pt m ask
register (EIAD) is set to "1" an d th e in terru pt factor flag (IAD)
is "1". (See Figu re 3.9.3.)
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CHAPTER 3: PERIPHERAL CIRCUITS (Interrupt and Halt)
• In t erru pt vect or address
Th e S1C62N51 in terru pt vector address is m ade u p of th e
low-order 3 bits of th e program cou n ter (12 bits), each of
wh ich is assign ed a specific fu n ction as sh own in Figu re
3.9.4.
PCP3 PCP2 PCP1 PCP0 PCS7 PCS6 PCS5 PCS4 PCS3 PCS2 PCS1 PCS0
0
0
0
1
0
0
0
0
0
×
×
×
Fig. 3.9.4
Assignment of the
Input (K00–K03) interrupt
A/D interrupt
Clock timer interrupt
interrupt vector address
Note th at all of th e th ree tim er in terru pts h ave th e sam e
vector address, an d software m u st be u sed to ju dge wh eth er
or n ot a given tim er in terru pt h as occu rred. For in stan ce,
wh en th e 32 Hz tim er in terru pt an d th e 8 Hz tim er in terru pt
are en abled at th e sam e tim e, th e accepted tim er in terru pt
m u st be iden tified by software. (Sim ilarly, th e K00–K03
in pu t in terru pts an d A/ D in terru pt m u st be iden tified by
software.)
Wh en an in terru pt is gen erated, th e h ardware resets th e
in terru pt flag (I) to en ter th e DI state. Execu te th e EI in -
stru ction as n ecessary to recover th e EI state after in terru pt
processin g.
Set th e EI state at th e start of th e in terru pt processin g
rou tin e to allow n estin g of th e in terru pts.
Th e in terru pt factor flags m u st always be reset before set-
tin g th e EI statu s in th e correspon din g in terru pt processin g
rou tin e. (Th e flag is reset wh en th e in terru pt factor flag is
read by software.)
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CHAPTER 3: PERIPHERAL CIRCUITS (Interrupt and Halt)
If th e EI in stru ction is execu ted with ou t resetting th e in ter-
ru pt factor flag after gen eratin g th e tim er in terru pt or A/ D
in terru pt, an d if th e correspon din g in terru pt m ask register
is still "1", th e sam e in terru pt is gen erated on ce m ore. (See
Figu re 3.9.5.)
If th e EI state is set with ou t resetting th e in terru pt factor
flag after gen eratin g th e in pu t in terru pt (K00–K03), th e sam e
in terru pt is gen erated on ce m ore. (See Figu re 3.9.5.)
Th e in terru pt factor flag m u st always be read (reset) in th e
DI state (in terru pt flag [I] = "0"). Th ere m ay be an operation
error if read in th e EI state.
Th e tim er in terru pt factor flags (IT32, IT8, IT2) an d A/ D
in terru pt factor flag (IAD) are set wh eth er th e correspon din g
in terru pt m ask register is set or n ot.
Th e in pu t in terru pt factor flag (IK0) is allowed to be set in
th e con dition wh en th e correspon din g in terru pt m ask regis-
ter (EIK00–EIK03) is set to "1" (in terru pt is en abled). (See
Figu re 3.9.5.)
Table 3.9.2 sh ows th e in terru pt vector m ap.
Table 3.9.2
Page
Step
00H
01H
02H
03H
04H
05H
06H
07H
Interrupt vector
Interrupt vector map
Initial reset
Clock timer interrupt
A/D interrupt
Clock timer interrupt and A/D interrupt
Input (K00–K03) interrupt
Input interrupt and clock timer interrupt
Input interrupt and A/D interrupt
Generation of all interrupt
1
Addresses (start address of in terru pt processin g rou tin es) to
ju m p to are written in to th e addresses available for in terru pt
vector allocation .
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S1C62N51 TECHNICAL SOFTWARE
CHAPTER 3: PERIPHERAL CIRCUITS (Interrupt and Halt)
Interrupt vector
(MSB)
K00
:
EIK00
Program counter of CPU
:
(three low-order bits)
(LSB)
K01
EIK01
IK0
INT
K02
(Interrupt request)
EIK02
K03
EIK03
IAD
EIAD
IT2
Interrupt factor flag
EIT2
IT8
Interrupt mask register
EIT8
Fig. 3.9.5
Internal interrupt
circuit
IT32
EIT32
• Rest art from h alt st at e by in t erru pt
Exa m p le s of inte rrup t
a nd ha lt c ontrol
p rog ra m
Main routine
Label
Mnemonic/operand
Comment
LD
X,0E8H
;Set address of K00 to K03
;interrupt mask register
;Enable K00 to K03
;input interrupt
OR
MX,1111B
;
;
LD
OR
LD
OR
X,0ECH
;Set address of A/D interrupt
;mask register
;Enable A/D interrupt
MX,0001B
X,0EBH
;mask register
MX,0111B
;Set address of timer interrupt
;Enable timer interrupt
;(32 Hz, 8 Hz, 2 Hz)
;Set interrupt flag (EI state is set)
;Halt mode
MAIN: EI
HALT
JP
MAIN
;Jump to MAIN
S1C62N51 TECHNICAL SOFTWARE
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CHAPTER 3: PERIPHERAL CIRCUITS (Interrupt and Halt)
Interruption vector routine
Label
Mnemonic/operand
Comment
ORG
JP
JP
JP
JP
100H
INIT
INTR
INTR
INTR
;Timer interrupt is generated
;A/D interrupt is generated
;Timer interrupt, A/D interrupt
;are generated
JP
JP
INTR
INTR
;K00 to K03 interrupt is generated
;Timer interrupt, K00 to K03 interrupt
;are generated
JP
JP
INTR
INTR
;A/D interrupt, K00 to K03 interrupt
;are generated
;Timer interrupt, A/D interrupt,
;K00 to K03 interrupt are generated
;
INTR:
LD
X,0EFH
;Address of timer interrupt factor flag
LD
LD
Y,TMFSK ;Address of timer interrupt factor flag buffer
MY,MX
FAN
JP
MY,0100B ;Check 2 Hz timer interrupt
Z,TI8RQ ;Jump if not 2 Hz timer interrupt
CALL
TINT2
;Call 2 Hz timer interrupt service routine
TI8RQ:
TI32RQ:
ADRQ:
LD
FAN
JP
Y,TMFSK ;Address of timer factor flag buffer
MY,0010B ;Check 8 Hz timer interrupt
Z,TI32RQ ;Jump if not 8 Hz timer interrupt
CALL
TINT8
;Call 8 Hz timer interrupt service routine
LD
FAN
JP
Y,TMFSK ;Address of timer factor flag buffer
MY,0001B ;Check 8 Hz timer interrupt
Z,ADRQ
TINT32
;Jump if not 32 Hz timer interrupt
;Call 32 Hz timer interrupt service routine
CALL
LD
X,0F0H
;Address of A/D interrupt factor flag
FAN
JP
MX,0001B ;Check A/D interrupt factor flag
Z,IK0RQ ;Jump if not A/D interrupt
CALL
ADIN
;Call A/D interrupt service routine
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S1C62N51 TECHNICAL SOFTWARE
CHAPTER 3: PERIPHERAL CIRCUITS (Interrupt and Halt)
IK0RQ:
LD
FAN
JP
X,0EDH
;Address of K00 to K03 input interrupt flag
MX,0001B ;Check K00 to K03 input interrupt
Z,INTEND ;Jump if not K00 to K03 input interrupt
CALL
IK0INT
;Call K00 to K03 input interrupt service
;routine
INTEND:
EI
RET
Th e above program is n orm ally u sed to restart th e CPU
wh en in th e h alt state by in terru pt an d to retu rn it to th e
h alt state again after th e in terru pt processin g is com pleted.
Th e processin g proceeds by repeatin g th e → h alt in terru pt
→ h alt → in terru pt cycle.
Th e in terru pt factor flag is reset wh en load by th e software.
Th u s, wh en u sin g in terru pts wh ich in terru pt factor flags are
in th e sam e address at th e sam e tim e, flag ch eck m u st be
don e after storin g th e data. For exam ple, store th e 1 word
in clu din g th e factor flag in th e RAM. (If ch eck is directly
don e by th e FAN in stru ction , th e factor flags of th e sam e
address are all reset.)
Readin g of in terru pt factor flags is available at EI, bu t be
carefu l in th e followin g cases.
If th e in terru pt m ask register valu e correspon din g to th e
in terru pt factor flags to be read is set to "1", an in terru pt
requ est will be gen erated by th e in terru pt factor flags set
tim in g, or an in terru pt requ est will n ot be gen erated.
S1C62N51 TECHNICAL SOFTWARE
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II-65
CHAPTER 4: SUMMARY OF PROGRAMMING POINTS
CHAPTER 4
SUMMARY OF PROGRAMMING
POINTS
•
Core CPU
After th e system reset, on ly th e program cou n ter (PC),
n ew page poin ter (NPP) an d in terru pt flag (I) are in itial-
ized by th e h ardware. Th e oth er in tern al circu its wh ose
settin gs are u n defin ed m u st be in itialized with th e pro-
gram .
•
•
Power Supply
Data Memory
Extern al load drivin g th rou gh th e ou tpu t voltage of con -
stan t voltage circu it or booster circu it is n ot perm itted.
– Sin ce som e portion s of th e RAM are also u sed as stack
area du rin g su brou tin e call or register savin g, see to it
th at th e data area an d th e stack area do n ot overlap.
– Th e stack area con su m es 3 words du rin g a su brou tin e
call or in terru pt.
– Address 00H–0FH in th e RAM is th e m em ory register area
addressed by th e register poin ter RP.
– Mem ory is n ot m ou n ted in u n u sed area with in th e m em -
ory m ap an d in m em ory area n ot in dicated in th is m an -
u al. For th is reason , n orm al operation can n ot be assu red
for program s th at h ave been prepared with access to
th ese areas.
•
Initial Reset
– Main tain th e in itial reset circu it at h igh level for at least 4
secon ds (in case of oscillation frequ en cy fosc = 32 kHz)
becau se n oise rejector is bu ilt-in .
– Wh en u tilizin g th e sim u ltan eou s h igh in pu t reset fu n c-
tion of th e in pu t ports (K00–K03), take care n ot to m ake
th e ports specified du rin g n orm al operation to go h igh
sim u ltan eou sly.
•
Input Port
Wh en m odifyin g th e in pu t port from h igh level to low level
with pu ll-down resistan ce, a delay will occu r at th e rise of
th e waveform du e to tim e con stan t of th e pu ll-down
resistan ce an d in pu t gate capacities. Provide appropriate
waitin g tim e in th e program wh en perform in g in pu t port
readin g.
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S1C62N51 TECHNICAL SOFTWARE
CHAPTER 4: SUMMARY OF PROGRAMMING POINTS
•
•
Output Port
I/O Port
Th e FOUT an d BUZZER ou tpu t sign al m ay produ ce
h azards wh en th e ou tpu t ports R00 an d R01 are tu rn ed
on or off.
– Wh en th e I/ O port is set to th e ou tpu t m ode an d a low-
im pedan ce load is con n ected to th e port pin , th e data
written to th e register m ay differ from th e data read.
– Wh en th e I/ O port is set to th e in pu t m ode an d a low-
level voltage (VSS) is in pu t by th e bu ilt-in pu ll-down
resistan ce, an erron eou s in pu t resu lts if th e tim e con -
stan t of th e capacitive load of th e in pu t lin e an d th e bu ilt-
in pu ll-down resistan ce load is greater th an th e read-ou t
tim e. Wh en th e in pu t data is bein g read, th e tim e th at th e
in pu t lin e is pu lled down is equ ivalen t to 0.5 cycles of th e
CPU system clock.
Hen ce, th e electric poten tial of th e pin s m u st settle with in
0.5 cycles. If th is con dition can n ot be m et, som e m easu re
m u st be devised, su ch as arran gin g a pu ll-down resist-
an ce extern ally, or perform in g m u ltiple read-ou ts.
•
LCD Driver
– Becau se th e display m em ory is for writin g on ly, re-writin g
th e con ten ts with com pu tin g in stru ction s (e.g., AND, OR,
etc.) wh ich com e with read-ou t operation s is n ot possible.
To perform bit operation s, a bu ffer to h old th e display
data is requ ired on th e RAM.
– Even wh en 1/ 2 du ty is selected, th e display data corre-
spon din g to COM2 an d COM3 are valid for static drive.
Hen ce, for static drive set th e sam e valu e to all display
m em ory correspon din g COM0–COM3.
– Even wh en 1/ 3 du ty is selected, th e display data corre-
spon din g to COM3 is valid for static drive. Hen ce, for
static drive set th e sam e valu e to all display m em ory
correspon din g COM0–COM3.
– For caden ce adju stm en t, set th e display data in clu din g
display data correspon din g to COM3.
– fosc in dicates th e oscillation frequ en cy of th e oscillation
circu it.
S1C62N51 TECHNICAL SOFTWARE
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II-67
CHAPTER 4: SUMMARY OF PROGRAMMING POINTS
•
A/D Converter
– Depen din g on th e in itial valu e of th e u p-cou n ter C0–C15,
th e u p/ down cou n ter TC0–TC15 m ay overflow wh ile th e
CR oscillation clock is bein g cou n ted. Wh en settin g th e
in itial valu e, pay atten tion to CR oscillation frequ en cy, its
flu ctu ation ran ge an d th e in pu t clock frequ en cy of th e
u p/ down cou n ter. If th e u p/ down cou n ter overflows, A/ D
con version is term in ated im m ediately, an d correct m eas-
u rem en t is im possible.
– If th e u p/ down cou n ter TC0–TC15 is m easu red after A/ D
con version , it m ay n ot in dicate "0000H". Th is is n ot du e
to in correct tim in g in term in atin g A/ D con version bu t
becau se th e cou n tin g down clock is in pu t after th e con -
trol sign al is ou tpu t to th e u p-cou n ter to term in ate
cou n tin g.
•
Supply Voltage Detec-
tion (SVD) Circuit
Sin ce su pply voltage detection is au tom atically perform ed
by th e h ardware every 2 Hz (0.5 sec) wh en th e h eavy load
protection fu n ction operates, do n ot perm it th e operation
of th e SVD circu it by th e software in order to m in im ize
power cu rren t con su m ption .
•
•
Heavy Load Protec-
tion Function
In th e h eavy load protection fu n ction (h eavy load protec-
tion m ode flag = "1"), su pply voltage detection th rou gh
th e SVDON register is n ot perm itted in order to m in im ize
power cu rren t con su m ption .
Interrupt
– Restart from th e HALT state is perform ed by th e in ter-
ru pt. Th e retu rn address after com pletion of th e in terru pt
processin g in th is case will be th e address followin g th e
HALT in stru ction .
– Wh en in terru pt occu rs, th e in terru pt flag will be reset by
th e h ardware an d it will becom e DI state. After com ple-
tion of th e in terru pt processin g, set to th e EI state
th rou gh th e software as n eeded.
Moreover, th e n estin g level m ay be set to be program -
m able by settin g to th e EI state at th e begin n in g of th e
in terru pt processin g rou tin e.
II-68
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S1C62N51 TECHNICAL SOFTWARE
CHAPTER 4: SUMMARY OF PROGRAMMING POINTS
– Be su re to reset th e in terru pt factor flag before settin g to
th e EI state on th e in terru pt processin g rou tin e. Th e
in terru pt factor flag is reset by readin g th rou gh th e
software. Not resettin g th e in terru pt factor flag an d
in terru pt m ask register bein g "1", will cau se th e sam e
in terru pt to occu r again .
– Th e in terru pt factor flag will be reset by readin g th rou gh
th e software. Becau se of th is, wh en m u ltiple in terru pt
factor flags are to be assign ed to th e sam e address,
perform th e flag ch eck after th e con ten ts of th e address
h as been stored in th e RAM. Direct ch eckin g with th e
FAN in stru ction will cau se all th e in terru pt factor flag to
be reset.
– Readin g of in terru pt factor flags is available at EI, bu t be
carefu l in th e followin g cases.
If th e in terru pt m ask register valu e correspon din g to th e
in terru pt factor flags to be read is set to "1", an in terru pt
requ est will be gen erated by th e in terru pt factor flags set
tim in g, or an in terru pt requ est will n ot be gen erated.
•
Vacant Register and
Read/Write
Writin g data in to th e addresses wh ere read/ write bits
an d read on ly bits are m ixed in 1 word (4 bits) does n ot
affect th e read on ly bits.
S1C62N51 TECHNICAL SOFTWARE
EPSON
II-69
APPENDIX A TABLE OF INSTRUCTIONS
APPENDIX A
Ta b le of Instruc tions
Operation Code
Flag
Mne-
monic
Classification
Operand
Clock
Operation
B
1
0
0
0
0
0
1
0
A
1
0
0
0
1
1
1
1
9
1
0
1
1
1
1
1
0
8
7
6
5
4
3
2
1
0
I D Z C
Branch
PSET
p
0
0
1
0 p4 p3 p2 p1 p0
5
5
5
5
5
5
5
7
NBP ←p4, NPP←p3~p0
instructions JP
s
0 s7 s6 s5 s4 s3 s2 s1 s0
0 s7 s6 s5 s4 s3 s2 s1 s0
1 s7 s6 s5 s4 s3 s2 s1 s0
0 s7 s6 s5 s4 s3 s2 s1 s0
1 s7 s6 s5 s4 s3 s2 s1 s0
PCB ←NBP, PCP←NPP, PCS ←s7~s0
PCB ←NBP, PCP←NPP, PCS ←s7~s0 if C=1
PCB ←NBP, PCP←NPP, PCS ←s7~s0 if C=0
PCB ←NBP, PCP←NPP, PCS ←s7~s0 if Z=1
PCB ←NBP, PCP←NPP, PCS ←s7~s0 if Z=0
PCB ←NBP, PCP←NPP, PCSH ←B, PCSL ←A
M(SP-1) ←PCP, M(SP-2) ←PCSH, M(SP-3) ←PCSL+1
SP←SP-3, PCP←NPP, PCS ←s7~s0
C, s
NC, s
Z, s
NZ, s
JPBA
1 1 1 1 0 1 0 0 0
CALL
CALZ
RET
s
s
0 s7 s6 s5 s4 s3 s2 s1 s0
0
1
1
0
1
1
1
0
0
1
1
0
1 s7 s6 s5 s4 s3 s2 s1 s0
7
7
M(SP-1) ←PCP, M(SP-2) ←PCSH, M(SP-3)← PCSL+1
SP←SP-3, PCP ←0, PCS ←s7~s0
1
1
1
1
1
1
1
0
0
1
1
1
1
1
1
1
1
1
0
PCSL← M(SP), PCSH←M(SP+1), PCP ←M(SP+2)
SP ←SP+3
RETS
RETD
12 PCSL←M(SP), PCSH←M(SP+1), PCP←M(SP+2)
SP← SP+3, PC← PC+1
l
l7 l6 l5 l4 l3 l2 l1 l0
12 PCSL ←M(SP), PCSH←M(SP+1), PCP←M(SP+2)
SP← SP+3, M(X) ←i3~i0, M(X+1) ←l7~l4, X← X+2
System
control
NOP5
NOP7
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
0
0
0
1
0
0
0
1
1
0
0
0
1
1
0
0
0
5
7
5
5
5
5
5
5
5
5
5
5
5
5
5
7
7
7
7
No operation (5 clock cycles)
No operation (7 clock cycles)
Halt (stop clock)
X← X+1
instructions HALT
Index
INC
X
operation
Y
Y← Y+1
instructions LD
X, x
Y, y
XH, r
XL, r
YH, r
YL, r
r, XH
r, XL
r, YH
r, YL
1 x7 x6 x5 x4 x3 x2 x1 x0
0 y7 y6 y5 y4 y3 y2 y1 y0
XH← x7~x4, XL ←x3~x0
YH← y7~y4, YL ←y3~y0
XH← r
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
1 r1 r0
0 r1 r0
1 r1 r0
0 r1 r0
1 r1 r0
0 r1 r0
1 r1 r0
0 r1 r0
XL← r
YH← r
YL← r
r ←XH
r ←XL
r ←YH
r ←YL
ADC XH, i
XL, i
i3 i2 i1 i0
i3 i2 i1 i0
i3 i2 i1 i0
i3 i2 i1 i0
↑ ↑
↓ ↓
XH← XH+i3~i0+C
XL← XL+i3~i0+C
YH← YH+i3~i0+C
YL← YL+i3~i0+C
↑ ↑
↓ ↓
YH, i
↑ ↑
↓ ↓
YL, i
↑ ↑
↓ ↓
II-70
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S1C62N51 TECHNICAL SOFTWARE
APPENDIX A TABLE OF INSTRUCTIONS
Operation Code
Flag
Mne-
monic
Classification
Operand
Clock
Operation
B
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
A
0
0
0
0
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
9
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
8
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
7
0
0
0
0
0
1
1
1
1
1
0
1
0
1
6
1
1
1
1
5
0
0
1
1
4
0
1
0
1
3
2
1
0
I D Z C
Index
CP
XH, i
XL, i
YH, i
YL, i
r, i
i3 i2 i1 i0
i3 i2 i1 i0
i3 i2 i1 i0
i3 i2 i1 i0
↑ ↑
↓ ↓
7
7
7
7
5
5
5
5
5
5
5
5
5
5
5
7
7
7
7
7
7
7
7
7
7
5
5
5
5
5
5
5
5
5
5
5
XH-i3~i0
operation
instructions
↑ ↑
↓ ↓
XL-i3~i0
↑ ↑
↓ ↓
YH-i3~i0
↑ ↑
↓ ↓
YL-i3~i0
Data
LD
0 r1 r0 i3 i2 i1 i0
r ←i3~i0
transfer
instructions
r, q
1
0
0
0
0
1
1
1
1
0
1
1
0
0
1
1
1
1
0 r1 r0 q1 q0
0 n3 n2 n1 n0
1 n3 n2 n1 n0
0 n3 n2 n1 n0
1 n3 n2 n1 n0
r ←q
A, Mn
B, Mn
Mn, A
Mn, B
A← M(n3~n0)
B← M(n3~n0)
M(n3~n0)←A
M(n3~n0)←B
LDPX MX, i
r, q
0
i3 i2 i1 i0
0 r1 r0 q1 q0
i3 i2 i1 i0
1 r1 r0 q1 q0
M(X)←i3~i0, X← X+1
r←q, X←X+1
LDPY MY, i
r, q
1
M(Y) ←i3~i0, Y ←Y+1
r ←q, Y←Y+1
LBPX MX, l
l7 l6 l5 l4 l3 l2 l1 l0
M(X) ←l3~l0, M(X+1)← l7~l4, X ←X+2
F←F i3~i0
Flag
SET
RST
F, i
F, i
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
1
0
1
0
1
1
0
0
0
0
0
0
0
1
1
1
i3 i2 i1 i0 ↑ ↑ ↑ ↑
i3 i2 i1 i0 ↓ ↓ ↓ ↓
operation
F←F i3~i0
instructions SCF
0
1
0
1
0
1
1
0
1
1
0
0
0
1
1
1
0
0
0
0
1
0
1
1
0
0
1
0
0
0
1
1
0
0
1
0
1
1
1
1
0
0
1
0
1
0
1
1
1
↑
↓
C←1
RCF
SZF
RZF
SDF
RDF
EI
C←0
↑
↓
Z←1
Z←0
↑
↓
D←1 (Decimal Adjuster ON)
D←0 (Decimal Adjuster OFF)
I ←1 (Enables Interrupt)
I ←0 (Disables Interrupt)
SP← SP+1
↑
↓
DI
Stack
INC
SP
operation
DEC SP
SP← SP-1
instructions PUSH
r
0 r1 r0
SP← SP-1, M(SP)←r
SP← SP-1, M(SP)←XH
SP← SP-1, M(SP)←XL
SP← SP-1, M(SP)←YH
SP← SP-1, M(SP)←YL
SP← SP-1, M(SP)←F
r ←M(SP), SP←SP+1
XH← M(SP), SP← SP+1
XL← M(SP), SP← SP+1
XH
XL
YH
YL
F
1
1
0
0
0
0
1
0
0
1
1
0
0
1
0
POP
r
0 r1 r0
XH
XL
1
1
0
1
1
0
S1C62N51 TECHNICAL SOFTWARE
EPSON
II-71
APPENDIX A TABLE OF INSTRUCTIONS
Operation Code
Flag
Mne-
monic
Classification
Operand
Clock
Operation
B
1
1
1
A
1
1
1
1
1
1
1
1
0
1
0
0
1
0
1
0
1
0
1
0
1
1
1
1
0
1
1
1
1
1
1
1
1
9
1
1
1
1
1
1
1
0
1
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
1
1
1
1
1
1
1
1
0
8
1
1
1
1
1
1
1
0
0
0
0
0
1
0
0
0
0
0
1
0
1
1
1
1
0
0
1
1
1
1
1
1
1
7
1
1
1
1
1
1
1
0
1
0
1
1
0
1
1
1
1
1
0
1
1
0
1
0
1
1
0
0
0
0
0
0
0
6
1
1
1
1
1
1
1
5
0
0
0
1
1
1
1
4
1
1
1
0
1
0
1
3
1
1
1
0
0
0
0
2
0
0
0
1
0
0
1
0
0
1
0
I D Z C
Stack
POP
YH
YL
F
5
5
5
5
5
5
5
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
5
7
7
7
7
7
7
7
YH← M(SP), SP← SP+1
operation
instructions
YL← M(SP), SP← SP+1
F←M(SP), SP←SP+1
SPH← r
↑ ↑ ↑ ↑
↓ ↓ ↓ ↓
LD
SPH, r 1
SPL, r
r, SPH 1
r, SPL
Arithmetic ADD r, i
0 r1 r0
0 r1 r0
1 r1 r0
1 r1 r0
1
SPL ← r
r← SPH
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
r← SPL
0 r1 r0 i3 i2 i1 i0
ꢀ ↑ ↑
↓ ↓
r← r+i3~i0
r← r+q
instructions
r, q
ADC r, i
r, q
0
0
0 r1 r0 q1 q0 ꢀ ↑ ↑
↓ ↓
1 r1 r0 i3 i2 i1 i0
ꢀ ↑ ↑
↓ ↓
r← r+i3~i0+C
r← r+q+C
0
0
0
1
1 r1 r0 q1 q0 ꢀ ↑ ↑
↓ ↓
SUB r, q
0 r1 r0 q1 q0 ꢀ ↑ ↑
r← r-q
↓ ↓
SBC
r, i
1 r1 r0 i3 i2 i1 i0
ꢀ ↑ ↑
↓ ↓
r← r-i3~i0-C
r← r-q-C
r, q
0
1
1 r1 r0 q1 q0 ꢀ ↑ ↑
↓ ↓
AND r, i
r, q
0 r1 r0 i3 i2 i1 i0
0 r1 r0 q1 q0
1 r1 r0 i3 i2 i1 i0
1 r1 r0 q1 q0
0 r1 r0 i3 i2 i1 i0
0 r1 r0 q1 q0
1 r1 r0 i3 i2 i1 i0
0 r1 r0 q1 q0
0 r1 r0 i3 i2 i1 i0
↑
↓
r← r i3~i0
1
0
↑
↓
r← r
r← r i3~i0
r← r
r← r i3~i0
r← r
q
OR
r, i
↑
↓
r, q
1
0
↑
↓
q
XOR r, i
r, q
↑
↓
1
1
↑
↓
q
CP
r, i
↑ ↑
↓ ↓
r-i3~i0
r-q
r, q
0
0
↑ ↑
↓ ↓
FAN r, i
r, q
↑
↓
r
r
i3~i0
q
0
1
0
1
1
0
0
0
0
0
1
0
1
1
1
1
1
1
1 r1 r0 q1 q0
1 r1 r0 r1 r0
↑
↓
RLC
RRC
INC
r
↑ ↑
↓ ↓
d3 ←d2, d2 ←d1, d1 ←d0, d0 ←C, C← d3
d3 ←C, d2 ←d3, d1 ←d2, d0 ←d1, C← d0
M(n3~n0) ←M(n3~n0)+1
r
0
1
1 r1 r0
↑ ↑
↓ ↓
Mn
0 n3 n2 n1 n0
1 n3 n2 n1 n0
↑ ↑
↓ ↓
DEC Mn
↑ ↑
↓ ↓
M(n3~n0) ←M(n3~n0)-1
ACPX MX, r
ACPY MY, r
SCPX MX, r
SCPY MY, r
0
0
1
1
1
1
1
1
0 r1 r0
1 r1 r0
0 r1 r0
1 r1 r0
ꢀ ↑ ↑
↓ ↓
M(X) ←M(X)+r+C, X ←X+1
M(Y) ←M(Y)+r+C, Y ←Y+1
M(X) ←M(X)-r-C, X← X+1
M(Y) ←M(Y)-r-C, Y← Y+1
r ←r
ꢀ ↑ ↑
↓ ↓
ꢀ ↑ ↑
↓ ↓
ꢀ ↑ ↑
↓ ↓
NOT
r
0 r1 r0 1
1
1
1
↑
↓
II-72
EPSON
S1C62N51 TECHNICAL SOFTWARE
APPENDIX A TABLE OF INSTRUCTIONS
Abbreviation s u sed in th e explan ation s h ave th e followin g
m ean in gs.
A .............. A register
B .............. B register
Symbols associated with
registers and memory
X .............. XHL register (low order eigh t bits of in dex
register IX)
Y .............. YHL register (low order eigh t bits of in dex
register IY)
XH ........... XH register (h igh order fou r bits of XHL register)
XL ............ XL register (low order fou r bits of XHL register)
YH ............ YH register (h igh order fou r bits of YHL register)
YL ............ YL register (low order fou r bits of YHL register)
XP ............ XP register (h igh order fou r bits of in dex
register IX)
YP ............ YP register (h igh order fou r bits of in dex
register IY)
SP ............ Stack poin ter SP
SPH .......... High -order fou r bits of stack poin ter SP
SPL .......... Low-order fou r bits of stack poin ter SP
MX, M(X) .. Data m em ory wh ose address is specified with
in dex register IX
MY, M(Y)... Data m em ory wh ose address is specified with
in dex register IY
Mn , M(n ) .. Data m em ory address 000H–00FH (address
specified with im m ediate data n of 00H–0FH)
M(SP) ....... Data m em ory wh ose address is specified with
stack poin ter SP
r, q ........... Two-bit register code
r, q is two-bit im m ediate data; accordin g to th e
con ten ts of th ese bits, th ey in dicate registers A,
B, an d MX an d MY (data m em ory wh ose ad-
dresses are specified with in dex registers IX an d
IY)
r
q
Registers specified
r1
0
r0
0
q1
0
q0
0
A
B
0
1
0
1
1
0
1
0
MX
MY
1
1
1
1
S1C62N51 TECHNICAL SOFTWARE
EPSON
II-73
APPENDIX A TABLE OF INSTRUCTIONS
Symbols associated with NBP ..... New ban k poin ter
program counter NPP ..... New page poin ter
PCB ..... Program cou n ter ban k
PCP ..... Program cou n ter page
PCS ..... Program cou n ter step
PCSH .. Fou r h igh order bits of PCS
PCSL ... Fou r low order bits of PCS
Symbols associated with
flags
F ......... Flag register (I, D, Z, C)
C ......... Carry flag
Z ......... Zero flag
D ......... Decim al flag
I .......... In terru pt flag
↓ ............. Flag reset
↑ ............. Flag set
ꢀ .......... Flag set or reset
Associated with p ......... Five-bit im m ediate data or label 00H–1FH
immediate data s .......... Eigh t-bit im m ediate data or label 00H–0FFH
l .......... Eigh t-bit im m ediate data
i .......... Fou r-bit im m ediate data
00H–0FFH
00H–0FH
Associated with
arithmetic and other
operations
+ ......... Add
- .......... Su btract
............. Logical AND
............. Logical OR
............ Exclu sive-OR
ꢀ......... Add-su btract in stru ction for decim al operation
wh en th e D flag is set
II-74
EPSON
S1C62N51 TECHNICAL SOFTWARE
APPENDIX B RAM MAP
APPENDIX B
RAM Ma p
S1C62N51 TECHNICAL SOFTWARE
EPSON
II-75
APPENDIX B RAM MAP
II-76
EPSON
S1C62N51 TECHNICAL SOFTWARE
APPENDIX C TABLE OF THE ICE COMMANDS
APPENDIX C
Ta b le of the ICE Com m a nd s
Item No.
Function
Command Format
Outline of Operation
Assemble command mnemonic code and store at address "a"
Contents of addresses a1 to a2 are disassembled and displayed
Contents of program area a1 to a2 are displayed
Content of data area a1 to a2 are displayed
Data d is set in addresses a1 to a2 (program area)
Data d is set in addresses a1 to a2 (data area)
Program is executed from the "a" address
Execution time and step counter selection
On-the-fly display selection
1
2
3
Assemble
Disassemble #L,a1,a2
Dump
Fill
#A,a
#DP,a1,a2
#DD,a1,a2
#FP,a1,a2,d
#FD,a1,a2,d
#G,a
4
5
Set
Run Mode
#TIM
#OTF
6
7
Trace
Break
#T,a,n
Executes program while displaying results of step instruction
from "a" address
Displays only the final step of #T,a,n
Sets Break at program address "a"
Breakpoint is canceled
Break condition is set for data RAM
Breakpoint is canceled
Break condition is set for Evaluation Board CPU internal registers
Breakpoint is canceled
Combined break conditions set for program data RAM address
and registers
#U,a,n
#BA,a
#BAR,a
#BD
#BDR
#BR
#BRR
#BM
#BMR
Cancel combined break conditions for program data ROM
address and registers
#BRES
All break conditions canceled
#BC
Break condition displayed
#BE
Enter break enable mode
#BSYN
#BT
Enter break disable mode
Set break stop/trace modes
#BRKSEL,REM
#MP,a1,a2,a3
Set BA condition clear/remain modes
Contents of program area addresses a1 to a2 are moved to
addresses a3 and after
8
Move
#MD,a1,a2,a3
Contents of data area addresses a1 to a2 are moved to addresses
a3 and after
9
Data Set
#SP,a
#SD,a
Data from program area address "a" are written to memory
Data from data area address "a" are written to memory
Display Evaluation Board CPU internal registers
Set Evaluation Board CPU internal registers
Reset Evaluation Board CPU
10
Change CPU #DR
Internal
Registers
#SR
#I
#DXY
#SXY
Display X, Y, MX and MY
Set data for X and Y display and MX, MY
S1C62N51 TECHNICAL SOFTWARE
EPSON
II-77
APPENDIX C TABLE OF THE ICE COMMANDS
Item No.
Function
Command Format
Outline of Operation
Display history data for pointer 1 and pointer 2
Display upstream history data
11
History
#H,p1,p2
#HB
#HG
Display 21 line history data
#HP
Display history pointer
#HPS,a
#HC,S/C/E
Set history pointer
Sets up the history information acquisition before (S),
before/after (C) and after (E)
#HA,a1,a2
Sets up the history information acquisition from program area
a1 to a2
#HAR,a1,a2
Sets up the prohibition of the history information acquisition
from program area a1 to a2
#HAD
#HS,a
Indicates history acquisition program area
Retrieves and indicates the history information which executed
a program address "a"
#HSW,a
#HSR,a
#RF,file
#RFD,file
#VF,file
#VFD,file
#WF,file
#WFD,file
#CL,file
#CS,file
#CVD
Retrieves and indicates the history information which wrote or
read the data area address "a"
Move program file to memory
12
File
Move data file to memory
Compare program file and contents of memory
Compare data file and contents of memory
Save contents of memory to program file
Save contents of memory to data file
Load ICE set condition from file
Save ICE set condition to file
Indicates coverage information
Clears coverage information
13
14
Coverage
#CVR
ROM Access #RP
#VP
Move contents of ROM to program memory
Compare contents of ROM with contents of program memory
Set ROM type
#ROM
#Q
15
16
17
Terminate
ICE
Command
Display
Self
Terminate ICE and return to operating system control
#HELP
#CHK
Display ICE instruction
Report results of ICE self diagnostic test
Diagnosis
means press the RETURN key.
II-78
EPSON
S1C62N51 TECHNICAL SOFTWARE
APPENDIX D CROSS-ASSEMBLER PSEUDO-INSTRUCTION LIST
APPENDIX D
Cross-a sse m b le r Pse ud o-instruc tion List
Item No. Pseudo-instruction
Meaning
Example of Use
1
EQU
To allocate data to label
ABC
BCD
EQU
EQU
9
(Equation)
ABC+1
2
ORG
To define location counter
ORG
ORG
100H
256
(Origin)
3
SET
(Set)
To allocate data to label
(data can be changed)
ABC
ABC
SET
SET
0001H
0002H
4
DW
To define ROM data
ABC
BCD
DW
DW
'AB'
(Define Word)
0FFBH
5
PAGE
(Page)
To define boundary of page
To define boundary of section
To terminate assembly
To define macro
PAGE
PAGE
1H
3
6
SECTION
(Section)
SECTION
7
END
END
(End)
8
MACRO
(Macro)
CHECK
LOCAL
LOOP
MACRO
LOOP
CP
DATA
9
LOCAL
(Local)
To make local specification of label
during macro definition
MX,DATA
NZ,LOOP
JP
10
ENDM
To end macro definition
ENDM
(End Macro)
CHECK
1
S1C62N51 TECHNICAL SOFTWARE
EPSON
II-79
International Sales Operations
AMERICA
ASIA
EPSON ELECTRONICS AMERICA, INC.
EPSON (CHINA) CO., LTD.
28F, Beijing Silver Tower 2# North RD DongSanHuan
ChaoYang District, Beijing, CHINA
- HEADQUARTERS -
1960 E. Grand Avenue
EI Segundo, CA 90245, U.S.A.
Phone: 64106655
Fax: 64107319
Phone: +1-310-955-5300
Fax: +1-310-955-5400
SHANGHAI BRANCH
4F, Bldg., 27, No. 69, Gui Jing Road
Caohejing, Shanghai, CHINA
- SALES OFFICES -
West
Phone: 21-6485-5552
Fax: 21-6485-0775
150 River Oaks Parkway
San Jose, CA 95134, U.S.A.
Phone: +1-408-922-0200
EPSON HONG KONG LTD.
20/F., Harbour Centre, 25 Harbour Road
Wanchai, Hong Kong
Phone: +852-2585-4600 Fax: +852-2827-4346
Telex: 65542 EPSCO HX
Fax: +1-408-922-0238
Fax: +1-815-455-7633
Central
101 Virginia Street, Suite 290
Crystal Lake, IL 60014, U.S.A.
Phone: +1-815-455-7630
EPSON TAIWAN TECHNOLOGY & TRADING LTD.
10F, No. 287, Nanking East Road, Sec. 3
Taipei
Northeast
301 Edgewater Place, Suite 120
Phone: 02-2717-7360
Fax: 02-2712-9164
Wakefield, MA 01880, U.S.A.
Telex: 24444 EPSONTB
Phone: +1-781-246-3600
Fax: +1-781-246-5443
HSINCHU OFFICE
13F-3, No. 295, Kuang-Fu Road, Sec. 2
HsinChu 300
Southeast
3010 Royal Blvd. South, Suite 170
Alpharetta, GA 30005, U.S.A.
Phone: +1-877-EEA-0020 Fax: +1-770-777-2637
Phone: 03-573-9900
Fax: 03-573-9169
EPSON SINGAPORE PTE., LTD.
No. 1 Temasek Avenue, #36-00
EUROPE
Millenia Tower, SINGAPORE 039192
Phone: +65-337-7911
Fax: +65-334-2716
EPSON EUROPE ELECTRONICS GmbH
SEIKO EPSON CORPORATION KOREA OFFICE
50F, KLI 63 Bldg., 60 Yoido-dong
Youngdeungpo-Ku, Seoul, 150-763, KOREA
- HEADQUARTERS -
Riesstrasse 15
80992 Munich, GERMANY
Phone: 02-784-6027
Fax: 02-767-3677
Phone: +49-(0)89-14005-0
Fax: +49-(0)89-14005-110
SALES OFFICE
Altstadtstrasse 176
51379 Leverkusen, GERMANY
Phone: +49-(0)2171-5045-0
SEIKO EPSON CORPORATION
ELECTRONIC DEVICES MARKETING DIVISION
Fax: +49-(0)2171-5045-10
Electronic Device Marketing Department
IC Marketing & Engineering Group
421-8, Hino, Hino-shi, Tokyo 191-8501, JAPAN
UK BRANCH OFFICE
Unit 2.4, Doncastle House, Doncastle Road
Bracknell, Berkshire RG12 8PE, ENGLAND
Phone: +81-(0)42-587-5816
Fax: +81-(0)42-587-5624
Phone: +44-(0)1344-381700
Fax: +44-(0)1344-381701
ED International Marketing Department Europe & U.S.A.
421-8, Hino, Hino-shi, Tokyo 191-8501, JAPAN
FRENCH BRANCH OFFICE
1 Avenue de l' Atlantique, LP 915 Les Conquerants
Phone: +81-(0)42-587-5812
Fax: +81-(0)42-587-5564
Z.A. de Courtaboeuf 2, F-91976 Les Ulis Cedex, FRANCE
ED International Marketing Department Asia
Phone: +33-(0)1-64862350
Fax: +33-(0)1-64862355
421-8, Hino, Hino-shi, Tokyo 191-8501, JAPAN
Phone: +81-(0)42-587-5814
Fax: +81-(0)42-587-5110
BARCELONA BRANCH OFFICE
Barcelona Design Center
Edificio Prima Sant Cugat
Avda. Alcalde Barrils num. 64-68
E-08190 Sant Cugat del Vallès, SPAIN
Phone: +34-93-544-2490
Fax: +34-93-544-2491
In pursuit of “Saving”Technology, Epson electronic devices.
Our lineup of semiconductors, liquid crystal displays and quartz devices
assists in creating the products of our customers’ dreams.
Epson IS energy savings.
S1C62N51
Technical Manual
ELECTRONIC DEVICES MARKETING DIVISION
EPSON Electronic Devices Website
http://www.epson.co.jp/device/
First issue February, 1992
M
Printed March, 2001 in Japan
A
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