S1D15208F00A [SEIKO]
LIQUID CRYSTAL DISPLAY DRIVER, PQFP128, PLASTIC, QFP-128;
| 型号： | S1D15208F00A |
| 厂家： | 
SEIKO EPSON CORPORATION |
| 描述： | LIQUID CRYSTAL DISPLAY DRIVER, PQFP128, PLASTIC, QFP-128 驱动 |
| 文件： | 总40页 (文件大小：311K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
4. S1D15206 Series
Rev. 3.5
Contents
1. DESCRIPTION ................................................................................................................................................4-1
2. FEATURES......................................................................................................................................................4-1
3. BLOCK DIAGRAM (S1D15206*00**) ............................................................................................................4-2
4. PIN LAYOUT ...................................................................................................................................................4-3
5. PIN DESCRIPTION .........................................................................................................................................4-6
6. FUNCTION DESCRIPTION.............................................................................................................................4-8
7. COMMANDS .................................................................................................................................................4-18
8. ABSOLUTE MAXIMUM RATINGS ................................................................................................................4-22
9. ELECTRICAL CHARACTERISTICS..............................................................................................................4-23
10. EXTERNAL WIRINGS ...................................................................................................................................4-32
11. DIMENSIONS ................................................................................................................................................4-37
– i –
Rev. 3.5
S1D15206 Series
• High-speed, 8-bit microprocessor interface allowing direct
connection to both the 8080 and 6800
• Supported serial interface
1. DESCRIPTION
The S1D15206 series is a single-chip LCD driver for dot-matrix
liquid crystal displays (LCD’s). It accepts serial or 8-bit parallel
display data directly from a microprocessor and stores data in an on-
chip display RAM. It can generate an LCD drive signal independent
from microprocessor clock.
• Rich command functions (upward compatible to S1D15200
Series); they are Read/Write Display Data, Display On/Off
Switching, Set Page Address, Set Initial Display Line, Set
Column Address, Read Status, Static Drive On/Off Switch-
ing, Select Duty, Duty+1, Read-Modify-Write, Select
Segment Driver Direction, Power Save, Reset, Set Power
Control, Set Electronic Controls, Clock Stop.
• On-chip CR oscillator circuit
• On-chip LCD power circuit (The on-chip and external LCD
power supplies are software selectable.)
• Very low power consumption
• Flexible power voltages; 2.4 to 6.0 V (VDD-VSS) and -13.0
to -4.0 V (VDD-V5)
• -40 to +85°C wide operating temperature range
• CMOS process
As the S1D15206 series features the very low power dissipation and
wide operating voltage range, it can easily realize a powerful but
compact display unit having a small battery.
A single chip of S1D15206 series can drive a 17×80-pixel or 33×64-
pixel LCD panel.
(Note: The S1D15206 series are not designed to have EMI resist-
ance.)
2. FEATURES
• Direct data display using the display RAM. When RAM
data bit is 0, it is not displayed; when 1, it is displayed.
• Large 80×33-bit RAM capacity
• 128-pin QFP5 package with aluminum pad or Au bump
• On-chip LCD driver circuit (97 segment and common
drivers)
Series Specifications (for 128-pin flat package)
Operating clock
(Internal OSC) (Typ.)
fCL
Segment
driver
Common
driver
VREG
type
COM
pin positions
Model
Duty
QFP
S1D15206F00A
S1D15206F11A
S1D15206F10A
S1D15206F14A
S1D15206F14Y
S1D15208F00A
2.9
*
*
*
*
*
*
Type A
Type B
5.8
2.9
Type 1
5
1/8, 1/9, 1/16, 1/17
80
64
17
33
20 kHz
2.9
2.9
2.9
5.8
Type 2
Type 1
26
5
Type A
1/32, 1/33
S1D15208D11B
—
*
VREG type
Type 1 VREG (Built-in power supply regulating voltage)
Temperature gradient: -0.17% /°C
Type 2 VREG (Built-in power supply regulating voltage)
Temperature gradient: 0.00% /°C
COMS pin positions Refer to No. P3 (Package pin layout), No. P4 (PAD layout) and No. P5 (PAD coordinates).
An S1D15206 series package has one of following subcodes according to its package type (an example of S1D15206):
S1D15206F****:
128-pin QFP5 flat package
128-pin QFP26 flat package
Bear chip
S1D15206F**Y*:
S1D15206D****:
S1D15206D**A* :Al-pad chip
S1D15206D**B* :Au-bump chip
S1D15206T****:
TCP
Rev.3.5
EPSON
4–1
S1D15206 Series
3. BLOCK DIAGRAM (S1D15206*00**)
CMOS
SEG0·····························SEG79 COM0 ····COM15
···············································
·····················
VSS
VDD
V1
V2
V3
V4
V5
Voltage
select
circuit
Segment driver
Common driver
Shift register
CAP1+
CAP1–
CAP2+
CAP2–
Display data latch
V
R
Power circuit
VOUT
80x33-dot display data RAM
Column address decoder
7-bit column address counter
7-bit column address register
Page address
register
FR
CL
Display timing
generator circuit
M/S
Status
register
Bus holder
Command decoder
Oscillator
Microprocessor interface
I/O buffer
SR2 SR1 WR
CS2 CS1 A0
D0 D1 D2 D3 D4 D5 D6 D7
RD
4–2
EPSON
Rev.3.5
S1D15206 Series
4. PIN LAYOUT
Package Pin Assignment
SEG54
SEG55
SEG56
SEG57
SEG58
SEG59
SEG60
SEG61
SEG15
64
103
SEG14
SEG13
SEG12
SEG11
SEG10
SEG9
SEG8
SEG7
SEG6
SEG5
SEG4
SEG3
SEG2
SEG1
SEG0
COMS
110
SEG62
SEG63
SEG64 (COM15)
SEG65 (COM14)
SEG66 (COM13)
SEG67 (COM12)
SEG68 (COM11)
SEG69 (COM10)
SEG70 (COM 9)
SEG71 (COM 8)
SEG72 (COM 7)
SEG73 (COM 6)
SEG74 (COM 5)
SEG75 (COM 4)
SEG76 (COM 3)
SEG77 (COM 2)
SEG78 (COM 1)
SEG79 (COM 0)
50
Index
[COM15]
120
COM15 (COM31) [COM14]
COM14 (COM30) [COM13]
COM13 (COM29)
COM12 (COM28)
COM11 (COM27)
COM10 (COM26)
COM9 (COM25)
COM8 (COM24)
[COM12]
[COM11]
[COM10]
[COM 9]
[COM 8]
[COM 7]
39
128
COM7 (COM23) [COM 6]
Pin name in ( ) apply to S1D15208.
Pin name in [ ] apply to S1D15206D10**(CMOS Pin=Type B).
*
*
Rev.3.5
EPSON
4–3
S1D15206 Series
Pad Layout
102
90
80
70
65
SEG54
SEG55
SEG56
SEG57
SEG58
SEG59
SEG60
SEG61
SEG15
SEG14
SEG13
SEG12
SEG11
SEG10
SEG9
SEG8
SEG7
SEG6
SEG5
SEG4
SEG3
SEG2
SEG1
SEG0
COMS
COM15 (COM31) [COM14]
COM14 (COM30) [COM13]
COM13 (COM29) [COM12]
COM12 (COM28) [COM11]
COM11 (COM27) [COM10]
COM10 (COM26) [COM 9]
COM9 (COM25) [COM 8]
COM8 (COM24) [COM 7]
COM7 (COM23) [COM 6]
COM6 (COM22) [COM 5]
103
110
64
Y
SEG62
SEG63
SEG64 (COM15)
SEG65 (COM14)
SEG66 (COM13)
SEG67 (COM12)
SEG68 (COM11)
SEG69 (COM10)
SEG70 (COM9)
SEG71 (COM8)
SEG72 (COM7)
SEG73 (COM6)
SEG74 (COM5)
SEG75 (COM4)
SEG76 (COM3)
SEG77 (COM2)
SEG78 (COM1)
SEG79 (COM0)
50
X
[COM15]
120
128
38
37
1
10
20
30
* Pin names in ( ) apply to S1D15208.
* Pin names in [
] apply to S1D15206D10** (CMOS pin = Type B).
Al- pad chip
• Chip size
5.92 mm × 4.68 mm
• Chip thickness0.4 mm
• Pad opening 90.2 µm × 90.2 µm
• Pad pitch
130 µm (Min)
Au- bump chip (reference)
• Chip size
5.92 mm × 4.68 mm
• Chip thickness0.4 mm
• Bump size
81.7 µm × 81.7 µm
• Bump height 22.5 µm
4–4
EPSON
Rev.3.5
S1D15206 Series
Pad Center Coordinates
PAD No.
PIN Name
X
Y
PAD No.
PIN Name
X
Y
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
SEG16
SEG17
SEG18
SEG19
SEG20
SEG21
SEG22
SEG23
SEG24
SEG25
SEG26
SEG27
SEG28
SEG29
SEG30
SEG31
SEG32
SEG33
SEG34
SEG35
SEG36
SEG37
SEG38
SEG39
SEG40
SEG41
SEG42
SEG43
SEG44
SEG45
SEG46
SEG47
SEG48
SEG49
SEG50
SEG51
SEG52
SEG53
SEG54
SEG55
SEG56
SEG57
SEG58
SEG59
SEG60
SEG61
SEG62
SEG63
2516
2367
2218
2088
1957
1827
1697
1567
1437
1307
1177
1046
916
786
656
526
396
266
135
5
–125
–255
–385
–515
–646
–776
–906
–1036
–1166
–1296
–1426
–1557
–1687
–1817
–1947
–2077
–2226
–2375
–2802
2185
1
2
3
4
5
6
7
8
9
V1
V2
V3
V4
V5
VR
VDD
VOUT
CAP2–
CAP2+
CAP1–
CAP1+
VSS
M/S
SR2
SR1
WR
RD
CS2
CS1
A0
FR
CL
D0
D1
D2
D3
D4
D5
D6
D7
–2767
–2637
–2507
–2377
–2246
–2116
–1985
–1857
–1727
–1522
–1318
–1113
–553
–356
–226
–95
35
165
295
425
555
719
849
979
1109
1239
1369
1500
1630
1760
1890
2069
2199
2329
2459
2589
2719
2802
–2106
–2149
–2176
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
–2166
–2185
COM0 (COM16) [CMOS ]
COM1 (COM17) [COM0 ]
COM2 (COM18) [COM1 ]
COM3 (COM19) [COM2 ]
COM4 (COM20) [COM3 ]
COM5 (COM21) [COM4 ]
COM6 (COM22) [COM5 ]
COM7 (COM23) [COM6 ]
COM8 (COM24) [COM7 ]
COM9 (COM25) [COM8 ]
COM10 (COM26) [COM9 ]
COM11 (COM27) [COM10]
COM12 (COM28) [COM11]
COM13 (COM29) [COM12]
COM14 (COM30) [COM13]
COM15 (COM31) [COM14]
COMS
SEG0
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
–1654
–1524
–1393
–1263
–1133
–1003
–873
–743
–612
–482
–352
–193
–63
67
197
327
457
588
718
848
978
1932
1802
1672
1541
1411
1281
1151
1021
891
760
599
469
339
[COM15]
SEG64 (COM15)
SEG65 (COM14)
SEG66 (COM13)
SEG67 (COM12)
SEG68 (COM11)
SEG69 (COM10)
SEG70 (COM9)
SEG71 (COM8)
SEG72 (COM7)
SEG73 (COM6)
SEG74 (COM5)
SEG75 (COM4)
SEG76 (COM3)
SEG77 (COM2)
SEG78 (COM1)
SEG79 (COM0)
209
78
–52
–182
–312
–442
–572
–703
–833
–963
–1093
–1223
–1353
1108
1238
1368
1499
1629
1759
* Pin names in ( ) apply to S1D15208.
* Pin names in [ ] apply to S1D15206D10 (CMOS pin = Type B).
*
Rev.3.5
EPSON
4–5
S1D15206 Series
5. PIN DESCRIPTION
Power Supply
Name
VDD
I/O
Description
+5VDC power supply. Common to microprocessor power supply pin VCC
Ground
Number of pins
Supply
Supply
Supply
.
1
1
5
VSS
V1, V2
V3, V4
V5
LCD driver supply voltages. The Set Power Control command can switch
the on-chip and external power supply modes of these pins.
When external mode selects, the voltage determined by LCD cell is
impedance-converted by a resistive divider or an operational amplifier for
application. Voltages should be the following relationship:
VDD ≥ V1 ≥ V2 ≥ V3 ≥ V4 ≥ V5
When master mode selects, these voltages are generated on the chip:
S1D15206
S1D15208
V1
V2
V3
V4
1/5 V5
2/5 V5
3/5 V5
4/5 V5
1/7 V5
2/7 V5
5/7 V5
6/7 V5
LCD Driver Supplies
Name
CAP1+
CAP1–
CAP2+
CAP2–
VOUT
I/O
Description
Number of pins
O
O
O
O
O
I
DC/DC voltage converter capacitor 1 positive connection
DC/DC voltage converter capacitor 1 negative connection
DC/DC voltage converter capacitor 2 positive connection
DC/DC voltage converter capacitor 2 negative connection
DC/DC voltage converter output
1
1
1
1
1
1
VR
Voltage adjustment pin. Applies voltage between VDD and V5 using
a resistive divider.
Microprocessor Interface
Name
I/O
Description
Number of pins
D0 to D7
(SI)
(SCL)
I/O
Data input/outputs. The 8-bit bidirectional data buses to be connected
to the standard 8-bit microprocessor data buses. When the serial
interface selects, D7 is serial data input (SI) and D6 is serial clock input
(SCL).
8
A0
I
Control/display data flag input. It is connected to the LSB of micro-
processor address bus. When LOW, the data on D0 to D7 is control data.
When HIGH, the data on D0 to D7 is display data.
1
CS1
CS2
I
I
Chip select input. Data input/output is enabled when -CS1 is LOW and
CS2 is HIGH.
2
1
RD
(E)
• Read enable input. When interfacing to an 8080-series microprocessor
and when its RD is LOW, the S1D15206 series data bus output is enabled.
• When interfacing to an 6800-series microprocessor and when its R/W
Enable (E) is HIGH, the S1D15206 series R/W input is enabled.
WR
(R/W)
• Write enable input. When interfacing to an 8080-series microprocessor,
WR is active LOW.
1
• When interfacing to an 6800-series microprocessor,
it will be read mode when R/W is HIGH and it will be write mode when
R/W is LOW.
R/W = “1” : Read
R/W = “0” : Write
4–6
EPSON
Rev.3.5
S1D15206 Series
Name
I/O
Description
Number of pins
SR1,
SR2
I
Microprocessor interface select, and parallel/serial data input select.
2
SR1
0
SR2
1
Type
8080 microprocessor bus (parallel
input)
1
1
6800 microprocessor bus (parallel
input)
Serial input
Reset
1
0
0
0
* In serial mode, no data can be read from RAM and D0 to
D5 are HZ. RD and WR must be HIGH or LOW.
When set for the 68 family MPU, the SR1 and SR2 timing must match or
SR1 must rise first.
LCD Driver Outputs
Name
M/S
I/O
I
Description
Normally “1”.
Number of pins
1
1
1
CL
I/O
I/O
O
Normally “1”.
FR
Normally “1”.
SEGn
LCD segment driver output. VDD, V2, V3, or V5 can select according
to the display RAM and FR signal.
80 (S1D15206)
or 64 (S1D15208)
RAM data FR signal Output voltage
of SEGn
1
0
1
0
–
VDD
V5
V2
V3
VDD
1
0
Power save
COMn
O
LCD common driver output. VDD, V1, V4, or V5 can select according
to IC internal scan signal and FR signal. The common scan sequence
is reversed in slave mode.
16 (S1D15206)
or 32 (S1D15208)
Internal scan
signal
FR
signal
Output voltage
of COMn
1
0
1
0
–
V5
VDD
V1
V4
VDD
1
0
Power save
COMS
O
Indicator COM output. COMS pin is equivalent to following COM output
pin when Duty+1 command is running:
1
S1D15206
S1D15208
1/9 duty 1/17 duty 1/33 duty
Indicator
COMS
output
COM8
COM16 COM32
Rev.3.5
EPSON
4–7
S1D15206 Series
6. FUNCTION DESCRIPTION
MPU Interface
Parallel/Serial Interface
The S1D15206 series can transfer data via 8-bit bidirectional data buses D0 to D7 or via serial data input D7 (SI). The 8-bit parallel data input
or serial data input, 8080/6800-series microprocessor, and reset status can select according to SR1 and SR2.
No data can be read from RAM and no status can be read during serial data input. Also, RD and WR are high or low, and D0 to D5 are open.
Table 1
SR1
SR2
Type
CS1
CS2
A0
RD
WR
Data (D0 to D7)
D0 to D7
0
1
8080 microprocessor
bus (parallel)
CS1
CS2
A0
RD
WR
1
1
6800 microprocessor
bus (parallel)
CS1
CS2
A0
E
R/W
D0 to D7
1
0
0
0
Serial input
Reset
CS1
CS1
CS2
CS2
A0
A0
0/1
RD
0/1
D6 (SCL) and D7 (SI)
— — — — — — —
WR
* When set for the 68 family interface, the SR1 and SR2 timing must match or SR1 must rise first.
SR1
SR2
The 68 family interface
RESET
Data Bus Signals
The S1D15206 series identifies the data bus signal according to A0, RD, and WR (E, R/W) signals.
Table 2
Common
6800 processor
8080 processor
Function
A0
1
WR (R/W)
RD
0
WR
1
1
0
1
0
Reads display data.
Writes display data.
Reads status.
1
1
0
0
0
1
0
1
0
Writes control data in internal register. (commands)
edge of every eighth serial clock signal.
Serial Interface (SR1 is high and SR2 is low)
The serial data input is determined to be the display data when A0
is high, and it is control data when A0 is low. A0 is read on rising
edge of every eighth clock signal.
Figure 1 shows a timing chart of serial interface signals. The serial
clock signal must be terminated correctly against termination reflec-
tion and ambient noise. Operation checkout on the actual machine
is recommended.
The serial interface consists of an 8-bit shift register and a 3-bit
counter. The serial data input and serial clock input are enabled
when CS1 is low and CS2 is high (in chip select status). When chip
is not selected, the shift register and counter are reset.
When serial data input is enabled by SR1 and SR2, D7 (SI) receives
serial data and D6 (SCL) receives serial clock. Serial data of D7, D6,
..., D0 is read at D7 in this sequence when serial clock goes high.
They are converted into 8-bit parallel data and processed on rising
4–8
EPSON
Rev.3.5
S1D15206 Series
CS1
CS2
D7(S1)
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D6(SCL)
A0
1
2
3
4
5
6
7
8
9
10
11
12
Figure 1
from display RAM in the first read (dummy) cycle, stores it in bus
holder, and outputs it onto system bus in the next data read cycle.
Also, the microprocessor temporarily stores display data in bus
holder, and stores it in display RAM until the next data write cycle
starts.
When viewed from the microprocessor, the S1D15206 series access
speed greatly depends on the cycle time rather than access time to the
display RAM (tACC and tDS). It shows the data transfer speed to/
from the microprocessor can increase. If the cycle time is inappro-
priate, the microprocessor can insert the NOP instruction that is
equivalent to the wait cycle setup. However, there is a restriction in
the display RAM read sequence. When an address is set, the
specified address data is NOT output at the immediately following
read instruction. The address data is output during second data read.
A single dummy read must be inserted after address setup and after
write cycle (refer to Figure 2).
Chip Select Inputs
The S1D15206 series can interface to microprocessor when CS1 is
LOW and CS2 is HIGH.
When these pins are set to any other combination, D0 to D7 are high
impedance. A0, RD, andWR input are disabled. However, the reset
signal is entered regardless of CS1 and CS2 setup. The internal IC
status including LCD driver circuit is held until a reset signal is
entered.
Access to Display Data RAM and Internal Registers
The S1D15206 series can perform a series of pipeline processing
between LSI’s using bus holder of internal data bus in order to match
the operating frequency of display RAM and internal registers with
the microprocessor. For example, the microprocessor reads data
•Write
WR
MPU
DATA
n
n+1
n+2
n+3
Latched
n
Bus holder
Write signal
n+1
n+2
n+3
Internal
timing
•Read
WR
RD
MPU
DATA
N
N
n
n+1
Address
preset
Read signal
Internal
timing
Preset
N
Incremented
N+1
Column
address
N
N+2
n
n+1
Read address n
n+2
Bus holder
Set address n
Dummy read
Read address n+1
n: Current data
N: Dummy data
Figure 2
Rev.3.5
EPSON
4–9
S1D15206 Series
unlocked when a column address is set again. The Column Address
counter is independent of Page Address register.
When ADC Select command is issued to display inverse display, the
column address decoder inverts the relationship between RAM
column address and display segment output.
Busy Flag
The Busy flag is set when the S1D15206 series starts to operate.
During operating, it accepts Read Status instruction only. The busy
flag signal is output at pin D7 when Read Status is issued. If the cycle
time (tcyc) is correct, the microprocessor needs not to check the flag
before issuing a command. This can greatly improve the microproc-
essor performance.
Page Address Register
This is a 4-bit page address register that provides page address to the
display RAM (refer to Figure 4). The microprocessor issues Set
Page Address command to change the page and access to another
page. Page address 4 (D2 is high, but D0 and D1 are low) is RAM
area dedicate to the indicator, and display data D0 is only valid.
Initial Display Line Register
When the display RAM data is read, the display line according to
COM0 (usually, the top line of screen) is determined using register
data. The register is also used for screen scrolling and page
switching.
Display Data RAM
The Set Display Start Line command sets the 5-bit display start
address in this register. The register data is preset on the line counter
each time FR signal status changes. The line counter is incremented
by oscillator circuit output (in master mode) or CL input (in slave
mode), and it generates a line address to allow 80-bit sequential data
output from display RAM to LCD driver circuit.
The display data RAM stores pixel data for LCD. It is a 33-column
by 80-row (4-page by 8+1 bit) addressable array. Each pixel can be
selected when page and column addresses are specified.
The time required to transfer data is very short because the micro-
processor enters D0 to D7 corresponding to LCD common lines as
shown in Figure 3. Therefore, multiple S1D15206’s can easily
configure a large display having the high flexibility with very few
data transmission restriction.
The microprocessor writes and reads data to/from the RAM through
I/O buffer. As LCD controller operates independently, data can be
written into RAM at the same time as data is being displayed,
without causing the LCD to flicker.
Column Address Counter
This is a 7-bit presettable counter that provides column address to the
display RAM (refer to Figure 4). It is incremented by 1 when a Read/
Write command is entered. However, the counter is not incremented
but locked if a non-existing address above 50H is specified. It is
D0
D1
1
0
COM0
COM1
D2
D3
D4
1
0
0
COM2
COM3
COM4
Display data RAM
Display on LCD
Figure 3
4–10
EPSON
Rev.3.5
S1D15206 Series
Relationship between display data RAM and addresses (if initial display line is 08):
COM
output
Line
address
00
Page
Data
address
D0
COM 0
COM 1
COM 2
COM 3
COM 4
COM 5
COM 6
COM 7
COM 8
COM 9
COM10
COM11
COM12
COM13
COM14
COM15
COM16
COM17
COM18
COM19
COM20
COM21
COM22
COM23
COM24
COM25
COM26
COM27
COM28
COM29
COM30
COM31
COM S
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
01
02
03
04
05
06
07
08
D2,D1,D0
=0,0,0
Page 0
Start
1/8
09
0A
0B
0C
0D
0E
0F
10
11
12
13
14
Page 1
0,0,1
Page 2
1/16
0,1,0
15
16
17
18
19
1A
1B
1C
1D
1E
1F
Page 3
Page 4
0,1,1
1,0,0
A
D
C
Column
address
D0=00001020304050607
D0=14F 4E 4D 4C 4B 4A
SEGOUT
4D 4E 4F
020100
777879
4948
0 1 2 3 4 5 6 7
Figure 4
The timing of LCD panel driver outputs is independent of the timing
of RAM data input from microprocessor.
Display Timing Generator Circuit
This section explains how the display timing generator circuit
operates.
LCD AC Signal (FR)
The LCD AC signal, FR, is generated from the display clock. The
FR controller generates dual-frame AC driver waveforms for LCD
panel driver circuit.
Signal generation to line counter and display data latch
circuit
The line address counter, RAM, and latch circuit of the S1D15206
series operate synchronous to the display clock (the oscillator circuit
outp).mm The LCD drive signal is sent to LCD panel driver output
pin SEGn.
Rev.3.5
EPSON
4–11
S1D15206 Series
• Dual-frame AC driver waveforms
(If S1D15206 is used in 1/16 duty)
15 16
1
2
3
4
5
6
11 12 13 14 15 16
1
2
Display clock
FR
VDD
V1
COM0
V4
V5
VDD
V1
COM1
V4
V5
RAM data
VDD
V2
V3
V5
SEGn
Common timing Signals
The common timing generator circuit uses the display clock to
generate common timing signal and FR frame signal. The Duty
Select command can select 1/8 or 1/16 duty (S1D15206). A
combination of Select Duty and Duty+1 commands can select 1/9 or
1/17 duty (S1D15206).
Display Data Latch Circuit
Power Supply Circuit
This circuit temporarily stores (or latches) display data (during a
single common signal period) when it is output from display RAM
to LCD panel driver circuit. This latch is controlled by Display ON/
OFF and Static Drive ON/OFF commands. These commands do not
alter the data.
The power supply circuit produces voltage to drive LCD panel at low
power consumption. The power circuit consists of three subcircuits:
voltage tripler, voltage regulator, and voltage follower. The voltage
tripler outputs VDD -(VSS×2) or -(VSS×3) voltage at VOUT. The
regulator circuit generates V5 voltage using external resistor. The
voltage follower circuit changes the impedance of V1 to V4 that are
generated from V5 through division with internal resistors. (Details
are explained later.)
S1D15206 series can drive LCD panel using on-chip power circuit.
However, the on-chip power circuit is intended to use for a small
LCD panel and it is inappropriate to a large panel requiring multiple
driver chips. As the large LCD panel has the dropped display quality
due to large load capacity, it must use an external power source.
The power circuit is controlled by Set Power Control command.
This command sets a three-bit data in Power Control register to
select one of eight power circuit functions. The external power
supply and part of on-chip power circuit functions can be used
simultaneously. The following explains how the Set Power Control
command works.
LCD Driver
This is a multiplexer circuit consisting of 96 segment outputs to
generate four-level LCD panel drive signals. The circuit also has a
pair of COM outputs for indicator display.
The COMn output has a shift register to sequentially output COM
scan signals. The LCD panel drive voltage is generated by a specific
combination of display data, COM scan signal, and FR signal.
Figure 6 gives an example of SEG and COM output waveforms.
Oscillation Circuit
This is a low power consumption CR oscillator having an oscillator
resistor, and its output is used as the display timing signal source or
as the clock for voltage boost circuit of LCD power supply.
The display clock output can be stopped by Clock Stop command to
minimize the current consumption of LCD panel.
4–12
EPSON
Rev.3.5
S1D15206 Series
[Control by Set Power Control command]
D2 turns on when triple booster control bit goes HIGH, and D2 turns off when this bit goes LOW.
D1 turns on when voltage regulator control bit goes HIGH, and D1 turns off when this bit goes LOW.
D0 turns on when voltage follower control bit goes HIGH, and D0 turns off when this bit goes LOW.
[Practical combination examples]
Voltage
booster
Voltage
regulator
Voltage
follower
External voltage Voltage booster Voltage regulator
D2 D1 D0
input
terminal
terminal
1
1
0
0
1
0
1
0
1
0
1
0
ON
ON
ON
OFF
ON
ON
OFF
ON
—
Used
Used
—
Used
OPEN
Used
OFF
OFF
To VOUT
To V1 to V5
OPEN
OPEN
OFF
OFF
OPEN
To use the on-chip (internal) power supply only, set
(D2,D1,D0)=(1,1,1).
Voltage tripler
If capacitors C1 are inserted between CAP1+ and CAP1-, between
CAP2+ and CAP2–, and between VSS and VOUT, the potential
between VDD and VSS is boosted to triple toward negative side and
it is output at VOUT. For double boosting, remove only capacitor C1
between CAP2+ and CAP2-, open CAP2+, and jumper between
CAP2- and VOUT. The double boosted voltage appears at VOUT
(CAP2-).
To use the voltage booster circuit only, set (D2,D1,D0)=(1,0,0).
To use the voltage regulator and voltage follower, set
(D2,D1,D0)=(0,1,1).
To use an external power supply only, set (D2,D1,D0)=(0,0,0).
The booster receives signals from oscillator circuit and, therefore,
the oscillator must be active. The following shows the boosted
potential.
Notes: 1. The voltage booster terminals are CAP1+, CAP1-, CAP2+,
and CAP2-.
2. The above listed examples are the most practical use to
control each circuit using control bits. Any other setup is
unpractical and omitted in this manual.
3. The V/F circuit alone cannot be used. When this circuit
is used, the V adjustment circuit must be set simultaneously.
(VCC=+5V) VDD=0V
(GND) VSS=-5V
VDD=0V
VSS=-5V
VOUT=2VSS =-10V
VOUT=3VSS =-15V
Potential during double boosting
Potential during triple boosting
Rev.3.5
EPSON
4–13
S1D15206 Series
Voltage regulator
The boosting voltage occurring at VOUT is sent to the voltage regulator and the V5 liquid crystal display (LCD) drive voltage is output. This
V5 voltage can be determined by the following equation when resistors Ra and Rb (R1, R2 and R3) are adjusted within the range of |V5|<|VOUT|.
VDD
R1
R2
VREG
Ra
Rb
Rb
Ra
V5=(1+ ) · VREG+IREF · Rb
∆R2
+
-
R3+R2–∆R2
R1+∆R2
V5
=(1+
) · VREG
IREF
Voltage regulation
current
UR
+IREF · (R3+R2–∆R2)
R3
where, VREG is the constant voltage source of the IC, and it is
To use the Electronic Volume Control Function, issue the Set Power
Control command to simultaneously operate both the voltage
regulator circuit and voltage follower circuit.
.
constant (VREG = –3.1 V). (VREG=Type1) VREG=VSS(VDD basis)
.
(VREG=Type2)
IREF is the voltage regulation current of the Electronic Volume
Also, when the voltage tripler off, the voltage must be supplied from
VOUT terminal.
.
Control Function, and IREF=2.4 µA if the electronic volume control
.
register (32-state) has (D4,D3,D2,D1,D0)=(1,1,1,1,1).
To adjust the V5 output voltage, insert a variable resistor between
VR, VDD and V5 as shown. A combination of R1 and R3 constant
resistors and R2 variable resistor is recommended for fine-adjustment
of V5 voltage.
When the Electronic Volume Control Function is used, the V5
voltage can be expressed as follows:
Rb
Ra
5
V5 = (1 +
) · VREG + IREF · Rb ..................
(Variable voltage range)
Setup example of resistors R1, R2 and R3:
When the Electronic Volume Control Function is OFF (electronic
volume control register values are (D4,D3,D2,D1,D0)
=(0,0,0,0,0)):
The increased V5 voltage is controlled by use of IREF current source
of the IC. (For 32 voltage levels, ∆IREF=IREF/31)
R3 + R2 – ∆R2
The minimum setup voltage of the V5 absolute value is determined
by the ratio of external Ra and Rb, and the increased voltage by the
Electronic Volume Control Function is determined by resistor Rb.
Therefore, the resistors must be set as follows:
1
V5 = (1 +
) · VREG .................
R1 + ∆R2
(As IREF = 0A)
• R1 + R2 + R3 = 6.0 MΩ ............................
2
(Determined by the current passing between VDD and V5)
• Variable voltage range by R2: –6.2 to –9.3 V
(Determined by the LCD characteristics)
∆R2 = 0Ω, VREG = –3.1 V
(1) Determine Rb resistor depending on the V5 variable voltage
range by use of the Electronic Volume Control.
V5 variable voltage range
Rb =
IREF
To obtain V5 = –9.3 V, from equation (1):
3
R2 + R3 = 2 · R1 .........................
(2) To obtain the minimum voltage of the V5 absolute value,
determine Ra using the Rb of Step (1) above.
∆R2 = R2, VREG = –3.1 V
To obtain V5 = –6.2 V, from equation (1):
4
R1 + R2 = 1 · R1 .........................
Rb
V5
Ra =
[V5 = (1 + Rb/Ra) · VREG]
–1
2
3
4
From equations
,
and
:
R1 = 2.0 MΩ
R2 = 1.0 MΩ
R3 = 3.0 MΩ
VREG
The S1D15206 series have the built-in VREG reference voltage and
REF current source which are constant during voltage variation.
I
The voltage regulator circuit has a temperature gradient of
approximately –0.17%/°C as the VREG voltage. To obtain another
temperature gradient, use the Electronic Volume Control Function
for software processing using the MPU.
As the VR pin has a high input impedance, the shielded and short
lines must be protected from a noise interference.
However, they may change due to the variation occurring in IC
manufacturing and due to the temperature change as shown below.
Consider such variation and temperature change, and set the Ra and
Rb appropriate to the LCD used.
V
V
REG =–3.1V±0.4V (Type1)
REG =VSS (VDD basis) (Type2)
VREG =–0.17%/˚C
VREG =–0.00%/˚C
When the VREG = Type 2, similarly preset R1, R2 and R3 on the basis
I
I
REF = –1.2 µA ± 40% (For 16 levels)
REF = –2.4 µA ± 40% (For 32 levels)
IREF = 0.011 µA/°C
IREF = 0.022 µA/°C
of VREG = VSS
.
Ra is a variable resistor that is used to correct the V5 voltage change
due to VREG and IREF variation. Also, the contrast adjustment is
recommended for each IC chip.
Before adjusting the LCD screen contrast, set the electronic volume
control register values to (D4,D3,D2,D1,D0)=(1,0,0,0,0) or
(0,1,1,1,1) first.
When not using the Electronic Volume Control Function, set the
register values to (D4,D3,D2,D1,D0)=(0,0,0,0,0) by sending the
RES signal or by issuing the Set Electronic Volume Control Register
command.
Voltage regulator circuit using the Electronic Volume
Control Function
The Electronic Volume Control Function can adjust the intensity
(brightness level) of liquid crystal display (LCD) screen by command
control of V5 LCD driver voltage.
This function sets five-bit data in the electronic volume control
register, and the V5 LCD driver voltage can be one of 32-state
voltages.
4–14
EPSON
Rev.3.5
S1D15206 Series
Setup example of constants when Electronic Volume Control
Function is used:
If Ta = 50°C:
V5 max = (1 + Rb/Ra) · VREG
V5 maximum voltage: V5 = –6.2 V (Electronic volume control
register values (D4,D3,D2,D1,D0)=(0,0,0,0,0))
V5 minimum voltages: V5 = –8.6 V (Electronic volume control
register values (D4,D3,D2,D1,D0)=(1,1,1,1,1))
V5 variable voltage range: 2.4 V
= (1 + 1 MΩ/1 MΩ) × (–3.1 V) × {1 + (–0.17%/°C)
× (50°C – 25°C)}
= –5.94 V
V5 min = V5 max + Rb · IREF
= –5.94 V + 1MΩ × {–2.4 µA + (0.022 µA/°C) ×
Variable voltage levels: 32 levels
(–50°C – 25°C)}
(1) Determining the Rb:
= –8.89 V
V5 variable voltage range
2.4 V
2.4 µA
The margin must also be determined in the same procedure given
above by considering the VREG and IREF variation. This margin
calculation results show that the V5 center value is affected by the
Rb =
=
|IREF
|
Rb = 1.0 MΩ
(2) Determining the Ra:
Rb
V
REG and IREF variation. The voltage setup width of the Electronic
Volume Control depends on the IREF variation. When the typical
value of 0.2 V/step is set, for example, the maximum variation range
of 0.12 to 0.28 V must be considered.
1.0 MΩ
Ra =
=
V5 max
VREG
–6.2 V
–3.1 V
–1
–1
Ra = 1.0 MΩ
When the VREG = Type 2, it so becomes that VREG = VSS and there
is no temperature gradient. However, IREF carries the same
temperature characteristics as with VREG = Type 1.
5
According to the V5 voltage and temperature change, equation can
be as follows (if VDD = 0 V reference):
If Ta = 25°C:
V5 max = (1 + Rb/Ra) · VREG
= (1 + 1 MΩ/1 MΩ) × (–3.1 V)
= –6.2 V
V5 min = V5 max + Rb · IREF
= –6.2 V + 1 MΩ × (–2.4 µA)
= –8.6 V
Voltage generator for LCD (Voltage fullower)
The V5 potential is divided using resistance within IC and V1, V2, V3
and V4 potentials are generated for LCD panel drive. These
potentials are then converted in impedance by voltage follower, and
sent to LCD driver circuit.
Because the LCD drive voltage has been fixed to each model, the
display quality may drop in specific duty selected by Select Duty
command. If it occurs, use an external power supply.
If Ta = –10°C:
V5 max = (1 + Rb/Ra) · VREG
= (1 + 1 MΩ/1MΩ) × (–3.1 V) × {1 + (–0.17%/°C)
× (–10°C – 25°C)}
Model
LCD drive voltage
= –6.57 V
S1D15206
S1D15208
1/5 of bias voltage
1/7 of bias voltage
V5 min = V5 max + Rb · IREF
= –6.57 V + 1MΩ × {–2.4 µA + (0.022 µA/°C) ×
(–10°C – 25°C)}
Subsection gives wiring examples and reference parts list when on-
chip power supply is used and when not used.
= –8.20 V
Command sequence for built-in power circuit startup
The built-in power circuit must follow the command sequence given below.
• To start the built-in power
circuit after release of Power
Save mode:
• To start the built-in power
circuit when logic units are
being powered:
Release the Power Save
mode. (Static drive is
OFF or display is ON.)
Hardware reset
(SR1=SR2='0')
Setup of power
control
Setup of power
control
*After approx. 200 msec
Display turns ON.
*After approx. 200 msec
Display turns ON.
* When the Set Power Control command is issued, the V DD level signal is output at both COM and SEG terminals for approximately 200 msec.
Any other command can be entered during this period.
Rev.3.5
EPSON
4–15
S1D15206 Series
When turning off the built-in power circuit, observe the following command sequence to mainyain power save status.
When turning off the built-in
power supply:
Display “OFF”
Command AEh
Command A5h
Power save
command
Static drive “ON”
Built-in power supply “OFF”
* Precautions when installing the COG
the resistance of ITO wiring is being inserted in series with the
switching transistor, thus dominating the boosting ability.
Consequently, the boosting ability will be hindered as a result
and pay sufficient attention to the wiring to respective boosting
capacitors.
When installing the COG, it is necessary to duly consider the fact that
there exists a resistance of the ITO wiring occurring between the
driver chip and the externally connected parts (such as capacitors and
resistors). By the influence of this resistance, non-conformity may
occur with the indications on the liquid crystal display.
Therefore, when installing the COG design the module paying
sufficient considerations to the following three points.
1. Suppress the resistance occurring between the driver chip pin to
the externally connected parts as much as possible.
2. Suppress the resistance connecting to the power supply pin of
the driver chip.
3. Make various COG module samples with different ITO sheet
resistance to select the module with the sheet resistance with
sufficient operation margin.
2. Connection of the smoothing capacitors for the liquid crystal
drive
The smoothing capacitors for the liquid crystal driving potentials
(V1. V2, V3 and V4) are indispensable for liquid crystal drives
not only for the purpose of mere stabilization of the voltage
levels. If the ITO wiring resistance which occurs pursuant to
installation of the COG is supplemented to these smoothing
capacitors, the liquid crystal driving potentials become unstable
to cause non-conformity with the indications of the liquid
crystal display. Therefore, when using the COG module, we
definitely recommend to connect reinforcing resistors externally.
Reference value of the resistance is 100kΩ to 1MΩ.
Meanwhile, because of the existence of these reinforcing
resistors, current consumption will increase.
Also, as for this driver IC, pay sufficient attention to the following
points when connecting to external parts for the characteristics of the
circuit.
1. Connection to the boosting capacitors The boosting capacitors
(the capacitors connecting to respective CAP pins and capacitor
being inserted between VOUT and VSS2) of this IC are being
switched over by use of the transistor with very low ON-
resistance of about 10Ω. However, when installing the COG,
Indicated below is an exemplary connection diagram of external
resistors.
Please make sufficient evaluation work for the display statuses with
any connection tests.
Exemplary connection diagram 1.
Exemplary connection diagram 2.
VDD
VDD
V
DD
VDD
R4
R4
V
V
V
1
2
3
V1
V2
V3
C2
C2
C2
C2
C2
C2
R4
R4
V
V
4
5
V
4
5
C
2
2
C
2
2
R4
R4
V
C
C
4–16
EPSON
Rev.3.5
S1D15206 Series
11. Static drive
12. Clock
: Off
: Output
Reset Circuit
The S1D15206 series chip parameters are initialized when both
SR1 and SR2 are set to low.
As explained in Section 4-32, the microprocessor should also be
reset when SR1 and SR2 are reset. The SR1 and SR2 go low only
when logical low pulses are entered at least 10 microseconds (refer
to Section for AC characteristics). The normal reset signal appears
1 microsecond after the rising edge of this signal.
If the on-board LCD power circuit of the S1D15206 series is not
used, both SR1 and SR2 must be low when an external LCD power
is supplied. If not low, the IC chip may be destroyed by surge
current. When reset, each register is cleared but the present setup of
oscillator circuit and output terminals (FR, CL, D0 to D7) is not
cleared.
● Initial parameter setup
1. Display
2. Duty cycle
3. ADC select
: Off
: 1/16 (S1D15206)
: Normal (D0 ADC com
mand is high and
ADC status flag is set)
: Off
: 0
: Line 1
: Address 0
: Page 0
4. Read-modify-write
5. Power Control register
6. Initial Display Line register
7. Column Address counter
8. Page Address register
9. Register data of serial interface : Cleared
10. Electronic control register
As the S1D15206 series does not have a Power-On Clear circuit,
both SR1 and SR2 must go low when logic power applies. If not, any
recovery may fail.
The Reset command can reset parameters 6 to 10 listed above.
: 0
0 1 2 3
0 1 2 3
16 0 1 2 3
32 0 1 2 3
16
32
COM 0
COM 1
COM 2
COM 3
COM 4
VDD
VSS
FR
VDD
V1
V2
V3
V4
V5
COM 0
COM 5
COM 6
COM 7
VDD
V1
V2
V3
V4
V5
COM 1
COM 2
SEG 0
SEG 1
COM 8
VDD
V1
V2
V3
V4
V5
COM 9
COM 10
COM 11
COM 12
VDD
V1
V2
V3
V4
V5
COM 13
COM 14
COM 15
VDD
V1
V2
V3
V4
V5
S
E
S
E
S S S
E E E
G G G G G
0
1 2 3 4
V5
V4
V3
V2
V1
COM -SEG 0
VDD
-V1
-V2
-V3
-V4
-V5
V5
V4
V3
V2
V1
VDD
-V1
-V2
-V3
-V4
-V5
COM -SEG 1
Figure 6
Rev.3.5
EPSON
4–17
S1D15206 Series
7. COMMANDS
Page 4–21 lists available commands. The S1D15206 series uses a
combination of A0, RD and WR (or R/W) signals to identify data bus
signals. As the chip analyzes and executes each command using
internal timing clock only (any external clock is required), its
processing speed is very HIGH and its busy check is usually not
required.
R/W
A0 RD WR D7 D6 D5 F4 D3 D2 D1 D0
0
1
0
0
A6 A5 A4 A3 A2 A1 A0
A6 A5 A4 A3 A2 A1 A0 Column address
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
:
(1) Display ON/OFF
:
Alternatively turns the display on and off.
1
0
0
1
1
1
1
7 9
R/W
(5) Read Status
A0 RD WR D7 D6 D5 F4 D3 D2 D1 D0
0
1
0
1
0
1
0
1
1
1
D
R/W
A0 RD WR D7 D6 D5 F4 D3 D2 D1 D0
The display turns off when D goes low, and it turns on when D
goes HIGH.
0
0
1
BUSY ADC ON/OFF RESET PS
0
0
0
(2) Initial Display Line
BUSY: When high, the S1D15206 series is busy due to internal
operation or reset. Any command is rejected until BUSY
goes LOW. The busy check is not required if enough time
is provided for each cycle.
Specifies line address (refer to Figure 4) to determine the initial
display line, or COM0. The RAM display data becomes the top
line of LCD screen. It is followed by the higher number of lines
in ascending order, corresponding to the duty cycle. When this
command changes the line address, the smooth scrolling or
page change takes place.
ADC:
Indicates the relationship between RAM column address
and segment drivers. When LOW, the display is normal
and column address “79-n” corresponds to segment driver
n. When HIGH, the display is reversed and column
address n corresponds to segment driver n.
R/W
A0 RD WR D7 D6 D5 F4 D3 D2 D1 D0
0
1
0
1
1
0
A4 A3 A2 A1 A0
HIGH-order bit
Line address
ON/OFF: Indicates whether the display is on or off. When goes low,
the display turns on. When goes HIGH, the display turns
off. This is the opposite of Display ON/OFF command.
←
A4
A3
A2
A1
A0
0
0
0
0
0
0
0
0
0
:
0
0
1
0
1
0
0
1
2
RESET: Indicates the initialization is in progress by SR1 and
SR2 to go LOW or by Reset command. When LOW,
the display is on. When HIGH, the chip is being reset.
:
1
1
1
1
1
1
1
1
0
1
3 0
3 1
PS:
When LOW, LCD panel is in Power Save mode.
(3) Set Page Address
(6) Write Display Data
Specifies page address to load display RAM data to page
address register. Any RAM data bit can be accessed when its
page address and column address are specified. The display
remains unchanged even when the page address is changed.
Page address 4 is the display RAM area dedicate to the indica-
tor, and only D0 is valid for data change.
Writes 8-bit data in display RAM. As the column address is
incremented by 1 automatically after each write, the microproc-
essor can continue to write data of multiple words.
R/W
A0 RD WR D7 D6 D5 F4 D3 D2 D1 D0
1
1
0
Write data
R/W
A0 RD WR D7 D6 D5 F4 D3 D2 D1 D0
(7) Read Display Data
Reads 8-bit data from display RAM area specified by column
address and page address. As the column address is incremented
by 1 automatically after each write, the microprocessor can
continue to read data of multiple words. A single dummy read
is required immediately after column address setup. Refer to
the display RAM section of FUNCTIONAL DESCRIPTION
for details.
0
1
0
1
0
1
1
1
A2 A1 A0
A2
0
0
0
0
A1
0
0
1
1
A0
Page Address
0
1
0
1
0
0
1
2
3
4
R/W
1
0
A0 RD WR D7 D6 D5 F4 D3 D2 D1 D0
(4) Set Column Address
1
0
1
Read data
Specifies column address of display RAM. When the micro-
processor repeats to access to the display RAM, the column
address counter is incremented by 1 during each access until
address 80 is accessed. The page address is not changed during
this time.
(8) ADC Select
Changes the relationship between RAM column address and
segment driver. The order of segment driver output pins can be
reversed by software. This allows flexible IC layout during
LCD module assembly. For details, refer to the column address
section of Figure 4. When display data is written or read, the
column address is incremented by 1 as shown in Figure 4.
4–18
EPSON
Rev.3.5
S1D15206 Series
R/W
R/W
A0 RD WR D7 D6 D5 F4 D3 D2 D1 D0
A0 RD WR D7 D6 D5 F4 D3 D2 D1 D0
0
1
0
1
0
1
0
0
0
0
D
0
1
0
1
0
1
0
1
0
1
D
When D is low, the right rotation (normal direction). When
D is HIGH, the left rotation (reverse direction).
Model
D
Duty
0
1
1/8 or 1/16
1/9 or 1/17
S1D15206
S1D15208
(9) Static Drive ON/OFF
Forcibly turns the entire display ON and makes all common
outputs selectable regardless of RAM data contents. The RAM
data is held.
0
1
1/32
1/33
(12) Read-Modify-Write
R/W
A pair of Read-Modify-Write and End commands must always
be used. Once Read-Modify-Write is issued, column address is
not incremented by Read Display Data command but
incremented by Write Display Data command only. It contin-
ues until End command is issued. When the End is issued,
column address returns to the address when Read-Modify-
Write was issued. This can reduce the microprocessor load
when data of a specific display area is repeatedly changed
during cursor blinking or others.
A0 RD WR D7 D6 D5 F4 D3 D2 D1 D0
0
1
0
1
0
1
0
0
0
0
D
When D goes LOW, the static drive turns off. When D goes
HIGH, the static drive turns on.
The LCD panel enters Power Save mode if Static Drive ON
command is issued when the display is off. Refer to the Power
Save section for details.
R/W
A0 RD WR D7 D6 D5 F4 D3 D2 D1 D0
(10) Select Duty
Selects the LCD driver duty. However, the bias of LCD driver
voltage is fixed when on-chip power circuit is used (refer to
Subsection).
0
1
0
1
1
1
0
0
0
0
0
Note: Any command except Read/Write Display Data and Set
Column Address can be issued during Read-Modify-Write
mode.
R/W
A0 RD WR D7 D6 D5 F4 D3 D2 D1 D0
0
1
0
1
0
1
0
1
0
0
D
• Cursor display sequence
Model
D
Duty
Set Page Address
0
1
1/8
1/16
S1D15206
S1D15208
Set Column Address
0
1
1/32
1/32
(11) Duty+1
Read-Modify-Write
Dummy Read
Increments the duty by 1. If 1/8 duty is set for the S1D15206,
for example, it is incremented to 1/9 duty. If 1/16 duty is set, it
is incremented to 1/17 duty. The COMS terminal functions as
COM8 or COM16. The display line of RAM area correspond-
ing to page address 4, or D0, is always accessed.
Read Data
Write Data
No
Completed?
Yes
End
Rev.3.5
EPSON
4–19
S1D15206 Series
(13) End
Cancels Read-Modify-Write mode and returns column address to the original address (when Read-Modify-Write was issued).
R/W
A0 RD WR D7 D6 D5 F4 D3 D2 D1 D0
0
1
0
1
1
1
0
1
1
1
0
Return
Column address
N
N+1
N+2
N+3
N+m
N
Read-Modify-Write mode is selected.
End
(14) Reset
D4
D3
D2
D1
D0
| V5 |
Low
Resets the Initial Display Line register, Column Address coun-
ter, Page Address register, register data of serial interface, and
Electronic Control register to their initial status. The Reset
command does not affect on the contents of display RAM.
Refer to the Reset circuit section of FUNCTIONAL DESCRIP-
TION.
0
0
0
0
0
0
0
0
0
↓
1
1
1
0
0
1
0
1
0
↓
1
1
1
1
1
1
0
1
1
1
0
1
R/W
High
A0 RD WR D7 D6 D5 F4 D3 D2 D1 D0
Set register to (D4,D3,D2,D1,D0)=(0,0,0,0,0) to suppress elec-
tronic control function.
0
1
0
1
1
1
0
0
0
1
0
The Reset command cannot initialize LCD power supply. Only
RES (that sets SR1 and SR2 to low) can initialize the supplies.
(17) Clock Stop
Stops clock output at CL to reduce current consumption.
(15) Set Power Control
R/W
Selects one of eight power circuit functions using 3-bit register.
An external power supply and part of on-chip power supply
functions can be used simultaneously. Refer to Power Circuit
section of FUNCTIONAL DESCRIPTION for details.
A0 RD WR D7 D6 D5 F4 D3 D2 D1 D0
0
1
0
1
1
1
0
0
1
1
D
Clock outputs when D is low, but clock stops when D is high.
R/W
A0 RD WR D7 D6 D5 F4 D3 D2 D1 D0
(18) Power Save (a combination with Static Drive command)
Sets LCD panel in power save mode if Static Drive ON is issued
when the display is off. Power consumption drops power
consumption level.
0
1
0
1
0
1
1
0
D2 D1 D0
When D0 goes LOW, voltage follower turns off. When D0 goes
HIGH, it turns on.
When D1 goes LOW, voltage regulator turns off. When D1 goes
HIGH, it turns on.
When D2 goes LOW, voltage booster turns off. When D2 goes
HIGH, it turns on.
When LCD panel enters Power Save mode:
(a) Both oscillator and power supply stop.
(b) LCD driver stops, and segment and common driver have
V
DD level output.
(c) External clock input is disabled, and clock output is set
to low (at CL).
(d) Both display data and operation mode before issue of
Power Save are held.
(16) Set Electronic Control
Adjusts the contrast of LCD panel display by changing V5 LCD
drive voltage that is output by voltage regulator of on-chip
power supply.
This command selects one of 32 V5 LCD drive voltages by
storing data in 5-bit register. The V5 voltage adjusting range
should be determined depending on the external resistance.
Refer to the Voltage Regulator Circuit section of FUNC-
TIONAL DESCRIPTION for details.
(As the power control register is cleared, the Set Power
Control command must be issued again after the Power
Save mode has been released.)
(e) All LCD driver voltages are fixed to VDD
.
The Power Save is released when the display is turned on or
when Static Drive OFF is issued. If external voltage driver
resistors are used to supply voltage to LCD panel, current
passing through resistors must be cut off. An external power
supply must be turned off if used; its voltage must be fixed to
floating or VDD level.
* When the S1D15206 series is operating, the internal status
data set by commands is held. However, the internal status
may change due to an excessive ambient noise. The package
and system noise generation must be suppressed or a noise
protection design must be considered.
This command is valid only when voltage regulator circuit is
turned on by Set Power Control command.
R/W
A0 RD WR D7 D6 D5 F4 D3 D2 D1 D0
0
1
0
1
0
0
D4 D3 D2 D1 D0
We recommend to periodically refresh the internal status
data to prevent a spike noise and other interference.
4–20
EPSON
Rev.3.5
S1D15206 Series
S1D15206 Series Command Table
Code
Command
Function
A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0
(1) Display ON/OFF
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
0
0
1
0
1
0
1
0
1
1
1
0
1
Turns on LCD panel when goes
HIGH, and turns off when goes LOW.
(2) Initial Display Line
(3) Set Page Address
(4) Set Column Address
Initial display address
Specifies RAM display line for
COM0.
1
1
Page address Sets the display RAM page in
Page Address register.
Column address
Sets RAM column address in
Column register.
(5) Read Status
0
1
1
0
0
1
0
1
1
0
1
0
Status
0
0
0
0
0
Reads the status information.
Writes data in display RAM.
Reads data from display RAM.
(6) Write Display Data
(7) Read Display Data
(8) ADC Select
Write data
Read data
1
0
1
0
0
0
1
Sets normal relationship between
RAM column address and seg-
ment driver when low, but re-
verses the relationship when HIGH.
(9) Static Drive ON/OFF
(10) Duty Select
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
1
1
0
0
0
0
1
Normal indication when LOW, but
full indication when HIGH.
0
1
Selects LCD driver duty of 1/8 (1/
16) when LOW and 1/16 (1/32)
when HIGH.
(11) Duty+1
0
0
1
1
0
0
1
1
0
1
1
1
0
0
1
0
0
0
1
0
0
1
Selects normal LCD driver duty
when LOW, and selects the duty
added by 1 when HIGH.
(12) Read-Modify-Write
0
Increments Column Address
counter during each write when
HIGH and during each read when
LOW.
(13) End
0
0
0
1
1
1
0
0
0
1
1
1
1
1
0
1
1
1
0
0
1
1
0
0
1
0
1
1
0
0
Releases the Read-Modify-Write.
Resets internal functions.
(14) Reset
(15) Set Power Control
Power control Selects various power circuit
functions.
(16) Set Electronic Control
(17) Clock Stop
0
0
–
1
1
–
0
0
–
1
1
–
0
1
–
0
1
–
Electronic control value
Sets V5 output voltage to Elec-
tronic Control register.
0
–
0
–
1
–
1
–
0
1
Stops clock output at CL when
LOW, and stops clock when HIGH.
(18) Power Save
–
A combination of Display OFF and
Static Drive ON commands.
Note: Do not use any other command, or the system malfunction may result.
Rev.3.5
EPSON
4–21
S1D15206 Series
8. ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Rating
–0.3 to +7.0
–0.3 to +6.0
–18.0 to +0.3
V5 to +0.3
Unit
V
VDD
Supply voltage range
Triple voltage
conversion
VDD
Driver supply voltage range (1)
Driver supply voltage range (2)
Input voltage range
V5
V
V
V1, V2, V3, V4
VIN
VO
–0.3 to VDD+0.3
–0.3 to VDD+0.3
250
V
Output voltage range
V
Allowable loss
PD
mW
°C
°C
Operating temperature range
TOPR
TSTG
–40 to +85
QFP • TCP
Bear chip
–65 to +150
–55 to +125
260-10 (at leads)
Storage temperature range
Soldering temperature and time
TSOLDER
°C•sec
VCC
VDD
GND
VSS
V1
to V5, VOUT, VREG
(Microprocessor side)
(S1D15206 series side)
Notes: 1. V1 to V5, VOUT, and VREG voltages are based on VDD=0 V.
2. Voltages VDD ≥ V1 ≥ V2 ≥ V3 ≥ V4 ≥ V5 VSS ≥ VOUT must always be satisfied.
3. If an LSI exceeds its absolute maximum rating, it may be damaged permanently. It is desirable to use it under electrical characteristics
conditions during general operation. Otherwise, an LSI malfunction or reduced LSI reliability may result.
4. The moisture resistance of the flat package may drop during soldering. Take care not to excessively heat the package resin during
chip mounting.
4–22
EPSON
Rev.3.5
S1D15206 Series
9. ELECTRICAL CHARACTERISTICS
DC Characteristics
VDD = 5 V ±10%, VSS = 0 V, Ta = –40 to +85°C unless otherwise noted.
Item
Power voltage (1)
Operating voltage
(2)
Symbol
VDD
Condition
Min.
2.4
Typ.
Max.
6.0
Unit
V
Pin used
VDD *1
V5 *2
V1, V2
V3, V4
*3
Operational
Operational
V5
–13.0
–4.0
V
Operational V1, V2
Operational V3, V4
0.6 × V5
V5
VDD
V
0.4 × V5
VDD
V
HIGH-level input voltage
LOW-level input voltage
HIGH-level output voltage
LOW-level output voltage
HIGH-level input voltage
LOW-level input voltage
VIHC
0.7 × VDD
0.8 × VDD
VSS
V
VDD = 2.7 V
VDD
VILC
0.3 × VDD
0.2 × VDD
VDD
V
V
V
V
V
*3
*4
*4
*5
*5
VDD = 2.7 V
VSS
VOHC
VOLC
VIHS
VILS
IOH = –1 mA
0.8 × VDD
0.8 × VDD
VSS
VDD = 2.7 V, IOH = –0.5 mA
IOH = 1 mA
VDD
0.2 × VDD
0.2 × VDD
0.8 × VDD
0.8 × VDD
0.6 × VDD
0.6 × VDD
1.0
VDD = 2.7 V, IOL = 0.5 mA
VSS
0.4 × VDD
0.4 × VDD
0.2 × VDD
0.2 × VDD
–1.0
VDD = 2.7 V
VDD = 2.7 V
Input leakage current
Output leakage current
LCD driver ON resistance
ILI
µA
µA
KΩ
*6
*7
ILO
–3.0
3.0
SEG0 to 79
COS0 to 15
COMS *9
RON
Ta = 25°C
V5 = –0.5 V
15.0
30.0
Static current consumption
Input pin capacity
IDDQ
CIN
fCL
CS = CL = VDD
0.05
5.0
2.9
5.8
3.0
8.0
3.7
7.4
µA
pF
VDD
Ta = 25°C, f = 1 MHz
Ta = 25°C, VDD = 2.7 to 5 V
Input pins
CL output frequency
2.4
4.8
kHz
*8
Applies to the
S1D15206*10**,
S1D15208*10**
Dynamic current consumption (1) when the built-in power supply is OFF
1.7 times of normal products apply to fCL = 5.8 kHz products of S1D15206F11** and S1D15208F11** .
Ta = 25°C
Remarks
*12
Item
Symbol
Conditions
Min.
Typ.
Max.
Unit
S1D15206
IDD (1)
VDD = 5.0V, V5–VDD = –6.0V
VDD = 3.0V, V5–VDD = –6.0V
VDD = 5.0V, V5–VDD = –8.0V
VDD = 3.0V, V5–VDD = –8.0V
–
9.1
18
µA
–
12.0
7.5
24
S1D15208
–
15
–
9.5
19
Rev.3.5
EPSON
4–23
S1D15206 Series
Dynamic current consumption (2) when the built-in power supply is ON (Display all white)
1.7 times of normal products apply to fCL = 5.8 kHz products of S1D15206F11** and S1D15208F11**.
Ta = 25°C
Remarks
*13
Item
Symbol
Conditions
Min.
Typ.
Max.
Unit
S1D15206
IDD (2) VDD = 5.0V, V5–VDD = –6.0V, dual boosting
VDD = 3.0V, V5–VDD = –6.0V, triple boosting
VDD = 5.0V, V5–VDD = –8.0V, dual boosting
VDD = 3.0V, V5–VDD = –8.0V, triple boosting
–
31
62
µA
–
44
88
S1D15208
–
37
74
–
55
110
Dynamic current consumption (2) when the built-in power supply is ON (Display checker pattern)
1.7 times of normal products apply to fCL = 5.8 kHz products of S1D15206F11** and S1D15208F11**.
Ta = 25°C
Item
Symbol
Conditions
Min.
Typ.
Max.
Unit
Remarks
*13
S1D15206
IDD (2) VDD = 5.0V, V5–VDD = –6.0V, dual boosting
VDD = 3.0V, V5–VDD = –6.0V, triple boosting
VDD = 5.0V, V5–VDD = –8.0V, dual boosting
VDD = 3.0V, V5–VDD = –8.0V, triple boosting
–
34
68
µA
–
46
92
S1D15208
–
42
84
–
60
120
Current consumption during Power Save mode V = 0 V, V = 2.7 to 5.5 V
SS
DD
Ta = 25°C
Remarks
—
Item
Symbol
IDDS1
Conditions
S1D15206, S1D15208
Min.
—
Typ.
3
Max.
6
Unit
Power save
mode
µA
Typical current consumption characteristics (reference data)
•
Dynamic current consumption (1) when LCD external power mode lamp is ON
20
(µA)
Conditions: The built-in power supply is
OFF and an external power
supply is used.
15
S1D15206 V5-VDD=–6.0V
S1D15208 V5-VDD=–8.0V
Ta=25°C
S1D15208
I DD (1)
10
5
Remarks: *12
1.7 times of normal products apply
to fCL = 5.8 kHz products of
S1D15206F11** and S1D15208F11**.
S1D15206
0
1
2
3
4
5
6
7
(V)
VDD
•
Dynamic current consumption (2) when the LCD built-in power supply lamp is ON
80
(µA)
Conditions: The built-in power supply is ON.
S1D15206 V5-VDD=–6.0V dual boosting
S1D15208 V5-VDD=–8.0V triple boosting
Ta=25°C
60
S1D15208
Remarks: *13
IDD (2)
1.7 times of normal products apply
to fCL = 5.8 kHz products of
S1D15206F11** and S1D15208F11**.
40
20
S1D15206
0
1
2
3
4
5
6
7
(V)
VDD
4–24
EPSON
Rev.3.5
S1D15206 Series
• Current consumption I DD during access (2) during MPU access cycle
It shows the current consumption when a checker
pattern is always written in fSYNC timing.
10
(mA)
S1D15206
When not accessed, only the current consumption
of IDD (2) occurs.
1
0.1
IDD(2)
Conditions: S1D15206 V5 – VDD = –6.0 V, dual boosting
S1D15208 V5 – VDD = –8.0 V, triple boosting
Ta = 25°C
S1D15208
0.01
0
0.01
f CYC
0.1
(MHz)
1
10
Item
Symbol
VDD
Conditions
—
Min.
2.4
Typ. Max.
Unit Pins used
Input voltage
—
—
—
6.0
—
V
V
V
*10
Booster output voltage
VOUT
VOUT
VDD reference (during triple boosting) –16.5
VOUT
VOUT
Voltage regulator circuit
operating voltage
VDD reference
–16.5
–4.0
Voltage follower operating
voltage
V5
VDD reference
–13.0
—
–4.0
V
*11
Reference voltage
VREG VDD reference Ta = 25°C
–3.5 –3.1 –2.7
V
VR
* See notes below.
*1 Although the wide range of operating voltage is guaranteed, a spike voltage change during access to the MPU is not guaranteed.
*2 The operating voltage range of the VDD and V5 systems (See Figure 9.)
The operating voltage range is applied if an external power supply is used.
*3 Pins D0 to D5, A0, CS1, CS2, RD (E), WR (R/W), M/S, CL, and FR
*4 Pins D0 to D7, FR, and CL
*5 Pins SI (D7), SCL (D6), SR1, and SR2
*6 Pins A0, RD (E), WR (R/W), CS1, CS2, M/S, SR1, and SR2
*7 Applied if pins D0 to D7, FR, and CL are high impedance.
*8 For the relationship between CL output frequency and frames, see Figure 7.
For the relationship between CL output frequency and power voltage, see Figure 8.
For the relationship between CL output frequency and temperature, see Figure 11.
*9 The resistance when the 0.1-volt voltage is applied between the SEG and COM output terminals and each power terminal (V1, V2, V3 or
V4). It must be within operating voltage (2).
RON = 0.1 V/∆I
where, ∆I is the current that flows between power supply and SEG or COM terminal when the 0.1-volt voltage is applied.
*10 If the triple voltage by the built-in power circuit are used the VDD primary power must be used within the input voltage range.
*11 The V5 voltage can be adjusted within the voltage follower operating range by use of voltage regulator.
*12 Applied if the built-in oscillation circuit is used and if not accessed by the MPU.
*13 Applied if the built-in oscillation circuit and the built-in power circuit are used, and if not accessed by the MPU.
The current flowing through the voltage regulator resistors (R1, R2 and R3) is not included.
When the built-in voltage booster is used, the current consumption for the VDD power supply is shown.
• Relationship between CL output frequency and frames
(S1D15206 series)
• Relationship between CL output frequency and power
voltage
The relationship between CL output frequency (fCL) and frame
frequency (fF) can be determined as follows:
Ta=25°C
6
f
CL=5.80
Applies to the
S1D15206*11**,
5
4
3
2
1
Duty
fF
S1D15208*11**
1/9
1/17
8 • FOSC/288
8 • fOSC/272
S1D15206
S1D15208
fCL
[KHz]
f
CL=2.90
1/33
8 • fOSC/264
Figure 7
("fF" indicates the LCD current alternating cycle, but not the
cycle of f F signals.)
0
2
4
6
8
VDD [V]
Figure 8
Rev.3.5
EPSON
4–25
S1D15206 Series
•
Operating voltage range on VDD and V5
-20
-15
-13
-4
[V]
-10
V5
-7.2
-5
2.4
6
0
2
4
8
VDD
[V]
•
IDD measuring circuits
A
A
VDD
VDD
V1
V2
V1
V2
0V
0V
-5V
-5V
S1D152
S1D152
V3
V4
V3
V4
0V
-2.7V
V5
V5
VSS
VSS
•
Relationship between CL output frequency and temperature
7
6
Applies to the
S1D15206*11**,
5
S1D15208*11**
4
fCL
[KHz]
3
2
1
-40
0
40
80
120
[
]
Ta ˚C
4–26
EPSON
Rev.3.5
S1D15206 Series
Read/write characteristics I (8080-series microprocessor)
tAH8
AC Characteristics
(1) System buses
A0
tAW8
CS1
(CS2="1")
tCYC8
tCCLW
tCCLR
WR,RD
tCCHW
tCCHR
tDH8
tDS8
D0~D7
(WRITE)
tACC8
tCH8
D0~D7
(READ)
VSS = 0 V, VDD = 5.0 V ±10%, Ta = –40 to +85°C
Parameter
Signal
Symbol
Condition
Min.
Max.
Unit
Address hold time
Address setup time
A0
tAH8
tAW8
5
5
ns
ns
System cycle time
tCYC8
400
ns
Control LOW pulse width (WR)
Control LOW pulse width (RD)
Control HIGH pulse width (WR)
Control HIGH pulse width (RD)
WR
RD
WR
RD
tCCLW
tCCLR
tCCHW
tCCHR
100
75
145
145
Data setup time
Data hold time
tDS8
tDH8
80
10
ns
ns
RD access time
Output disable time
D0 to D7
tACC8
tCH8
CL=100pF
80
60
ns
ns
10
VSS = 0 V, VDD = 2.7 V to 4.5 V, Ta = –40 to +85°C
Parameter
Signal
Symbol
Condition
Min.
Max.
Unit
Address hold time
Address setup time
A0
tAH8
tAW8
10
10
ns
ns
System cycle time
tCYC8
800
ns
Control LOW pulse width (WR)
Control LOW pulse width (RD)
Control HIGH pulse width (WR)
Control HIGH pulse width (RD)
WR
RD
WR
RD
tCCLW
tCCLR
tCCHW
tCCHR
185
185
285
285
ns
ns
Data setup time
Data hold time
tDS8
tDH8
160
20
ns
ns
RD access time
Output disable time
D0 to D7
tACC8
tCH8
CL=100pF
180
120
ns
ns
20
Notes: 1. tCCLW and tCCLR are limited depending on the overlap time of CS1 LOW (CS2 HIGH) and WR or RD LOW.
2. The input signal rise and fall times must be within 15 nanoseconds.
3. All signal timings are limited based on 20% and 80% of VDD voltage.
Rev.3.5
EPSON
4–27
S1D15206 Series
(2) System buses
Read/write characteristics II (6800-series microprocessor)
A0
tAH6
tAW6
CS1
(CS2="1")
tCYC6
tEWLW
tEWLR
RD (E)
tEWHW
tEWHR
WR (R/W)
tDH6
tDS6
D0~D7
(WR1TE)
tACC6
tOH6
D0~D7
(READ)
VSS = 0 V, VDD = 5.0 V ±10%, Ta = –40 to +85°C
Parameter
Signal
Symbol
Condition
Min.
Max.
Unit
System cycle time
tCYC6
400
ns
Address setup time
Address hold time
WR (R/W)
A0
tAW6
tAH6
20
10
ns
ns
Data setup time
Data hold time
tDS6
tDH6
80
10
ns
ns
D0 to D7
Output disable time
Access time
tOH6
tACC6
CL=100pF
10
60
90
ns
ns
Enable
READ
tEWLR
tEWLW
tEWHR
tEWHW
85
75
ns
ns
ns
ns
RD (E)
RD (E)
LOW pulse width WRITE
Enable
READ
135
145
HIGH pulse width WRITE
VSS = 0 V, VDD = 2.7 V to 4.5 V, Ta = –40 to +85°C
Parameter
Signal
Symbol
Condition
Min.
Max.
Unit
System cycle time
tCYC6
800
ns
Address setup time
Address hold time
WR (R/W)
A0
tAW6
tAH6
40
20
ns
ns
Data setup time
Data hold time
tDS6
tDH6
160
20
ns
ns
D0 to D7
Output disable time
Access time
tOH6
tACC6
CL=100pF
20
120
180
ns
ns
Enable
LOW pulse width WRITE
Enable READ
HIGH pulse width WRITE
READ
tEWLR
tEWLW
tEWHR
tEWHW
185
145
285
325
ns
ns
ns
ns
RD (E)
RD (E)
Notes: 1. tEWHR and tEWHW are limited depending on the overlap time of CS1 LOW (CS2 high) and RD (E) HIGH.
2. The input signal rise and fall times must be within 15 nanoseconds.
3. All signal timings are limited based on 20% and 80% of VDD voltage.
4–28
EPSON
Rev.3.5
S1D15206 Series
(3) Serial interface
tCSS
tCSH
CS1
(CS2="1")
tSAS
tSAH
A0
tSCYC
tSLW
Serial clock (D6)
Serial data (D7)
tSHW
tSDH
tSDS
D1 data
D0 data
D7 data
VSS = 0 V, VDD = 5.0 V ±10%, Ta = –40 to +85°C
Parameter
Signal
Symbol
Condition
Min.
Max.
Unit
Serial clock cycle
Serial clock HIGH pulse width
Serial clock LOW pulse width
Serial clock
tSCYC
tSHW
tSLW
500
150
150
ns
ns
ns
Address setup time
Address hold time
A0
tSAS
tSAH
120
200
ns
ns
Data setup time
Data hold time
Serial data
tSDS
tSDH
120
120
ns
ns
CS serial clock time
CS1
(CS2="1")
tCSS
tCSH
80
400
ns
ns
VSS = 0 V, VDD = 2.7 to 4.5V, Ta = –40 to +85°C
Parameter
Signal
Symbol
Condition
Min.
Max.
Unit
Serial clock cycle
Serial clock HIGH pulse width
Serial clock LOW pulse width
Serial clock
tSCYC
tSHW
tSLW
1000
300
300
ns
ns
ns
Address setup time
Address hold time
A0
tSAS
tSAH
250
400
ns
ns
Data setup time
Data hold time
Serial data
tSDS
tSDH
250
250
ns
ns
CS serial clock time
CS1
(CS2="1")
tCSS
tCSH
160
800
ns
ns
Notes: 1. The input signal rise and fall times must be within 15 nanoseconds.
2. All signal timings are limited based on 20% and 80% of VDD voltage.
Rev.3.5
EPSON
4–29
S1D15206 Series
(4) Display control timing
t WHCL
CL
FR
tr
tf
t WLCL
tDFR
VSS = 0 V, VDD = 5.0 V ±10%, Ta = –40 to +85°C
Parameter
LOW level pulse width
HIGH level pulse width
Rise time
Signal
Symbol
Condition
Min.
35
Typ.
Max.
Unit
µs
CL
tWLCL
tWHCL
tr
35
µs
30
30
120
120
1.0
ns
Fall time
tf
ns
FR delay time
FR
tDFR
–1.0
0.2
µs
VSS = 0 V, VDD = 2.7 V to 4.5 V, Ta = –40 to +85°C
Parameter
LOW level pulse width
HIGH level pulse width
Rise time
Signal
Symbol
tWLCL
tWHCL
tr
Condition
Min.
70
Typ.
Max.
Unit
µs
CL
70
µs
60
60
240
240
2.0
ns
Fall time
tf
ns
FR delay time
FR
tDFR
–2.0
0.4
µs
Output timing
Parameter
VSS = 0 V, VDD = 5.0 V ±10%,Ta = –40 to +85°C
Signal
Symbol
Condition
Min.
Typ.
Max.
Unit
FR delay time
FR
tDFR
CL=100pF
0.2
0.4
µs
VSS = 0 V, VDD = 2.7 V to 4.5 V, Ta = –40 to +85°C
Parameter
Signal
Symbol
Condition
Min.
Typ.
Max.
Unit
FR delay time
FR
tDFR
CL=100pF
0.4
0.8
µs
Notes: 1. All signal timings are limited based on 20% and 80% of VDD voltage.
4–30
EPSON
Rev.3.5
S1D15206 Series
(5) Reset timing
t RW
Reset input
(SR1 and SR2
are LOW.)
t R
Internal circuit
status
During reset
End of reset
VDD = 5.0 V ±10%, Ta = –40 to +85°C
Parameter
Reset time
Signal
Symbol
tR
Condition
Condition
Min.
1.0
10
Typ.
Max.
Unit
µs
Reset LOW pulse width
Reset input
tRW
µs
V
DD = 2.7 V ±10%, Ta = –40 to +85°C
Parameter
Reset time
Signal
Symbol
tR
Min.
3.0
30
Typ.
Max.
Unit
µs
Reset LOW pulse width
Reset input
tRW
µs
Notes: 1. tR (reset time) represents the period from rising edge of reset input to end of internal circuit reset. The S1D15206 series can
operate normally after tR.
2. tRW specifies the minimum pulse width of reset input. The low pulse exceeding tRW is required for reset.
3. The input signal rise and fall times must be within 15 nanoseconds.
4. All signal timings are limited based on 20% and 80% of VDD voltage.
Rev.3.5
EPSON
4–31
S1D15206 Series
10. EXTERNAL WIRINGS
Power Supply and LCD Power Circuit
If a single S1D15206 series chip is used and if on-board power supply is used and not used
If on-chip power supply is used
If on-chip power supply is NOT used
VDD
VDD
M/S
M/S
VOUT
VOUT
CAP1+
CAP1-
CAP2+
CAP2-
VSS
CAP1+
CAP1-
CAP2+
CAP2-
VSS
C1
C1
C1
S1D152*******
S1D152*******
VDD
V1
VDD
V1
V2
V3
V4
V5
V2
V3
V4
V5
External
power
supply
C2
R1
VR
VR
R2
R3
Parts list (Reference)
.
Variable V5 = –9.3 to –6.2 V
.
C 1
C 2
R 1
R 1
R 1
0.1 to 1 µF
Note: Use jumper and shielded wires
as the input impedance of VR
terminal is high.
0.1 to 1 µF
2.0 MΩ
1.0 MΩ
3.0 MΩ
Setting value for your reference: 100 kΩ to 1 MΩ.
S1D1520*D****
VDD, V0
In order to select an optimum value for resistor R4, you should
reference the LCD and the drive waveform.
R4
R4
Notes: 1. Because of high input impedance on VR terminal,
wiring should made as short as possible and shielded
wire should be used for the wiring.
C2
V1
V2
V3
V4
2. C1 and C2 depend on size of the liquid crystal panel
to be driven. The value to be selected for C1 and C2
must be able to stabilize the liquid crystal drive
voltage.
[A setting example]
Turn on the voltage regulator circuit and the voltage
follower circuit to apply voltage to VOUT externally.
Display the LCD heavy load patterns (horizontal
stripe-shaped), then select the C2 value that can
stabilize the liquid crystal drive voltages (V1 to V5).
All C2 capacity values selected, however, must be
the same. Then, turn on every built-in power
supplies and select an appropriate C1 value.
3. In order to regulate the voltage, a capacitor must be
connected between VDD and VSS (near to the IC).
R4
R4
V5
4–32
EPSON
Rev.3.5
S1D15206 Series
Microprocessor Interface
The S1D15206 series chips can directly connect to 8080 and 6800-series microprocessors. Also, serial interfacing requires less signal lines
between them.
8080-series microprocessors
Wiring example 1:
VCC
VDD
A0
A0
SR2
CS2
A1 to A7
IORQ
Decoder
RESET
CS1
S1D15206
MPU
D0 to D7
RD
D0 to D7
RD
WR
SR1
WR
RES
VSS
GND
Wiring example 2:
VCC
VDD
A0
A0
SR2
CS2
A1 to A7
IORQ
Decoder
RESET
CS1
S1D15206
MPU
D0 to D7
RD
D0 to D7
RD
WR
SR1
WR
RES
VSS
GND
Rev.3.5
EPSON
4–33
S1D15206 Series
6800-series microprocessors
Wiring example 1:
VCC
VDD
A0
A0
SR2
CS2
A1 to A15
VMA
Decoder
RESET
CS1
S1D15206
MPU
D0 to D7
E
D0 to D7
RD (E)
WR (R/W)
SR1
R/W
RES
VSS
GND
Wiring example 2:
VCC
VDD
A0
A0
SR2
CS2
A1 to A15
VMA
Decoder
RESET
CS1
S1D15206
MPU
D0 to D7
E
D0 to D7
RD (E)
WR (R/W)
SR1
R/W
RES
VSS
GND
4–34
EPSON
Rev.3.5
S1D15206 Series
Serial interface
Wiring example 1:
VDD
VCC
A0
Port 1
Port 2
SR2
CS1
CS2
RD
WR
S1D15206
MPU
Port 3
Port 4
SI (D7)
SCL (D6)
SR1
RES
GND
VSS
RESET
Wiring example 2:
VDD
VCC
A0
Port 1
SR2
Port 2
CS1
CS2
RD
WR
S1D15206
MPU
Port 3
Port 4
SI (D7)
SCL (D6)
SR1
RES
GND
VSS
RESET
Rev.3.5
EPSON
4–35
S1D15206 Series
LCD Panel and Wiring Examples
Single-chip configuration
S1D15206 : 80×17dot
S1D15208 : 64×33dot
SEG
SEG
80
64
S1D15206
S1D15208
COM
COM
COM
17
17
16
4–36
EPSON
Rev.3.5
S1D15206 Series
11. DIMENSIONS
Plastic 128-Pin QFP5 Package
± 0.4
± 0.1
23.6
20.0
102
65
103
64
Index
128
39
1
38
0.2
± 0.1
0.5
1.8
The package dimensions are subject to change without notice.
Rev.3.5
EPSON
4–37
S1D15206 Series
TPC shape S1D15206T00A (Reference drawing)
*
( M a r k i n g a r e a )
( M o l d a r e a )
This dimensional outline drawing is subject to change for improvements without prior notice
4–38
EPSON
Rev.3.5
相关型号：
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