S1D15300D15A_技术文档

5. S1D15300 Series

Rev. 1.4

Contents

1. DESCRIPTION ................................................................................................................................................5-1

2. FEATURES......................................................................................................................................................5-1

3. BLOCK DIAGRAM (S1D15300D00B ) ...........................................................................................................5-2

*

4. PAD LAYOUT ..................................................................................................................................................5-3

5. PIN DESCRIPTION .........................................................................................................................................5-5

6. FUNCTIONAL DESCRIPTION ........................................................................................................................5-8

7. COMMANDS .................................................................................................................................................5-19

8. COMMAND SETTING (For Refrence) ...........................................................................................................5-24

9. ABSOLUTE MAXIMUM RATINGS ................................................................................................................5-27

10. ELECTRICAL CHARACTERISTICS..............................................................................................................5-28

11. MPU INTERFACE (For Reference) ...............................................................................................................5-36

12. CONNECTION BETWEEN LCD DRIVERS...................................................................................................5-37

– i –

Rev. 1.4

S1D15300 Series

tions. Accordingly, this driver can be operated with a minimum

current consumption and its on-board low-current-consumption

liquid crystal power supply can implement a high-performance

handy display system with a minimum current consumption and a

smallest LSI configuration.

Two types of S1D15300 series are available: one in which common

outputs are arranged on a single side and the other in which common

outputs are arranged on both sides.

1. DESCRIPTION

The S1D15300 series is a single-chip LCD driver for dot-matrix

liquid crystal displays (LCD’s) which is directly connectable to a

microcomputer bus. It accepts 8-bit serial or parallel display data

directly sent from a microcomputer and stores it in an on-chip

display RAM. It generates an LCD drive signal independent of

microprocessor clock.

The use of the on-chip display RAM of 65 × 132 bits and a one-to-

one correspondence between LCD panel pixel dots and on-chip

RAM bits permits implementation of displays with a high degree of

freedom.

As a total of 133 circuits of common and segment outputs are

incorporated, a single chip of S1D15300 can make 33 × 100-dot (16

× 16-dot kanji font: 6 columns × 2 lines) displays, and a single chip

of S1D15301 can make 65 × 132-dot (kanji font: 8 columns x 4 lines)

displays when the S1D15301 is combined with the common driver

S1D16700.

2. FEATURES

• Direct RAM data display using the display RAM. When

RAM data bit is 0, it is not displayed. When RAM data bit

is 1, it is displayed. (At normal display)

• RAM capacity: 65 × 132 = 8580 bits

• High-speed 8-bit microprocessor interface allowing direct

connection to both the 8080 and 6800.

• Serial interface

The S1D15302 can display the 65 × 200-dot (or 12-column by 4-line

Kanji font) area using two ICs in master and slave modes. As an

independent static indicator display is provided for time-division

driving, the low-power display is realized during system standby

and others.

• Many command functions: Read/Write Display Data, Dis-

play ON/OFF, Normal/Reverse Display, Page Address Set,

Set Display Start Line, Set Column Address, Read Status,

All Display ON/OFF, Set LCD Bias, Electronic contrast

Controls, Read Modify Write, Select Segment Driver Direc-

tion, Power Save

No external operation clock is required for RAM read/write opera-

• Series specifications (in cases of chip shipments)

Type 1 [V_REG(Built-in power supply regulating voltage)

Temperature gradient: -0.2% / °C]

Name

Duty

1/33

1/65

LCD bias

1/5, 1/6

1/6, 1/8

Segment driver COM driver Display area Remarks

✽✽

S1D15300D00

S1D15300D10

S1D15301D00

S1D15302D00

100

132

100

33

0

33 × 100

65 × 132

65 × 200

COM single-side layout

COM dual-side layout

S1D16700 is used as the COM.

COM single-side, right-hand layout

33

✽✽

S1D15302D11

S1D15305D10

1/65

1/35

1/6, 1/8

1/5, 1/6

100

98

33

35

65 × 200

35 × 98

COM single-side, left-hand layout

COM both-side layout

✽✽

Type 2 [V_REGTemperature gradient: 0.00% / °C]

Name

Duty

1/33

1/65

1/17

1/9

LCD bias

1/5, 1/6

1/6, 1/8

1/5

Segment driver COM driver Display area Remarks

✽✽

S1D15300D15

S1D15302D14

S1D15303D15

S1D15304D14

100

116

124

33

17

9

33 × 100

65 × 200

17 × 116

9 × 124

COM both-side layout

COM single-side, right-hand layout

COM both-side layout

1/5

COM single-side layout

Note: The S1D15300 series has the following subcodes depending on their shapes. (The S1D15300 examples are given.)

: TCP (The TCP subcode differs from the inherent chip subcode.)

^S1D15300T****

^S1D15300D****

^S1D15300D**^A*

: Bear chips

: Al-pad chip

^S1D15300D**^B*

: Au-bump chip

• On-chip LCD power circuit: Voltage booster, voltage

regulator, voltage follower × 4.

• Wide operating temperature range:

Ta = -40 to 85°C

• On-chip electronic contrast control functions

• Ultra low power consumption

• CMOS process

• Package: TCP and bare chip

• Non-radiation-resistant design

• Power supply voltages:

V

_DD- V_SS-2.4 V to -6.0 V

_DD- V5 -4.5 V to -16.0 V

Rev.1.4

EPSON

5–1

S1D15300 Series

3. BLOCK DIAGRAM (S1D15300D00B )

*

COMS

O15

O0

O99 O100

·····················

VSS

···············································

VDD

V1

V2

V3

Segment driver

Common driver

Shift register

V4

V5

CAP1+

CAP1–

Display data latch

Power supply

CAP2+

circuit

CAP2–

CAP3–

VOUT

VR

132 x 65-dot

display data RAM

Output

status

selector

circuit

Column address decoder

8-bit column address counter

8-bit column address register

Page address

register

FRS

FR

Display timing

generator circuit

CL

DYO

DOF

M//S

Status

register

Bus holder

Command decoder

Oscillator

VS1

Microprocessor interface

I/O buffer

D4 D3

CS1 CS2 A0 RD WR C86 P/S RES

(E) (R/W)

D7 D6

(SI) (SCL)

D5

D2 D1

D0

5–2

EPSON

Rev.1.4

S1D15300 Series

4. PAD LAYOUT

S1D15300 series chips

51

1

52

172

Die No.

86

138

137

87

Chip Size:

Pad Pitch:

6.65x4.57 mm

118 µm (Min.)

^S1D1530*^D**^A*

(Al-pad chip)

90x90 µm

300 µm

Pad Center Size:

Chip Thickness:

^S1D1530*^D**^B*

(Al-bump chip)

76x76 µm

Bump Size:

Bump Height:

Chip Thickness:

23µm (Typ.)

625 µm

Rev.1.4

EPSON

5–3

S1D15300 Series

Pad Center Coordinates

Unit: µm

PAD PIN

No. Name

51 O5

PAD PIN

No. Name

X

Y

X

Y

No. Name

X

Y

No. Name

151 O105

152 O106

153 O107

154 O108

155 O109

156 O110

157 O111

158 O112

159 O113

160 O114

161 O115

162 O116

163 O117

164 O118

165 O119

166 O120

167 O121

168 O122

169 O123

170 O124

171 O125

172 O126

X

Y

1

2

3

4

5

6

7

8

9

O127

O128

O129

O130

O131

2986 2142

2862

-2986 2142 101 O55

-3178 2006 102 O56

1888 103 O57

1770 104 O58

1652 105 O59

1534 106 O60

1416 107 O61

1298 108 O62

1180 109 O63

1062 110 O64

-1298 -2142

-1180

-1062

-944

3178 -472

-354

-236

-118

0

52 O6

2738

53 O7

2614

54 O8

2490

55 O9

-826

COMS 2366

56 O10

57 O11

58 O12

59 O13

60 O14

61 O15

62 O16

63 O17

64 O18

65 O19

66 O20

67 O21

68 O22

69 O23

70 O24

71 O25

72 O26

73 O27

74 O28

75 O29

76 O30

77 O31

78 O32

79 O33

80 O34

81 O35

82 O36

83 O37

84 O38

85 O39

86 O40

87 O41

88 O42

89 O43

90 O44

91 O45

92 O46

93 O47

94 O48

95 O49

96 O50

97 O51

98 O52

99 O53

100 O54

-708

118

FRS

FR

2242

2124

2006

1888

1770

1652

1534

1416

1298

1180

1062

944

-590

236

-472

354

DYO

-354

472

10 CL

-236

590

11 DOF

12 VS1

13 M/S

14 RES

15 P/S

16 CS1

17 CS2

18 C86

19 A0

944

826

708

590

472

354

236

118

0

111 O65

112 O66

113 O67

114 O68

115 O69

116 O70

117 O71

118 O72

119 O73

-118

708

0

826

118

944

236

1062

1180

1298

1416

1534

1652

1770

1888

2006

354

472

590

708

826

20 WR(W/R)

21 RD(E)

22 VDD

23 D0

708

-118 120 O74

-236 121 O75

-354 122 O76

-472 123 O77

-590 124 O78

-708 125 O79

-826 126 O80

-944 127 O81

-1062 128 O82

-1180 129 O83

-1298 130 O84

-1416 131 O85

-1534 132 O86

-1652 133 O87

-1770 134 O88

-1888 135 O89

-2006 136 O90

-2986 -2142 137 O91

944

590

1062

1180

1298

1416

1534

1652

1770

1888

2006

2124

2242

2366

2490

2614

2738

2862

2986

3178 -2006

-1888

-1770

-1652

-1534

-1416

-1298

-1180

-1062

-944

472

354

24 D1

236

25 D2

118

26 D3

0

27 D4

-118

-236

-354

-472

-590

-708

-826

28 D5

29 D6(SCL)

30 D7(SI)

31 VSS

32 VOUT

33 CAP3-

34 CAP1+ -944

35 CAP1- -1062

36 CAP2+ -1180

37 CAP2- -1298

38 V5

39 VR

40 VDD

41 V1

42 V2

43 V3

44 V4

45 V5

46 O0

47 O1

48 O2

49 O3

50 O4

-1416

-1534

-1652

-1770

-1888

-2006

-2124

-2242

-2366

-2490

-2614

-2738

-2862

-2738

-2614

-2490

-2366

-2242

-2124

-2006

-1888

-1770

-1652

-1534

-1416

138 O92

139 O93

140 O94

141 O95

142 O96

143 O97

144 O98

145 O99

146 O100

147 O101

148 O102

149 O103

150 O104

-826

-708

-590

5–4

EPSON

Rev.1.4

S1D15300 Series

5. PIN DESCRIPTION

Power Supply

Name

V_DD

I/O

Description

+5V power supply. Connect to microprocessor power supply pin V_CC

Ground

Number of pins

Supply

.

2

1

V_SS

V1, V2

V3, V4

V5

LCD driver supply voltages. The voltage determined by LCD cell is

impedance-converted by a resistive driver or an operational amplifier

for application. Voltages should be the following relationship:

6

V

_DD≥ V1 ≥ V2 ≥ V3 ≥ V4 ≥ V5

When the on-chip operating power circuit is on, the following voltages

are given to V₁to V₄by the on-chip power circuit. Voltage selection is

performed by the Set LCD Bias command. (The S1D15303 and S1D15304

are fixed to 1/5 bias.)

S1D15300/S1D15305 S1D15301

S1D15302

V1

V2

V3

V4

1/5•V5 1/6•V5 1/6•V5 1/8•V5 1/6•V5 1/8•V5

2/5•V5 2/6•V5 2/6•V5 2/8•V5 2/6•V5 2/8•V5

3/5•V5 4/6•V5 4/6•V5 6/8•V5 4/6•V5 6/8•V5

4/5•V5 5/6•V5 5/6•V5 7/8•V5 5/6•V5 7/8•V5

S1D15303

S1D15304

V1

V2

V3

V4

1/5•V5

2/5•V5

3/5•V5

4/5•V5

1/5•V5

2/5•V5

3/5•V5

4/5•V5

LCD Driver Supplies

Name

CAP1+

CAP1–

CAP2+

CAP2–

CAP3–

V_OUT

I/O

Description

Number of pins

O

I/O

I

DC/DC voltage converter capacitor 1 positive connection

DC/DC voltage converter capacitor 1 negative connection

DC/DC voltage converter capacitor 2 positive connection

DC/DC voltage converter capacitor 2 negative connection

DC/DC voltage converter capacitor 1 negative connection

DC/DC voltage converter output

1

VR

Voltage adjustment pin. Applies voltage between V_DDand V5 using

a resistive divider.

Microprocessor Interface

Name

I/O

Description

Number of pins

D0 to D7

I/O

8-bit bi-directional data bus to be connected to the standard 8-bit or 16-bit

microprocessor data bus.

8

(SI)

(SCL)

When the serial interface selects;

D7: Serial data input (SI)

D6: Serial clock input (SCL)

A0

I

Control/display data flag input. It is connected to the LSB of micro-

processor address bus. When LOW, the data on D0 to D7 is control data.

When HIGH, the data on D0 to D7 is display data.

1

RES

When RES is caused to go LOW, initialization is executed.

A reset operation is performed at the RES signal level.

1

2

1

CS1

CS2

I

Chip select input. Data input/output is enabled when -CS1 is LOW and

CS2 is HIGH. When chip select is non-active, D0 to D7 will be "HZ".

RD

(E)

• When interfacing to an 8080 series microprocessor:

Active LOW. This input connects the RD signal of the 8080 series

microprocessor. While this signal is LOW, the S1D15300 series data

bus output is enabled.

• When interfacing to a 6800 series microprocessor:

Active HIGH. This is used as an enable clock input pin of the 6800 series

microprocessor.

Rev.1.4

EPSON

5–5

S1D15300 Series

Name

I/O

Description

Number of pins

WR

(R/W)

I

• Write enable input. When interfacing to an 8080-series microprocessor,

WR is active LOW.

1

• When interfacing to an 6800-series microprocessor,

it will be read mode when R/W is HIGH and it will be write mode when

R/W is LOW.

R/W = “1”:Read

R/W = “0”:Write

C86

P/S

I

Microprocessor interface select terminal.

C86 = HIGH: 6800 series microprocessor interface

C86 = LOW: 8080 series microprocessor interface

1

Serial data input/parallel data input select pin.

P/S Chip select Data/command Data Read/write Serial clock

HIGH CS1, CS2

LOW CS1, CS2

A0

D0-D7 RD, WR

—

SI(D7) Write only SCL(D6)

* In serial mode, no data can be read from RAM.

When P/S = LOW, D0 to D5 are HZ and RD and WR must be fixed HIGH

or LOW.

LCD Driver Outputs

Name

I/O

Description

Number of pins

M/S

I

S1D15300 series master/slave mode select input. When a necessary

signal is output to the LCD, the master operation is synchronized with

the LCD system, while when a necessary signal is input to the LCD,

the slave operation is synchronized with the LCD system.

M/S = HIGH: Master operation

1

M/S = LOW : Slave operation

The folLOWing is provided depending on the M/S status.

Power

supply

circuit

OSC

Model

Status

CL

FR

DYO

FRS DOF

circuit

Master Enabled Enabled Output Output Output Output Output

^S1D1530*^D****

Slave Disabled Disabled Input Input

HZ

Input

CL

FR

I/O

Display clock input/output. When the S1D15300 series selects master/

slave mode, each CL pin is connected. When it is used in

combination with the common driver, this input/output is connected to

common driver YSCL pin.

M/S = HIGH: Output

M/S = LOW: Input

1

LCD AC signal input/output. When the S1D15300 series selects master/

slave mode, each FR pin is connected.

When the S1D15300 series selects master mode this input/output is

connected to the common driver FR pin.

M/S = HIGH: Output

M/S = LOW: Input

DYO

Common drive signal output. This output is enabled for only at master

operation and connects to the common driver DIO pin. It becomes HZ

at slave operation.

VS1

O

Test pin. Don’t connect.

1

DOF

I/O

LCD blanking control input/output. When the S1D15300 series selects

master/slave mode, the respective DOF pin is connected. When it

is used in combination with the common driver (S1D16305), this output/

input is connected to the common driver DOFF pin.

M/S = HIGH: Output

M/S = LOW: Input

FRS

O

Static drive output.

This is enabled only at master operation and used together with the FR

pin. This output becomes HZ at slave operation.

1

5–6

EPSON

Rev.1.4

S1D15300 Series

Name

I/O

Description

Number of pins

On

(SEG n)

(Com n)

O

LCD drive output. The following assignment is made depending on

the model.

132

SEG

COM

O0~O99

O100~O131

^S1D15300D00**

^S1D15300D10**

^S1D15300D15**

^S1D15301D00**

^S1D15302D00**

^S1D15302D14**

^S1D15302D11**

^S1D15303D15**

^S1D15304D14**

^S1D15305D10**

O16~O115

O0~O131

O0~O99

O0~O15, O116~O131

O100~O131

O32~O131

O8~O123

O0~O123

O18~O115

O0~O31

O0~O7, O124~O131

O124~O131

O0~O17, O116~O131

SEG output. LCD segment drive output. One of VDD, V2, V3 and

V5 levels is selected by combination of the contents of display RAM

and FR signal.

On output voltage

Normal display Reverse display

RAM data

HIGH

FR

HIGH

LOW

HIGH

LOW

–

V_DD

V2

V5

V3

V2

V_DD

V5

0

V3

Power save

V_DD

COM output. LCD common drive output. One of VDD, V1, V4 and V5

levels is selected by combination of scan data and FR signal.

Scan data

HIGH

FR

On output voltage

HIGH

LOW

HIGH

LOW

V5

V_DD

V1

LOW

V4

Power save

–

V_DD

COMS

O

Indicator COM output. When it is not used, it is made open.

Effective only with the S1D15300, S1D15302, S1D15303 and S1D15304,

S1D15305 and “HZ” with the S1D15301.

1

When multiple numbers of the S1D15300, S1D15302, S1D15303 and

S1D15304, S1D15305 are used, the same COMS signal is output to both

master and slave units.

Total

172

Rev.1.4

EPSON

5–7

S1D15300 Series

6. FUNCTIONAL DESCRIPTION

Microprocessor Interface

Interface type selection

The S1D15300 series can transfer data via 8-bit bi-directional data buses (D7 to D0) or via serial data input (SI). When HIGHor LOW is selected

for the polarity of P/S pin, either 8-bit parallel data input or serial data input can be selected as shown in Table 1. When serial data input is selected,

RAM data cannot be read out.

Table 1

P/S

Type

CS1

CS2

A0

RD

WR

C86

D7

D6

D0 to D5

HIGH

LOW

Parallel input

Serial input

CS1

CS2

A0

RD

–

WR

–

C86

–

D7

SI

D6

SCL

D0 to D5

(HZ)

“–” must always be HIGH or LOW.

Parallel input

When the S1D15300 series selects parallel input (P/S = HIGH), the 8080 series microprocessor or 6800 series microprocessor can be selected

by causing the C86 pin to go HIGH or LOW as shown in Table 2.

Table 2

C86

Type

CS1

CS2

A0

RD

WR

D0 to D7

HIGH

6800 micro-

processor bus

8080 micro-

processor bus

CS1

CS2

A0

E

R/W

D0 to D7

LOW

CS1

CS2

A0

RD

RW

D0 to D7

Data Bus Signals

The S1D15300 series identifies the data bus signal according to A0, E, R/W, (RD, WR) signals.

Table 3

Common

6800 processor

8080 processor

Function

A0

1

(R/W)

RD

0

WR

1

0

1

0

Reads display data.

Writes display data.

Reads status.

1

0

1

0

1

0

Writes control data in internal register. (Command)

Serial Interface (P/S is low)

The serial interface consists of an 8-bit shift register and a 3-bit counter. The serial data input and serial clock input are enabled when CS1 is

low and CS2 is high (in chip select status). When chip is not selected, the shift register and counter are reset.

Serial data of D7, D6, ..., D0 is read at D7 in this sequence when serial clock (SCL) goes high. They are converted into 8-bit parallel data and

processed on rising edge of every eighth serial clock signal.

The serial data input (S1) is determined to be the display data when A0 is high, and it is control data when A0 is low. A0 is read on rising edge

of every eighth clock signal.

Figure 1 shows a timing chart of serial interface signals. The serial clock signal must be terminated correctly against termination reflection and

ambient noise. Operation checkout on the actual machine is recommended.

CS1

CS2

D7 D6 D5 D4 D3 D2 D1

D0 D7 D6 D5 D4 D3 D2 D1

SI

SCL

1

2

3

4

5

6

7

8

9

10

11 12

13 14

A0

Figure 1

5–8

EPSON

Rev.1.4

S1D15300 Series

Also, the microprocessor temporarily stores display data in bus

holder, and stores it in display RAM until the next data write cycle

starts.

Chip Select Inputs

The S1D15300 series has two chip select pins, CS1 and CS2 and can

interface to a microprocessor when CS1 is low and CS2 is high.

When these pins are set to any other combination, D0 to D7 are high

impedance and A0, RD and WR inputs are disabled.

When serial input interface is selected, the shift register and counter

are reset.

When viewed from the microprocessor, the S1D15300 series access

speed greatly depends on the cycle time rather than access time to the

display RAM (t_ACC). It shows the data transfer speed to/from the

microprocessor can increase. If the cycle time is inappropriate, the

microprocessor can insert the NOP instruction that is equivalent to

the wait cycle setup. However, there is a restriction in the display

RAM read sequence. When an address is set, the specified address

data is NOT output at the immediately following read instruction.

The address data is output during second data read. A single dummy

read must be inserted after address setup and after write cycle (refer

to Figure 2).

Access to Display Data RAM and Internal Registers

The S1D15300 series can perform a series of pipeline processing

between LSI’s using bus holder of internal data bus in order to match

the operating frequency of display RAM and internal registers with

the microprocessor. For example, the microprocessor reads data

from display RAM in the first read (dummy) cycle, stores it in bus

holder, and outputs it onto system bus in the next data read cycle.

•Write

WR

MPU

DATA

n

n+1

n+2

n+3

Latched

n

Bus holder

Write signal

n+1

n+2

n+3

Internal

timing

•Read

WR

RD

MPU

DATA

N

n

n+1

Address

preset

Read signal

Internal

timing

Preset

Incremented

N+1

Column

address

N

N+2

N

n

n+1

n+2

Bus holder

Set address n

Dummy read

Data Read address n

Data Read address n+1

Figure 2

COM0 (usually, the top line of screen) is determined using register

data. The register is also used for screen scrolling and page

switching.

Busy Flag

The Busy flag is set when the S1D15300 series starts to operate.

During operating, it accepts Read Status instruction only. The busy

flag signal is output at pin D7 when Read Status is issued. If the cycle

time (t_cyc) is correct, the microprocessor needs not to check the flag

before issuing a command. This can greatly improve the microproc-

essor performance.

The Set Display Start Line command sets the 6-bit display start

address in this register. The register data is preset on the line counter

each time FR signal status changes. The line counter is incremented

by CL signal and it generates a line address to allow 132-bit

Initial Display Line Register

When the display RAM data is read, the display line according to

Rev.1.4

EPSON

5–9

S1D15300 Series

RAM area dedicate to the indicator, and display data D0 is only

valid.

Column Address Counter

This is a 8 bit presettable counter that provides column address to the

display RAM (refer to Figure 4). It is incremented by 1 when a Read/

Write command is entered. However, the counter is not incremented

but locked if a non-existing address above 84H is specified. It is

unlocked when a column address is set again. The Column Address

counter is independent of Page Address register.

When ADC Select command is issued to display inverse display, the

column address decoder inverts the relationship between RAM

column address and display segment output.

Display Data RAM

The display data RAM stores pixel data for LCD. It is a 65-column

by 132-row (8-page by 8 bit+1) addressable array. Each pixel can

be selected when page and column addresses are specified.

The time required to transfer data is very short because the micro-

processor enters D0 to D7 corresponding to LCD common lines as

shown in Figure 3. Therefore, multiple S1D15300 can easily

configure a large display having the high flexibility with very few

data transmission restriction.

The microprocessor writes and reads data to/from the RAM through

I/O buffer. As LCD controller operates independently, data can be

written into RAM at the same time as data is being displayed,

without causing the LCD to flicker.

Page Address Register

This is a 4-bit page address register that provides page address to the

display RAM (refer to Figure 4). The microprocessor issues Set

Page Address command to change the page and access to another

page. Page address 8 (D3 is high, but D2, D1 and D0 are low) is

D0

D1

1

0

COM0

COM1

D2

D3

D4

1

0

COM2

COM3

COM4

Display data RAM

Display on LCD

Figure 3

5–10

EPSON

Rev.1.4

S1D15300 Series

Relationship between display data RAM and addresses (if initial display line is 1CH):

Line

address

00

01

02

03

04

05

06

07

08

09

0A

0B

0C

0D

0E

0F

10

11

12

13

14

15

16

17

18

COM

output

Page

Data

address

D0

COM 0

COM 1

COM 2

COM 3

COM 4

COM 5

COM 6

COM 7

COM 8

COM 9

COM10

COM11

COM12

COM13

COM14

COM15

COM16

COM17

COM18

COM19

COM20

COM21

COM22

COM23

COM24

COM25

COM26

COM27

COM28

COM29

COM30

COM31

COM32

COM33

COM34

COM35

COM36

COM37

COM38

COM39

COM40

COM41

COM42

COM43

COM44

COM45

COM46

COM47

COM48

COM49

COM50

COM51

COM52

COM53

COM54

COM55

COM56

COM57

COM58

COM59

COM60

COM61

COM62

COM63

COMS

D1

D2

D3, D2,

Page 0

D3

D4

D5

D6

D7

D0

D1

D2

D3

D4

D5

D6

D7

D0

D1

D2

D3

D4

D5

D6

D7

D0

D1

D2

D3

D4

D5

D6

D7

D0

D1

D2

D3

D4

D5

D6

D7

D0

D1

D2

D3

D4

D5

D6

D7

D0

D1

D2

D3

D4

D5

D6

D7

D0

D1

D2

D3

D4

D5

D6

D7

D0

D1,D0

0,0,0,0

Page 1

0,0,0,1

0,0,1,0

0,0,1,1

0,1,0,0

0,1,0,1

0,1,1,0

Page 2

1/64

19

1A

1B

1C

1D

1E

1F

Page 3

Start

20

21

22

23

24

25

26

27

28

29

2A

2B

2C

2D

2E

2F

30

31

32

33

34

35

36

37

38

39

3A

3B

3C

3D

3E

3F

Page 4

1/32

Page 5

Page 6

Page 7

Page 8

0,1,1,1

1,0,0,0

Page 8 is accessed during

1/65 or 1/33 duty.

Figure 4

Rev.1.4

EPSON

5–11

S1D15300 Series

Output Status Selector

The S1D15300 series except S1D15301 can set a COM output scan direction to reduce restrictions at LCD module assembly. This scan direction

is set by setting “1” or “0” in the output status register D3. Fig.5 shows the status.

Fig. 5 shows the status.

LCD output

O0

O131

83 (H)

0 (H)

ADC

"0"

"1"

0 (H)

83 (H)

Column address

Display data RAM

(D0)

D3

0

1

0

1

–

0

1

0

1

0

1

0

1

0

1

SEG100

COM0

COM31

COM0

✽✽

S1D15300D00

COM31

✽✽

S1D15300D10

S1D15300D15

S1D15301D00

S1D15302D00

S1D15302D14

COM15

0

SEG100

SEG132

COM16 31

COM15

0

SEG100

0

COM0

COM31

COM0

COM31

COM0

SEG100

✽✽

S1D15302D11

S1D15303D15

S1D15304D14

S1D15305D10

31

COM7

COM8

0

COM8

15

0

SEG116

SEG124

SEG98

15

COM7

COM0

COM7

7

0

COM18 33

COM17

0

SEG98

COM16 33

The COMS pin is assigned to COM32 on S1D15300 and it is assigned to COM64 on S1D15302 independent from their output status.

The COMS pin of the S1D15303 is assigned to COM16 the COMS pin of the S1D15304 is assigned to COM8 and the COMS pin of the S1D15305

is assigned to COM34.

^{Figure 5 shows the COM output pin numbers of S1D15302D00}** ^{and S1D15302D11}** ^{in the master mode. In the slave mode, COM0 to}

COM31 must be replaced by COM32 to COM63.

FR (master output)

64

0

1

2

30 31

64

0

1

2

30 31

Master Common

Slave Common

63 64

32 33 34

62 63 64

32

When the S1D15300 is operated in slave mode on the assumption of

multi-chip, the FR pin and CL pin become input pins.

Display Timing Generator

This section explains how the display timing generator circuit

operates.

Common timing signal generation

The display clock generates an internal common timing signal and

a start signal (DYO) to the common driver. A display clock resulting

from frequency division of an oscillation clock is output from the CL

pin.

When an AC signal (FR) is switched, a high pulse is output as a DYO

output at the training edge of the previous display clock.

Refer to Fig. 6. The DYO output is output only in master mode.

When the S1D15300 series is used for multi-chip, the slave requires

to receive the FR, CL, DOF signals from the master.

Table 4 shows the FR, CL, DYO and DOF status.

Table 4

Signal generation to line counter and display data latch

circuit

The display clock (CL) generates a clock to the line counter and a

latch signal to the display data latch circuit.

The line address of the display RAM is generated in synchronization

with the display clock. 132-bit display data is latched by the display

data latch circuit in synchronization with the display clock and

output to the segment LCD drive output pin.

The display data is read to the LCD drive circuit completely

independent of access to the display data RAM from the microproc-

essor.

Operation

Model

FR

Output Output Output Output

Input Input Hz Input

CL

DYO

DOF

mode

LCD AC signal (FR) generation

Master

^{S1D1530 D}****

The display clock generates an LCD AC signal (FR). The FR causes

the LCD drive circuit to generate a AC drive waveform.

It generates a 2-frame AC drive waveform.

*

Slave

HZ denotes a high-impedance status.

5–12

EPSON

Rev.1.4

S1D15300 Series

Example of S1D15300D00B 1/33 duty

*

•

Dual-frame AC driver waveforms

32 33

1

2

3

4

5

6

28 29 30 31 32 33

1

2

3

4

5

CL

FR

DYO

V

DD

V1

COM0

COM1

V4

V5

V

DD

V1

V4

V5

RAM data

SEGn

V

DD

V2

V3

V5

Fig. 6

The power circuit is controlled by Set Power Control command.

This command sets a three-bit data in Power Control register to

select one of eight power circuit functions. The external power

supply and part of internal power circuit functions can be used

simultaneously. The following explains how the Set Power

Control command works.

Display Data Latch Circuit.

This circuit temporarily stores (or latches) display data (during a

single common signal period) when it is output from display RAM

to LCD panel driver circuit. This latch is controlled by Display in

normal/in reverse Display ON/OFF and Static All-display on com-

mands. These commands do not alter the data.

[Control by Set Power Control command]

LCD Driver

This is a multiplexer circuit consisting of 133 segment outputs to

generate four-level LCD panel drive signals. The LCD panel drive

voltage is generated by a specific combination of display data, COM

scan signal, and FR signal. Figure 8 gives an example of SEG and

COM output waveforms.

D2 turns on when triple booster control bit goes high, and D2 turns

off when this bit goes low.

D1 turns on when voltage regulator control bit goes high, and D1

turns off when this bit goes low.

Oscillator Circuit

D0 turns on when voltage follower control bit goes high, and D0

turns off when this bit goes low.

This is an oscillator having a complete built-in type CR, and its

output is used as the display timing signal source or as the clock for

voltage booster circuit of the LCD power supply.

[Practical combination examples]

Status 1: To use only the internal power supply.

Status 2: To use only the voltage regulator and voltage follower.

Status 3: To use only the voltage follower. input the external

voltage as V5=Vout.

Status 4: To use only an external power supply because the internal

power supply does not operate.

The oscillator circuit is available in master mode only.

The oscillator signal is divided and output as display clock at CL pin.

Power Supply Circuit

The power supply circuit generates voltage to drive the LCD panel

at low power consumption, and is available in S1D15300 master

mode only. The power supply circuit consists of a voltage booster

voltage regulator, and LCD drive voltage follower.

The power supply circuit built in the S1D15300 series is set for a

small-scale LCD panel and is inappropriate to a large-pixel panel

and a large-display-capacity LCD panel using multiple chips. As the

large LCD panel has the dropped display quality due to a large load

capacity, it must use an external power source.

* The voltage booster terminals are CAP1+, CAP1-, CAP2+, CAP2-

and CAP3-.

* Combinations other than those shown in the above table are

possible but impractical.

Voltage

booster

Voltage

regulator

Voltage

follower

External voltage Voltage booster Voltage regulator

D2 D1 D0

input

terminal

1

2

3

4

1

0

1

0

1

0

ON

—

Used

OFF

V_OUT

V₅

OPEN

Used

OFF

ON

OPEN

OFF

V₁to V₅

Rev.1.4

EPSON

5–13

S1D15300 Series

For double boosting, remove only capacitor C1 between CAP2+ and

CAP2- from the connection of triple boosting operation, open

CAP+2 and jumper between CAP2- and VOUT (CAP3-). The

double boosted voltage appears at VOUT (CAP3-, CAP2-).

For quadruple boosting, set a VSS voltage range so that the voltage

at VOUT may not exceed the absolute maximum rating.

As the booster circuit uses signals from the oscillator circuit, the

oscillator circuit must operate.

Booster circuit

If capacitors C1 are inserted between CAP1+ and CAP1-, between

CAP2+ and CAP2-, CAP1+ and CAP3- and VSS and VOUT, the

potential between VDD and VSS is boosted to quadruple toward the

negative side and it is output at VOUT.

For triple boosting, remove only capacitor C1 between CAP+1 and

CAP3- from the connection of quadruple boosting operation and

jumper between CAP3- and VOUT. The triple boosted voltage

appears at VOUT (CAP3-).

Subsection 10.1.1 gives an external wiring example to use master

and slave chips when on-board power supply is active.

(V_CC=+5V) V_DD=0V

(GND) V_SS=-5V

V_DD=0V

V_SS=-5V

V_DD=0V

V_SS=-3V

V_OUT=2V_SS=-10V

V_OUT=3V_SS=-15V

V_OUT=3V_SS=-12V

Potential during double boosting

Potential during triple boosting

Potential during quadruple boosting

Voltage regulator circuit

The boosting voltage occurring at V_OUTis sent to the voltage regulator and the V₅liquid crystal display (LCD) driver voltage is output. This

V₅voltage can be determined by the following equation when resistors Ra and Rb (R1, R2 and R3) are adjusted within the range of |V5| < |V_OUT|.

1

Rb

Ra

To obtain V₅= -10 V, from equation

R2 + R3 = 2.92 × R1 .....................

∆R2 = R2, V_REG= –2.55V

1

:

V

5

=(1+

) VREG+IREF · Rb

3

R3+R2-∆R2

R1+∆R2

=(1+

) VREG

To obtain V₅= -6 V, from equation

:

4

1.35 × (R1 + R2) = R3 ..................

+IREF · (R3+R2-∆R2)

2

3

4

From equations

,

and

:

V

DD

R1=1.27MΩ

R2=0.85MΩ

R3=2.88MΩ

R1

V

REG

Ra

Rb

The voltage regulator circuit has a temperature gradient of

approximately -0.2%/°C as the V_REGvoltage. To obtain another

temperature gradient, use the Electronic Volume Control Function

for software processing using the MPU.

∆R2

+

-

5

R2

R3

VR IREF

As the V_Rpin has a high input impedance, the shielded and short

lines must be protected from a noise interference.

Voltage regulator using the Electronic Volume Control

Function

The Electronic Volume Control Function can adjust the intensity

(brightness level) of liquid crystal display (LCD) screen by command

control of V₅LCD driver voltage.

This function sets five-bit data in the electronic volume control

register, and the V₅LCD driver voltage can be one of 32-state

voltages.

To use the Electronic Volume Control Function, issue the Set Power

Control command to simultaneously operate both the voltage

regulator circuit and voltage follower circuit.

V

_REGis the constant voltage source of the IC, and in case of Type 1,

.

it is constant and V_REG=–2.55 V (if V_DDis 0 V), In case of Type 2,

V

variable resistor between V_R, V_DDand V₅as shown. A combination

of R1 and R3 constant resistors and R2 variable resistor is

recommended for fine-adjustment of V₅voltage.

.

_REG=V_SS(V_DDbasis). To adjust the V₅output voltage, insert a

Setup example of resistors R1, R2 and R3:

Also, when the boosting circuit is off, the voltage must be supplied

from V_OUTterminal.

When the Electronic Volume Control Function is used, the V₅

voltage can be expressed as follows:

When the Electronic Volume Control Function is OFF (electronic

volume control register values are (D4,D3,D2,D1,D0)=(0,0,0,0,0)):

( 1 + R3 + R2 – ∆R2)

1

V5 =

V_REG.......................

Rb

Ra

R1 + ∆R2

5

V₅= (1 +

) V_REG+ Rb × ∆I_REF........................

(As I_REF= 0 A)

• R1 + R2 + R3 = 5MΩ ................................

2

Variable voltage range

(Determined by the current passing between V_DDand V₅)

• Variable voltage range by R2 V₅= –6 to –10 V

(Determined by the LCD characteristics)

The increased V₅voltage is controlled by use of I_REFcurrent source

of the IC. (For 32 voltage levels, ∆I_REF= I_REF/31)

∆R2 = OΩ, V_REG= –2.55V

5–14

EPSON

Rev.1.4

S1D15300 Series

The minimum setup voltage of the V₅absolute value is determined

by the ratio of external Ra and Rb, and the increased voltage by the

Electronic Volume Control Function is determined by resistor Rb.

Therefore, the resistors must be set as follows:

S1D15300 Series V5

[V]

-10V

V5

1) Determine Rb resistor depending on the V₅variable voltage

range by use of the Electronic Volume Control.

V5 variable voltage range

(32 levels)

V₅variable voltage range

-5V

Rb =

I_REF

2) To obtain the minimum voltage of the V₅absolute value, determine

Ra using the Rb of Step 1) above.

(VDD) 0V

-20

0

20

Ta

40

60

Rb

V₅

V_REG

Ra =

[¡C]

{V₅= (1 + Rb/Ra) × V_REG}

–1

5

According to the V₅voltage and temperature change, equation can

be as follows (if V_DD= 0 V reference):

The S1D15300 series have the built-in V_REGreference voltage and

_REFcurrent source which are constant during voltage variation.

I

However, they may change due to the variation occurring in IC

manufacturing and due to the temperature change as shown below.

Consider such variation and temperature change, and set the Ra and

Rb appropriate to the LCD used.

Ta=–10°C

V₅max = (1+Rb/Ra) × V_REG

= (1+625k/462k) × (–2.55V)

× {1+(–0.2%/°C) × (–10°C–25°C)}

= –6.42V

(Ta=–10°C)

V

_REG= –2.55V±0.20V (Type1)

_REG= V_SS(V_DDbasis) (Type2) V_REG= –0.00%/˚C

V_REG= –0.2%/˚C

V₅min = V₅max + Rb × I_REF

(Ta=–10°C)

= –6.42V + 625k

I

_REF= –3.2µA±40% (For 16 levels) I_REF= 0.023µA/°C

–6.5µA±40% (For 32 levels) 0.052µA/°C

× {–6.5µA+(0.052µA/°C) × (–10°C–25°C)}

= –11.63V

Ra is a variable resistor that is used to correct the V₅voltage change

due to V_REGand I_REFvariation. Also, the contrast adjustment is

recommended for each IC chip.

Before adjusting the LCD screen contrast, set the electronic volume

control register values to (D4,D3,D2,D1,D0)=(1,0,0,0,0) or

(0,1,1,1,1) first.

Ta=–50°C

V₅max = (1+Rb/Ra) × V_REG

= (1+625k/462k) × (–2.55V)

× {1+(–0.2%/°C) × (50°C–25°C)}

= –5.7V

(Ta=50°C)

V₅min = V₅max + Rb × I_REF

(Ta=50°C)

When not using the Electronic Volume Control Function, set the

register values to (D4,D3,D2,D1,D0)=(0,0,0,0,0) by sending the

RES signal or the Set Electronic Volume Control Register command.

= –5.7V + 625k

× {–6.5µA+(0.052µA/°C) × (50°C–25°C)}

= –8.95V

Setup example of constants when Electronic Volume Control

Function is used:

The margin must also be determined in the same procedure given

above by considering the V_REGand I_REFvariation. This margin

calculation results show that the V₅center value is affected by the

V₅maximum voltage:

V₅minimum voltages:

V₅= –6 V (Electronic volume control

register values (D4,D3,D2,D1,D0) =

(0,0,0,0,0))

V₅= –10 V (Electronic volume control

register values (D4,D3,D2,D1,D0) =

(1,1,1,1,1))

V

_REGand I_REFvariation. The voltage setup width of the Electronic

Volume Control depends on the I_REFvariation. When the typical

value of 0.2 V/step is set, for example, the maximum variation range

of 0.12 to 0.28 V must be considered.

In case of Type 2, it so becomes that V_REG= V_SS(V_DDbasis) and

there is no temperature gradient. However, I_REFcarries the same

temperature characteristics as with Type 1.

V₅variable voltage range: 4 V

Variable voltage levels:

32 levels

1) Determining the Rb:

Command Sequence when Built-in Power Supply is Turned

OFF

V₅variable voltage range

4V

To turn off the built-in power supply, follow the command sequence

as shown below to turn it off after making the system into the standby

mode.

R3 =

=

| I_REF

|

6.5µA Rb = 625KΩ

2) Determining the Ra:

Static Indicator ON

Display OFF

Command ADh

Command AEh

Command A5h

Rb

Ra =

625kΩ

–6V

–2.55V

=

V₅max

V_REG

–1

Power Save

Command

Ra = 462KΩ

Entire Displays ON

Built-in Power OFF

Ta=25°C

V₅max = (1+Rb/Ra) × V_REG

= (1+625k/442k) × (–2.55V)

= –6.0V

V₅min = V₅max + Rb × I_REF

= –6V + 625k × (–6.5µA)

= –10.0V

Rev.1.4

EPSON

5–15

S1D15300 Series

Voltage generator circuit

1–1 Power set command

when the built-in power supply

is used (triple boosting)

1–2 when the on-chip power circuit is used 2 when VOUT is input from the outside

(D2, D1, D0) = (0, 1, 1)

(D2, D1, D0) = (1, 1, 1)

VDD

M/S

V

SS

V

SS

VSS

CL

CAP3-

CAP1+

CAP1-

CAP2+

CAP2-

CAP3-

CAP1+

CAP1-

CAP2+

CAP2-

CAP3-

CAP1+

CAP1-

CAP2+

CAP2-

C1

V

SS

VSS

V

SS

V

SS

VSS

C1

External

power

supply

C1

R3

V

OUT

V

OUT

V

OUT

R3

R1

R3

R1

V

5

V

5

V

5

S1D15300 series

R2

R

V

DD

V

DD

VDD

R1

V

DD

V

DD

V

DD

V1

V2

V3

V4

V5

V1

V2

V3

V4

V5

V

1

2

3

4

5

C2

3 when V5 is input from the outside

4 when the on-chip power circuit is used

(D2, D1, D0) = (0, 0, 1)

VDD

M/S

V

SS

VSS

CL

CAP3-

CAP1+

CAP1-

CAP2+

CAP2-

CAP3-

CAP1+

CAP1-

CAP2+

CAP2-

VSS

External

power

V

OUT

V

OUT

supply

V

5

V

5

S1D15300 series

R

V

DD

VDD

V

DD

V

DD

V

1

2

3

4

5

V

1

2

3

4

5

External

power

supply

C2

5–16

EPSON

Rev.1.4

S1D15300 Series

=

Reference setup value: S1D15300 V5

S1D15301 V5

-7 to -9 V

-11 to -13 V (variable)

Reset Circuit

S1D15302 V5

When the RES input goes low, this LSI is initialized.

Initialized status

SED1530

SED1531

SED1532

1.0~4.7 uF

0.47~1.0 uF

1 MΩ

C1

C2

R1

R2

R3

1.0~4.7 uF

1. Display OFF

2. Normal display

3. ADC select: Normal display (ADC command D0 =

low)

4. Read modify write OFF

5. Power control register (D2, D1, D0) = (0, 0, 0)

6. Register data clear in serial interface

7. LCD power supply bias ratio 1/6 (S1D15300), 1/8

(S1D15301, SE1D15302)

0.22~0.47 uF 0.47~1.0 uF

700 KΩ

200 KΩ

1 MΩ

200 KΩ

4 MΩ

200 KΩ

1.6 MΩ

4 MΩ

8. Static indicator: OFF

LCD

SIZE

16 × 50 mm

32 × 64 mm 32 × 100 mm

9. Display start line register set at line 1

10. Column address counter set at address 0

11. Page address register set at page 0

12. Output status register (D3) = (0)

13. Electronic control register set at 0

14. Test command OFF

DOT

CONFIGURATION

32 × 100

64 × 128

64 × 200

1: As the input impedance of VR is high, a noise protection using

short wire and cable shield is required.

As seen in 11. Microprocessor Interface (Reference Example),

connect the RES pin to the reset pin of the microprocessor and

initialize the microprocessor at the same time.

*2: C1 and C2 depend on the capacity of the LCD panel to be

driven. Set a value so that the LCD drive voltage may be stable.

In case the S1D15300 series does not use the internal LCD power

supply circuit, the RES must be low when the external LCD power

supply is turned on.

[Setup example]

Turn on the voltage regulator and voltage follower and give an

external voltage to VOUT. Display a horizontal-stripe LCD

heavy load pattern and determine C2 so that the LCD drive

voltage (V1 to V5) may be stable. However, the capacity value

of C2 must be all equal. Next, turn on all the on-board power

supplies and determine C1.

When RES goes low, each register is cleared and set to the above

initialized status. However, it has no effect on the oscillator circuit

and output pins (FR, CL, DYO, D0 to D7).

The initialization by RES pin signal is always required during

power-on. If the control signal from the MPU is HZ, an overcurrent

may flow through the IC. A protection is required to prevent the HZ

signal at the input pin during power-on.

*3: LCD SIZE means the length and breadth of the display portion

of the LCD panel.

Be sure to initialize it by RES pin when turning on the power supply.

When the reset command is used, only parameters 8 to 14 in the

above initialization are executed.

Model

LCD drive voltage

S1D15300

S1D15301

S1D15302

1/5 or 1/6 bias

1/6 or 1/8 bias

* Precautions when installing the COG

the resistance of ITO wiring is being inserted in series with the

switching transistor, thus dominating the boosting ability.

Consequently, the boosting ability will be hindered as a result

and pay sufficient attention to the wiring to respective boosting

capacitors.

When installing the COG, it is necessary to duly consider the fact

that there exists a resistance of the ITO wiring occurring between the

driver chip and the externally connected parts (such as capacitors

and resistors). By the influence of this resistance, non-conformity

may occur with the indications on the liquid crystal display.

Therefore, when installing the COG design the module paying

sufficient considerations to the following three points.

1. Suppress the resistance occurring between the driver chip pin to

the externally connected parts as much as possible.

2. Suppress the resistance connecting to the power supply pin of

the driver chip.

3. Make various COG module samples with different ITO sheet

resistance to select the module with the sheet resistance with

sufficient operation margin.

2. Connection of the smoothing capacitors for the liquid crystal

drive

The smoothing capacitors for the liquid crystal driving potentials

(V1. V2, V3 and V4) are indispensable for liquid crystal drives

not only for the purpose of mere stabilization of the voltage

levels. If the ITO wiring resistance which occurs pursuant to

installation of the COG is supplemented to these smoothing

capacitors, the liquid crystal driving potentials become unstable

to cause non-conformity with the indications of the liquid

crystal display. Therefore, when using the COG module, we

definitely recommend to connect reinforcing resistors externally.

Reference value of the resistance is 100kΩ to 1MΩ.

Meanwhile, because of the existence of these reinforcing

resistors, current consumption will increase.

Also, as for this driver IC, pay sufficient attention to the following

points when connecting to external parts for the characteristics of the

circuit.

1. Connection to the boosting capacitors The boosting capacitors

(the capacitors connecting to respective CAP pins and capacitor

being inserted between VOUT and VSS2) of this IC are being

switched over by use of the transistor with very low ON-

resistance of about 10Ω. However, when installing the COG,

Indicated below is an exemplary connection diagram of external

resistors.

Please make sufficient evaluation work for the display statuses with

any connection tests.

Rev.1.4

EPSON

5–17

S1D15300 Series

Exemplary connection diagram 1.

Exemplary connection diagram 2.

VDD

R4 R4

V1

V2

V3

V1

V2

V3

C2

R4

C2

R4

V4

V5

V4

V5

C2

R4 R4

C2

V

DD

COM 0

COM 1

COM 2

COM 3

COM 4

FR

V

SS

DD

V

1

2

3

4

COM 0

5

DD

COM 5

COM 6

COM 7

V

1

2

3

4

COM 1

COM 2

SEG 0

VD⁵D

V

1

2

3

4

5

COM 8

COM 9

COM 10

COM 11

COM 12

VDD

V

1

2

3

4

COM 13

COM 14

COM 15

5

DD

V1

V2

V3

V4

V5

SEG 1

S

E

G

0

S

E

G

2

S

E

G

3

S

E

G

4

E

G

1

V

4

3

2

1

COM -SEG 0

DD

-V

1

2

3

4

5

V

5

V

4

3

2

1

DD

COM -SEG 1

-V1

-V2

-V3

-V4

-V5

Figure 8

5–18

EPSON

Rev.1.4

S1D15300 Series

7. COMMANDS

E

R/W

A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0

The S1D15300 series uses a combination of A0, RD (E) and WR (R/

W) signals to identify data bus signals. As the chip analyzes and

executes each command using internal timing clock only regardless

of external clock, its processing speed is very high and its busy check

is usually not required. The 8080 series microprocessor interface

enters a read status when a low pulse is input to theRD pin and a write

status when a low pulse is input to the WR pin. The 6800 series

microprocessor interface enters a read status when a high pulse is

input to the R/W pin and a write status when a low pulse is input to

this pin. When a high pulse is input to the E pin, the command is

activated. (For timing, see Timing Characteristics.) Accordingly, in

the command explanation and command table, RD (E) becomes 1

(high) when the 6800 series microprocessor interface reads status or

display data. This is an only different point from the 8080 series

microprocessor interface.

0

1

0

1

0

1

A3 A2 A1 A0

A3

A2

A1

A0

Page Address

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

2

3

4

5

6

7

8

(4) Set Column Address

Specifies column address of display RAM. Divide the column

address into 4 higher bits and 4 lower bits. Set each of them

succession. When the microprocessor repeats to access to the

display RAM, the column address counter is incremented by 1

during each access until address 132 is accessed. The page

address is not changed during this time.

Taking the 8080 series microprocessor interface as an example,

commands will be explained below.

When the serial interface is selected, input data starting from D7 in

sequence.

(1) Display ON/OFF

E

R/W

Alternatively turns the display on and off.

A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0

E

R/W

Higher bits

Lower bits

0

1

0

1 A7 A6 A5 A4

0 A3 A2 A1 A0

A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0

0

1

0

1

0

1

0

1

D

The display turns off when D goes low, and it turns on when D

goes high.

A7 A6 A5 A4 A3 A2 A1 A0 Column address

0

1

0

1

:

(2) Start Display Line

Specifies line address (refer to Figure 4) to determine the initial

display line, or COM0. The RAM display data becomes the top

line of LCD screen. It is followed by the higher number of lines

in ascending order, corresponding to the duty cycle. When this

command changes the line address, the smooth scrolling or

page change takes place.

:

1

0

1

1 3 1

(5) Read Status

E

R/W

A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0

E

R/W

A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0

0

1

BUSY ADC ON/OFF RESET

0

1

0

1

A5 A4 A3 A2 A1 A0

BUSY: When high, the S1D15206 series is busy due to internal

operation or reset. Any command is rejected until BUSY

goes low. The busy check is not required if enough time

is provided for each cycle.

←

High-order bit

A5

A4

A3

A2

A1

A0

Line address

0

1

0

1

0

1

2

ADC:

Indicates the relationship between RAM column address

and segment drivers. When low, the display is normal and

column address “131-n” corresponds to segment driver n.

When high, the display is reversed and column address n

corresponds to segment driver n.

:

1

0

1

6 2

6 3

(3) Set Page Address

Specifies page address to load display RAM data to page

address register. Any RAM data bit can be accessed when its

page address and column address are specified. The display

remains unchanged even when the page address is changed.

Page address 8 is the display RAM area dedicate to the indica-

tor, and only D0 is valid for data change.

ON/OFF: Indicates whether the display is on or off. When goes low,

the display turns on. When goes high, the display turns

off. This is the opposite of Display ON/OFF command.

RESET: Indicates the initialization is in progress by RES signal

or by Reset command. When low, the display is on.

When high, the chip is being reset.

(6) Write Display Data

Writes 8-bit data in display RAM. As the column address is

incremented by 1 automatically after each write, the microproc-

essor can continue to write data of multiple words.

E

R/W

A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0

1

0

Write data

Rev.1.4

EPSON

5–19

S1D15300 Series

(7) Read Display Data

E

R/W

Reads 8-bit data from display RAM area specified by column

address and page address. As the column address is incremented

by 1 automatically after each write, the microprocessor can

continue to read data of multiple words. A single dummy read

is required immediately after column address setup. Refer to

the display RAM section of FUNCTIONAL DESCRIPTION

for details. Note that no display data can be read via the serial

interface.

A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0

0

1

0

1

0

1

0

1

D

The potential V5 is resistively divided inside the IC to produce

potentials V1, V2, V3 and V4 which are necessary to drive the LCD.

The bias ratio can be selected using the LCD bias setting command.

(The S1D15303 and S1D15304 are fixed to 1/5 bias.)

Moreover, the potentials V1, V2, V3 and V4 are converted in the

impedance and supplied to the LCD drive circuit.

A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0

1

0

1

Read data

Model

Bias ratio of LCD power supply

1/5 bias or 1/6 bias

S1D15300

S1D15301

S1D15302

S1D15303

S1D15304

(8) ADC Select

Changes the relationship between RAM column address and

segment driver. The order of segment driver output pins can be

reversed by software. This allows flexible IC layout during

LCD module assembly. For details, refer to the column address

section of Figure 4. When display data is written or read, the

column address is incremented by 1 as shown in Figure 4.

1/6 bias or 1/8 bias

1/5 bias

(12) Read-Modify-Write

E

R/W

A pair of Read-Modify-Write and End commands must always

be used. Once Read-Modify-Write is issued, column address is

not incremented by Read Display Data command but

incremented by Write Display Data command only. It contin-

ues until End command is issued. When the End is issued,

column address returns to the address when Read-Modify-

Write was issued. This can reduce the microprocessor load

when data of a specific display area is repeatedly changed

during cursor blinking or others.

A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0

0

1

0

1

0

1

0

D

When D is low, the right rotation (normal direction). When D

is high, the left rotation (reverse direction).

(9) Normal/Reverse Display

Reverses the Display ON/OFF status without rewriting the

contents of the display data RAM.

E

R/W

A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0

E

R/W

A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0

0

1

0

1

0

1

0

1

0

1

0

1

D

Note: Any command except Read/Write Display Data and Set

Column Address can be issued during Read-Modify-Write

mode.

When D is low, the RAM data is high, being LCD ON potential

(normal display).

When D is high, the RAM data is low, being LCD ON potential

(reverse display).

• Cursor display sequence

Set Page Address

(10) Entire Display ON

Forcibly turns the entire display on regardless of the contents of

the display data RAM. At this time, the contents of the display

data RAM are held.

Set Column Address

This command has priority over the Normal/Reverse Display

command. When D is low, the normal display status is pro-

vided.

Read-Modify-Write

Dummy Read

E

R/W

A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0

0

1

0

1

0

1

0

1

0

D

When D is high, the entire display ON status is provided.

If the Entire Display ON command is executed in the display

OFF status, the LCD panel enters Power Save mode. Refer to

the Power Save section for details.

Read Data

Write Data

(11) Set LCD Bias

Selects a bias ratio of the voltage required for driving the LCD.

No

Completed?

This command is enabled when the voltage follower in the

power supply circuit operates.

(The LCD bias setting command is invalid for the S1D15303

and S1D15304. They are being fixed to the 1/5 bias.)

Yes

End

5–20

EPSON

Rev.1.4

S1D15300 Series

(13) End

Cancels Read-Modify-Write mode and returns column address to the original address (when Read-Modify-Write was issued).

E

R/W

A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0

0

1

0

1

0

1

0

Return

Column address

N

N+1

N+2

N+3

N+m

N

Read-Modify-Write mode is selected.

End

(14) Reset

D4

D3

D2

D1

D0

| V5 |

LOW

Resets the Initial Display Line register, Column Address coun-

ter, Page Address register, and output status selector circuit to

their initial status. The Reset command does not affect on the

contents of display RAM. Refer to the Reset circuit section of

FUNCTIONAL DESCRIPTION.

0

:

0

1

0

1

0

↓

1

0

1

0

1

E

R/W

A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0

HIGH

0

1

0

1

0

1

0

Set register to (D4,D3,D2,D1,D0)=(0,0,0,0,0) to suppress elec-

tronic control function.

The Reset command cannot initialize LCD power supply. Only

the Reset siganl to the RES pin can initialize the supplies.

(18) Static Indicator

This command turns on or off static drive indicators. The

indicator display is controlled by this command only, and it is

not affected by the other display control commands.

Either FR or FRS terminal is connected to either of static

indicator LCD drive electrodes, and the remaining terminal is

connected to another electrode. When the indicator is turned

on, the static drive operates and the indicator blinks at an

interval of approximately one second. The pattern separation

between indicator electrodes are dynamic drive electrodes is

recommended. A closer pattern may cause an LCD and

electrode deterioration.

(15) Output Status Select Register

Applicable to the S1D15300 and S1D15302. When D is high

or low, the scan direction of the COM output pin is selectable.

Refer to Output Status Selector Circuit in Functional Descrip-

tion for details.

E

R/W

A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0

0

1

0

1

0

D

D: Selects the scan direction of COM output pin

* : Invalid bit

E

R/W

A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0

(16) Set Power Control

0

1

0

1

0

1

0

1

0

D

Selects one of eight power circuit functions using 3-bit register.

An external power supply and part of on-chip power circuit can

be used simultaneously. Refer to Power Supply Circuit section

of FUNCTIONAL DESCRIPTION for details.

D 0: Static indicator OFF

1: Static indicator ON

(19) Power Save (Compound Command)

E

R/W

When all displays are turned on during indicator off, the Power

Save command is issued to greatly reduce the current consump-

tion.

A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0

0

1

0

1

0

1

A2 A1 A0

If the static indicators are off, the Power Save command sleeps

the system. If on, this command stands by the system.

When A0 goes low, voltage follower turns off. When A0 goes

high, it turns on.

When A1 goes low, voltage regulator turns off. When A1 goes

high, it turns on.

When A2 goes low, voltage booster turns off. When A2 goes

high, it turns on.

Release the Sleep mode using the both Power Save OFF

command (Indicator ON command or All Indicator Displays

OFF command) and Static Indictor ON command.

Release the Standby mode using the Power Save OFF command

(Indicator ON command or All Indicator Displays OFF

command).

(17) Set Electronic Control

Adjusts the contrast of LCD panel display by changing V5 LCD

drive voltage that is output by voltage regulator of on-board

power supply.

Static OFF

Indicator ON

This command selects one of 32 V5 LCD drive voltages by

storing data in 5-bit register. The V5 voltage adjusting range

should be determined depending on the external resistance.

Refer to the Voltage Regulator section of FUNCTIONAL

DESCRIPTION for details.

Power Save (compound command)

(Sleep mode)

(Standby mode)

Power Save OFF (Display ON command or

Entire Displays OFF command)

R/W

A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0

0

1

0

1

0

A4 A3 A2 A1 A0

Static Indicator ON

(Sleeve mode released)

(Standby mode released)

Rev.1.4

EPSON

5–21

S1D15300 Series

Sleep mode

When an external power supply is used, likewise, the function

of this external power supply must be stopped so that it may be

fixed to floating or VDD level, prior to or concurrently with

causing the S1D15300 series to go to the sleep mode or standby

mode.

This mode stops every operation of the LCD display system,

and can reduce current consumption nearly to a static current

value if no access is made from the microprocessor. The

internal status in the sleep mode is as follows:

(1) Stops the oscillator circuit and LCD power supply circuit.

(2) Stops the LCD drive and outputs the VDD level as the

segment/common driver output.

(3) Holds the display data and operation mode provided before

the start of the sleep mode.

When the common driver S1D16305 or S1D16501 is combined

with the S1D15301 in the configuration, the DOF pin of the

S1D15301 must be connected to the DOFF pin of the S1D16305

or S1D16501.

(4) The MPU can access to the built-in display RAM.

(20) Test Command

This is the dedicate IC chip test command. It must not be used

for normal operation. If the Test command is issued errone-

ously, set the -RES input to low or issue the Reset command to

release the test mode.

Standby mode

Stops the operation of the duty LCD display system and turns

on only the static drive system to reduce current consumption

to the minimum level required for static drive.

The ON operation of the static drive system indicates that the

S1D15300 series is in the standby mode. The internal status in

the standby mode is as follows:

E

R/W

A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0

0

1

0

1

(1) Stops the LCD power supply circuit.

(2) Stops the LCD drive and outputs the VDD level as the

segment/common driver output. However, the static drive

system operates.

(3) Holds the display data and operation mode provided before

the start of the standby mode.

(4) The MPU can access to the built-in display RAM.

When the RESET command is issued in the standby mode,

the sleep mode is set.

* : Invalid bit

Cautions: The S1D15300 Series holds an operation status

specified by each command. However, the internal

operation status may be changed by a high level of

ambient noise. It must be considered to suppress the

noise on the its package and system or to prevent an

ambient noise insertion. To prevent a spike noise, a

built-in software for periodical status refreshment is

recommended to use.

When the LCD drive voltage level is given by an external

resistive driver, the current of this resistor must be cut so that it

may be fixed to floating or VDD level, prior to or concurrently

with causing the S1D15300 series to go to the sleep mode or

standby mode.

The test command can be inserted in an unexpected

place. Therefore, it is recommended to enter the test

mode reset command F0h during the refresh

sequence.

5–22

EPSON

Rev.1.4

S1D15300 Series

Code

Command

Function

A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0

(1) Display ON/OFF

0

1

0

1

0

1

0

1

0

1

0

1

Turns on LCD panel when goes

high, and turns off when goes low.

(2) Initial Display Line

(3) Set Page Address

0

Start display address

Specifies RAM display line for

COM0.

1

0

1

0

Page address

Sets the display RAM page in

Page Address register.

(4) Set Column Address

4 higher bits

0

Higher column

address

Sets 4 higher bits of column

address of display RAM in register

(4) Set Column Address

4 lower bits

0

Lower column

address

Sets 4 lower bits of column

address of display RAM in register

(5) Read Status

0

1

0

1

0

1

0

1

0

Status

0

Reads the status information.

Writes data in display RAM.

Reads data from display RAM.

(6) Write Display Data

(7) Read Display Data

(8) ADC Select

Write data

Read data

1

0

1

0

1

Sets normal relationship between

RAM column address and seg-

ment driver when low, but re-

verses the relationship when high.

(9) Normal/Reverse Display

(10) Entire Display ON/OFF

(11) Set LCD Bias

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Normal indication when low, but

full indication when high.

0

1

Selects normal display (0) or

Entire Display ON (1).

0

1

Sets LCD drive voltage bias ratio.

(12) Read-Modify-Write

0

Increments Column Address

counter during each write when

high and during each read when

low.

(13) End

0

1

0

1

0

1

0

1

0

*

1

*

0

*

Releases the Read-Modify-Write.

Resets internal functions.

(14) Reset

(15) Set Output Status

Register

0

1

Selects COM output scan

direction. * Invalid data

(16) Set Power Control

0

–

1

–

0

–

0

1

–

0

–

1

0

1

–

0

1

Operation

status

Selects the power circuit

operation mode.

(17) Set Electronic Control

Register

Electronic control value

Sets V5 output voltage to Elec-

tronic Control register.

(18) Set Standby

0

–

1

–

1

–

0

–

0

1

Selects standby status.

0: OFF 1: ON

(19) Power Save

–

Compound command of display

OFF and entire display ON

(20) Test Command

(21) Test Mode Reset

0

1

0

1

*

IC Test command. Do not use!

Command of test mode reset

0

Note: Do not use any other command, or the system malfunction may result.

Rev.1.4

EPSON

5–23

S1D15300 Series

8. COMMAND SETTING (For Refrence)

Instruction Setup Examples

Initial setup

Note: As power is turned on, this IC outputs non-LCD-drive potentials V2 – V6 from SEG terminal (generates output for driving the LCD)

and V1 – V4 from COM terminal (also used for generating the LCD drive output). If charge remains on the smoothing capacitor being

inserted between the above LCD driving terminals, the display screen can be blacked out momentarily. In order to avoid this trouble,

it is recommended to employ the following powering on procedure.

• When the built-in power is used immediately after the main power is turned on:

Turn on VDD and VSS power while maintaining

RES terminal at LOW.

Wait until the power supply is stabilized.

Cancel the reset mode (RES terminal = HIGH).

Turn on the initial setup mode (Default). *1

Function select through the commands (user setup).

LCD bias set *2

Operations ranging from powering on

through the power control set must be

completed within 5 ms.

ADC select *3

Common output mode select *4

Function select through the command (user setup).

Electronic volume *5

Function select through the command (user setup)

Power control set *6

Initial setup is complete

* This duration of 5 ms depends on the panel characteristics as well as capacity of the capacitor concerned.

Notes: *1: Refer to the “Reset Circuit” in the Function Description.

*2: Refer to the “LCD Bias Set” in the Command Description (11).

*3: Refer to the “ADC Select” in the Command Description (8).

*4: Refer to the “Output State Register Set” in the Command Description (15)

*5: Refer to the “Supply Circuit” in the Function Description and the “Electronic Volume Register Set” in the Command Description

(17).

*6: Refer to the “Supply Circuit” in the Function Description and the “Power Control Set” in the Command Description (16).

5–24

EPSON

Rev.1.4

S1D15300 Series

• When the built-in power supply is not used immediately after the main power is turned on:

Turn VDD and VSS power on with

RES terminal being set to LOW.

Wait until the power supply is stabilized.

Cancel the reset mode (RES terminal = HIGH)

The power save mode must be turned

on within 5 ms from powering on.

Turn on the initial setup mode (Default) *1

Turn on the power save mode (multiple commands) *7

Function select through the commands (user setup)

LCD bias set *2

ADC select *3

Common output mode select *4

Function select through the command (user setup)

Electronic volume *5

Turn off the power save mode *6

Operations ranging from turning off of

the power save mode through the

power control set must be completed

within 5 ms.

Function select through the command (user setup)

Power control set * 7

Initial setup is complete

* This duration of 5 ms depends on the panel characteristics as well as capacity of the capacitor concerned. Check them on the actual system.

Notes: *1: Refer to the “Reset Circuit” in the Function Description.

*2: Refer to the “LCD Bias Set” in the Command Description (11).

*3: Refer to the “ADC Select” in the Command Description (8).

*4: Refer to the “Output State Register Set” in the Command Description (15)

*5: Refer to the “Supply Circuit” in the Function Description and the “Electronic Volume Register Set” in the Command Description

(17).

*6: Refer to the “Supply Circuit” in the Function Description and the “Power Control Set” in the Command Description (16).

*7: You can select either the sleep mode or standby mode for the power save mode. Refer to the “Power Save (Multiple Commands)”

in the Command Description (19).

Rev.1.4

EPSON

5–25

S1D15300 Series

• Data Display

Initial setup is complete

Function select through the commands (user setup)

Display start line set *8

Page address set *9

Column address set *10

Function select through the command (user setup)

Display data write *11

Function select through the command (user setup)

Display ON/OFF *12

Data display is complete

Notes: *8: Refer to the “Display Line Set” in the Command Description (2).

*9: Refer to the “Page Address Set” in the Command Description (3).

*10:Refer to the “Column Address Set” in the Command Description (4).

*11:Refer to the “Display Data Write” in the Command Description (6).

*12:Refer to the “Display ON/OFF” in the Command Description (1). It is recommended to avoid the all-white-display of the display

start data.

• Powering Off *13

The time spent for the operations ranging from power

Any state

save through powering off (VDD – VSS = 2.4V) (tH)

must be longer than the time required for V5 to V1 go

under the LCD panel threshold voltage (normally 1V).

Function select through the command (user setup)

* tH is determined by time constant of the external

Power save *14

resisters Ra and Rb (for adjusting voltages V5 to V1)

and the smoothing capacitor C2.

* It is recommended to cut tH shorter by connecting a

Turn VDD and VSS power off

resistor between VDD and V5.

Notes: *13:This IC functions as the logic circuit of the power supplies VDD – VSS, and used for controlling the driver of LCD power supplies

VDD – V5. Thus, if power supplies VDD – VSS are turned off while voltage is still present on LCD power supplies VDD – V5, drivers

(COM and SEG) may output uncontrolled voltage. Therefore, you are required to observe the following powering off procedure:

Turn the built-in power supply off, then turn off the IC power supplies (VDD – VSS) only after making sure that potential of V5 –

V1 is below the LCD panel threshold voltage level. Refer to the “Supply Circuit” in the Function Description.

*14:When the power save command is entered, you must not implement reset from RES terminal until VDD – VSS power are turned off.

Refer to the “Power Save” in the Command Description.

• Refresh

It is recommended that the operating modes and display contents be refreshed periodically to prevent the effect of unexpected noise.

Refresh sequence

Cancel the test mode *15

Set every command according to the state being selected

(including setup of the default state).

Refresh the DDRAM.

Notes: *15:Refer to the “Test Mode Cancellation” in the Command Description (21).

5–26

EPSON

Rev.1.4

S1D15300 Series

9. ABSOLUTE MAXIMUM RATINGS

Parameter

Symbol

Rating

Unit

–0.3 to +7.0

–0.3 to +6.0

–0.3 to +4.5

–18.0 to +0.3

V₅to +0.3

Supply voltage range

Triple boosting

V_DD

V

Quadruple boosting

Supply voltage range (1) (V_DDLevel)

Supply voltage range (2) (V_DDLevel)

Input voltage range

V₅, V_OUT

V₁, V₂, V₃, V₄

V_IN

V

–0.3 to V_DD+0.3

–40 to +85

V

Output voltage range

V_O

V

Operating temperature range

T_OPR

°C

TCP

Storage temperature range

Bear chip

–55 to +100

–55 to +125

T_STR

°C

V

CC

V

DD

SS

VDD

GND

V

V₁to V₄

V₅, V_OUT

(System)

(S1D15300 series)

Notes: 1. V1 to V5, V_OUT, voltages are based on V_DD=0 V.

2. Voltages V_DD≥ V1 ≥ V2 ≥ V3 ≥ V4 ≥ V5 must always be satisfied.

3. If an LSI exceeds its absolute maximum rating, it may be damaged permanently. It is desirable to use it under electrical characteristics

conditions during general operation. Otherwise, an LSI malfunction or reduced LSI reliability may result.

Rev.1.4

EPSON

5–27

S1D15300 Series

10. ELECTRICAL CHARACTERISTICS

DC Characteristics

V_SS= 0 V, V_DD= 5 V ±10%, Ta = –40 to +85°C unless otherwise noted.

Item

Symbol

Condition

Min.

4.5

Typ.

5.0

–

Max.

5.5

Unit Pin used

Recommended

Operation

Power voltage (1)

V_DD

V

V_SS*1

Operational

2.4

6.0

Operating voltage

(2)

Operational

V₅

VDD level (V_DD= 0 V)

–16.0

0.4 × V₅

V₅

–

–4.5

V

V₅*2

Operational V₁, V₂

Operational V₃, V₄

–

V_DD

V₁, V₂

V₃, V₄

*3

–

0.6 × V₅

V_DD

HIGH-level input voltage

LOW-level input voltage

HIGH-level output voltage

LOW-level output voltage

HIGH-level input voltage

LOW-level input voltage

V_IHC

0.7 × V_DD

0.8 × V_DD

V_SS

–

V_DD= 2.7 V

–

V_DD

*3

V_ILC

–

0.3 × V_DD

0.2 × V_DD

V_DD

V

*3

V_DD= 2.7 V

V_SS

–

*3

V_OHC

V_OLC

V_IHS

V_ILS

I_OH= –1 mA

0.8 × V_DD

V_SS

–

*5

V_DD= 2.7 V, I_OH= –0.5 mA

I_OL= 1 mA

–

V_DD

*5

–

0.2 × V_DD

V_DD

*5

V_DD= 2.7 V, I_OL= 0.5 mA

V_SS

–

*5

0.85 × V_DD

0.8 × V_DD

V_SS

*4

–

V_DD= 2.7 V

V_DD

*4

0.15 × V_DD

0.2 × V_DD

1.0

*4

V_DD= 2.7 V

V_SS

*4

–

Input leakage current

Output leakage current

LCD driver ON resistance

I_LI

I_LO

VIN = V_DDor V_SS

–1.0

–

µA

kΩ

*6

–3.0

–

3.0

*7

SEG n

COM n

R_ON

Ta = 25°C

V₅= –14.0 V

V₅= –8.0 V

–

2.0

3.0

0.01

5.0

22

3.0

VDD level

–

4.5

*8

Static current consumption

I_SSQ

I_5Q

VIN = V_DDor V_SS

–

5.0

µA

V_SS

V₅

V₅= –18.0 V (V_DDlevel)

Ta = 25°C, f = 1 MHz

–

15.0

Input pin capacity

C_IN

–

8.0

pF

*3 *4

*9

Oscillation frequency

f_OSC

Ta = 25°C

V_DD= 5 V

18

26

kHz

V_DD= 2.7 V

18

22

26

Item

Symbol

Condition

Min.

2.4

Typ.

Max.

6.0

4.5

–

Unit Pin used

Input voltage

V_DD

Triple boosting

–

V

*10

Quadruple boosting

Triple voltage conversion (VDD level)

(VDD level)

2.4

Booster output voltage

Voltage regulator operation

voltage

V_OUT

–18.0

V

V_OUT

–6.0

Voltage follower operation

voltage

V5

(VDD level)

–18.0

–16.0

–

–6.0

–4.5

V

*11

Reference voltage

V_REG

Ta = 25°C (VDD level)

–2.75 –2.55 –2.35

For the mark *, refer to P. 1–25

5–28

EPSON

Rev.1.4

S1D15300 Series

Dynamic current consumption (1) when the built-in power supply is OFF

Ta = 25°C

Item

S1D15300/

S1D15305

S1D15301

Symbol

Condition

Min.

—

Typ.

24

22

40

36

39

32

20

Max.

40

Unit

Note

V_DD= 5.0V, V₅– V_DD= –8.0 V

V_DD= 3.0V, V₅– V_DD= –8.0 V

V_DD= 5.0V, V₅– V_DD= –11.0 V

V_DD= 3.0V, V₅– V_DD= –11.0 V

V_DD= 5.0V, V₅– V_DD= –11.0 V

V_DD= 3.0V, V₅– V_DD= –11.0 V

V_DD= 3.0V, V₅– V_DD= –5.0 V

—

35

—

65

I_DD

(1)

—

60

µA

*12

S1D15302

—

65

—

55

S1D15303

S1D15304

—

35

V

_DD= 3.0V, V₅– V_DD= –5.0 V

—

35

Dynamic current consumption (2) when the built-in power supply is ON

Ta = 25°C

Item

S1D15300/

S1D15305

S1D15301

Symbol

Condition

Min.

—

Typ.

41

Max.

70

Unit

Note

V_DD= 5.0V, V₅– V_DD= –8.0 V, dual boosting

V_DD= 3.0V, V₅– V_DD= –8.0 V, triple boosting

V_DD= 5.0V, V₅– V_DD= –11.0 V, triple boosting

V_DD= 3.0V, V₅– V_DD= –11.0 V, quadruple boosting

V_DD= 5.0V, V₅– V_DD= –11.0 V, triple boosting

V_DD= 3.0V, V₅– V_DD= –11.0 V, quadruple boosting

V_DD= 3.0V, V₅– V_DD= –5.0 V, dual boosting

—

48

80

—

96

160

190

160

190

50

I_DD

(1)

—

118

95

µA

*13

S1D15302

—

114

30

S1D15303

S1D15304

—

32

55

Current consumption during Power Save mode

V_SS= 0 V, V_DD= 2.7 to 5.5 V Ta=25°C

Item

Symbol

I_DDS1

Condition

Min.

—

Typ.

0.01

10

Max.

1

Unit

Note

During sleep

During standby

S1D15300, S1D15301, S1D15302

µA

I_DDS2

—

20

Typical current consumption characteristics (reference

data)

• Dynamic current consumption (1) when LCD external

power mode lamp is ON

80

(uA)

Condition: The built-in power supply is

OFF and an external power

supply is used.

S1D15300/S1D15305 V5-VDD=–8.0V

60

S1D15301 V5-VDD=–11.0V

S1D15302 V5-VDD=–11.0V

S1D15303 V5-VDD=–6.0V

S1D15304 V5-VDD=–6.0V

Ta=25°C

IDD (1)

(ISS+15)

S1D15301, S1D15302

S1D15300/S1D15305

40

Remarks: ✽12

20

0

S1D15303, S1D15304

1

2

3

4

5

6

7

(V)

VDD

Rev.1.4

EPSON

5–29

S1D15300 Series

•

Dynamic current consumption (2) when the LCD built-in

power circuit lamp is ON

200

(uA)

Condition: The built-in power circuit is ON.

S1D15300/S1D15305: V5-VDD=–8.0 V,

triple boosting

S1D15301: V5-VDD=–11.0 V,

quadruple boosting

S1D15302: V5-VDD=–11.0 V,

quadruple boosting

S1D15303: V5-VDD=–5.0 V,

dual boosting

150

IDD (1)

S1D15301, S1D15302

100

S1D15304: V5-VDD=–5.0 V,

dual boosting

Ta=25°C

S1D15300/S1D15305

50

S1D15303, S1D15304

Remarks: ✽13

0

1

2

3

4

5

6

7 (V)

VDD

*1 Though the wide range of operating voltages is guaranteed, a spike voltage change may affect the voltage assurance during access from

the microprocessor.

*2

V

_DDand V₅operating voltage range. (Refer to Fig. 10.)

The operating voltage range applies if an external power supply is used.

*3 A0, D0 - D5, D6, D7 (SI), RD (E), WR (R/W), CS1, CS2, FR, M/S, C86, P/S and DOF pins

*4 CL, SCL (D6) and RES pins

*5 D0 - D5, D6, D7 (SI), FR, FRS, DYO, DOF and CL pins

*6 A0, RD (E), WR (R/W), CS1, CS2, M/S, RES, C86 and P/S pins

*7 Applies when the D0 - D7, FR, CL, DYO and DOF pins are in high impedance,

*8 Resistance value when 0.1 V is applied between the output pin SEGn or COMn and each power supply pin (V1, V2, V3, V4).

This is specified in the operating voltage (2) range.

R ON = 0.1 V/∆I (∆I: Current flowing when 0.1 V is applied in the ON status.)

*9 For the relationship between oscillation frequency and frame frequency, refer to Fig. 9.

*10 For triple or quadruple boosting using the on-chip power useing the primary-side power supply V_DDmust be used within the input voltage

range.

*11 The voltage regulator adjusts V₅within the voltage follower operating voltage range.

*12, *13 Current that each IC unit consumes. It does not include the current of the LCD panel capacity, wiring capacity, etc.

This is current consumption under the conditions of display data = checker, display ON, S1D15300 = 1/33 duty (1/6 Bias), and S1D15301

and S1D15302 = 1/65 duty. (1/8 Bias)

*12 Applies to the case where the on-chip oscillator circuit is used and no access is made from the microprocessor.

*13 Applies to the case where the on-chip oscillator circuit and the on-chip power circuit are used and no access is made from the

microprocessor.

The current flowing through voltage regulation resistors (R1, R2 and R3) is not included.

The current consumption, when the on-chip voltage booster is used, is for the power supply V_DD

.

•

Relationship between oscillation frequency and frame frequency

The relationship between oscillation frequency f_OSCand LCD frame frequency, f_Fcan be obtained by the following expression.

Duty

1/33

f CL

f F

S1D15300

f OSC/8

f OSC/(8*33)

S1D15301

S1D15302

1/65

f OSC/4

f OSC/(4*65)

S1D15303

S1D15304

S1D15305

1/17

1/9

f OSC/8

f OSC/(8*17)

f OSC/(8*9)

f OSC/(8*35)

1/35

(f_Fdoes not indicate the FR signal cycle but the AC cycle.)

Fig. 9

Relationship between clock (f_CL) and frame frequency f_F

5–30

EPSON

Rev.1.4

S1D15300 Series

• V_SSand V₅operating voltage range

-20

-15

-10

-5

-16

-11

[V]

V5-VDD

Operating

range

2.4 3.5

0

2

4

6

8

VDD

[V]

Fig 10

• Current consumption at access IDD (2) - Microprocessor access cycle

This indicates current consumption when data is always

written on the checker pattern at fcyc. When no access

is made, only IDD (1) occurs.

10

[mA]

S1D15301,

1

S1D15302

I

DD (2)

S1D15300,

S1D15303,

S1D15304,

S1D15305

Condition: S1D15300/S1D15305 V5-VDD=-8.0V,

0.1

triple boosting

S1D15301 V

quadruple boosting

S1D15302 V -VDD=-11.0V,

quadruple boosting

5-VDD=-11.0V,

0.01

0

5

0.01

0.1

1

10

S1D15303 V

dual boosting

5-VDD=-6.0V,

fcyc [MHz]

S1D15304 V

dual boosting

Ta = 25¡C

5-VDD=-6.0V,

Fig. 11

Rev.1.4

EPSON

5–31

S1D15300 Series

AC Characteristics

(1) System buses

Read/write characteristics I (8080-series microprocessor)

A0

tAW8

tAH8

CS1

(CS2="1")

tCYC8

tCCLW

tCCLR

WR,RD

tCCHW

tCCHR

tDH8

tDS8

D0~D7

(WRITE)

tACC8

tCH8

D0~D7

(READ)

V_DD= 5.0 V ±10%, Ta = –40 to +85°C

Parameter

Signal

Symbol

Condition

Min.

Max.

Unit

Address hold time

Address setup time

A0

t_AHIGH8

t_AW8

10

–

ns

System cycle time

t_CYC8

166

–

ns

Control LOW pulse width(WR)

Control LOW pulse width(RD)

Control HIGH pulse width (WR)

Control HIGH pulse width (RD)

WR

RD

WR

RD

t_CCLOWW

t_CCLOWR

t_CCHIGHW

t_CCHIGHR

30

70

100

70

–

ns

Data setup time

Data hold time

t_DS8

t_DHIGH8

20

10

–

ns

RD access time

Output disable time

D0 to D7

t_ACC8

t_CHIGH8

CL=100pF

–

10

70

50

ns

V_DD= 2.7 V to 4.5 V, Ta = –40 to +85°C

Parameter

Signal

Symbol

Condition

Min.

Max.

Unit

Address hold time

Address setup time

A0

t_AH8

t_AW8

19

15

–

ns

System cycle time

t_CYC8

450

–

ns

Control LOW pulse width (WR)

Control LOW pulse width (RD)

Control HIGH pulse width (WR)

Control HIGH pulse width (RD)

WR

RD

WR

RD

t_CCLW

t_CCLR

t_CCHW

t_CCHR

60

140

200

140

–

ns

Data setup time

Data hold time

t_DS8

t_DH8

40

15

–

ns

RD access time

Output disable time

D0 to D7

t_ACC8

t_CH8

CL=100pF

–

10

140

100

ns

Notes: 1. The input signal rise/fall time (t_r, t_f) is specified at 15 ns or less.

When system cycle time is used at a high speed, it is specified by t_r+ t_f≤ (t_CYC8- t_CCLW) or

t_r+ t_f≤ (t_CYC8- t_CCLR- t_CCHR).

2. Every timing is specified on the basis of 20% and 80% of V_DD

.

3. t_EWHRand t_EWHWare specified by the overlap period in which CS1 is “0” (CS2 = “1”) and WR and RD are “0”.

4. When it is expected that Vss ranges from -2.4 V to -4.5 V during the operation, increase all the above specifications from -2.7 V to

-4.5 V by 30% before the operation.

5–32

EPSON

Rev.1.4

S1D15300 Series

(2) System buses

Read/write characteristics II (6800-series microprocessor)

A0

R/W

tAH6

tAW6

CS1

(CS2="1")

tCYC6

tEWHW tEWHR

tEWLW tEWLR

E

tDS6

tDH6

D0~D7

(WR1TE)

tACC6

tOH6

D0~D7

(READ)

V_DD= 5.0 V ±10%, Ta = –40 to +85°C

Parameter

Signal

Symbol

Condition

Min.

Max.

Unit

System cycle time

t_CYC6

166

–

ns

Address setup time

Address hold time

A0

W/R

t_AW6

t_AH6

10

–

ns

Data setup time

Data hold time

t_DS6

t_DH6

20

10

–

ns

D0 to D7

Output disable time

Access time

t_OH6

t_ACC6

CL=100pF

10

–

50

70

ns

Enable

READ

t_EWHR

t_EWHW

t_EWLR

t_EWLW

70

30

–

ns

E

LOW pulse width WRITE

Enable READ

70

HIGH pulse width WRITE

100

V_DD= 2.7 V to 4.5 V, Ta = –40 to +85°C

Parameter

Signal

Symbol

Condition

Min.

Max.

Unit

System cycle time

t_CYC6

450

–

ns

Address setup time

Address hold time

A0

R/W

t_AW6

t_AH6

15

19

–

ns

Data setup time

Data hold time

t_DS6

t_DH6

40

15

–

ns

D0 to D7

Output disable time

Access time

t_OH6

t_ACC6

CL=100pF

10

–

100

140

ns

Enable

LOW pulse width WRITE

Enable READ

HIGH pulse width WRITE

READ

t_EWHR

t_EWHW

t_EWLR

t_EWLW

140

60

–

ns

E

140

200

Notes: 1. The input rise/fall time (t_r, t_f) is specified at 15 ns or less. When the system cycle time is used at a high speed, it is specified by

t_r+ t_f≤ (t_CYC6- t_EWLW- t_EWHW) or tr + tf ≤ (t_CYC6- t _EWLR- t_EWHR).

2. Every timing is specified on the basis of 20% and 80% of V_DD

.

3. t_EWHRand t_EWHWare specified by the overlap period in which CS1 is “0” (CS2 = “1”) and E is “1”.

4. When it is expected that Vss ranges from -2.4 V to -4.5 V during the operation, increase all the above specifications from -2.7 V to

-4.5 V by 30% before the operation.

Rev.1.4

EPSON

5–33

S1D15300 Series

(3) Serial interface

tCSS

tCSH

CS1

(CS2="1")

tSAS

tSAH

A0

tSCYC

tSLW

SCL

SI

tSHW

tSDH

tf

tr

tSDS

V_DD= 5.0 V ±10%, Ta = –40 to +85°C

Parameter

Signal

Symbol

Condition

Min.

Max.

Unit

Serial clock cycle

Serial clock HIGH pulse width

Serial clock LOW pulse width

SCL

t_SCYC

t_SHW

t_SLW

250

100

75

–

ns

Address setup time

Address hold time

A0

SI

t_SAS

t_SAH

50

200

–

ns

Data setup time

Data hold time

t_SDS

t_SDH

50

–

ns

CS serial clock time

CS

t_CSS

t_CSH

30

100

–

ns

V_DD= 2.7 to 4.5V, Ta = –40 to +85°C

Parameter

Signal

Symbol

Condition

Min.

Max.

Unit

Serial clock cycle

Serial clock HIGH pulse width

Serial clock LOW pulse width

SCL

t_SCYC

t_SHW

t_SLW

500

200

150

–

ns

Address setup time

Address hold time

A0

SI

t_SAS

t_SAH

100

400

–

ns

Data setup time

Data hold time

t_SDS

t_SDH

100

–

ns

CS serial clock time

CS

t_CSS

t_CSH

60

200

–

ns

Notes: 1. The input signal rise and fall times must be within 15 nanoseconds.

2. All signal timings are limited based on 20% and 80% of V_DDvoltage.

3. When it is expected that Vss ranges from -2.4 V to -4.5 V during the operation, increase all the above specifications from -2.7 V to

-4.5 V by 30% before the operation.

5–34

EPSON

Rev.1.4

S1D15300 Series

(4) Display control timing

CL

(OUT)

t

DFR

FR

t

DOH

t

DOL

DYO

Output timing

V_DD= 5.0 V ±10%, Ta = –40 to +85°C

Parameter

Signal

FR

Symbol

t_DFR

Condition

Min.

Typ.

10

Max.

40

Unit

ns

FR delay time

CL = 50 pF

–

DYO HIGH delay time

DYO LOW delay time

DYO

t_DOH

40

100

ns

t_DOL

40

ns

Output timing

V_SS= 0 V, V_DD= 2.7 V to 4.5 V, Ta = –40 to +85°C

Parameter

Signal

FR

Symbol

t_DFR

Condition

Min.

Typ.

15

Max.

80

Unit

ns

FR delay time

CL = 50 pF

–

DYO HIGH delay time

DYO LOW delay time

DYO

t_DOH

70

200

ns

t_DOL

70

ns

Notes: 1. The otput timing is valid in master mode.

2. Every timing is specified on the basis of 20% and 80% of V_DD

.

(5) Reset timing

t RW

RES

t R

Internal circuit

status

During reset

End of reset

V_DD= 5.0 V ±10%, Ta = –40 to +85°C

Parameter

Signal

Symbol

t_R

Condition

Min.

0.5

Typ.

Max.

Unit

µs

Reset time

–

Reset LOW pulse width

RES

t_RW

0.5

µs

V

_DD= 2.7 V to 4.5 V, Ta = –40 to +85°C

Parameter

Reset time

Signal

Symbol

t_R

Min.

1.0

Typ.

Max.

Unit

µs

–

Reset LOW pulse width

RES

t_RW

1.0

µs

Note: The reset timing is specified on the basis of 20% and 80% of VDD.

Rev.1.4

EPSON

5–35

S1D15300 Series

11. MPU INTERFACE (For Reference)

The S1D15300 series chips can directly connect to 8080 and 6800-series microprocessors. Also, serial interfacing requires less signal lines

between them. When multiple chips are used in the S1D15300 series they can be connected to the microprocessor and one of them can be selected

by Chip Select.

8080-series microprocessors

VDD

VCC

VDD

A0

C86

A1 to A7

IORQ

CS1

CS2

Decoder

V

SS

DD

S1D15300

MPU

D0 to D7

RD

D0 to D7

RD

WR

P/S

WR

VSS

RES

GND

RESET

VSS

6800-series microprocessors

V

DD

V

DD

V

CC

VDD

A0

C86

CS1

CS2

A1 to A15

VMA

Decoder

S1D15300

MPU

D0 to D7

E

D0 to D7

E

R/W

P/S

R/W

VSS

RES

GND

RESET

V

SS

Serial interface

VDD

VCC

A0

C86

CS1

CS2

A1 to A7

Decoder

RESET

V

DD

S1D15300

MPU

or GND

Port 1

Port 2

SI

SCL

P/S

RES

GND

V

SS

V

SS

5–36

EPSON

Rev.1.4

S1D15300 Series

12. CONNECTION BETWEEN LCD DRIVERS

The LCD panel display area can easily be expanded by use of multiple S1D15300 series chips. The S1D15300 series can also be connected to

the common driver (S1D16305).

S1D15301 to S1D16305 (S1D16305)

VDD

S11D16305

DIO

S1D15301

(master)

FR

M/S

DOFF

YSCL

DOF

CL

DYO

DOF

S1D15300 to S1D15301

VDD

S1D15300

(master)

S1D15300

(slave)

M/S

FR

M/S

VSS

CL

DYO

CL

DYO

DOF

S1D15302 to S1D15302

VDD

S1D15302

(master)

S1D15302

(slave)

M/S

FR

M/S

VSS

CL

DYO

CL

DYO

DOF

Rev.1.4

EPSON

5–37

S1D15300 Series

S1D15300 : 100×33dot

SEG (100)

S1D15300D00A

S1D15300D10A

*

COM (33)

COM (17)

COM (16)

COM(65)

S1D16700

132×65 dot

DOFF DIO YSCL FR

SEG(132)

VDD

FR

CL

M/S

S1D15301

DYO

DOF

S1D15302 : 200×65 dot

SEG(100)

S1D15302

S1D15302

<Slave>

COM(33)

VDD

COM(32)

FR

DOF

FR

DOF

M/S

CL

M/S

5–38

EPSON

Rev.1.4

S1D15300 Series

Dimensional outline drawing of the flexible substrate

(an example) The dimensions are subject to change without prior notice.

( M o l d , m a r k i n g a r e a )

Rev.1.4

EPSON

5–39


型号：	S1D15300D15A
厂家：	SEIKO EPSON CORPORATION
描述：	Interface Circuit
文件：	总41页 (文件大小：325K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

S1D15300D15A [SEIKO]

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