S1D15B01T00_技术文档

13. S1D15B01 Series

Rev. 1.1a

Contents

1. DESCRIPTION ..............................................................................................................................................13-1

2. FEATURES....................................................................................................................................................13-1

3. BLOCK DIAGRAM.........................................................................................................................................13-2

4. PIN LAYOUT .................................................................................................................................................13-3

5. PIN DESCRIPTION .......................................................................................................................................13-6

6. FUNCTIONAL DESCRIPTION ......................................................................................................................13-8

7. COMMAND DESCRIPTION ........................................................................................................................13-24

8. COMMAND SETTING .................................................................................................................................13-32

9. ABSOLUTE MAXIMUM RATING.................................................................................................................13-36

10. ELECTRICAL CHARACTERISTICS............................................................................................................13-37

11. THE MPU INTERFACE (REFERENCE EXAMPLES) .................................................................................13-53

12. CAUTION.....................................................................................................................................................13-54

– i –

Rev. 1.1a

S1D15B01 Series

1. DESCRIPTION

2. FEATURES

The S1D15B01 series is a single-chip liquid crystal

display (=LCD) driver for dot-matrix LCDs that can be

connected directly to a microprocessor (=MPU) bus. It

accepts 8-bit parallel or serial display data from a MPU,

stores it in an on-chip display data RAM (=DDRAM),

and generates a LCD drive signal independent of the

MPU clock.

The use of the on-chip DDRAM of 65×132 bits and a

one-to-one correspondence between LCD panel pixel

dots and on-chip DDRAM bits offer high flexibility in

graphic display.

• Direct display by DDRAM :

Bit data of DDRAM “0” .... a dot of display is OFF

“1” .... a dot of display is ON

(at Display normal)

• DDRAM capacity : 65×132=8580bits

• High-speed 8-bit Serial interface/8-bit MPU interface

(The chip can be connected directly to both the 8080-

series MPUs and the 6800-series MPUs) .

• Many command functions :

Display ON/OFF, Display normal/reverse, Display

all points ON/OFF,

The S1D15B01 series does not need external operation

clock for DDRAM read/write operations, and has a on-

chip LCD power supply circuit featuring very low

current consumption with few external components,

and moreover has a on-chip CR oscillator circuit.

Consequently, the S1D15B01 can be realize a high-

performance handy display system with a minimum

current consumption and the fewest components.

Page address set, Column address set, Display start

line address set,

Segment/Common driver direction select,

Display data Read/Write ,Read modify write,

Power control set, Electronic contrast control, LCD

bias set,

Power saver, Reset

• On-chip low power supply circuit for LCD driving

voltage generation

Booster circuit (with boost ratios of Double/Triple/

Quadruple/Quintuple)

Voltage regulator circuit (with high-accuracy

electronic voltage adjustment function)

Voltage follower (with V1 to V4 voltage dividing

resistors)

• On-chip CR oscillation circuit (external clock can

also be input.)

• Very low power consumption

• Power supply :

Logic power supply : VDD-VSS=1.7 to 5.5V

Booster reference supply : VDD2-VSS=1.7 to 5.5V

LCD driving power supply : V0-VSS=4.5 to 16.0V

• Wide range of operating temperatures -40 to 85°C

• CMOS process

• Package : Au bump chip and TCP

• These ICs are not designed for strong radio/optical

activity proof.

Series Specifications

Product Name Duty

Bias

SEG Dr

COM Dr

VREG

Voltage

Shipping Forms

Temperature

Gradient

Condition

S1D15B01D00B 1/65 1/9,1/7

132

65

–0.05%/˚C

Internal voltage

V0 or VOUT

Bare Chip

*

*S1D15B01D01B

1/65 1/9,1/7

Bare Chip

external voltage

*

*S1D15B01D02B

132

65

–0.05%/˚C

V0 ~ V4 extarnal

Bare Chip

voltage

*

^*S1D15B01T00**

TCP

* : Start the development on demands

** : Under development

Rev. 1.1a

EPSON

13–1

S1D15B01 Series

3. BLOCK DIAGRAM

• • • • • • • • • • • • • • • • • • • • • • • • •

• • • • • • • • • •

VDD

V

0

1

2

3

4

V

SEG Drivers

COM Drivers

Shift register

VSS

Display data latch circuit

CAP1+

CAP1–

CAP2+

CAP2–

CAP3+

CAP4+

Display data RAM

132 x 65

V

DD2

VOUT

VR

Column address

CL

Bus holder

Command decoder

Status

MPU

Interface

13–2

EPSON

Rev. 1.1a

S1D15B01 Series

4. PIN LAYOUT

73

1

74

282

y

D15B1D^0B

Die No.

x

(0, 0)

Alignment mark 1

Alignment mark 2

246

247

110

111

Chip size

10.82mm×2.81mm

70µm (Min.)

Bump pitch

Bump size

PAD No.1 to 73

91µm× 91µm

91µm×45.5µm

45.5µm× 91µm

91µm×45.5µm

PAD No.74 to 110

PAD No.111 to 246

PAD No.247 to 282

Bump height

Chip thickness

Ground bias

17µm (Typ.)

625µm

VSS

Alignment mark 1 Center coordinates (µm)

Size (µm)

(–4965, –1231)

31 70

Alignment mark 2 Center coordinates (µm)

Size (µm)

(4947, –1224)

81

Rev. 1.1a

EPSON

13–3

S1D15B01 Series

Pad Center Coordinates

Unit: µm

PAD

No.

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

100

Name

TEST13 –1882 1248

PAD

No.

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

129

130

131

132

133

134

135

136

137

138

139

140

141

142

143

144

145

146

147

148

149

150

Name

COM6 –5255 –631

PAD

No.

1

2

3

4

5

6

7

Name

(NC)

TEST0 4592

TEST1 4462

TEST2 4332

X

Y

X

Y

X

Y

4852 1248

4722

VSS

VR

V0

V1

V2

V3

V4

–2051

–2181

–2311

–2441

–2571

–2701

–2831

COM5

COM4

COM3

COM2

COM1

COM0

COMS

(NC)

–701

–771

–842

–912

–982

–1052

–1122

–1193

–1263

VSS

4202

TEST3 4072

TEST4 3942

TEST5 3812

RES

CS

VSS

WR

RD

VDD

CL

8

9

CAP2+ –2961

CAP2+ –3091

CAP2– –3221

CAP2– –3351

CAP4+ –3481

CAP4– –3611

VOUT –3741

CAP1+ –3871

CAP1+ –4001

CAP1– –4131

CAP1– –4261

CAP3+ –4391

CAP3+ –4521

(NC) –4651

(NC) –4781

(NC) –5255 1264

(NC)

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

3682

3552

3422

3292

3162

3032

2902

2772

2642

(NC) –4738 –1248

(NC) –4668

SEG0 –4598

SEG1 –4528

SEG2 –4458

SEG3 –4388

SEG4 –4317

SEG5 –4247

SEG6 –4177

SEG7 –4107

SEG8 –4037

SEG9 –3966

SEG10 –3896

SEG11 –3826

SEG12 –3756

SEG13 –3686

SEG14 –3615

SEG15 –3545

SEG16 –3475

SEG17 –3405

SEG18 –3335

SEG19 –3264

SEG20 –3194

SEG21 –3124

SEG22 –3054

SEG23 –2984

SEG24 –2913

SEG25 –2843

SEG26 –2773

SEG27 –2703

SEG28 –2633

SEG29 –2562

SEG30 –2492

SEG31 –2422

SEG32 –2352

SEG33 –2282

SEG34 –2211

SEG35 –2141

SEG36 –2071

SEG37 –2001

A0

D7,SI

D6,SCL 2512

D5

D4

D3

D2

D1

2382

2252

2122

1992

1862

1732

1602

1472

1342

1212

1082

952

822

692

562

432

302

172

3

D0

(NC)

1194

1124

1054

984

913

843

774

703

633

562

492

422

352

282

211

141

71

COM31

COM30

COM29

COM28

COM27

COM26

COM25

COM24

COM23

COM22

COM21

COM20

COM19

COM18

COM17

COM16

COM15

COM14

COM13

COM12

COM11

COM10

COM9

VDD

VDD2

TEST6

VDD

P/S

C86

VSS

TEST7

TEST8

TEST9 –166

VSS

–335

–465

–595

–725

–855

–985

–1115

–1245

VSS

1

(NC)

VOUT

(NC)

TEST10 –1414

TEST11 –1583

TEST12 –1713

–69

–140

–210

–280

–350

–420

–491

–561

COM8

COM7

13–4

EPSON

Rev. 1.1a

S1D15B01 Series

Unit: µm

PAD

No.

Name

PAD

No.

Name

PAD

No.

Name

X

Y

X

Y

X

Y

151

152

153

154

155

156

157

158

159

160

161

162

163

164

165

166

167

168

169

170

171

172

173

174

175

176

177

178

179

180

181

182

183

184

185

186

187

188

189

190

191

192

193

194

195

196

197

198

199

200

SEG38 –1931 –1248

SEG39 –1860

SEG40 –1790

SEG41 –1720

SEG42 –1650

SEG43 –1580

SEG44 –1509

SEG45 –1439

SEG46 –1369

SEG47 –1299

SEG48 –1229

SEG49 –1158

SEG50 –1088

SEG51 –1018

SEG52 –948

SEG53 –878

SEG54 –807

SEG55 –737

SEG56 –667

SEG57 –597

SEG58 –527

SEG59 –456

SEG60 –386

SEG61 –316

SEG62 –246

SEG63 –176

SEG64 –105

201

202

203

204

205

206

207

208

209

210

211

212

SEG88 1579 –1248

SEG89 1650

SEG90 1720

SEG91 1790

SEG92 1860

SEG93 1930

SEG94 2001

SEG95 2071

SEG96 2141

SEG97 2211

SEG98 2281

SEG99 2352

251

252

253

254

255

256

257

258

259

260

261

262

263

264

265

266

267

268

369

270

271

272

273

274

275

276

277

278

279

280

281

282

COM35 5248 –944

COM36

COM37

COM38

COM39

COM40

COM41

COM42

COM43

COM44

COM45

COM46

COM47

COM48

COM49

COM50

COM51

COM52

COM53

COM54

COM55

COM56

COM57

COM58

COM59

COM60

COM61

COM62

COM63

COMS

–874

–804

–734

–664

–593

–523

–453

–383

–313

–242

–172

–102

–32

38

109

179

249

319

389

460

530

600

670

740

811

881

951

1021

1091

1162

1232

213 SEG100 2422

214 SEG101 2492

215 SEG102 2562

216 SEG103 2632

217 SEG104 2703

218 SEG105 2773

219 SEG106 2843

220 SEG107 2913

221 SEG108 2983

222 SEG109 3054

223 SEG110 3124

224 SEG111 3194

225 SEG112 3264

226 SEG113 3334

227 SEG114 3405

228 SEG115 3475

229 SEG116 3545

230 SEG117 3615

231 SEG118 3685

232 SEG119 3756

233 SEG120 3826

234 SEG121 3896

235 SEG122 3966

236 SEG123 4036

237 SEG124 4107

238 SEG125 4177

239 SEG126 4247

240 SEG127 4317

241 SEG128 4387

242 SEG129 4458

243 SEG130 4528

244 SEG131 4598

SEG65

SEG66

SEG67

SEG68

SEG69

SEG70

SEG71

SEG72

SEG73

SEG74

SEG75

SEG76

SEG77

SEG78

SEG79

–35

35

105

175

246

316

386

456

526

597

667

737

807

877

948

(NC)

SEG80 1018

SEG81 1088

SEG82 1158

SEG83 1228

SEG84 1299

SEG85 1369

SEG86 1439

SEG87 1509

245

246

247

248

249

250

(NC)

COM32

COM33

COM34

4668

4738

5248 –1225

–1155

–1085

–1015

Rev. 1.1a

EPSON

13–5

S1D15B01 Series

5. PIN DESCRIPTION

Power supply pins

Number of

pins

Name

I/O

Description

VDD

Supply Power supply. Connect to MPU power pin VCC.

Supply Externally-input reference power supply for booster circuit.

Supply This is a 0V terminal connected to the system GND.

5

3

7

5

VDD2

VSS

V0, V1, V2 Supply Multi-level power supply for LCD drive. The voltages are

V3, V4

determined by LCD cell.The voltages should maintain the following

relationship : V0 ≥ V1 ≥ V2 ≥ V3 ≥ V4 ≥ VSS.

When on-chip power supply circuit turns on, V0 voltage are

generated, and the following voltages are generated to V1 to V4.

Either voltage can be selected by LCD bias set command.

SED15B1

V1

V2

V3

V4

6/7 • V0, 8/9 • V0

5/7 • V0, 7/9 • V0

2/7 • V0, 2/9 • V0

1/7 • V0, 1/9 • V0

LCD power supply circuit pins

Number of

pins

Name

I/O

Description

CAP1+

CAP1–

CAP2+

CAP2–

CAP3+

CAP4+

VOUT

O

I

Boosting capacitor positive connection pin.

Boosting capacitor negative connection pin.

Boosting capacitor positive connection pin.

Boosting capacitor negative connection pin.

Boosting capacitor positive connection pin.

Booster output.

2

4

1

VR

Voltage adjustment pin. Provides V0 voltage using external resistors.

When internal resistors are used, this pin cannot be used.

System bus connection pins

Number of

pins

Name

I/O

Description

D7 to D0

I/O

8-bit bi-directional data bus to be connected to the standard 8-bit or

16-bit MPU data bus.

8

(SI)

(SCL)

When the serial interface is selected (P/S=LOW) ;

D7 : Serial data input (SI)

D6 : Serial clock input (SCL)

A0

I

Control/data flag input.

A0=HIGH : The data on D7 to D0 is display data.

A0=LOW : The data on D7 to D0 is control data.

1

CS

I

Chip select input. Data input is enable when CS is low.

1

When RES is caused to go low, initialization is executed.

A reset operation is performed at the RES signal level.

RES

13–6

EPSON

Rev. 1.1a

S1D15B01 Series

Number of

pins

Pin name

I/O

Description

RD

(E)

I

• When connected to an 8080-series MPU ;

1

This is active-LOW. This pin is connected to the RD signal of the

8080-series MPU. While this signal is low, SED15B1 series data

bus is an output status.

• When connected to an 6800-series MPU ;

This is active-HIGH. This is used as an enable clock input pin of the

6800-series MPU.

WR

(R/W)

I

• When connected to an 8080-series MPU ;

This is active-LOW. This pin is connected to the WR signal of the

8080-series MPU. The signals on the data bus are latched at the

rising edge of the WR signal.

1

•When connected to an 6800-series MPU ;

This is the read/write control signal input .

R/W=HIGH : Read.

R/W=LOW : Write.

C86

P/S

I

MPU interface selection pin.

1

C86=HIGH : 6800-series MPU interface

C86=LOW : 8080-series MPU interface

Serial data input/parallel data input selection pin.

P/S=HIGH : Parallel data input

P/S=LOW : Serial data input

The following applies depending on the P/S status :

P/S Data/Command

Data

Read/Write Serial Clock

RD, WR

HIGH

LOW

A0

D7 to D0

SI (D7)

Write only

SCL (D6)

In serial mode, no data can be read from DDRAM.

When P/S=LOW,D5 to D0 are HZ. D5 to D0 may be HIGH, LOW or

Open, and moreover A0, RD, WR, C86 may be HIGH, LOW or

Open.

LCD driver pins

Number of

pins

Name

CL

I/O

Description

I

External clock input. When external clock is halted, CL must be LOW.

If internal clock (on-chip CR oscillation circuit) is selected, CL

connected to VDD.

1

SEG0 to

SEG131

O

LCD segment driver output.

132

64

2

COM0 to

COM63

LCD common driver output.

COMS

LCD common driver output for the indicator. When it is not used,

it is made open.

Test pins

Name

Number of

pins

I/O

Description

TEST0 to

TEST13

I/O

These are terminals for IC chip testing.

TEST1 to TEST4 are recommended to connect to VDD or VSS.The others set to open.

14

Note and caution

• If control signal from MPU is HZ, an over-current may flow through the IC. A protection is required to prevent

the HZ signal at the input pins.

Rev. 1.1a

EPSON

13–7

S1D15B01 Series

6. FUNCTIONAL DESCRIPTION

Microprocessor Interface

Interface type selection

or LOW, it is possible to select either 8-bit parallel data

input or 8-bit serial data input as shown in Table 1.

The S1D15B01 series can transfer data via 8-bit bi-

directional data buses (D7 to D0) or via serial data input

(SI). Through selecting the P/S pin polarity to the HIGH

Table 1

P/S

CS

A0 RD WR C86 D7

D6

D5 to D0

–

HIGH:Parallel Input

LOW:Serial Input

A0 RD WR C86 D7

D6

A0

–

SI SCL

– : HIGH, LOW or Open

Parallel interface

8080-series MPU or a 6800-series MPU (as shown in

Table 2) by selecting C86 pin to either HIGH or LOW.

When the parallel interface has been selected (P/S=

HIGH), then it is possible to connect directly to either an

Table 2

C86

CS

A0

RD

E

WR

R/W

WR

D7 to D0

HIGH:6800-series MPU bus

LOW:8080-series MPU bus

RD

Moreover, the S1D15B01 series identifies the data bus

signal according to A0, RD(E), WR(R/W) signals, as

shown in Table 3.

Table 3

Common

6800-series

8080-series

Function

A0

1

R/W

RD

0

WR

1

0

Reads the display data

Writes the display data

1

0

1

0

Writes control data (command)

Serial interface

When the serial interface has been selected (P/S=

LOW),only writing display data and control data is

possible by four input signals. The serial data input (SI)

and serial clock input (SCL) are enabled when CS is

low. When chip is not selected, the shift register and

counter which compose serial interface are reset.

The serial data is read from the serial data input pin in

the rising edge of the serial clocks D7,D6 through D0,

in this order. This data is converted to 8 bits parallel data

in the rising edge of the eighth serial clock for the

processing.

The A0 input is used to determine whether the serial

data input is display data or command data; when

A0=HIGH, the data is display data, and when A0=LOW

then the data is command data. The A0 input is read and

used for detection every 8th rising edge of the serial

clock after the chip becomes active.

Figure 1 is a serial interface signal chart.

13–8

EPSON

Rev. 1.1a

S1D15B01 Series

CS

SI

D7

1

D6

2

D5

3

D4

4

D3

5

D2

6

D1

7

D0 D7

D6

10

D5

D4

D3

13

D2

14

SCL

8

9

11

12

A0

Figure 1

* When the chip is not active, the shift registers and the counter are reset to their states.

* Reading is not possible while in serial interface mode.

* Caution is required on the SCL signal when it comes to line-end reflections and external noise.

We recommend that operation be rechecked on the actual equipment.

In order to realize the higher speed accessing, the

S1D15B01 series can perform a type of pipeline

processing between LSIs using bus holder of internal

data bus when data is sent from/to the MPU. For

example, when the MPU writes data to the DDRAM,

once the data is stored in the bus holder, then it is written

to the DDRAM before the next data write cycle. And

when the MPU reads the contents of the DDRAM, the

first data read cycle (dummy read cycle) stores the read

data in the bus holder, and then the data is read from the

bus holder to the system bus at the next data read cycle.

Thus, there is a certain restriction in the DDRAM read

sequence. When an address is set, the specified address

data is NOT output at the immediately following read

instruction. The address data is output during second

data read. A single dummy read must be inserted after

address setup and after write cycle (refer to Figure 2).

Chip select input

The MPU interface (either parallel or serial) is enabled

only when CS=LOW.

When the chip select is inactive, D7 to D0 enter a high

impedance state, and A0, RD and WR inputs are disabled.

When the serial interface is selected, the shift register

and the counter are reset.

Access to DDRAM and internal registers

In accessing the DDRAM and the internal registers of

the S1D15B01 series, the MPU is required to satisfy the

only cycle time (tCYC), and is not needed to consider the

wait time. Accordingly, it is possible to transfer data at

higher speed.

Write

WR

DATA

N

N+1

N+2

N+3

Latch

N

N+1

N+2

N+3

BUS Holder

Write Signal

Read

WR

RD

DATA

N

n

n+1

Address Preset

Read Signal

Column Address

Bus Holder

Preset N

N

Increment N+1

n

N+2

n+1

n+2

Address Set

#n

Dummy

Read

Data Read

#n

Data Read

#n+1

Figure 2

Rev. 1.1a

EPSON

13–9

S1D15B01 Series

DDRAM and page/column address circuit

As is shown in Figure 3, the D7 to D0 display data from

the MPU corresponds to the LCD common direction.

The DDRAM stores pixel data for LCD. It is a 65-row

(8 page by 8 bit + 1) by 132-column addressable array.

D0 0 1 1 1

D1 1 0 0 0

D2 0 0 0 0

D3 0 1 1 1

D4 1 0 0 0

—

0

COM0

COM1

COM2

COM3

COM4

—

DDRAM

Display on LCD

Figure 3

Each pixel can be selected when page address and

column address are specified(refer to Figure 5).

The MPU issues Page address set command to change

the page and access to another page. Page address 8

(D3,D2,D1,D0 = 1,0,0,0) is DDRAM area dedicate to

the indicator, and display data D0 is only valid.

automatically incremented by +1 when a Display data

read/write command is entered. After the last column

address (83H), column address returns to 00H and page

address incremented by +1 (refer to Figure 4). After the

very last address (column = 83H,page = 8H),both column

address and page address return to 00H (column address

= 00H, page address = 0H).

The DDRAM column address is specified by Column

address set command. The specified column address is

Data

D0

D1

D2

D3

D4

D5

0H

0

1

2

130

262

394

526

658

790

922

1054

1186

82H

131

263

395

527

659

791

923

1055

1187

83H

D6

D7

1H 132 133 134

2H 264 265 266

Page address 3H 396 397 398

4H 528 529 530

5H 660 661 662

6H 792 793 794

7H 924 925 926

8H 1056 1057 1058

00H 01H 02H

Column address

D0

Data for the page address 8H

Figure 4

The MPU reads from and writes to the DDRAM through

the I/O buffer independent of the LCD controller

operation. Therefore, data can be written to the DDRAM

at the same time as data is being displayed, without

causing the LCD to flicker.

Furthermore, as is shown in Table 4, Segment driver

direction select command can be used to reverse the

relationship between the DDRAM column address and

segment output. This allows flexible IC layout during

LCD module assembly.

13–10

EPSON

Rev. 1.1a

S1D15B01 Series

82H 83H

Table 4

Column Address

00H

01H

02H

81H

Normal Direction

Reverse Direction

SEG0

SEG1

SEG2

SEG129 SEG130 SEG131

SEG2 SEG1 SEG0

SEG131 SEG130 SEG129

Line address circuit

common driver direction is normal, or the COM63

output when common driver direction is reversed.And

the display area is followed by the higher number line

addresses in ascending order from the display start line

address, corresponding to the duty cycle. This allows

flexible IC layout during LCD module assembly.

If the display start line address is changed dynamically

using the Display start line address set command,then

screen scrolling and page swapping can be performed.

The line address circuit specifies the line address (as

shown Figure 5) relating to the COM output when the

contents of the DDRAM are displayed. The display start

line address, what is normally the top line of the display,

can be specified by Display start line address set

command. And Common driver direction select

command can be used to reverse the relationship between

the DDRAM line address and common output. For

example, as is shown in Table 5, the display start line

address corresponds to the COM0 output when the

Table 5 (at display start line address=1CH)

Line Address

Normal Direction

Reverse Direction

1CH

1DH

3FH

00H

1AH

1BH

COM0

COM1

COM35 COM36

COM28 COM27

COM62

COM1

COM63

COM0

COM63 COM62

Display data latch circuit

The display data latch circuit is a latch temporarily

stored the display data that is output to the LCD driver

circuit from the DDRAM.

command, and Displayed all points ON/OFF command

control only the data within the latch, and do not change

the data within the DDRAM.

Display ON/OFF command, Display normal/reverse

Rev. 1.1a

EPSON

13–11

S1D15B01 Series

Display Data RAM

The display data RAM stores pixel data for the LCD.

It is a 132-colunm×65-row addressale array as shown in Figure 5.

COM Output

Normal Reverse

Direction Direction

Page Address

Data

Line

Address

D3

0

D2

0

D1

0

D0

0

D0

D1

D2

D3

D4

D5

D6

D7

D0

D1

D2

D3

D4

D5

D6

D7

D0

D1

D2

D3

D4

D5

D6

D7

D0

D1

D2

D3

D4

D5

D6

D7

D0

D1

D2

D3

D4

D5

D6

D7

D0

D1

D2

D3

D4

D5

D6

D7

D0

D1

D2

D3

D4

D5

D6

D7

D0

D1

D2

D3

D4

D5

D6

D7

D0

00H

01H

02H

03H

04H

05H

06H

07H

08H

09H

0AH

0BH

0CH

0DH

0EH

0FH

10H

11H

12H

13H

14H

15H

16H

17H

18H

19H

1AH

1BH

1CH

1DH

1EH

1FH

20H

21H

22H

23H

24H

25H

26H

27H

28H

29H

2AH

2BH

2CH

2DH

2EH

2FH

30H

31H

32H

33H

34H

35H

36H

37H

38H

39H

3AH

3BH

3CH

3DH

3EH

3FH

COM0 COM63

COM1 COM62

COM2 COM61

COM3 COM60

COM4 COM59

COM5 COM58

COM6 COM57

COM7 COM56

COM8 COM55

COM9 COM54

COM10 COM53

COM11 COM52

COM12 COM51

COM13 COM50

COM14 COM49

COM15 COM48

COM16 COM47

COM17 COM46

COM18 COM45

COM19 COM44

COM20 COM43

COM21 COM42

COM22 COM41

COM23 COM40

COM24 COM39

COM25 COM38

COM26 COM37

COM27 COM36

COM28 COM35

COM29 COM34

COM30 COM33

COM31 COM32

COM32 COM31

COM33 COM30

COM34 COM29

COM35 COM28

COM36 COM27

COM37 COM26

COM38 COM25

COM39 COM24

COM40 COM23

COM41 COM22

COM42 COM21

COM43 COM20

COM44 COM19

COM45 COM18

COM46 COM17

COM47 COM16

COM48 COM15

COM49 COM14

COM50 COM13

COM51 COM12

COM52 COM11

COM53 COM10

COM54 COM9

COM55 COM8

COM56 COM7

COM57 COM6

COM58 COM5

COM59 COM4

COM60 COM3

COM61 COM2

COM62 COM1

COM63 COM0

COMS COMS

Page 0

Page 1

Page 2

0

1

0

1

0

1

0

Page 3

Page 4

Start

0

1

0

1

0

Page 5

Page 6

0

1

0

1

0

1

0

Page 7

Page 8

Column Address

00H 01H 02H 03H 04H 05H 06H

7DH 7EH 7FH 80H 81H 82H 83H

Regardless of the display start

line address, S1D15B01

accesses 65th line.

Normal Direction

Reverse Direction

SEG

Output

Figure 5

13–12

EPSON

Rev. 1.1a

S1D15B01 Series

and the display data latch circuit. The display data is

latched to the display data latch circuit and is output to

the segment drive output pin by synchronizing to the

display clocks. The read operation of display data to the

liquid crystal drive circuit is completely independent of

the access to the display data RAM from MPU. Therefore

even when the display data RAM is asynchronously

accessed during liquid crystal display, the access will

not have any adverse effect on the display such as

flickering.

Oscillation circuit

The S1D15B01 series has a complete on-chip CR

oscillation circuit, and its output is used as the display

timing signal source.

The on-chip oscillation circuit is available when CL =

HIGH.

And the S1D15B01 series is also capable external clock

input from CL pin. (When external clock is halted, CL

must be LOW.)

The circuit also generates COM scan signal and the

LCD AC signal (FR) from the display clocks. As shown

in Figure 6, the FR normally generates the 2- frame AC

drive waveforms .

Display timing generator circuit

The display timing generator circuit generates the timing

signals from the display clocks to the line address circuit

2-frame AC drive waveforms

64 65

1

2

3

4

5

6

60 61 62 63 64 65

1

2

3

4

5

6

CL

FR

V

0

1

COM0

V

4

SS

V

0

1

COM1

V

4

SS

RAM

DATA

V

0

2

SEGn

3

SS

Figure 6

Rev. 1.1a

EPSON

13–13

S1D15B01 Series

LCD driver circuits

These are multiplexers outputting the LCD panel driving

4-level signal which level is determined by a combination

of display data, COM scan signal, and LCD AC signal

(FR). Figure 7 shows an example of SEG and COM

output waveforms.

COM0

V

DD

SS

FR

COM1

COM2

COM3

COM4

V

0

1

2

COM5

COM6

COM7

COM0

COM1

COM2

V

3

4

SS

V0

V1

V2

COM8

V

3

4

SS

COM9

COM10

COM11

COM12

COM13

COM14

COM15

V0

V1

V2

V

3

4

SS

V0

V1

V2

SEG0

SEG1

SEG2

V

3

4

SS

V0

V1

V2

V

3

4

SS

V0

V1

V2

V

3

4

SS

V5

V4

V3

V

2

COM0—SEG0

1

DD

—V

1

2

—V

3

4

5

V5

V4

V3

V

—V

2

COM0—SEG1

1

DD

1

2

3

4

5

Figure 7

13–14

EPSON

Rev. 1.1a

S1D15B01 Series

Power supply circuit

The power supply circuit generates the voltage to drive

the LCD panel at low power consumption.

S1D15B01D00B which use a booster circuit, voltage

*

regulator circuit, and voltage follower circuit, every

circuit is required to be turnend ON or OFF at the same

time by Power control set command. In the case of

using S1D15B01D00B /S1D15B01D02B which need

The power supply circuit consists of a booster circuit,

voltage regulator circuit, and voltage follower circuit,

and is controlled by Power control set command. Using

this command, the booster circuit, the voltage regulator

circuit, and the voltage follower circuit can be

independently turned ON or OFF. In the case of using

*

the external power supply and use part of on-chip power

supply circuit, each must be set the appropriate state as

shown in the Table 6.

Table 6

Power supply

condition

Product name*²Booster Voltage Voltage

circuit regulator follower

External

voltage

input

Boosting

system pin*³

circuit

On-chip power

supply used

S1D15B01D00B

S1D15B01D01B

ON

VDD2

Used

Open

*

Voltage regulator

circuit and Voltage

follower circuit only

OFF

ON

VOUT

Voltage follower

circuit only

S1D15B01D01B

S1D15B01D02B

OFF

ON

V0=VOUT*⁴

Open

*

External power

supply only

OFF

V0=VOUT*⁴

V1 to V4

*

*1 Combinations other than those shown in above table are possible but impractical.

*2 Chose the appropriate product according to the power supply condition.

*3 The boosting system pin indicates the CAP+, CAP1–, CAP2+, CAP2–, CAP3+, and CAP4+ pin.

*4 Both V0 pin and VOUT pin should be connected to external power supply.

Booster circuit

Using the booster circuit, it is possible to produce

Quintuple/Quadruple/Triple/Double boosting of the

VDD2-VSS voltage level.

boosted to quadruple toward the positive side and it is

output at VOUT pin.

Triple boosting :

Quintuple boosting :

Connect capacitor between CAP1+ and CAP1–, between

CAP2+ and CAP2–, between VOUT and VDD2, and

jumper between CAP3+, CAP4+ and VOUT, the triple

boosted voltage appears at VOUT pin.

Connect capacitor between CAP1+ and CAP1–, between

CAP2+ and CAP2–, between CAP3+ and CAP1–,

between CAP4+ and CAP2–, between VOUT and VDD2,

the potential between VDD2 and VSS is boosted to

quintuple toward the positive side and it is output at

VOUT pin.

Double boosting :

Connect capacitor between CAP1+ and CAP1–, between

VOUT and VDD2, open CAP2–, and jumper between

CAP2+, CAP3+, CAP4+ and VOUT, the double boosted

voltage appears at VOUT pin.

Quadruple boosting :

Connect capacitor between CAP1+ and CAP1–, between

CAP2+ and CAP2–, between CAP3+ and CAP1–,

between VOUT and VDD2, and jumper between CAP4+

and VOUT, the potential between VDD2 and VSS is

The boosted voltage relationships are shown in Figure

8.

Rev. 1.1a

EPSON

13–15

S1D15B01 Series

V

DD2 or VSS

OUT

V

DD2 or VSS

OUT

V

DD2 or VSS

OUT

V

DD2 or VSS

OUT

+

V

CAP3+

CAP1–

CAP3+

CAP1–

CAP3+

CAP1–

CAP3+

CAP1–

+

CAP1+

CAP4+

+

CAP1+

CAP4+

CAP2–

CAP4+

CAP2–

CAP4+

CAP2–

CAP2+

OPEN

+

CAP2+

Quintuple Boosting

Quadruple Boosting

Triple Boosting

Double boosting

V

OUT = 5 x VDD2

= 13.5V

V

OUT = 4 x VDD2

= 10.8V

V

OUT = 3 x VDD2

= 8.1V

VOUT = 2 x VDD2

= 5.4V

V

DD2 = 2.7V

V

DD2 = 2.7V

SS = 0V

V

DD2 = 2.7V

SS = 0V

V

DD2 = 2.7V

VSS = 0V

V

VSS = 0V

Quintuple Boosting

Quadruple Boosting

Triple Boosting

Double boosting

Figure 8

* VDD2 voltage must be set so that VOUT voltage does not exceed the absolute maximum rated value.

* The Capacitance depend on the load of the LCD panel to be driven. Set a value that LCD driver voltage may be stable

(reference value = 1.0 to 4.7 µF).

Voltage regulator circuit

The boosting voltage occurring at the VOUT pin is sent

to the voltage regulator, and the V0 voltage (LCD driver

voltage) is output.

Because the S1D15B01 series has the high-accuracy

constant voltage source, the 32-level electronic volume

function and the internal resistor for the V0 voltage

regulator (= V0-resistor), it is possible to construct a

high-accuracy voltage regulator circuit without external

component. And V0 voltage can be adjusted by

commands only to adjust the LCD contrast.

equations within the range of V0 < VOUT.

V0 = (1+Rb/Ra)•VEV

VEV = (1–α /200) •VREG (Equation A-1)

VREG is the on-chip constant voltage as shown in Table

7 at Ta=25°C.

Table 7

Model

VREG Thermal Gradient

1.3V –0.05%/°C

(A) When the V0-resistor is used.

^S1D15B01*****

Through the use of the V0-resistor and the electronic

volume function, V0 voltage can be controlled by

commands only (without adding any external resistors).

The V0 voltage can be calculated using the following

13–16

EPSON

Rev. 1.1a

S1D15B01 Series

Internal Rb

Internal Ra

–

+

V

0

V

EV (Constant voltage source

+ electronic volume)

VSS

Figure 9

α is a value of the electronic volume, and can be set to

one of 32-states by Electronic volume command setting

the 5-bit data in the electronic volume register. Table 8

shows the value of α.

Rb/Ra is the V0-resistor ratio, and can be set to one of

7-states by V0-resistor ratio set command setting the 3-

bit data in the V0-resistor ratio register. Table 9 shows

the value of (1+Rb/Ra) ratio (reference value).

Table 8

Table 9

1+Rb/Ra

D4

D3

D2

D1

D0

α

D3 D2 D1

S1D15B01

0

:

0

1

0

1

0

31

30

29

:

2

0

1

0

1

0

1

0

1

0

1

0

1

0

1

5.60

5.86

6.15

6.46

6.81

7.20

7.64

:

1

0

1

0

1

0

External resistor can be used.

Figure 10 shows V0 voltage measured by V0-resistor ratio and electronic voltage at Ta=25°C.

V

0

- resister ratio

11

10

9

110

101

100

011

010

001

000

8

7

6

5

4

3

2

1

0

Electronic volume resister

Figure 10

Rev. 1.1a

EPSON

13–17

S1D15B01 Series

When selection Ta=25°C and V0=7V for S1D15B01 series on which temperature gradient=–0.05%/°C. Using Figure

10 and equation A-1, the following setup is enabled.

Table 10

Commands

Register

D7

0

D6

0

D5

1

D4

D3

0

D2

0

D1

0

D0

1

V0-resister ratio set

Electronic volume

0

1

0

1

In this case, the variable range and the notch width of the V0 voltage is shown as Table 11, as dependent on the electronic

volume.

Table 11

V0

Min.

Typ.

Max.

Units

Variable range

Notch width

6.44[α=31]

7.05[α=15]

7.62[α=0]

[V]

[mV]

37

(B) When external resistors are used. (1)

(The V0-resistor is not used.)

The V0 voltage can also be set without using the V0-resistor by adding resistors Ra' and Rb' between VSS and VR, and

between VR and V0, respectively. In this case, the electronic volume command makes it possible to adjust the contrast

of the LCD by controlling V0 voltage. In the range where V0 < VOUT, the V0 voltage can be calculated using equation

B-1 based on the external resistors Ra' and Rb'.

V0=(1+Rb'/Ra')•VEV

VEV=(1–α/200)•VREG

(Equation B-1)

VREG is the on-chip constant voltage as shown in Table 8 at Ta=25°C.

External Rb'

–

V0

+

VEV (Constant voltage source + electronic volume)

External Ra'

VSS

Figure 11

13–18

EPSON

Rev. 1.1a

S1D15B01 Series

When selection Ta=25°C and V0=11V for S1D15B01 series on which temperature gradient=–0.05%/°C.

The central value of the electronic volume register is (D5, D4, D3, D2, D1, D0)=(1, 0, 0, 0, 0,), that is α =15.

So, according to equation B-1 and VREG=1.3V, the Rb'/Ra' is shown as follows.

V0 =(1+Rb'/Ra')•(1–α/200) •VREG

11V=(1+Rb'/Ra')•(1–15/200) •1.3V

(Equation B-2)

Moreover, when the value of the current running through Ra' and Rb' is set to 5 µA,

Ra'+Rb'=2.2MΩ

(Equation B-3)

Consequently, by equation B-2 and B-3,

Rb'+Ra'=8.15

Ra'=240kΩ

Ra'=1960kΩ

In this case, the variable range and the notch width of the V0 voltage is, as shown Table 12, as dependent on the electronic

volume.

Table 12

V0

Min.

Typ.

Max.

Units

Variable range

Notch width

10.01[α=31]

11.0[α=15]

11.9[α=0]

[V]

[mV]

59

(C) When external resistors are used. (2)

(The V0-resistor is not used.)

When the external resistors described above are used, adding a variable resistor as well make it possible to perform fine

adjustments on Ra' and Rb', to set the V0 voltage. In this case, the electronic volume function makes it possible to control

the V0 voltage by commands to adjust the LCD contrast. In the range where V0<VOUT the V0 voltage can be calculated

by equation C-1 below based on the R1 and R2 (variable resistors) and R3 settings, where R2 can be subjected to fine

adjustments (∆ R2).

V0 ={1+(R3+R2–∆ R2)/(R1+∆ R2)}•VEV

={1+(R3+R2–∆ R2)/(R1+∆ R2)}• (1–α/200)•VREG

[

VEV=(1–α/200)•VREG]

(Equation C-1)

External

resistor R3

Rb'

Ra'

R2

VR

External

resistor R2

+

–

V

0

External

resistor R1

VEV (Constant voltage source + electronic volume)

V

SS

Figure 12

Rev. 1.1a

EPSON

13–19

S1D15B01 Series

When selection Ta=25°C and V0=5V to V0=9V (using R2) for S1D15B01 series on which temperature gradient=–

0.05%/°C.

The central value of the electronic volume register is (D5, D4, D3, D2, D1, D0)=(1, 0, 0, 0, 0,), that is α=15.

So, according to equation C-1 and VREG=1.3V, the R1, R2, R3, are shown as follows. (when ∆ R2=0Ω at V0=9V and

∆ R2=R2 at V0=5V)

9V ={1+(R3+R2)/R1}•(1–15/200) •1.3V

5V ={1+R3/(R1+R2)}•(1–15/200) •1.3V

(Equation C-2)

(Equation C-3)

Moreover, when the value of the current running through V0 and VSS is set to 5 µ A at V0=7V (central value),

R1+R2+R3=1.4MΩ

(Equation C-3)

With this, according to equation C-2, C-3 and C-4,

R1=187kΩ

R2=150kΩ

R3=1063kΩ

In this case, if V0 is set to 7V as central value, ∆ R2 becomes 53kΩ

And, the variable range and the notch width of the V0 voltage is, as shown Table 13, as dependent on the electronic

volume. (∆ R2=53kΩ)

Table 13

V0

Min.

Typ.

Max.

Units

Variable range

Notch width

6.41[α=31]

7.0[α=15]

7.58[α=0]

[V]

[mV]

37

* When the V0-resistor or the electronic volume function is used, it is necessary to at least set the voltage regulator circuit

and the voltage follower circuit to an operating mode using the power control set commands. Moreover, it is necessary

to provide a voltage from VOUT when the Booster circuit is OFF.

* The VR terminal is enabled only when the V0-resistor is not used. When the V0-resistor is used, then the VR terminal

is left open.

* Because the input impedance of the VR terminal is high, it is necessary to take into consideration short leads, shield

cables, etc. to handle noise.

Voltage Follower Circuit

The V0 voltage is divided to generate the V1, V2, V3 and V4 voltages by on-chip resistor circuit. And the V1, V2, V3

and V4 voltages are impedance-converted by voltage follower,and provide to LCD driver circuit.

LCD bias ratio can be selected by LCD bias set command which is 1/7 bias or 1/9 bias for S1D15B01 series.

Power supply turn off sequence

Only S1D15B01D00B which is used as on-chip power supply LCD driver, has the faculty of VOUT shorts to VDD2

*

when the RES pin is LOW, and V0 shorts to VSS when the RES pin is LOW or reset command is issued. When the on-

chip power supply is turned off, it is recommended to be the RES pin is LOW., for the purpose of the electric discharge

on the LCD panel.

S1D15B01D00B /S1D15B01D02B which is used as external power supply LCD driver, don't have such a discharge

*

faculty, so that VOUT and V0 need to short to VSS, when the external power supply turn off or power saver.

See the section on the Command Description for details.

13–20

EPSON

Rev. 1.1a

S1D15B01 Series

Reference Circuit Examples

Figure 13 ~ 18 shoes reference circuit examples.

(1) When used all of the booster circuit, voltage regulator circuit and V/F circuit [S1D15B01D00B ]

*

1 Use the voltage regulator with V0-resistor

(Example where VDD=VDD2, with 5 × boosting)

2 Use the voltage regulator with external resistor

(Example where VDD=VDD2, with 5 × boosting)

VDD

VDD2

VOUT

VDD2

VOUT

C1

CAP3+

C1

CAP1-

C1

CAP1-

C1

CAP1+

CAP4+

C1

CAP2-

C1

CAP2-

C1

CAP2+

R3

R2

V0

VR

VSS

VR

R1

VSS

V1

V2

V3

V4

V1

V2

V3

V4

VSS

Figure 13

Figure 14

(2) When used only the voltage regulator circuit and V/F circuit [S1D15B01D01B ]

*

1 Use the voltage regulator with V0-resistor

2 Use the voltage regulator with external resistor

VDD

V

DD2

OUT

V

DD2

OUT

Extemal

power

Extemal

power

CAP3+

CAP1-

CAP1+

CAP4+

CAP2-

CAP2+

CAP3+

CAP1-

CAP1+

CAP4+

CAP2-

CAP2+

supply

R3

R2

R1

V

0

V0

VR

V

SS

V

SS

1

2

3

4

1

2

3

4

VSS

Figure 15

Figure 16

Rev. 1.1a

EPSON

13–21

S1D15B01 Series

(3) When used only the V/F circuit

(4) When the on-chip power supply is not used

[S1D15B01D01B ]

[S1D15B01D02B ]

*

VDD

V

DD2

OUT

V

DD2

OUT

Extemal

power

CAP3+

CAP1-

CAP1+

CAP4+

CAP2-

CAP2+

CAP3+

CAP1-

CAP1+

CAP4+

CAP2-

CAP2+

supply

V0

VR

V

SS

V

SS

1

2

3

4

1

2

3

4

VSS

Extemal

power

supply

Figure 17

Figure 18

Example of shared reference settings

When V0 can vary between 8 and 12V

ltem

C1

Set value

1.0 ~ 4.7

Units

µF

Figure 14

* Because the VR terminal input impedance is high, use short leads and shield lines.

13–22

EPSON

Rev. 1.1a

S1D15B01 Series

Reset Circuit

When RES pin goes low,or when Reset command is

used,this LSI is initialized.

Initialized states :

• V0-resistor ratio register (D2, D1, D0) = (0, 0, 0)

• Electronic volume register (D4, D3, D2, D1, D0) =

(1, 0, 0, 0, 0)

• Serial interface internal shift register and counter

clear

• Power saver mode is entered.

• Oscillation circuit is stopped.

• The LCD power supply circuit is stopped.

• Display OFF

• LCD power supply bias ratio = 1/7 bias

• Test mode is released.

• V0 is shorted to VSS *¹

• VOUT is shorted to VDD2 *¹*²

When reset is detected, this LSI is set to above initialized

states. However it has no effect on contents of DDRAM.

As seen in “Microprocessor Interface (Reference

Example)”, connect RES pin to the reset pin of the MPU

and initialize the MPU at the same time. The initialization

by RES pin is always required during power-on.

• Display all points ON

• Segment/common driver outputs go to the VSS

level.

• Display normal

• Page address=0H

• Column address=00H

If the control signal from MPU is HZ, an overcurrent

may flow through the LSI. A protection is required to

prevent the HZ signal at the input pin during power-on.

In case the S1D15B01 series does not use the on-chip

LCD power supply circuit, RES pin must be HIGH

when the external LCD power supply is turned on.

• Display start line address=00H

• Segment driver direction = normal

• Common driver direction = normal

• Read modify write OFF

• Power control register (D2, D1, D0) = (0, 0, 0)

*¹This faculty is available only S1D15B01D00B .

*

*²This faculty is not available by reset command, it is abailable only when hard reset : RES=LOW is active.

Rev. 1.1a

EPSON

13–23

S1D15B01 Series

7. COMMAND DESCRIPTION

The S1D15B01 series identifies the data bus by a combination of A0, RD (E), WR (R/W) signals.

In the 8080-series MPU interface, the command is activated when a low pulse is input to RD pin for reading and when

a low pulse is input to WR pin for writing. In the 6800-series MPU interface, the S1D15B01 series enters a read mode

when a high level is input to R/W pin and a write mode when a low level is input to R/W pin, and the command is activated

when a high pulse is input to E pin. Therefore, in the command explanation and command table, the 6800-series MPU

interface is different from the 8080-series MPU interface in that RD (E) becomes “1 (H)” in Display data read command.

And when the serial interface is selected, the data is input in sequence starting with D7.

Taking the 8080-series MPU interface as an example, commands will be explained below.

Explanation of commands

(1) Display ON/OFF

This command turns the display ON and OFF.

E

R/W

A0

D7 D6

D5

D4

D3 D2

D1

D0

Setting

RD WR

0

1

0

1

0

1

0

1

0

1

Display OFF

Display ON

When the Display OFF command is executed when in the Display all points ON mode , Power saver mode is entered.

See the section on the Power saver for details.

(2) Display normal/reverse

This command can reverse the lit and unlit display without overwriting the contents of the DDRAM.

E

R/W

A0

D7 D6

D5

D4

D3 D2

D1

D0

Setting

RD WR

0

1

0

1

0

1

0

1

0

Normal:DDRAM Data HIGH

=LCD ON voltage

Reverse:DDRAM Data LOW

=LCD ON voltage

1

(3) Display all points ON/OFF

This command makes it possible to force all display points ON regardless of the content of the DDRAM. Even when

this is done, the DDRAM contents are maintained. This command takes priority over the Display normal/reverse

command.

E

R/W

A0

D7 D6

D5

D4

D3 D2

D1

D0

Setting

RD WR

0

1

0

1

0

1

0

1

0

1

Normal display mode

Display all points ON

When the Display all points ON command is executed when in the Display OFF mode, Power saver mode is entered.

See the section on the Power saver for details.

13–24

EPSON

Rev. 1.1a

S1D15B01 Series

(4) Page address set

This command specifies the page address of the DDRAM (refer to Figure 5).

Specifying the page address and column address enables to access a desired bit of the DDRAM. After the last column

address (83H), page address incremented by +1 (refer to Figure 4). After the very last address (column = 83H, page =

8H), page address return to 0H.

Page address 8H is the DDRAM area dedicate to the indicator, and only D0 is valid for data change.

See the function explanation in “DDRAM and page/column address circuit”, for detail.

E

R/W

A0

D7 D6

D5

D4

D3 D2

D1

D0

Page address

RD WR

0

1

0

1

0

1

0

:

0

1

0

1

0

0H

1H

2H

:

0

1

0

1

0

1

0

7H

8H

(5) Column address set

This command specifies the column address of the DDRAM (refer to Figure 5).

The column address is split into two sections (the upper 4-bits and lower 4-bits) when it is set (fundamentally, set

continuously).

Each time the DDRAM is accessed, the column address automatically increments by +1, making it possible for the MPU

to continuously access to the display data. After the last column address (83H) ,column address returns to 00H (refer

to Figure 4).

See the function explanation in “DDRAM and page/column address circuit”, for detail.

E

R/W

A0

D7 D6

D5

D4

D3 D2

D1

D0

RD WR

0

1

0

1

0

A7 A6

A3 A2

A5

A1

A4

A0

Upper bit address

Lower bit address

A7 A6

A5

A4

A3 A2

A1

A0

Column address

0

:

0

1

0

1

0

00H

01H

02H

:

1

0

1

0

1

82H

83H

(6) Display start line address set

This command is used to specify the display start line address of the DDRAM (refer to Figure 5).

If the display start line address is changed dynamically using this command, then screen scrolling, page swapping can

be performed.

See the function explanation in “Line address circuit”, for detail.

E

R/W

A0

D7 D6

D5

D4

D3 D2

D1

D0

Line address

RD WR

0

1

0

1

0

:

0

1

0

1

0

00H

01H

02H

:

1

0

1

3EH

3FH

Rev. 1.1a

EPSON

13–25

S1D15B01 Series

(7) ADC Select (Segment driver direction select)

This command can reverse the correspondence between the DDRAM column address and the segment driver output.

See the function explanation in “DDRAM and page/column address circuit”, for detail.

E

R/W

A0

D7 D6

D5

D4

D3 D2

D1

D0

Setting

RD WR

0

1

0

1

0

1

0

1

Normal

Reverse

(8) Common driver direction select

This command can reverse the correspondence between the DDRAM line address and the common driver output. See

the function explanation in “Line address circuit”, for detail.

E

R/W

A0

D7 D6

D5

D4

D3 D2

D1

D0

Setting

RD WR

0

1

0

1

0

1

*

Normal

Reverse

*Disabled bit

(9) Display data read

This command reads 8-bit data from the specified DDRAM address. Since the column address is automatically

incremented by +1 after each read ,the MPU can continuously read multiple-word data. One dummy read is required

immediately after the address has been set. See the function explanation in “Access to DDRAM and internal registers”

and “DDRAM and page/column address circuit”, for detail.

E

R/W

A0

D7 D6

D5

D4

D3 D2

D1

D0

RD WR

1

0

1

Read Data

(10) Display data write

This command writes 8-bit data to the specified DDRAM address. Since the column address is automatically

incremented by +1 after each write ,the MPU can continuously write multiple-word data. See the function explanation

in “DDRAM and page/column address circuit”, for detail.

E

R/W

A0

D7 D6

D5

D4

D3 D2

D1

D0

RD WR

1

0

Write Data

13–26

EPSON

Rev. 1.1a

S1D15B01 Series

(11) Read modify write

This command is used paired with End command. Once this command is issued, the column address is not incremented

by Display data read command, but is incremented by Display data write command. This mode is maintained until End

command is issued. When End command is issued, the column address returns to the address it was at when Read modify

write command was issued. This function makes it possible to reduce the MPU load when there are the data to change

repeatedly in a specified display region, such as blinking cursor.

E

R/W

A0

D7 D6

D5

D4

D3 D2

D1

D0

RD WR

0

1

0

1

0

*When End command is issued, only column address returns to the address it was at when Read modify write

command was issued, but page address does not return. Consequently, Read modify Write mode cannot be used

over pages.

*Even if Read modify write mode, other commands besides Display data read/write can also be used. However,

Column address set command cannot be used.

The sequence for cursor display

Page Address Set

Column Address Set

Read Modify Write

Dummy Read

Data Read

Data Write

No

Completed?

Yes

End

Figure 19

Rev. 1.1a

EPSON

13–27

S1D15B01 Series

(12) End

This command releases the Read modify write mode, and returns the column address to the address it was when Read

modify write command was issued .

E

R/W

A0

D7 D6

D5

D4

D3 D2

D1

D0

RD WR

0

1

0

1

0

1

0

Return

Column address

N

N+1

N+2

N+3

• • •

N+m

N

End

Read Modify Write

Figure 20

(13) Power control set

This command sets the on-chip power supply function ON/OFF. See the function explanation in “Power supply circuit”,

for detail.

E

R/W

A0

D7 D6

D5

D4

D3 D2

D1

D0

Mode

RD WR

0

1

0

1

0

1

0

1

Booster : OFF

Booster : ON

0

1

Voltage regulator : OFF

Voltage regulator : ON

0

1

Voltage follower : OFF

Voltage follower : ON

(14) V0-resistor ratio set

This command sets the internal resistor ratio “Rb/Ra” for the V0 voltage regulator to adjust the contrast of LCD panel

display. See the function explanation in “Power supply circuit”, for detail.

E

R/W

A0

D7 D6

D5

D4

D3 D2

D1

D0

Rb/Ra : V0 voltage

RD WR

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

SMALL

↓

LOW

↓

LARGE

External resistor mode

HIGH

13–28

EPSON

Rev. 1.1a

S1D15B01 Series

(15) Electronic volume

This command sets a value of electronic volume “α” for the V0 voltage regulator to adjust the contrast of LCD panel

display. See the function explanation in “Power supply circuit”, for detail.

E

R/W

A0

D7 D6

D5

D4

D3 D2

D1

D0

α

:

V0 voltage

RD WR

0

1

0

1

0

↓

1

0

1

0

1

0

31

LOW

↓

1

0

1

0

HIGH

(16) LCD bias set

This command selects the voltage bias ratio required for the LCD. This command is enabled when the voltage follower

circuit operates.

E

R/W

Bias

S1D15B01

A0

D7 D6

D5

D4

D3 D2

D1

D0

RD WR

0

1

0

1

0

1

0

1

0

1

1/9 bias

1/7 bias

(17) Power saver

When the display all points ON command is executed when in the display OFF mode, power saver mode is entered, and

the power consumption can be greatly reduced.

Power saver (Display OFF & Display all points ON)

Power saver mode

Power saver OFF (Display all points OFF)

Power saver mode cancel

Figure 21

This mode stops every operation of the LCD display system, and can reduce current consumption nearly to a static

current value if no access is made from the MPU. The internal states in the power saver mode is as follows:

• The oscillation circuit is stopped.

• The LCD power supply circuit is stopped.

• The LCD driver circuit is stopped and segment/common driver outputs output the VSS level.

• The display data and operation mode before execution of the Power saver command are held, and the MPU can

access to the DDRAM and internal registers.

Rev. 1.1a

EPSON

13–29

S1D15B01 Series

(18) Reset

This LSI is in initialized by this command. And when S1D15B01D00B is used, V0 is shorted to VSS. (Only when RES=

*

LOW, VOUT is shorted to VSS. So VOUT is not shorted to VSS by this commands.) See the function explanation in “Reset

circuit”, for detail.

E

R/W

A0

D7 D6

D5

D4

D3 D2

D1

D0

RD WR

0

1

0

1

0

1

0

(19) NOP

Non-operation command

E

R/W

A0

D7 D6

D5

D4

D3 D2

D1

D0

RD WR

0

1

0

1

0

1

(20) Test

This is a command for LSI chip testing. Please do not use. If the test command is issued by accident, it can be cleared

by applying an LOW signal to the RES pin, or by issuing the Reset command or the Display ON/OFF command.

E

R/W

A0

D7 D6

D5

D4

D3 D2

D1

D0

RD WR

0

1

0

1

*

1

*

* Disabled bit

(Note):

The S1D15B01 series chip maintain their operating modes ,but excessive external noise, etc., may happen to change

them. Thus in the packaging and system design it is necessary to suppress the noise or take measures to prevent the noise.

Moreover, it is recommended that the operating modes are refreshed periodically to prevent the effects of unanticipated

noise.

13–30

EPSON

Rev. 1.1a

S1D15B01 Series

Command Table

Table 14

Code

Command

A0 XR XW D7 D6 D5 D4 D3 D2 D1 D0

Function

(1) Display ON/OFF

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

LCD display

0:OFF, 1:ON

(2) Display normal/reverce 0

0

1

LCD display

0:normal, 1:reverce

(3) Display all points ON/OFF

(4) Page address set

0

1

LCD display

0:normal display, 1:all points ON

address

Sets the DDRAM page address

Sets the DDRAM column address

(5) Column address set

Upper 4-bit address

Column address set

Lower 4-bit address

(6) Display start line

address set

address

Sets the DDRAM display start line

address.

(7) Segment driver

directuin select

1

0

*

0

*

0

1

Sets the correspondence

between the DDRAM column

address and the SEG driver output.

0:normal, 1:reverse

(8) Common driver

direction select

0

1

0

1

0

1

*

Sets the correspondence

between the DDRAM line address

and the COM driver output.

0:normal, 1:reverse

(9) Display data read

(10) Display data write

(11) Read modify write

(12) End

1

0

-

0

1

-

1

0

-

Read data

Write data

Reads from the DDRAM.

Writes to the DDRAM.

1

0

1

-

1

0

-

1

0

1

-

0

1

0

1

0

1

0

Column address increment

at write:+1, at read:0.

Releases Read modify write mode.

(13) Power control set

(14) V0-resistor ratio set

(15) Electronic volume

(16) LCD bias set

(17) Power saver

(18) Reset

Operating Sets the on-chip power supply

mode

circuit operating mode.

Resistor

ratio

Sets the V0-resistor ratio value.

Electronic volume

value

Sets the electronic volume value.

0

1

0

1

Sets the LCD drive voltage bias ratio.

S1D15B01 0:1/9bias, 1:1/7bias

-

Compound command of Display

OFF and Display all points ON

0

1

0

1

*

0

1

0

*

0

*

1

*

0

1

*

Internal reset

(19) NOP

Non-operation

(20) Test

IC test command. Do not use.

(Note)*:disabled bit

Rev. 1.1a

EPSON

13–31

S1D15B01 Series

8. COMMAND SETTING

Instruction Setup of S1D15B01D00B : Reference

*

(1) Initialization

Turn on the VDD - VSS,

the RES pin = LOW *1

VDD2 - VSS keeping

When the power is stabilized

Release the reset state. (RES pin = HIGH)

Initialize state (Default) *2

Function set up by command input (user setup)

(2)Display normal/reverse *3

(7)Segment driver direction set *4

(8)Common driver direction set *5

(16)LCD bias set *6

Function set up by command input (user setup)

(14)Setting built-in resistance ratio for

regulation of the V0 voltage *7

(15)Electronic volume control set *8

Power saver OFF

(17)Display all points OFF *9

Function set up by command input (user setup)

(13)Power control set *10

This concludes the initialization

Notes: Refer to respective sections or paragraphs listed below

*1: Description of Timing characteristics; Notes for Power on Sequence

*2: Description of functional; Reset Circuit

*3: 7.Command Description; Display normal/reverse

*4: 7.Command Description; Segment driver direction select

*5: 7.Command Description; Common driver direction select

*6: 7.Command Description; LCD bias set

*7: Description of functions; Power supply circuit & Command description; V0-resistor ratio set

*8: Description of functions; Power supply circuit & Command description; Electronic volume

*9: 7.Command Description; Power saver

*10: Description of functions; Power supply circuit & Command description; Power control set

13–32

EPSON

Rev. 1.1a

S1D15B01 Series

(2) Data display

End of initialization

Function set up by command input (user setup)

(6) Display start line address set *11

(4) Page address set *12

(5) Column address set *13

Function set up by command input (user setup)

(10) Display data write *14

Function set up by command input (user setup)

(1) Display ON/OFF *15

End of data display

Notes: Reference items

*11: 7.Command Description; Display start line address set

*12: 7.Command Description; Page address set

*13: 7.Command Description; Column address set

*14: 7.Command Description; Display data write

*15: 7.Command Description; Display ON/OFF

(3) Power OFF *16

Optional status

Function set up by command input (user setup)

(17)Power saver *17

Reset active

(18)RES pin = LOW or reset command *18

(19)Turn OFF the VDD2 - VSS, VDD - VSS *19

Notes: Reference items

*16: After turning OFF the internal power supply, turn OFF the power supply of this IC.

(Function Description; Power supply circuit)

When the power of this IC is turned OFF with the internal power supply is held in the ON status, since the where

the voltage is supplied, even though an only little, to on chip LCD drive circuit is still continued, it is featured

to ill affect the display quality of the LCD panel. To avoid this, be sure to observe the power OFF sequence

strictly.

*17: 7.Command Description; Power saver

*18: It is recommended to be RES pin=LOW. Only if it is not possible to be RES pin=LOW, ase reset command.

*19: Set the time tL from reset active to turning off the VDD2/VDD power, longer then the time tH when the potential

of V0 ~ V4 becomes below the threshold voltage (approximately 1V) of the LCD panel. (tL > tH) If tL < tH, an

irregular display may occur.

Refer to the < Reference Data > as below. When tH is too long, insert a resis for between V0 and VSS to reduce

it.

Rev. 1.1a

EPSON

13–33

S1D15B01 Series

Condition: VDD=VDD2=1.8V, Quintuple boosting, Boosting Capacitance 1 µ F,

Set the V0 voltage to 8V

tH (µ s) is calculated the following equation.

tH=tH0×V0+∆ tH×CL×V0

CL

tH0

:The capacitance of LCD panel connected between V0 and VSS

:tH at the CL=0

∆ tH :tH when the V0 drops 1V per the CL=1pF.

This is reference data, so it is needed to estimate a real LCD module since tH is depends on the VDD/VDD2 voltage and

the capacitance of LCD panel.

1 In case of RES pin=LOW

RES = L

Power OFF

Power

t

L

saver

VDD2

/VDD

SEG

COM

1.7V

As power VDD, VDD2 is

shut off, it becomes

V

SS

impossible to fix output

V

V⁰

V

V¹

V²

At or under Vth on LCD.

Use 1.0[V] as a reference.

V³

VS⁴S

t

H

Figure 22

S1D15B01D00B has the discharge faculty that is shorted VOUT to VDD2, when RES pin=LOW.

*

As tH0=70(µs/V), ∆ tH=0.079(µs/V/nF) by measurement, tH is calculated as follows, when V0=7V and CL=100pF.

tH=tH0×V0+∆ tH×CL×V0=70×7+0.079×100×7=545µs

2 In case of reset command

reset

command

Power OFF

Power

t

L

saver

VDD2

/VDD

SEG

COM

1.7V

As power VDD, VDD2 is

shut off, it becomes

V

SS

impossible to fix output

V

V⁰

V

V¹

V²

At or under Vth on LCD.

Use 1.0[V] as a reference.

V³

VS⁴S

t

H

Figure 23

VOUT is not shorted to VDD2 by reset command, so tH is longer than the case of RES pin=LOW.

As tH0=175(µs/V), ∆ tH=0.23(µs/V/nF) by measurement, tH is calculated as follows, when V0=7V and CL=100pF.

tH=tH0×V0+∆ tH×CL×V0=175×7+0.23×100×7=1386µs

13–34

EPSON

Rev. 1.1a

S1D15B01 Series

(3) Refresh

It is recommended that the operating modes and display contents be refreshed periodically to prevent the effect of

unexpected noise.

Refresh sequence

Set all commands to ready state

Test mode reset command

(Display ON/OFF) *20

Refreshing DDRAM

Notes: Reference items

*20: 7.Command description; Display ON/OFF

Rev. 1.1a

EPSON

13–35

S1D15B01 Series

9. ABSOLUTE MAXIMUM RATING

Unless otherwise noted, VSS = 0V.

Table 15

Parameter

Symbol

VDD

Conditions

–0.3 to 7.0

–0.3 to 6.0

–0.3 to 4.5

–0.3 to 3.6

Unit

V

Power supply voltage (1)

Power supply voltage (2)

Double boosting

VDD2

V

Triple boosting

Quadruple boosting

Quintuple boosting

Power supply voltage (3)

Power supply voltage (4)

Input voltage

V0, VOUT

V1, V2, V3, V4

VIN

–0.3 to 18.0

–0.3 to V0

V

–0.3 to VDD+0.3

–40 to 85

V

Output voltage

VO

V

Operating temperature

TOPR

°C

Storage temperature

TCP

TSTR

–55 to 100

Bare chip

–55 to 125

V0, VOUT

₁to

V

V4

V

CC

VDD, VDD2

VSS

GND

VSS

System

S1D15B01 series

Notes and Conditions

1. Voltage V0 ≥ V1 ≥ V2 ≥ V3 ≥ V4 ≥ VSS must always be satisfied.

2. If the LSI exceeds its absolute maximum rating, it may be damage permanently. It is desirable to use it under electrical

characteristics conditions during general operation. Otherwise, a malfunction of the LSI may be caused and LSI

reliability may be affected.

13–36

EPSON

Rev. 1.1a

S1D15B01 Series

10. ELECTRICAL CHARACTERISTICS

DC Characteristics

Table 16

VSS=0V, VDD=3V±10%, Ta=–40 to 85°C unless otherwise noted.

Item

Recommended

Symbol

Condition

Min.

Typ.

Max.

Unit Pin used

Power

VDD

(Relative to VSS)

1.8

–

3.6

V

VDD *1

voltage(1) operation

Operational

1.7

1.8

–

5.5

3.6

V

Power

Recommended

VDD2

(Relative to VSS)

VDD2 *1

voltage(2) operation

Operational

Booster circuit

operatinal

voltage

1.7

3.0

2.0

1.7

6.0

–

5.5

5.0

4.0

3.0

16.0

Double boosting

Triple boosting

Quadruple boosting

Quintuple boosting

(Relative to VSS)

Voltage regulator

VOUT

V

VOUT

operational voltage

Voltage follower

V0

V1, V2

V3, V4

VREG

VIH

4.5

0.6×V0

VSS

–

16.0

V0

V0 *2

V1,V2

V3,V4

*3

operational voltage

–

0.4×V0

1.34

Reference voltage

Ta=25°C

1.26

1.30

–

V

High-level input voltage

Low-level input voltage

High-level output voltage

Low-level output voltage

Input leakage current

Output leakage current

LCD driver ON resistance

0.8×VDD

VSS

VDD

*4

VIL

–

0.2×VDD

VDD

V

VOH

VOL

ILI

IOH=-0.5mA

IOL=0.5mA

0.8×VDD

VSS

–

V

*5

–

0.2×VDD

–1.0

V

–1.0

–

µA

kΩ

*6

*7

ILO

–3.0

–

–3.0

RON

V0=8V

2.0

5.0

SEGn,

Ta=25°C

COMn *8

Static current

consumption

IDDQ

I0Q

Ta=25°C

–

0.01

20

5

15

µA

VDD,

VDD2

V0=16V

Ta=25°C

V5

Input terminal

capacitance

CIN

f =1MHz

Ta=25°C

35

pF

Oscillation frequency

fOSC

Ta=25°C

4.55

5.2

5.85

kHz

*9

Relationship between oscillation frequency fosc and frame rate frequency fFR : fFR = fosc/ 65

Relationship between external clock (CL) frequency fCL and frame rate frequency fFR : fFR =fCL/ 8/ 65

Rev. 1.1a

EPSON

13–37

S1D15B01 Series

Current consumption

Dynamic current consumption (1) : During display, when the internal power supply circuit is OFF

(external power supply is used).

Table 17

Item

Display Pattern OFF

Ta=25˚C

Symbol

Condition

Min.

Typ.

20

Max.

33

Unit

Notes

^S1D15B01*****

I0(1)

VDD=VDD2=2.7V, V0=8.0V

VDD=VDD2=2.7V, V0=11.0V

–

µA

*10

29

48

Table 18

Item

Display Pattern Checker

Ta=25˚C

Symbol

Condition

Min.

Typ.

24

Max.

40

Unit

Notes

^S1D15B01*****

I0(1)

VDD=VDD2=2.7V, V0=8.0V

VDD=VDD2=2.7V, V0=11.0V

–

µA

*10

33

55

Dynamic current consumption (2) : During display, when the internal power supply circuit is ON.

Table 19

Item

Display Pattern OFF

Ta=25˚C

Symbol

Condition

Min.

Typ.

Max.

Unit

Notes

IDD+IDD2

VDD=VDD2=2.7V, V0=8.0V

Triple boosting

–

75

125

µA

*9

^S1D15B01*****

(2)

VDD=VDD2=2.7V, V0=8.0V

Quadruple boosting

–

96

160

198

VDD=VDD2=2.7V, V0=8.0V

Quadruple boosting

119

Table 20

Item

Display Pattern Checker

Ta=25˚C

Symbol

Condition

Min.

Typ.

Max.

Unit

Notes

IDD+IDD2

VDD=VDD2=2.7V, V0=8.0V

Triple boosting

–

86

143

µA

*9

^S1D15B01*****

(2)

VDD=VDD2=2.7V, V0=8.0V

Quadruple boosting

–

110

136

183

227

VDD=VDD2=2.7V, V0=8.0V

Quadruple boosting

Table 21

Item

Power saver

Ta=25˚C

Symbol

Condition

Min.

Typ.

Max.

Unit

Notes

IDD(2)

VDD=VDD2=1.7V to 3.6V

–

0.01

5

µA

*9

^S1D15B01*****

13–38

EPSON

Rev. 1.1a

S1D15B01 Series

Reference data

Dynamic current consumption (1) : During display, when the internal power supply circuit is OFF

(external power supply is used).

Conditions : Internal power supply OFF. External supply in use.

V0=8.0V, Display pattern : OFF, Ta=25˚C

50

40

30

V0 = 11.0V

20

V0 = 8.0V

10

0

1

2

3

4

5

6

7

8

VDD = VDD2 [V]

Figure 24

Conditions : Internal power supply OFF. External supply in use.

V0=8.0V, Display pattern : Checker, Ta=25˚C

50

40

30

20

10

V0 = 11.0V

V0 = 8.0V

0

1

2

3

4

5

6

7

8

VDD = VDD2 [V]

Figure 25

Rev. 1.1a

EPSON

13–39

S1D15B01 Series

Dynamic current consumption (2) : During display, when the internal power supply circuit is ON.

Conditions : Internal power supply ON.

V0=8.0V, Display pattern : OFF, Ta=25˚C

140

×5

120

×4

100

×3

80

×2

60

40

20

0

1

2

3

4

5

6

VDD + VDD2 [V]

Figure 26

Conditions : Internal power supply ON.

V0=8.0V, Display pattern : Checker, Ta=25˚C

160

140

120

100

80

×5

×4

×3

×2

60

40

20

0

1

2

3

4

5

6

VDD + VDD2 [V]

Figure 27

13–40

EPSON

Rev. 1.1a

S1D15B01 Series

Dynamic current consumption (3) : During access and display (Checker pattern is constantly written at fCYC and

displayed), when the on-chip power supply circuit is ON.

10

1

0.1

0.01

0.001

0.01

0.1

1

10

fCYC [MHz]

Figure 28

Rev. 1.1a

EPSON

13–41

S1D15B01 Series

VDD, VDD2 and V0 (VOUT) operation voltage range

(1) S1D15B01D00B

1 VDD=VDD2

*

In the range of VDD=VDD2<3.2V, the maximum V0 voltage is determined by VOUT voltage of the quintuple boosting.

It is necessary to keep VOUT > V0 for preventing irregular display. The voltage of VOUT - V0 is determined by LCD

panel, so it is recommended to check the actual LCD module and set them.

20

16

15

Operating range

10

8.5

4.5

5

0

1.7

2

3.2

5.5

0

1

3

4

5

6

V

DD = VDD2 [V]

Figure 29

2 VDD<VDD2

In the case, it is necessary to keep 1.7V≤VDD≤VDD2≤3.6V. And the VDD2 should be set to keep VOUT>V0.

20

16

15

11

10

5

Operating range

4.5

1.7

3.6

4

0

1

2

3

5

6

V

DD [V]

Figure 30

13–42

EPSON

Rev. 1.1a

S1D15B01 Series

(2) S1D15B01D01B

*

If VDD=VDD2, the operating range of VDD/VDD2 is 1.7V≤VDD=VDD2≤4.5V. And if VDD<VDD2, the operating range

of VDD/VDD2 is 1.7V≤VDD<VDD2≤3.6V

1 Eternal voltage : VOUT

In this case, the relationship between VOUT and VDD/VDD2 is required as shown in Figure 31.

20

VDD < VDD2

VDD = VDD2

16

15

Operating range

10

5

8

6

1.7

2.4

3.6

4

4.5

0

1

2

3

5

6

V

DD / VDD2 [V]

Figure 31

2 Eternal voltage : V0

In this case, the relationship between V0 and VDD/VDD2 is required as shown in Figure 32.

20

V

DD < VDD2

VDD = VDD2

16

11

15

Operating range

10

5

4.5

1.7

2

3.6

4.5

0

1

3

4

5

6

V

DD / VDD2 [V]

Figure 32

(3) S1D15B01D02B

*

Eternal voltage: V0, V1 to V4

In this case, V0 operating range is same as Figure 32, and V0≥V1≥V2≥V3≥V4≥VSS is required.

Rev. 1.1a

EPSON

13–43

S1D15B01 Series

*1. Though the wide range of operating voltage is guaranteed, performance cannot be guaranteed if there are sudden

fluctuations to the voltage during being accessed from MPU.

This VDD, VDD2 operational voltage range (1.7V to 5.5V) is in case of VDD=VDD2. If VDD≠VDD2, it becomes to

be 1.7V≤VDD<VDD2≤3.6V.

*2. VDD, VDD2 and V0 operating voltage range is shown in Figure.

*3. VREG is internal constant voltage source for V0 voltage regulator circuit.

*4. D7 (SI), D6 (SCL), D5 to D0, A0, CS, RES, RD (E), WR (R/W),C86, P/S and CL pins

*5. D7 to D0 pins

*6. A0, CS, RES, RD (E), WE (R/W), C86, P/S and CL pins

*7. D7 (SI), D6 (SCL) and D5 to D0 pins

*8. Resistance value when 0.1V is applied between the output pin SEGn or COMn and each power supply pin (V0, V1,

V2, V3, V4, VSS). This is specified in the “Voltage follower operating voltage” range. RON = 0.1V/∆I (∆I : Current

flowing when 0.1V is applied between that output pin and those power supply pin).

*9. Current that each IC unit consumes. It does not include the current of the LCD panel capacity, wiring capacity, etc.

13–44

EPSON

Rev. 1.1a

S1D15B01 Series

Timing Characteristics

System Bus Read/Write Characteristics 1 (For the 8080-series MPU)

A0

tAW8

tAH8

CS1

(CS2="1")

tCYC8

*1

tCCLR, tCCLW

WR, RD

tCCHR, tCCHW

CS1

(CS2="1")

*2

tf

tr

WR, RD

tDS8

tDH8

D0 to D7

(Write)

tACC8

tOH8

D0 to D7

(Read)

Figure 33

Table 22

[VDD=4.5V to 5.5V, Ta=–40 to 85°C]

Item

Signal

Symbol

tAH8

Condition

Min.

0

Max.

Units

Address hold time

A0

–

ns

Address setup time

tAW8

0

System cycle time

tCYC8

tCCLW

tCCLR

tCCHW

tCCHR

160

30

70

30

Control LOW pulse width(Write)

Control LOW pulse width(Read)

Control HIGH pulse width(Write)

Control HIGH pulse width(Read)

WR

RD

WR

RD

Data setup time

Data hold time

Access time

D7 to D0

tDS8

tDH8

20

0

–

tACC8

tOH8

CL=100pF

–

70

50

Output disable time

5

Rev. 1.1a

EPSON

13–45

S1D15B01 Series

Table 23

[VDD=2.7V to 4.5V, Ta=–40 to 85°C]

Item

Signal

Symbol

tAH8

Condition

Min.

0

Max.

Units

Address hold time

A0

–

ns

Address setup time

tAW8

0

System cycle time

tCYC8

tCCLW

tCCLR

tCCHW

tCCHR

260

60

120

60

Control LOW pulse width(Write)

Control LOW pulse width(Read)

Control HIGH pulse width(Write)

Control HIGH pulse width(Read)

WR

RD

WR

RD

Data setup time

Data hold time

Access time

D7 to D0

tDS8

tDH8

35

0

–

tACC8

tOH8

CL=100pF

–

120

100

Output disable time

10

Table 24

[VDD=1.7V to 2.7V, Ta=–40 to 85°C]

Item

Signal

Symbol

tAH8

Condition

Min.

0

Max.

Units

Address hold time

A0

–

ns

Address setup time

tAW8

0

System cycle time

tCYC8

tCCLW

tCCLR

tCCHW

tCCHR

700

120

240

120

Control LOW pulse width(Write)

Control LOW pulse width(Read)

Control HIGH pulse width(Write)

Control HIGH pulse width(Read)

WR

RD

WR

RD

Data setup time

Data hold time

Access time

D7 to D0

tDS8

tDH8

90

0

–

tACC8

tOH8

CL=100pF

–

240

200

Output disable time

10

*1. This is in the case of making the access by WR and RD, setting the CS1=LOW.

*2. This is in the case of making the access by CS1, setting the WR, RD=LOW.

*3. The rise and fall times (tr and tf) of the input signal are specified for less than 15 ns. When using the system cycle

<

time at high speed, they are specified for (tr+tf) (tCYC8-tCCLW) or (tr+tf) (tCYC8-tCCLR-tCCHR).

=

*4. All timings are specified based on the 20 and 80% of VDD.

*5. tCCLW and tCCLR are specified for the overlap period when CS1 is at LOW (CS2=HIGH) level and WR,RD are at

the LOW level.

13–46

EPSON

Rev. 1.1a

S1D15B01 Series

System Bus Read/Write Characteristics 2 (For the 6800-series MPU)

A0

R/W

tAW6

tAH6

CS1

(CS2="1")

tCYC6

*1

*2

tEWHR, tEWHW

E

tEWLR, tEWLWW

CS1

(CS2="1")

tr

tf

E

tDS6

tDH6

D0 to D7

(Write)

tACC6

tOH6

D0 to D7

(Read)

Figure 34

Table 25

[VDD=4.5V to 5.5V, Ta=–40 to 85°C]

Item

Signal

A0,

Symbol

tAH6

Condition

Min.

0

Max.

–

Units

Address hold time

Address setup time

System cycle time

Enable

ns

WR

tAW6

0

–

tCYC6

tEWHW

tEWHR

tEWLW

tEWLR

tDS6

160

30

70

30

20

0

–

Width

E

–

HIGH pulse width Read

–

Enable

Width

Read

–

LOW pulse width

Data setup time

Data hold time

Access time

–

D7 to D0

–

tDH6

–

tACC6

tOH6

CL=100pF

–

70

50

Output disable time

5

Rev. 1.1a

EPSON

13–47

S1D15B01 Series

Table 26

[VDD=2.7V to 4.5V, Ta=–40 to 85°C]

Item

Address hold time

Address setup time

System cycle time

Enable

Signal

A0,

Symbol

tAH6

Condition

Min.

0

Max.

Units

–

ns

WR

tAW6

0

tCYC6

tEWHW

tEWHR

tEWLW

tEWLR

tDS6

260

60

120

60

35

0

–

Width

E

–

HIGH pulse width Read

–

Enable

Width

Read

–

LOW pulse width

Data setup time

Data hold time

–

D7 to D0

–

tDH6

–

Access time

tACC6

tOH6

CL=100pF

–

120

100

Output disable time

10

Table 27

[VDD=1.7V to 2.7V, Ta=–40 to 85°C]

Item

Address hold time

Address setup time

System cycle time

Enable

Signal

A0,

Symbol

tAH6

Condition

Min.

0

Max.

Units

–

ns

WR

tAW6

0

tCYC6

tEWHW

tEWHR

tEWLW

tEWLR

tDS6

700

120

240

120

90

–

Width

E

–

HIGH pulse width Read

–

Enable

Width

Read

–

LOW pulse width

Data setup time

Data hold time

–

D7 to D0

–

tDH6

0

–

Access time

tACC6

tOH6

CL=100pF

–

240

200

Output disable time

10

*1. This is in the case of making the access by E, setting the CS1=LOW.

*2. This is in the case of making the access by CS1, setting the E=HIGH.

*3. The rise and fall times (tr and tf) of the input signal are specified for less than 15 ns. When using the system cycle

<

time at high speed, they are specified for (tr+tf) (tCYC6-tEWLW-tEWHW) or (tr+tf) (tCYC6-tEWLR-tEWHR).

=

*4. All timings are specified based on the 20 and 80% of VDD.

*5. tEWLW and tEWLR are specified for the overlap period when CS1 is at LOW (CS2=HIGH) level and E is at the HIGH

level.

13–48

EPSON

Rev. 1.1a

S1D15B01 Series

Serial interface

t

CSS

t

CSH

CS

t

SAS

t

SAH

A0

t

SCYC

t

SLW

SCL

t

SHW

t

f

t

r

t

SDS

t

SDH

SI

Figure 35

Table 28

VDD=4.5 to 5.5V, Ta=–40 to 85°C

Item

Signal

Symbol

tSCYC

tSHW

Condition

Min.

40

Max.

Units

Serial clock cycle

SCL

–

ns

Serial clock HIGH pulse width

Serial clock LOW pulse width

15

tSLW

15

Address setup time

Address hold time

A0

SI

tSAS

tSAH

10

20

–

Data setup time

Data hold time

tSDS

tSDH

3

–

CS serial clock time

CS

tCSS

tCSH

10

25

–

Table 29

VDD=2.7 to 4.5V, Ta=–40 to 85°C

Item

Signal

Symbol

tSCYC

tSHW

Condition

Min.

70

Max.

Units

Serial clock cycle

SCL

–

ns

Serial clock HIGH pulse width

Serial clock LOW pulse width

25

tSLW

25

Address setup time

Address hold time

A0

SI

tSAS

tSAH

20

40

–

Data setup time

Data hold time

tSDS

tSDH

5

–

CS serial clock time

CS

tCSS

tCSH

15

50

–

Rev. 1.1a

EPSON

13–49

S1D15B01 Series

Table 30

VDD=1.7 to 2.7V, Ta=–40 to 85°C

Item

Signal

Symbol

tSCYC

tSHW

Condition

Min.

150

50

Max.

Units

Serial clock cycle

SCL

–

ns

Serial clock HIGH pulse width

Serial clock LOW pulse width

tSLW

50

Address setup time

Address hold time

A0

SI

tSAS

tSAH

45

90

–

Data setup time

Data hold time

tSDS

tSDH

10

–

CS serial clock time

CS

tCSS

tCSH

50

–

100

Note : 1. The input Signal rise and fall times must be with in 10ns.

2. Every timing is specified on the basis of 20% and 80% of VDD.

13–50

EPSON

Rev. 1.1a

S1D15B01 Series

Reset timing

t

RW

RES

t

R

Internal circuit

state

During reset

Normal operation

Figure 36

Table 31

Parameter

Reset time

VDD=4.5 to 5.5V, Ta=–40 to 85°C

Signal

Symbol

tR

Condition

Min.

–

Max.

250

–

Units

ns

Reset LOW pulse width

RES

tRW

250

Table 32

VDD=2.7 to 4.5V, Ta=–40 to 85°C

Parameter

Reset time

Signal

Symbol

Min.

Max.

Units

tR

–

500

ns

Reset LOW pulse width

RES

tRW

500

–

Table 33

VDD=1.7 to 2.7V, Ta=–40 to 85°C

Parameter

Reset time

Signal

Symbol

Min.

Max.

Units

tR

–

1000

ns

Reset LOW pulse width

RES

tRW

1000

–

Note : 1. The input Signal rise and fall times must be with in 10ns.

2. Every timing is specified on the basis of 20% and 80% of VDD.

Rev. 1.1a

EPSON

13–51

S1D15B01 Series

Notes for Power on Sequence

It is preferable to turn on power supply VDD and VDD2

at the same time, but if VDD turn on after VDD2, then it

is necessary that the below 3 conditions are satisfied.

V

DD2

DD

t1

V

CS

t2

RES

Figure 37

A. t1 < 1ms, during this timing, all input pins are fixed to VSS.

B. CS becomes HIGH simultaneously with VDD.

C. t2 > 100ns (Reset is canceled after VDD2 and rise up).

13–52

EPSON

Rev. 1.1a

S1D15B01 Series

11. THE MPU INTERFACE (REFERENCE EXAMPLES)

The S1D15B01 series can directly be connected to the 80 system MPU and 68 series MPU. It can also be operated with

a fewer signal lines by using the serial interface.

After the initialization using the RES pin, the respective input pins of the S1D15B01 series need to controlled normally.

(1) 80 series MPU

VDD

V

DD

V

CC

C86

P/S

A0

A1 to A7

IORQ

CS

Decoder

RESET

D0 to D7

RD

WR

RD

WR

RES

V

SS

GND

V

SS

DD

Figure 38

(2) 6800 series MPU

V

DD

V

CC

C86

P/S

A0

A1 to A15

VMA

CS

Decoder

RESET

D0 to D7

E

R/W

RES

E

R/W

RES

V

SS

GND

VSS

Figure 39

(3) Using serial interface

VDD

VCC

C86

P/S

A0

A1 to A7

Decoder

RESET

CS

SI

SCL

RES

Port1

Port2

VDD or VSS

RES

VSS

GND

VSS

Figure 40

Rev. 1.1a

EPSON

13–53

S1D15B01 Series

12. CAUTION

Please be advised on the following points in the use of

this development specification.

1. This development specification is subject to change

without previous notice.

[Precaution on light]

Property of semiconductor devices may be affected

when they are exposed to light, possibly resulting in

malfunctioning of the ICs. To prevent such

malfunctioning of the ICs mounted on the boards or

products, make sure that:

(1) Your design and mounting layout done are so that

the IC is not exposed to light in actual use.

(2) The IC is protected from light in the inspection

process.

2. This development specification does not guarantee or

furnish the industrial property right not its execution.

Application examples in this development

specification are intended to ensure your better

understanding of the product. Thus the manufacturer

shall not be liable for any trouble arising in your

circuits from using such application example.

Numerical values provided in the property table of

this manual are represented with their magnitude on

the numerical line.

(3) The IC is protected from light in its front, rear and

side faces.

[Precautions when installing the COG]

3. No part of this development specification may not be

reproduced, copied or used for commercialpurpose

without a written permission from the manufacturer.

When installing the COG, it is necessary to duly

consider the fact that there exists a resistance of the

ITO wiring occurring between the driver chip and the

externally connected parts (such as capacitors and

resistors). By the influence of this resistance, non-

conformity may occur with the indications on the

liquid crystal display.

In handling of semiconductor devices, your attention is

required to following points.

Therefore, when installing the COG design the module

paying sufficient considerations to the following three

points.

1. Suppress the resistance occurring between the

driver chip pin to the externally connected parts

as much as possible.

2. Suppress the resistance connecting to the power

supply pin of the driver chip.

3. Make various COG module samples with different

ITO sheet resistance to select the module with the

sheet resistance with sufficient operation margin.

13–54

EPSON

Rev. 1.1a

International Sales Operations

AMERICA

ASIA

EPSON ELECTRONICS AMERICA, INC.

HEADQUARTERS

150 River Oaks Parkway

San Jose, CA 95134, U.S.A.

EPSON (CHINA) CO., LTD.

28F, Beijing Silver Tower 2# North RD DongSanHuan

ChaoYang District, Beijing, CHINA

Phone : 64106655

Fax : 64107319

Phone : +1-408-922-0200

Fax : +1-408-922-0238

SHANGHAI BRANCH

4F, Bldg., 27, No. 69, Gui Jing Road

Caohejing, Shanghai, CHINA

SALES OFFICES

West

1960 E. Grand Avenue

Phone : 21-6485-5552

Fax : 21-6485-0775

El Segundo, CA 90245, U.S.A.

EPSON HONG KONG LTD.

20/F., Harbour Centre, 25 Harbour Road

Wanchai, Hong Kong

Phone : +1-310-955-5300

Fax : +1-310-955-5400

Central

Phone : +852-2585-4600

Fax : +852-2827-4346

101 Virginia Street, Suite 290

Crystal Lake, IL 60014, U.S.A.

Phone : +1-815-455-7630

Telex : 65542 EPSCO HX

Fax : +1-815-455-7633

EPSON TAIWAN TECHNOLOGY & TRADING LTD.

10F, No. 287,Nanking East Road, Sec. 3

Taipei

Northeast

301 Edgewater Place, Suite 120

Wakefield, MA 01880, U.S.A.

Phone : 02-2717-7360

Fax : 02-2712-9164

Telex : 24444 EPSONTB

Phone : +1-781-246-3600

Fax : +1-781-246-5443

HSINCHU OFFICE

13F-3, No.295, Kuang-Fu Road, Sec. 2

HsinChu 300

Phone : 03-573-9900

Southeast

3010 Royal Blvd. South, Suite 170

Alpharetta, GA 30005, U.S.A.

Phone : +1-877-EEA-0020 Fax : +1-770-777-2637

Fax : 03-573-9169

EPSON SINGAPORE PTE., LTD.

No. 1 Temasek Avenue, #36-00

EUROPE

EPSON EUROPE ELECTRONICS GmbH

HEADQUARTERS

Millenia Tower, SINGAPORE 039192

Phone : +65-337-7911

Fax : +65-334-2716

Riesstrasse 15

SEIKO EPSON CORPORATION

KOREA OFFICE

80992 Munich, GERMANY

Phone : +49- (0) 89-14005-0

Fax : +49- (0) 89-14005-110

50F, KLI 63 Bldg., 60 Yoido-dong

SALES OFFICE

Altstadtstrasse 176

Youngdeungpo-Ku, Seoul, 150-763, KOREA

Phone : 02-784-6027

Fax : 02-767-3677

51379 Leverkusen, GERMANY

Phone : +49- (0) 2171-5045-0 Fax : +49- (0) 2171-5045-10

SEIKO EPSON CORPORATION

ELECTRONIC DEVICES MARKETING DIVISION

UK BRANCH OFFICE

Unit 2.4, Doncastle House, Doncastle Road

Bracknell, Berkshire RG12 8PE, ENGLAND

Phone : +44- (0) 1344-381700 Fax : +44- (0) 1344-381701

Electronic Device Marketing Department

IC Marketing & Engineering Group

421-8, Hino, Hino-shi, Tokyo 191-8501, JAPAN

Phone: +81-(0)42-587-5816

Fax: +81-(0)42-587-5624

FRENCH BRANCH OFFICE

1 Avenue de l’ Atlantique, LP 915 Les Conquerants

Z.A. de Courtaboeuf 2, F-91976 Les Ulis Cedex, FRANCE

Phone : +33- (0) 1-64862350 Fax : +33- (0) 1-64862355

ED International Marketing Department

Europe & U.S.A.

421-8, Hino, Hino-shi, Tokyo 191-8501, JAPAN

Phone: +81-(0)42-587-5812

Fax: +81-(0)42-587-5564

BARCELONA BRANCH OFFICE

Barcelona Design Center

Edificio Prima Sant Cugat

ED International Marketing Department

Asia

421-8, Hino, Hino-shi, Tokyo 191-8501, JAPAN

Avda. Alcalde Barrils num. 64-68

`

E-08190 Sant Cugat del Valles, SPAIN

Phone: +81-(0)42-587-5814

Fax: +81-(0)42-587-5110

Phone : +34-93-544-2490 Fax: +34-93-544-2491


型号：	S1D15B01T00
厂家：	SEIKO EPSON CORPORATION
描述：	Liquid Crystal Driver, 197-Segment, CMOS, TCP 驱动接口集成电路
文件：	总59页 (文件大小：373K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

S1D15B01T00 [SEIKO]

相关型号：

S1D15B10D00B0

S1D15B10T

S1D15E00D00B

S1D15E00T00A

S1D15E05D00A

S1D15E05D00B

S1D15E05D00E

S1D15E06

S1D15E06D00A

S1D15E06D00B

S1D15E06D00E

S1D15E06D01B000