S1D17E01D00A100 [SEIKO]
LIQUID CRYSTAL DISPLAY DRIVER, UUC200, DIE-200;
| 型号： | S1D17E01D00A100 |
| 厂家： | 
SEIKO EPSON CORPORATION |
| 描述： | LIQUID CRYSTAL DISPLAY DRIVER, UUC200, DIE-200 驱动 接口集成电路 |
| 文件： | 总35页 (文件大小：433K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MF1515-02
S1D17E01 Series
Rev.1.0
NOTICE
No part of this material may be reproduced or duplicated in any form or by any means without the written
permission of Seiko Epson. Seiko Epson reserves the right to make changes to this material without notice.
Seiko Epson does not assume any liability of any kind arising out of any inaccuracies contained in this material
or due to its application or use in any product or circuit and, further, there is no representation that this material is
applicable to products requiring high level reliability, such as, medical products. Moreover, no license to any
intellectual property rights is granted by implication or otherwise, and there is no representation or warranty that
anything made in accordance with this material will be free from any patent or copyright infringement of a third
party. This material or portions thereof may contain technology or the subject relating to strategic products
under the control of the Foreign Exchange and Foreign Trade Law of Japan and may require an export license
from the Ministry of International Trade and Industry or other approval from anther government agency.
All other product names mentioned herein are trademarks and/or registered trademarks of their respective
companies.
©SEIKO EPSON CORPORATION 2003, All rights reserved.
CONTENTS
1. DESCRIPTION....................................................................................................................................1
2. FEATURES .........................................................................................................................................1
3. BLOCK DIAGRAM .............................................................................................................................2
4. PAD LAYOUT......................................................................................................................................3
5. PAD CENTRAL COORDINATES .......................................................................................................4
6. PIN DESCRIPTION.............................................................................................................................6
7. FUNCTIONAL DESCRIPTION ...........................................................................................................8
8. ABSOLUTE MAXIMUM RATINGS...................................................................................................18
9. ELECTRICAL CHARACTERISTICS................................................................................................19
10. LCD DRIVE POWER SUPPLY.........................................................................................................27
11. EXAMPLES OF CONNECTION .......................................................................................................29
12. NOTES ..............................................................................................................................................32
－i－
Rev.1.0
S1D17E01 Series
1. DESCRIPTION
The S1D17E01 is a 160-output, low On resistance, common (row) driver suitable for driving a medium capacity
dot matrix LCD panel and has a built-in, low current consumption LCD drive power supply circuit.
When used in combination with the S1D17A07, it enables a high-performance handy display system with
minimum power consumption.
2. FEATURES
ꢀNumber of LCD drive outputs: 160
ꢀHigh duty drivability: 1/320 (Reference)
ꢀCommon output On resistance: 1 kΩ (Typ.)
ꢀPin selection in output shift direction
ꢀNo-bias display-off function
ꢀBuilt-in, low-consumption LCD drive power supply circuit
Boosting circuit (boosting multiples: 3, 4, 5, 6, 8, 10 and 12)
Voltage adjusting circuit
Voltage follower (built-in split resistors for V1 to V4 voltage generation)
ꢀSupply voltages
Logic power supply:
LCD power supply:
VDD-VSS = 2.7 to 6.0 V
V0-GND = 11 to 36 V
ꢀWide range of operating temperature: -25 to +85°C
ꢀCMOS process
ꢀAvailable packages: Chip: S1D17E01D00A100 (Al pad)
ꢀNo light- and radiation-resistance design is provided for this chip.
Rev.1.0
EPSON
1
S1D17E01 Series
3. BLOCK DIAGRAM
ꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁ
VDD
V0
V1
LCD driver (160-bit)
V2
V3
V4
VSS
VR
CAPL+
CAPL-
CAP1+
CAP1-
CAP2+
CAP2-
CAP3+
CAP4+
CAP5+
VDD2
Level shifter (160-bit + 1)
FR
Bi-directional shift register (160-bit)
VOUT
BIAS1
BIAS2
BIAS3
EV0
EV1
EV2
EV3
EV4
EV5
WR
MS
HPM
DC
POR
2
EPSON
Rev.1.0
S1D17E01 Series
4. PAD LAYOUT
161
162
101
100
Die No.
Y
X
(0,0)
200
62
1
61
Chip size:
6.63 mm × 4.09 mm
100 µm
Pad pitch:
Chip thickness:
525±25 µm
Al Pad model (S1D17E01D00A100)
Scribe parallel Scribe vertical
(X)
(Y)
93.2µm
83.2µm
Pad opening dimension A
Pad opening dimension B
83.2µm
93.2µm
×
×
PAD No. 1 to 61, 101 to 161
PAD No. 62 to 100, 162 to 200
Rev.1.0
EPSON
3
S1D17E01 Series
5. PAD CENTRAL COORDINATES
Unit: µm
PAD NO. Pin Name
X
Y
PAD NO. Pin Name
X
Y
PAD NO. Pin Name
X
Y
1
2
DUMMY
OUT 159
OUT 158
OUT 157
OUT 156
OUT 155
OUT 154
OUT 153
OUT 152
OUT 151
OUT 150
OUT 149
OUT 148
OUT 147
OUT 146
OUT 145
OUT 144
OUT 143
OUT 142
OUT 141
OUT 140
OUT 139
OUT 138
OUT 137
OUT 136
OUT 135
OUT 134
OUT 133
OUT 132
OUT 131
OUT 130
OUT 129
OUT 128
OUT 127
OUT 126
OUT 125
OUT 124
OUT 123
OUT 122
OUT 121
OUT 120
OUT 119
OUT 118
OUT 117
OUT 116
OUT 115
OUT 114
OUT 113
OUT 112
OUT 111
OUT 110
OUT 109
OUT 108
OUT 107
OUT 106
OUT 105
OUT 104
OUT 103
OUT 102
OUT 101
-3000
-2900
-2800
-2700
-2600
-2500
-2400
-2300
-2200
-2100
-2000
-1900
-1800
-1700
-1600
-1500
-1400
-1300
-1200
-1100
-1000
-900
-800
-700
-600
-500
-400
-300
-200
-100
0
-1895
61
62
OUT 100
OUT 99
OUT 98
OUT 97
OUT 96
OUT 95
OUT 94
OUT 93
OUT 92
OUT 91
OUT 90
OUT 89
OUT 88
OUT 87
OUT 86
OUT 85
OUT 84
OUT 83
OUT 82
OUT 81
OUT 80
OUT 79
OUT 78
OUT 77
OUT 76
OUT 75
OUT 74
OUT 73
OUT 72
OUT 71
OUT 70
OUT 69
OUT 68
OUT 67
OUT 66
OUT 65
OUT 64
OUT 63
OUT 62
OUT 61
OUT 60
OUT 59
OUT 58
OUT 57
OUT 56
OUT 55
OUT 54
OUT 53
OUT 52
OUT 51
OUT 50
OUT 49
OUT 48
OUT 47
OUT 46
OUT 45
OUT 44
OUT 43
OUT 42
OUT 41
3000
3167
-1895
-1900
-1800
-1700
-1600
-1500
-1400
-1300
-1200
-1100
-1000
-900
-800
-700
-600
-500
-400
-300
-200
-100
0
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
OUT 40
OUT 39
OUT 38
OUT 37
OUT 36
OUT 35
OUT 34
OUT 33
OUT 32
OUT 31
OUT 30
OUT 29
OUT 28
OUT 27
OUT 26
OUT 25
OUT 24
OUT 23
OUT 22
OUT 21
OUT 20
OUT 19
OUT 18
OUT 17
OUT 16
OUT 15
OUT 14
OUT 13
OUT 12
OUT 11
OUT 10
OUT 9
OUT 8
OUT 7
OUT 6
OUT 5
OUT 4
OUT 3
OUT 2
OUT 1
OUT 0
VR
1000
900
1895
3
63
800
4
64
700
5
65
600
6
66
500
7
67
400
8
68
300
9
69
200
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
70
100
71
0
72
-100
-200
-300
-400
-500
-600
-700
-800
-900
-1000
-1100
-1200
-1300
-1400
-1500
-1600
-1700
-1800
-1900
-2000
-2100
-2200
-2300
-2400
-2500
-2600
-2700
-2800
-2900
-3000
-3167
73
74
75
76
77
78
79
80
81
82
100
83
200
84
300
85
400
86
500
87
600
88
700
89
800
90
900
91
1000
1100
1200
1300
1400
1500
1600
1700
1800
1900
1895
100
92
200
93
300
94
400
95
500
96
600
97
700
98
800
99
900
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
1000
1100
1200
1300
1400
1500
1600
1700
1800
1900
2000
2100
2200
2300
2400
2500
2600
2700
2800
2900
3000
2900
2800
2700
2600
2500
2400
2300
2200
2100
2000
1900
1800
1700
1600
1500
1400
1300
1200
1100
1900
1800
1700
1600
1500
1400
1300
1200
1100
1000
900
V0
V1
V2
V3
V4
VOUT
CAP5+
CAP3+
CAP1+
CAP1-
CAP4+
CAP2+
CAP2-
VDD2
800
700
600
500
CAPL+
CAPL-
MS
400
300
200
HPM
100
4
EPSON
Rev.1.0
S1D17E01 Series
Unit: µm
PAD NO. Pin Name
X
Y
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
DC
EV0
-3167
0
-100
-200
-300
-400
-500
-600
-700
-800
-900
-1000
-1100
-1200
-1300
-1400
-1500
-1600
-1700
-1800
-1900
EV1
EV2
EV3
EV4
EV5
WR
BIAS1
BIAS2
BIAS3
DIO2
YSCL
FR
______
DSPOF
VSS
SHL
VDD
DIO1
POR
Rev.1.0
EPSON
5
S1D17E01 Series
6. PIN DESCRIPTION
Power Supply Pins
Number
of pins
1
Pin name
I/O
Function
VDD
Power Supplies electric power to the internal logic and built-in power supply circuit.
supply VDD = 2.7 to 6.0V
VSS
Power 0V pin connected to the system ground.
supply
1
5
V0, V1, V2
V3, V4
Supply Multi-level, LCD drive power supply pins. The voltage specified according to
LCD cells is impedance-converted by a split resistor or operational amplifier
and applied. The voltages need to be specified based on the VSS to
establish the following relationship:
V0≥V1≥V2≥V3≥V4≥VSS
LCD Power Supply Circuit Pins
Number
of pins
Pin name
I/O
Function
CAPL+
CAPL-
VDD2
O
O
It is connects the positive going side of primary boosting circuit capacitor.
It is connects the negative going side of primary boosting circuit capacitor.
It is primary boosting circuit output pin. Outputs twice as mulch voltage as
the VDD.
1
1
1
I/O
Connect to VDD when boosting with the secondary booster circuit only and
not the primary booster circuit.
CAP1+
CAP1-
O
O
It is connects the positive going side of secondary boosting circuit capacitor.
It is connects the negative going side of secondary boosting circuit
capacitor.
1
1
CAP2+
CAP2-
O
O
It is connects the positive going side of secondary boosting circuit capacitor.
It is connects the negative going side of secondary boosting circuit
capacitor.
1
1
CAP3+
CAP4+
CAP5+
VOUT
O
O
O
O
It is connects the positive going side of secondary boosting circuit capacitor.
It is connects the positive going side of secondary boosting circuit capacitor.
It is connects the positive going side of secondary boosting circuit capacitor.
It is secondary boosting circuit output pin. Outputs twelve-times as much
voltage as the VDD at maximum boosting.
1
1
1
1
VR
I
Voltage regulating pin. Applies V0 voltage using an external connection
resistor.
1
6
EPSON
Rev.1.0
S1D17E01 Series
System Bus Connection Pins
Number
of pins
1
Pin name
I/O
Function
MS
I
Master/slave switch pin.
MS = HIGH (master): boosting circuit, voltage regulating circuit and V/F
circuits are turned on.
MS = LOW (slave): boosting circuit, voltage regulating circuit and V/F
circuits are turned off.
POR
POR
HPM
I
I
Resets the device when set to LOW.
1
1
Reset operation depends on the POR signal level.
Valid only in master operation. The pin is fixed to LOW in slave operation.
Power control pin of the LCD drive power supply circuit.
HPM = HIGH: High power mode
HPM = LOW: Normal mode
Valid only in master operation. The pin is fixed to HIGH or LOW in slave
operation.
DC
BIAS1 to BIAS3
EV0 to EV5
WR
I
I
I
I
Used to discharge the residual power from the LCD panel, power supply
pins and others before turning the built-in power supply off. It is
recommended that the power be turned off after setting DC to LOW.
The pin is fixed to LOW in slave operation.
Bias setting pins (1/12 to 1/19 bias ratios are available).
Valid only in master operation. The pin is fixed to HIGH or LOW in slave
operation.
1
3
6
1
EV0 to EV5
Data bus: V0 voltage regulating pins.
The V0 voltage can be regulated at 64 levels.
Valid only in master operation. The pin is fixed to HIGH or LOW in slave
operation.
Inputs data bus read clocks.
Reads data at the rise time.
Only valid for master function. When POR is in LOW level during master
function, fix WR to HIGH level. Fix to HIGH level during slave function.
･Inputs built-in power supply circuit boosting clocks.
･Inputs common driver serial data shift clocks.
Shifts scan data at the fall edge.
YSCL
I
I/O
I
1
2
1
DIO1
DIO2
Bi-directional shift register scan pulse.
I/O is set depending on an input from the SHL.
The output changes at the YSCL fall edge.
Inputs shift direction select signals and I/O control signals of the DIO pin.
SHL
SHL
LOW
HIGH
COM output shift direction
159
DIO1
Input
DIO2
Output
Input
0
159
0
Output
FR
I
I
1
1
Inputs LCD drive output AC signals.
Inputs LCD blanking control signals.
______
DSPOF
All common outputs are set to the VSS level when LOW is input.
Liquid Crystal Drive Pins
Number
of pins
160
Pin name
I/O
Function
COM0 to
COM159
Outputs LCD drive common (row) signals.
Changes at the YSCL fall edge.
O
Total: 199
Rev.1.0
EPSON
7
S1D17E01 Series
7. FUNCTIONAL DESCRIPTION
7.1 Bi-directional Shit Register
Bi-directional shit register for transferring common data. The shift direction is selected depending on an input
from the SHL. Scan data is read at the YSCL fall edge and the output is sent to the level shifter.
7.2 Level Shifter
Voltage level interface circuit for converting the signal voltage level from the logic system level to the LCD drive
system level.
7.3 LCD Driver
Outputs LCD drive voltages.
______
The table below shows the relationship among display blanking signal DSPOF, shift register contents, AC signal
FR and common output voltage:
______
DSPOF
HIGH
LOW
Shift register contents
FR
Common output voltage
HIGH
LOW
HIGH
LOW
VSS
HIGH
(Select level)
V0
V1
LOW
(Non-select level)
V4
VSS
7.4 Power Supply Circuit
Low-consumption, power supply circuit to generate voltages required for driving LCD, which consists of
boosting circuit, voltage regulating circuit and voltage follower circuits. The power supply circuit turns the
boosting circuit, voltage regulating circuit and voltage follower circuits on and off using an input from the MS
pin.
To set the power supply circuit in the slave state and drive the common driver only using external power supply,
be sure to set each circuit as shown in the table below:
Voltage
regulating
circuit
Voltage
follower
circuit
Boosting
system pin
*1
Boosting
circuit
External
voltage input
Operating state
MS pin
Internal power
supply only
HIGH
LOW
ON
ON
ON
VDD
Used
External power
supply only
VDD, V0
V1, V4
OFF
OFF
OFF
Open
*1 Boosting system pins refer to CAPL+, CAPL-, VDD2, CAP1+, CAP1-, CAP2+, CAP2-, CAP3+, CAP4+
and CAP5+, VOUT.
8
EPSON
Rev.1.0
S1D17E01 Series
7.5 Boosting Circuit
The boosting circuit consists of primary and secondary boosting circuits as follows:
Using the primary and secondary boosting circuits enables the VDD-VSS voltage to be amplified 12, 10, 8, 6 and 4
times. Using the secondary boosting circuit solely enables the VDD-VSS voltage to be amplified 6, 5, 4 and 3
times.
Primary booster circuit
Secondary booster circuit
VOUT pin
VDD2 pin
12 times as much voltage as VDD-VSS
VSS pin
6 times
VDD pin
VSS pin
Double
VSS pin
Boosting Circuit Diagram
ꢁ12-times boosting (primary + secondary boosting circuits)
Connect capacitors between CAPL+ and CAPL-, CAP1+ and CAP1-, CAP2+ and CAP2-, CAP3+ and CAP1-,
CAP4+ and CAP2-, CAP5+ and CAP1-, VDD2 and VDD or VSS, and VOUT and VDD2 or VSS. This amplifies the
positive VDD-VSS voltage 12 fold, which is output to the VOUT pin.
ꢁ10-times boosting (primary + secondary boosting circuits)
Connect capacitors between CAPL+ and CAPL-, CAP1+ and CAP1-, CAP2+ and CAP2-, CAP3+ and CAP1-,
CAP4+ and CAP2-, VDD2 and VDD or VSS, and VOUT and VDD2 or VSS, and jumper between CAP5+ and VOUT.
This amplifies the positive VDD-VSS voltage 10 fold, which is output to the VOUT pin.
ꢁ8-times boosting (primary + secondary boosting circuits)
Connect capacitors between CAPL+ and CAPL-, CAP1+ and CAP1-, CAP2+ and CAP2-, CAP3+ and CAP1-,
VDD2 and VDD or VSS, and VOUT and VDD2 or VSS, and jumper between CAP5+, CAP4+ and VOUT. This
amplifies the positive VDD-VSS voltage 8 fold, which is output to the VOUT pin.
ꢁ6-times boosting (primary + secondary boosting circuits)
Connect capacitors between CAPL+ and CAPL-, CAP1+ and CAP1-, CAP2+ and CAP2-, VDD2 and VDD or
VSS, and VOUT and VDD2 or VSS, and jumper between CAP5+, CAP4+, CAP3+ and VOUT. This amplifies the
positive VDD-VSS voltage 6 fold, which is output to the VOUT pin.
ꢁ6-times boosting (secondary boosting circuit only)
Connect capacitors between CAP1+ and CAP1-, CAP2+ and CAP2-, CAP3+ and CAP1-, CAP4+ and CAP2-,
CAP5+ and CAP1-, and VOUT and VDD2 or VSS, open CAPL+ and CAPL-, and jumper between VDD2 and VDD.
This amplifies the positive VDD-VSS voltage 6 fold, which is output to the VOUT pin.
ꢁ5-times boosting (secondary boosting circuit only)
Connect capacitors between CAP1+ and CAP1-, CAP2+ and CAP2-, CAP3+ and CAP1-, CAP4+ and CAP2-,
and VOUT and VDD2 or VSS, open CAPL+ and CAPL-, and jumper between CAP5+ and VOUT, and VDD2 and
VDD. This amplifies the positive VDD-VSS voltage 5 fold, which is output to the VOUT pin.
ꢁ4-times boosting (primary + secondary boosting circuits)
Connect capacitors between CAPL+ and CAPL-, CAP1+ and CAP1-, VDD2 and VDD or VSS, and VOUT and
VDD2 or VSS, open CAP2-, and jumper between VOUT and CAP5+, CAP4+, CAP3+ and CAP2+. This amplifies
the positive VDD-VSS voltage 4 fold, which is output to the VOUT pin.
ꢁ4-times boosting (secondary boosting circuit only)
Connect capacitors between CAP1+ and CAP1-, CAP2+ and CAP2-, CAP3+ and CAP1-, and VOUT and VDD2
or VSS, open CAPL+ and CAPL-, and jumper between CAP5+ and VOUT, CAP4+ and VOUT, and VDD2 and
VDD. This amplifies the positive VDD-VSS voltage 4 fold, which is output to the VOUT pin.
ꢁ3-times boosting (secondary boosting circuit only)
Connect capacitors between CAP1+ and CAP1-, CAP2+ and CAP2-, and VOUT and VDD2 or VSS, open CAPL+
and CAPL-, and jumper between VOUT and CAP5+, CAP4+ and CAP3+, and VDD2 and VDD. This amplifies the
positive VDD-VSS voltage 3 fold, which is output to the VOUT pin.
Rev.1.0
EPSON
9
S1D17E01 Series
The figures below show the connections and voltage relationships:
VDD or VSS
VDD2
VDD or VSS
VDD2
VDD or VSS
VDD2
+
+
+
+
+
+
VDD2 or VSS
VOUT
VDD2 or VSS
VOUT
VDD2 or VSS
VOUT
CAP5+
CAP3+
CAP1+
CAP1-
CAP5+
CAP3+
CAP1+
CAP1-
CAP5+
CAP3+
CAP1+
CAP1-
+
+
+
+
+
+
+
CAP4+
CAP2+
CAP2-
CAP4+
CAP2+
CAP2-
CAP4+
CAP2+
CAP2-
+
+
+
+
+
+
CAPL+
CAPL-
CAPL+
CAPL-
CAPL+
CAPL-
+
+
12-times Boosting Circuit
(Primary + Secondary Boosting Circuits)
10-times Boosting Voltage Relationship
(Primary + Secondary Boosting Circuits)
8-times Boosting Circuit
(Primary + Secondary Boosting circuits)
VOUT=12×VDD
=36.0V
VOUT=10×VDD
=30.0V
VOUT=8×VDD
=24.0V
VDD=3.0V
VSS=0V
VDD=3.0V
VSS=0V
VDD=3.0V
VSS=0V
12-times Boosting Voltage Relationship 10-times Boosting Voltage Relationship 8-times Boosting Voltage Relationship
(Primary + Secondary Boosting Circuits)
(Primary + Secondary Boosting Circuits)
(Primary + Secondary Boosting Circuits)
10
EPSON
Rev.1.0
S1D17E01 Series
VDD or VSS
VDD2
VDD
VDD
+
+
VDD2
VDD2
VDD2 or VSS
VOUT
VDD2 or VSS
VOUT
VDD2 or VSS
VOUT
+
+
CAP5+
CAP3+
CAP1+
CAP1-
CAP5+
CAP3+
CAP1+
CAP1-
CAP5+
+
+
+
CAP3+
+
CAP1+
+
+
CAP1-
CAP4+
CAP2+
CAP2-
CAP4+
CAP2+
CAP2-
CAP4+
+
+
+
CAP2+
+
+
+
CAP2-
CAPL+
CAPL-
OPEN
OPEN
CAPL+
CAPL-
OPEN
OPEN
CAPL+
CAPL-
6-times Boosting Circuit
6-times Boosting Circuit
5-times Boosting Circuit
(Primary + Secondary Boosting Circuits)
(Secondary Boosting Circuits Only)
(Secondary Boosting Circuit Only)
VOUT=6×VDD
=33.0V
VOUT=5×VDD
=27.5V
VOUT=6×VDD
=18.0V
VDD=5.5V
VSS=0V
VDD=5.5V
VSS=0V
VDD=3.0V
VSS=0V
6-times Boosting Voltage Relationship 6-times Boosting Voltage Relationship 5-times Boosting Voltage Relationship
(Primary + Secondary Boosting Circuits)
(Secondary Boosting Circuit Only)
(Secondary Boosting Circuit Only)
Rev.1.0
EPSON
11
S1D17E01 Series
VDD or VSS
VDD
VDD
+
+
VDD2
VDD2
VDD2
VDD2 or VSS
VOUT
VDD2 or VSS
VOUT
VDD2 or VSS
VOUT
+
+
CAP5+
CAP3+
CAP1+
CAP1-
CAP5+
CAP3+
CAP1+
CAP1-
CAP5+
CAP3+
CAP1+
CAP1-
+
+
+
+
+
CAP4+
CAP2+
CAP2-
CAP4+
CAP2+
CAP2-
CAP4+
CAP2+
CAP2-
+
OPEN
CAPL+
CAPL-
OPEN
OPEN
CAPL+
CAPL-
OPEN
OPEN
CAPL+
CAPL-
+
4-times Boosting Circuit
4-times Boosting Circuit
3-times Boosting Circuit
(Primary + Secondary Boosting Circuits)
(Secondary Boosting Circuit Only)
(Secondary Boosting Circuit Only)
VOUT=4×VDD
=22.0V
VOUT=3×VDD
=16.5V
VOUT=4×VDD
=12.0V
VDD=5.5V
VSS=0V
VDD=5.5V
VSS=0V
VDD=3.0V
VSS=0V
4-times Boosting Voltage Relationship 4-times Boosting Voltage Relationship 3-times Boosting Voltage Relationship
(Primary + Secondary Boosting Circuits)
(Secondary Boosting Circuit Only)
(Secondary Boosting Circuit Only)
12
EPSON
Rev.1.0
S1D17E01 Series
* When using the primary and secondary boosting circuits for boosting, keep the VDD between 2.7V and 3.0V.
* When using the secondary boosting circuit only for boosting, keep the VDD between 2.7V and 6.0V.
* The VDD voltage times the boosting multiple is output to the VOUT pin as an ideal value.
* The VOUT voltage drops depending on the load.
Reference data: VOUT load current characteristic
40 V
Decuple booster
30 V
Setting condition
VDD = 3V
Octuple booster
20 V
10 V
0 V
Sextuple booster
fYSCL=11.2kHz
Boosting capacitor=2.2µF
0.0 mA
0.5 mA
1.0 mA
1.5 mA
2.0 mA
｜IOUT｜: power consumption of the whole LCD module
* It is recommended that the V0 voltage be set to about 90% of the VOUT voltage or lower.
* The boosting capacitor differs by the load of the LCD panel. Set a value that stabilizes the LCD drive voltage
(standard value=1.0 to 4.7µF).
* The tables below show the maximum VDD voltages and the ideal VOUT voltages corresponding to them:
Maximum VDD Voltages
bias
1/12
3V
3V
3V
3V
3V
6V
6V
6V
6V
1/13
1/14
1/15
1/16
1/17
1/18
1/19
4-times boosting
6-times boosting
8-times boosting
10-times boosting
12-times boosting
3-times boosting
4-times boosting
5-times boosting
6-times boosting
Unavailable Unavailable Unavailable Unavailable Unavailable Unavailable Unavailable
3V
3V
3V
3V
6V
6V
6V
6V
3V
3V
3V
3V
6V
6V
6V
6V
3V
3V
3V
3V
6V
6V
6V
6V
3V
3V
3V
3V
6V
6V
6V
6V
3V
3V
3V
3V
6V
6V
6V
6V
3V
3V
3V
3V
6V
6V
6V
6V
3V
3V
3V
3V
6V
6V
6V
6V
Primary
+ secondary
Boosting
Secondary
Boosting
only
Ideal VOUT Voltages Corresponding to Maximum VDD Voltages
bias
1/12
12V
18V
24V
30V
36V
18V
24V
30V
36V
1/13
1/14
1/15
1/16
1/17
1/18
1/19
4-times boosting
6-times boosting
8-times boosting
10-times boosting
12-times boosting
3-times boosting
4-times boosting
5-times boosting
6-times boosting
Unavailable Unavailable Unavailable Unavailable Unavailable Unavailable Unavailable
18V
24V
30V
36V
18V
24V
30V
36V
18V
24V
30V
36V
18V
24V
30V
36V
18V
24V
30V
36V
18V
24V
30V
36V
18V
24V
30V
36V
18V
24V
30V
36V
18V
24V
30V
36V
18V
24V
30V
36V
18V
24V
30V
36V
18V
24V
30V
36V
18V
24V
30V
36V
18V
24V
30V
36V
Primary
+ secondary
Boosting
Secondary
Boosting
only
Rev.1.0
EPSON
13
S1D17E01 Series
7.6 Voltage Regulating Circuit
The amplified voltage generated at the VOUT pin outputs LCD drive voltage V0 through the voltage regulating
circuit.
The S1D17E01 series incorporate a 64-level electronic volume function.
ꢂWhen an external resistor is used1
Set LCD supply voltage V0 by adding resistor Ra between VSS and VR, and resistor Rb between VR and V0.
By using external resistors and the electronic volume function, the V0 voltage can be controlled with a relevant
command only to adjust the LCD tone.
The V0 voltage can be obtained from Expression A-1 within the range of V0 < VOUT.
V0==((11++RRbb//RRaa))ꢃꢃ(V1-EαV /400)ꢃVDD
[VEV=(1-α/400)ꢃVDD]
(Expression A-1)
VDD is the logic power supply inside the IC.
External Rb
VR
V0
+
External Ra
VEV (VDD + electronic volume)
VSS
For α, one of 64 levels can be set by setting data in the 6-bit electronic volume latch circuit using the electronic
volume function. The table below shows available α values:
EV5
0
0
EV4
0
0
EV3
0
0
EV2
0
0
EV1
0
0
EV0
0
1
α
63
62
61
0
0
0
0
1
0
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
0
1
2
1
0
<Setup example>
When selecting V0 = 21.0 V, the intermediate value of the electronic volume resistor is (EV5, EV4, EV3,
EV2, EV1, EV0) = (1, 0, 0, 0, 0, 0), resulting in α = 31.Therefore, from Expression A-1 and VDD = 3.0 V,
Rb/Ra can be expressed as follows:
V0=(1+Rb/Ra)ꢃ(1-α/400)ꢃVDD
21.0V=(1+Rb/Ra)ꢃ(1-31/400)ꢃ3.0V
Assuming that the current flowing through Rb and Ra is 5µA:
Ra+Rb= 4.2MΩ
(Expression A-2)
(Expression A-3)
As a result, Ra and Rb can be obtained as follows from A-2 and A-3:
Rb/Ra= 6.59
Ra= 553.5kΩ
Rb= 3646.5kΩ
14
EPSON
Rev.1.0
S1D17E01 Series
In this case, the V0 voltage variable range and pitch width are controlled by the electronic volume function as
shown below:
V0
Min.
Typ.
21.00 [α=31]
55.9
Max.
Unit
V
Variable range
Pitch width
19.18 [α=63]
22.76 [α=0]
mV
◇When an external resistor is used2
When using the above external resistor, LCD drive voltage V0 can also be set by adding a variable resistor to
finely tune Ra and Rb. As in the above case, by using external resistors and the electronic control function,
LCD drive voltage V0 can be controlled with a relevant command to adjust the LCD tone.
The V0 voltage can be obtained from Expression B-1 as follows by setting external resistors R1, R2 (variable
resistor) and R3 within the range of V0 < VOUT and finely tuning R2 (∆R2):
V0=={{11++((RR33++RR22--∆∆RR22))//((RR11++∆∆RR22))}}ꢃꢃ(V1-EαV/400)ꢃVDD
[VEV=(1-α/400)ꢃVDD]
(Expression B-1)
External
resistor R3
Rb
Ra
ΔR2
VR
+
External
resistor R2
VR
V0
External
resistor R1
VEV (VDD + electronic volume)
VSS
<Setup example>
When selecting V0 = 15.0 to 19.0V (using R2), the intermediate value of the electronic volume resistor is
(EV5, EV4, EV3, EV2, EV1, EV0) = (1, 0, 0, 0, 0, 0), resulting in α = 31.Therefore, from Expression B-1
and VDD = 3.0 V, R1, R2 and R3 can be expressed as follows (when∆R2 = 0 Ω at V0 = 19.0V and ∆R2 = R2
at V0V=0=15{.10+V(R):3+R2-∆R2)/(R1+∆R2)}ꢃ(1-α/400)ꢃVDD
19.0V={1+(R3+R2)/R1}ꢃ(1-31/400)ꢃ3.0V
15.0V={1+R3/(R1+R2)}ꢃ(1-31/400)ꢃ3.0V
(Expression B-2)
(Expression B-3)
Assuming that the current flowing through V0 and VSS is 5µA at V0 = 17.0V (typical value):
R1+R2+R3= 3.4MΩ
(Expression B-4)
As a result, R1, R2 and R3 can be obtained as follows from Expressions B-2, B-3 and B-4:
R1= 495kΩ
R2= 132kΩ
R3= 2773kΩ
Rev.1.0
EPSON
15
S1D17E01 Series
In this case, ∆R2 is 59kΩ when V0 is set to the typical value of 17.0V.
The V0 voltage variable range and pitch width are controlled by the electronic control function as shown below:
(∆R2=59kΩ)
V0
Min.
Typ.
17.00 [α=31]
45.3
Max.
Unit
V
Variable range
Pitch width
15.51 [α=63]
18.41 [α=0]
mV
* Since the VR pin has a high input impedance, noise reduction measures should be taken such as using short and
shielded wires.
7.7 LCD Voltage Generator Circuit
The V0 voltage is divided by resistance within the IC chip to generate voltages V1, V2, V3 and V4 required for
driving LCD. Then, voltages V1, V2, V3 and V4 are impedance-converted by the voltage follower circuit and
supplied to the LCD drive circuit.
The bias ratio between 1/12 and 1/19 can be selected using bias setting pins BIAS1, BIAS2 and BIAS3. The
table below shows available bias settings:
Bias Setting
Bias setting
BIAS3 BIAS2 BIAS1
V1
V2
V3
V4
1/12
LOW
LOW
LOW
LOW
HIGH
HIGH
HIGH
HIGH
LOW
LOW
HIGH
HIGH
LOW
LOW
HIGH
HIGH
LOW
HIGH
LOW
HIGH
LOW
HIGH
LOW
HIGH
11/12V0
12/13V0
13/14V0
14/15V0
15/16V0
16/17V0
17/18V0
18/19V0
10/12V0
11/13V0
12/14V0
13/15V0
14/16V0
15/17V0
16/18V0
17/19V0
2/12V0
2/13V0
2/14V0
2/15V0
2/16V0
2/17V0
2/18V0
2/19V0
1/12V0
1/13V0
1/14V0
1/15V0
1/16V0
1/17V0
1/18V0
1/19V0
1/13
1/14
1/15
1/16
1/17
1/18
1/19
16
EPSON
Rev.1.0
S1D17E01 Series
7.8 Timing Diagram
SHL=LOW
1/240 Duty
1 frame
(240 lines)
DIO1
YSCL
FR
XINH
Q0
Shift
register
Q1
Q2
DIO2
160 lines
V0
V1
COM0
V4
VSS
V0
V1
COM1
V4
VSS
V0
V1
COM2
V4
VSS
Rev.1.0
EPSON
17
S1D17E01 Series
8. ABSOLUTE MAXIMUM RATINGS
Item
Symbol
Rated value
Unit
Supply voltage (1)
VDD
-0.3 to +7.0
V
ꢄBoosting using primary and secondary boosting circuits
VDD
-0.3 to +3.5
-0.3 to +3.5
-0.3 to +3.5
-0.3 to +3.5
-0.3 to +3.3
-0.3 to +7.0
V
4-times boosting
6-times boosting
8-times boosting
10-times boosting
12-times boosting
Supply voltage (2)
VDD2
V
V
ꢄBoosting using secondary boosting circuit only
-0.3 to +7.0
-0.3 to +7.0
-0.3 to +7.0
-0.3 to +6.6
-0.3 to +40
-0.3 to V0
VDD2
3-times boosting
4-times boosting
5-times boosting
6-times boosting
Supply voltage (3)
V0, VOUT
V
V
Supply voltage (4)
Input voltage
V1,V2,V3,V4
VI
VO
-0.3 to VDD+0.3
-0.3 to VDD+0.3
20
V
Output voltage
V
DIO output current
Operating temperature
IO
mA
°C
°C
Topr
Tstg1
-25 to +85
-65 to +150
Chip
Storage
temperature
System side
S1D17E01 series
V0,VOUT
V1
V2
40V
VCC
VDD
V3
3.5V
3.5V
V4
GND
VSS
VSS
Note 1: All voltages are based on the condition that the VSS is equal to 0V.
Note 2: Voltages V0 to V4 must always satisfy the condition of V0≥V1≥V2≥V3≥V4≥VSS.
Note 3: Do not let the logic system power float or drop under the function voltage range (VDD=2.7 to 6.0V)
during application of LCD drive power supply since the LSI may get permanently broken. Especially
be careful with the power sequence when turning ON and OFF the system power.
Note 4: If the LSI chip is used in an environment exceeding the absolute maximum ratings, it may be destroyed
permanently. During normal operation, electrical characteristics conditions should be observed.
Otherwise, the LSI chip may malfunction or the LSI reliability may drop.
18
EPSON
Rev.1.0
S1D17E01 Series
9. ELECTRICAL CHARACTERISTICS
9.1 DC Characteristics
Unless otherwise specified, VSS = 0V, VDD = 6.0, Ta = -25 to +85°C
Applicable
Item
Symbol
Condition
Min.
Typ.
Max.
Unit
pin
Operating Operable
VDD
VDD
2.7
6.0
V
voltage (1)
boosting
circuit
operating
voltage
4-times boosting
(primary + secondary boosting)
6-times boosting
(primary + secondary boosting)
8-times boosting
2.7
3.0
V
(primary + secondary boosting)
10-times boosting
(primary + secondary boosting)
12-times boosting
(primary + secondary boosting)
Operating Operable
VDD2
VDD2
2.7
2.7
6.0
6.0
V
V
voltage (2)
boosting
circuit
3-times boosting
(secondary boosting only)
4-times boosting
(secondary boosting only)
5-times boosting
operating
voltage
(secondary boosting only)
6-times boosting
(secondary boosting only)
Voltage adjusting
circuit operating
voltage
VOUT
(VSS reference)
VOUT
11.0
36.0
V
Voltage follower
operating voltage
V0
V1,V2
V3,V4
VIH
V0
V1, V2
V3, V4
*1
11.0
0.6 × V0
VSS
36.0
V0
V
V
0.4 × V0
V
HIGH level input voltage
LOW level input voltage
HIGH level output voltage
LOW level output voltage
Input leak current
0.8 × VDD
V
VDD = 2.7 to 6.0V
DIO1, DIO2
VIL
0.2 × VDD
V
VOH
VOL
ILI
VDD =
2.7 to 6.0V
IOH=-0.4mA
IOL= 0.4mA
VDD - 0.4
V
DIO1, DIO2
0.4
2.0
5.0
V
VSS ≤ VIN ≤ VDD
*1
µA
µA
I/O leak current
ILI/O
VSS ≤ VIN ≤ VDD
V0 = 11.0 to 36.0V , Ta = 25°C
VIH = VDD, VIL = VSS
DIO1, DIO2
Static current
IVSS
VSS
5
µA
VIH = VDD, VIL = VSS
∆VON
= 0.5V
Ta = 25°C
V0=36.0V
1/24bias
V0=20.0V
1/20bias
0.9
1.0
1.3
Output resistance
RON
O0 to O159
kΩ
1.5
30
50
Input pin capacitance
I/O pin capacitance
CI
Freq. =1MHz
*1
pF
pF
Ta = 25°C
Chip unit
CI/O
DI01,DI02
______
*1 MS, HPM, DC, POR, EV0 to EV5, WR, BIAS1 to BIAS3, SHL, YSCL, FR, DSPOF
Rev.1.0
EPSON
19
S1D17E01 Series
9.2 Current Consumption
9.2.1 Dynamic current consumption values (1)
When common output = ON and built-in power supply circuit = OFF
Applicable
pin
Item
Symbol
Condition
Min.
Typ.
Max.
Unit
VDD = 6.0V, VIH = VDD
VIL = VSS ,fYSCL = 22.4kHz
fFR = 70Hz, Ta = 25°C,
No load, Input data = 1/320
VDD = 3.0V
Logic system average
current consumption
(1)
IDD(1)
15
30
VDD
µA
Other conditions are the same
as those of VDD = 6.0V.
V0 = 30.0V, V1 = 28.0V
V4 = 2.0V
VDD = 6.0V, VSS = 0V
Other conditions are the same
as those of IDD(1).
10
10
20
Liquid crystal drive
system average
current consumption
(1)
IV0
V0
100
µA
9.2.2 Dynamic current consumption values (2)
When common output and built-in power supply circuit = ON
Common conditions: VIH = VDD, VIL = VSS, fYSCL = 11.2kHz, fFR = 70Hz, Ta = 25°C, no load,
input data = 1/160
The output is set to V0 = 21V by the voltage adjusting circuit.
ꢂPrimary and secondary boosting circuits
Applicable
Item
Symbol
Condition
Min.
Typ.
0.61
1.08
0.77
1.36
0.94
1.65
Max.
1.02
1.80
1.29
2.27
1.57
2.76
Unit
pin
Logic system
average current
consumption (2)
VDD=3.0V
Normal mode
High power
mode
8-times
boosting
IDD(2) VDD=3.0V
10-times
Normal mode
High power
mode
VDD
mA
boosting
VDD=3.0V
12-times
boosting
Normal mode
High power
mode
ꢂSecondary boosting circuit only
Applicable
pin
Item
Symbol
Condition
Min.
Typ.
0.43
0.84
0.55
1.06
0.67
1.29
Max.
0.72
1.40
0.92
1.77
1.12
2.15
Unit
Logic system
average current
consumption (3)
VDD=6.0V
4-times
boosting
VDD=6.0V
5-times
boosting
VDD=6.0V
6-times
Normal mode
High power
mode
Normal mode
High power
mode
VDD
mA
IDD(3)
Normal mode
High power
mode
boosting
20
EPSON
Rev.1.0
S1D17E01 Series
Operating voltage range: VDD-VOUT (Master mode)
As shown in the figures below, the VOUT voltage must be set within the VDD-VOUT operating voltage range using
an appropriate amplifying method. Be sure to maintain the relationship of VOUT > V0 to avoid display failure.
Since the|VOUT-V0|voltage is determined based on the LCD panel to be used, it is recommended that it be set
after checking the LCD module.
Operating Voltage Range When Primary and Secondary Boosting Circuits Are Used
40
36
35
32.4
30
25
Operating voltage
range
20
15
11
10
5
0
2.7
0
1
2
3
4
5
6
VDD [V]
Operating Voltage Range When Only Secondary Boosting Circuit Is Used
40
36
35
30
Operating voltage range
25
20
16.2
15
11
10
5
0
2.7
0
1
2
3
4
5
6
VDD [V]
Rev.1.0
EPSON
21
S1D17E01 Series
Operating voltage range: VDD-V0 (Slave mode)
As shown in the figures below, the V0 voltage must be set within the VDD-V0 operating voltage range.
40
36
35
Operating voltage
30
range
25
20
15
11
10
5
0
2.7
0
1
2
3
4
5
6
7
VDD [V]
22
EPSON
Rev.1.0
S1D17E01 Series
9.3 AC Characteristics
9.3.1 Power supply circuit input timing characteristics
ꢂReset timing characteristics
RW
t
POR
f
r
t
t
tRES
Internal
circuit status
Reset period
Normal operation
VDD = 4.5 to 6.0V, Ta = -25 to +85°C
Item
Reset time
Symbol
Condition
Min.
Max.
Unit
ns
tRES
tRW
tr
250
Reset LOW pulse width
Input signal rise time
Input signal fall time
250
ns
50
50
ns
tf
ns
VDD = 2.7 to 4.5V, Ta = -25 to +85°C
Item
Symbol
Condition
Min.
Max.
Unit
ns
Reset time
tRES
tRW
tr
500
Reset LOW pulse width
Input signal rise time
Input signal fall time
500
ns
50
50
ns
tf
ns
Rev.1.0
EPSON
23
S1D17E01 Series
ꢂData bus write characteristics
tf
tr
WR
WRL
DSW
t
t
tDHW
EV0 to EV5
VDD = 4.5 to 6.0V, Ta = -25 to +85°C
Item
Symbol
tWRL
tDSW
tDHW
tr
Condition
Min.
60
Max.
Unit
ns
WR LOW level width
Data setup time
60
ns
Data hold time
10
ns
Input signal rise time
Input signal fall time
50
50
ns
tf
ns
VDD = 2.7 to 4.5V, Ta = -25 to +85°C
Item
Symbol
tWRL
tDSW
tDHW
tr
Condition
Min.
60
Max.
Unit
ns
WR LOW level width
Data setup time
60
ns
Data hold time
10
ns
Input signal rise time
Input signal fall time
50
50
ns
tf
ns
24
EPSON
Rev.1.0
S1D17E01 Series
9.3.2 Common driver input timing characteristics
FR
*1
tWCLH
DFR
t
tf
tWCLL
YSCL
tr
tCCL
DLS
t
tDLH
DIO1
DIO2
(IN)
VDD = 4.5 to 6.0V, Ta = -25 to +85°C
Item
Symbol
Condition
Min.
400
25400
60
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MS = LOW: Slave mode
MS = HIGH: Master mode
MS = LOW: Slave mode
MS = HIGH: Master mode
MS = LOW: Slave mode
MS = HIGH: Master mode
YSCL cycle
tCCL
tWCLH
tWCLL
YSCL HIGH pulse width
YSCL LOW pulse width
400
330
25000
50
Data setup time
Data hold time
Input signal rise time
Input signal fall time
tDLS
tDLH
tr
40
50
50
tf
VDD = 2.7 to 4.5V, Ta = -25 to +85°C
Item
Symbol
Condition
Min.
800
25400
80
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MS = LOW: Slave mode
MS = HIGH: Master mode
MS = LOW: Slave mode
MS = HIGH: Master mode
MS = LOW: Slave mode
MS = HIGH: Master mode
YSCL cycle
tCCL
YSCL HIGH pulse width
YSCL LOW pulse width
tWCLH
tWCLL
400
660
25000
90
Data setup time
Data hold time
Input signal rise time
Input signal fall time
tDLS
tDLH
tr
70
50
50
tf
*1 tDFR: Set in the range that the On output waveform remains normal when the FR signal change point and
the LP signal fall timing are basically 0ns.
Rev.1.0
EPSON
25
S1D17E01 Series
9.3.3 Common driver output timing characteristics
FR
YSCL
tpdYDO
DIO1
DIO2
(IN)
tpdYSCL
______
DSPOF
tpdFR
tpdXDSP
On
(COM)
VDD = 4.5 to 6.0V, V0 = 11.0 to 36.0V, Ta = -25 to +85°C
Item
Symbol
tpdYDO
tpdYSCL
tpdXDSP
tpdFR
Condition
Min.
Max.
100
800
800
800
Unit
CL = 15pF
YSCL fall → DIO output delay time
ns
YSCL fall → ON output delay time
ns
______
CL = 50pF
DSPOF → ON output delay time
FR → ON output delay time
ns
ns
VDD = 2.7 to 4.5V, V0 = 11.0 to 36.0V, Ta = -25 to +85°C
Item
Symbol
tpdYDO
tpdYSCL
tpdXDSP
tpdFR
Condition
Min.
Max.
Unit
YSCL fall → DIO output delay time
CL = 15pF
200
ns
YSCL fall → ON output delay time
1200
1200
1200
ns
______
CL = 50pF
DSPOF → ON output delay time
FR → ON output delay time
ns
ns
26
EPSON
Rev.1.0
S1D17E01 Series
10. LCD DRIVE POWER SUPPLY
Since the voltage of the LCD drive system of this LSI is high, if the voltage is applied to the LCD drive system
while the logic system power is floating or lower than the function voltage range (VDD=2.7 to 6.0V), and LCD
drive signal is output before the applied voltage of the LCD drive is stabilized, the LSI may be permanently
broken with overcurrent.
______
It is recommended that the display-off function (DSPOF) be used to keep the LCD drive output voltage at the
VSS level until the LCD drive voltage is stabilized.
When turning the power on and off, observe the following sequences:
______
Power ON: Logic system ON → LCD drive system ON → Display ON (DSPOF = HIGH)
(Built-in power supply ON: Boosting)
______
Power OFF: Display OFF (DSPOF = LOW) → LCD drive system OFF
(Built-in power supply OFF: Boosting stopped)
→
Discharge (DC = LOW) → Logic system OFF
ꢂBuilt-in power supply ON sequence
To turn the built-in power supply on, it is recommended that the following sequences be observed:
VDD
Internal Boosting clock operation
POR
DC
YSCL
______
LOW→HIGH after V0 to V4
power supplies are stabilized
DSPOF
V0,V1,V4,VSS
Common
V
SS
Common driver operation
V0
V1
V2
V3
V4
Power supply output
VSS
Boosting
* The time to stabilization for the LCD drive power V0, V1, V2, V3 and V4 depends on the LCD module.
During this period, set common driver scan pulse input DI01 or DI02 to the VSS level (check the condition on
the actual module).
Reference data: Rise time of
built-in power supply
1500 ms
Setting condition
VDD=3V
1000 ms
500 ms
0 ms
fYSCL=11.2kHz
Boosting capacitor =2.2µF
2 µF
3 µF
4 µF 5 µF
0 µF 1 µF
Capacity of V0 to V4
Rev.1.0
EPSON
27
S1D17E01 Series
ꢂBuilt-in power supply OFF sequence
To turn the built-in power supply off, it is recommended that the following sequence be observed to set the
system in the power save state beforehand so that the residual power is discharged from the LCD panel, power
supply pins and others.
Power OFF
2.7V
VDD
t
L
Internal Boosting clock
POR
DC
YSCL
______
DSPOF
V0,V1,V4,VSS
Common
output
SS
V
Common driver operation
t
H
Rough guideline: Lower than
liquid crystal Vth (1.0[V])
0
V
1
V
Power
supply
output
V2
V3
4
VSS
V
Boosting
Residual power discharged
* Set the tL so that the relationship of tL > tH is protected.
* The discharge time for residual charge depends on the LCD module.
(Confirm with the actual module).
Reference data: Fall time of built-in power supply
500 ms
400 ms
300 ms
200 ms
100 ms
0 ms
Setting condition
VDD=3V
fYSCL=11.2kHz
Boosting capacitor =2.2µF
0 µF
1 µF
2 µF
3 µF
4 µF
5 µF
Capacity of V0 to V4
ꢂON/OFF sequence when using common driver with external power supply
t1, t2, t3 > 0 sec
V0
V1,V4
t1
t2
VDD
VSS
t3
______
t3
DSPOF
28
EPSON
Rev.1.0
S1D17E01 Series
11. EXAMPLES OF CONNECTION
ꢅ320 × 240 dot
DIO1
DIO1
YSCL
YSCL
FR
DSPOF
FR
DSPOF
SHL
______
______
S1D17E01(1)
(master mode)
12-times boosting
BIAS1
BIAS2
BIAS3
EV0 to EV5
WR
COM0
EV0 to
EV5
WR
DC
COM159
DC
POR
POR
MS
HPM
DIO2
320 × 240 dot
1/320 duty
DIO1
YSCL
FR
______
DSPOF
SHL
S1D17E01(2)
(slave mode)
BIAS1
BIAS2
BIAS3
EV0 to EV5
WR
COM0
COM159
DC
POR
MS
HPM
DIO2
…..
…..
SEG0
DMS
SEG119
SEG0
DMS
SEG119
S/C
S/C
S1D17A07(1)
(segment mode)
S1D17A07(2)
(segment mode)
EIO1
SHL
EIO2
EIO1
SHL
EIO2
XSCL
D0 to D7
Rev.1.0
EPSON
29
S1D17E01 Series
ꢅ240 × 240 dot
DIO1
DIO1
YSCL
YSCL
FR
DSPOF
FR
DSPOF
SHL
______
______
S1D17E01(1)
(master mode)
BIAS1
BIAS2
BIAS3
EV0 to EV5
WR
10-times boosting
COM0
EV0 to
EV5
WR
COM159
DC
DC
POR
POR
240 ꢆ 240 dot
MS
HPM
1/240 duty
DIO2
EIO1
LP
COM0
S1D17A07(1)
(common mode)
FR
______
DSPOF
SHL
COM79
COM80
XSCL
DMS
S/C
COM119
EIO2
…..
…..
SEG0
DMS
SEG119
SEG0
DMS
SEG119
S/C
S/C
S1D17A07(2)
S1D17A07(3)
(segment mode)
(segment mode)
EIO1
SHL
EIO2
EIO1
SHL
EIO2
XSCL
D0 to D7
30
EPSON
Rev.1.0
S1D17E01 Series
ꢅ160 × 240 dot
DIO1
DIO1
YSCL
YSCL
FR
DSPOF
FR
DSPOF
______
______
S1D17E01(1)
(master mode)
8-times boosting
SHL
BIAS1
BIAS2
BIAS3
EV0 to EV5
WR
COM0
160ꢆ240 dot
EV0 to
EV5
1/160 duty
WR
DC
COM159
DC
POR
POR
MS
HPM
DIO2
…..
…..
SEG0
DMS
SEG119
SEG0
DMS
SEG119
S/C
S/C
S1D17A07(1)
S1D17A07(2)
(segment mode)
(segment mode)
EIO1
SHL
EIO2
EIO1
SHL
EIO2
XSCL
D0 to D7
ꢅ160 × 120 dot
DIO1
DIO1
YSCL
YSCL
FR
DSPOF
FR
DSPOF
______
______
S1D17E01(1)
SHL
(master mode)
BIAS1
BIAS2
BIAS3
EV0 to EV5
WR
8-times boosting
COM0
EV0 to
EV5
WR
160ꢆ120 dot
1/160 duty
COM159
DC
DC
POR
POR
MS
HPM
DIO2
…..
SEG0
DMS
SEG119
S/C
S1D17A07(1)
(segment mode)
EIO1
SHL
EIO2
XSCL
D0 to D7
Rev.1.0
EPSON
31
S1D17E01 Series
12. NOTES
When using these development specifications, note the following points:
1. The contents of these development specifications are subject to change without notice for improvement.
2. There is no representation or warranty that anything made in accordance with this material will be free from
any patent or copyright infringement of a third party.
Examples shown in these development specifications are for understanding our products, and we are not
responsible for any circuit problems that may occur when using them.
“Large” or “Small” in the characteristics table refers to the relationship on a numbered line.
3. No part of this material may be reproduced or duplicated in any form or by any means without the written
permission of Seiko Epson.
The following S1D17E01 series handling notes must be used.
IC handling notes on light:
As a semiconductor chip is principally identical to a solar cell, its performance may change if exposed to
bright light. Therefore, the IC may malfunction if exposed to light.
1. Design and mount the IC so that it is not exposed to light during actual operation.
2. In the test process, check the design and mounting of the IC so that it is not exposed to light.
3. Take all surfaces, top, bottom and sides, of the IC chip into consideration when blocking out light.
IC handling notes on ambient noise and others:
1. The internal state of the S1D17E01 series may change if excessive ambient noise is inserted. Measures
are required to prevent noise generation or influence in terms of mounting and the system itself.
2. It is recommended that the operating state be periodically refreshed (by means of electronic control, for
example) to avoid spike noise.
32
EPSON
Rev.1.0
相关型号：
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