S1F81100F00A00M [SEIKO]
SWITCHING CONTROLLER, 1200kHz SWITCHING FREQ-MAX, PQFP48, 4 X 4 MM, QFP12-48;
| 型号： | S1F81100F00A00M |
| 厂家： | 
SEIKO EPSON CORPORATION |
| 描述： | SWITCHING CONTROLLER, 1200kHz SWITCHING FREQ-MAX, PQFP48, 4 X 4 MM, QFP12-48 开关 |
| 文件： | 总79页 (文件大小：1106K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
-
MF1521 03
Power Supply IC
S1F81100
Technical Manual
NOTICE
No part of this material may be reproduced or duplicated in any form or by any means without the written
permission of Seiko Epson. Seiko Epson reserves the right to make changes to this material without notice.
Seiko Epson does not assume any liability of any kind arising out of any inaccuracies contained in this material
or due to its application or use in any product or circuit and, further, there is no representation that this material
is applicable to products requiring high level reliability, such as, medical products. Moreover, no license to
any intellectual property rights is granted by implication or otherwise, and there is no representation or warranty
that anything made in accordance with this material will be free from any patent or copyright infringement of a
third party. This material or portions thereof may contain technology or the subject relating to strategic
products under the control of the Foreign Exchange and Foreign Trade Law of Japan and may require an export
license from the Ministry of International Trade and Industry or other approval from anther government agency.
©SEIKO EPSON CORPORATION 2003, All rights reserved.
Intel is registered trademark of Intel Corporation.
XScale is trademark of Intel Corporation.
All other product names mentioned herein are trademarks and/or registered trademarks of their respective
companies.
Configuration of product number
ꢀDEVICES
S1
F
81100
F
00A0
00
Packing specifications
00: Besides tape & reel
0A: TCP BL 2 directions
0B: Tape & reel Back
0C: TCP BR 2 directions
0D: TCP BT 2 directions
0E: TCP BD 2 directions
0F: Tape & reel FRONT
0G: TCP BT 4 directions
0H: TCP BD 4 directions
0J: TCP SL 2 directions
0K: TCP SR 2 directions
0L: Tape & reel LEFT
0M:TCP ST 2 directions
0N: TCP SD 2 directions
0P: TCP ST 4 directions
0Q: TCP SD 4 directions
0R: Tape & reel RIGHT
99: Specs not fixed
Specifications
Shape
(F : QFP)
Model number
Model name
(F : Power Supply)
Product classification
(S1:Semiconductors)
CONTENTS
1. DESCRIPTION....................................................................................................................................1
1.1 Features .....................................................................................................................................1
1.2 Block Diagram............................................................................................................................2
1.3 Package Dimensions and Pin Assignment................................................................................4
1.4 Pin Descriptions .........................................................................................................................6
1.5 Mask Options .............................................................................................................................8
2. INPUT VOLTAGE AND INITIAL RESET............................................................................................9
2.1 Input Voltage ..............................................................................................................................9
2.1.1 Main Battery <VIN>.......................................................................................................9
2.1.2 Sub-Battery <VBAK> .....................................................................................................9
2.1.3 Constant Voltage for Internal Circuits <VD1>...............................................................9
2.1.4 Reference Voltage for Internal Circuits <VREF>.........................................................10
2.1.5 Voltage for External Interface Pins <BATT_VCC>......................................................10
2.2 Initial Reset...............................................................................................................................12
2.2.1 Reset Input Pin <XRST>............................................................................................12
2.2.2 Reset Output Pin <nRESET> ....................................................................................12
2.3 Test Pin <XTEST0>..................................................................................................................12
3. REGULATOR AND OPERATION ....................................................................................................13
3.1 CH-1 (VCC1) Output Voltage.....................................................................................................14
3.1.1 Main Regulator (PWM Controller)..............................................................................14
3.1.2 Sub-Regulator (Backup Regulator)............................................................................14
3.1.3 Light-Load Mode Function .........................................................................................15
3.1.4 Soft Start Function .....................................................................................................16
3.1.5 Output Voltage Setting Function ................................................................................16
3.1.6 Power OFF Function..................................................................................................19
3.1.7 Power Good Function ................................................................................................20
3.1.8 CH-1 (VCC1) Mask Options of Output Voltage ...........................................................20
3.1.9 CH-1 (VCC1) Output Voltage Proof Function..............................................................20
3.2 CH-2 (VCC2) Output Voltage.....................................................................................................21
3.2.1 Main Regulator (PWM Controller)..............................................................................21
3.2.2 Sub-Regulator (Backup Regulator)............................................................................21
3.2.3 Light-Load Mode Function .........................................................................................22
3.2.4 Soft Start Function .....................................................................................................23
3.2.5 Short-Circuit Proof Function.......................................................................................23
3.2.6 Power OFF Function..................................................................................................23
3.2.7 Power Good Function ................................................................................................24
3.2.8 CH-2 (VCC2) Mask Options Concerning Output Voltage............................................24
3.3 CH-3 (VCC3) Output Voltage.....................................................................................................25
3.3.1 Main Regulator (PWM Controller)..............................................................................25
3.3.2 Sub-Regulator (Backup Regulator)............................................................................25
3.3.3 Light-Load Mode Function .........................................................................................26
3.3.4 Soft Start Function .....................................................................................................27
3.3.5 Short-Circuit Proof Function.......................................................................................27
3.3.6 Power OFF Function..................................................................................................27
3.3.7 Power Good Function ................................................................................................28
3.3.8 CH-3 (VCC3) Mask Options Concerning Output Voltage............................................28
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3.4 CH-4 (VCC4) Output Voltage.....................................................................................................29
3.4.1 Main Regulator (Series Regulator) ............................................................................29
3.4.2 Power OFF Function..................................................................................................29
3.5 Output Timing of Regulator on Initial Startup...........................................................................30
4. OPERATION MODES.......................................................................................................................31
4.1 Description of Each Operation Mode.......................................................................................31
4.2 Sleep Mode..............................................................................................................................31
4.2.1 Transitioning to and Canceling the Sleep Mode........................................................31
4.2.2 Transitioning to and Canceling the Sleep Mode When CH-1 Voltage Change
is Made.......................................................................................................................32
4.2.3 Transitioning to and Canceling the Sleep Mode When CH-1 Voltage Change
is not Made.................................................................................................................33
4.2.4 Mask Options Associated with the Sleep Mode ........................................................34
4.3 Deep Sleep Mode ....................................................................................................................36
4.3.1 Transitioning to and Canceling the Deep Sleep Mode ..............................................36
4.3.2 Mask Options Associated with the Deep Sleep Mode...............................................37
4.4 Ultra-Power-Saving Mode........................................................................................................38
5. I2C CONTROLLER ...........................................................................................................................39
5.1 Description ...............................................................................................................................39
5.1.1 Basic Specifications ...................................................................................................39
5.1.2 Start and Stop Conditions..........................................................................................39
5.1.3 Data Transfer (command format)...............................................................................40
5.1.4 Behavior During Malfunction Conditions....................................................................41
5.2 Control Address & Control Data List........................................................................................42
6. AUXILIARY FUNCTIONS AND OPERATIONS...............................................................................46
6.1 Oscillator Circuit/Clock Selecting Function..............................................................................46
6.2 Output Voltage Determining Function......................................................................................47
6.3 Input Voltage Determining Function.........................................................................................48
6.4 General-Purpose I/O Ports ......................................................................................................49
6.4.1 Description .................................................................................................................49
6.4.2 Mask Options Associated with the General-Purpose I/O Ports.................................50
7. BASIC EXTERNAL CONNECTION DIAGRAMS............................................................................51
8. ELECTRICAL CHARACTERISTICS ...............................................................................................53
9. PACKAGE ........................................................................................................................................66
10. PAD LAYOUT ...................................................................................................................................68
11. TERMINAL EQUIVALENT CIRCUIT................................................................................................70
APPENDIX SELECTION OF PWM CONTROLLER’S EXTERNAL COMPONENTS........................72
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1. DESCRIPTION
The S1F81100 is a power IC for the system equipped with a 4-channel regulator. Batteries such as lithium ion
batteries are used to generate each output voltage via external devices. The 4-channel regulator consisting of
PWM controller with 3 channels and series regulator with 1 channel are independent of each other and can be
controlled separately.
On this series, an I2C controller (for the slave function), input and output voltage detecting functions,
general-purpose I/O pins, etc. are provided.
Moreover, this series exhibits power saving performance by effectively using the normal, Sleep, Deep Sleep and
ultra-energy-saving modes provided as operation mode according to the situation.
The S1F81100 is also equipped with an I/O pin dedicated for interface to Intel’s PXA250/210 (XScaleTM)
processor, and is most suitable for use as a power supply unit for mobile devices such as PDAs equipped with
an XScaleTM and smart-phone.
Product number
Shipping forms
Die form
QFP12-48 Package
QFN7-48 Package
S1F81100D0 000
**
S1F81100F0 000
**
S1F81100F5 000
**
Note: The above is replaced with a serial number depending on the option.
*
ꢀ Product List
The following optional products (including those under development) are currently prepared for the S1F81100.
For the mask options, refer to Section 1.5.
Table 1.1 Product List
Mask Option
Model
Package
[No.1]
CH-2
3.3V
[No.2]
[others]
CH-3
S1F81100F0E1000
* S1F81100F0F0000
* Under development
QFP12-48
QFP12-48
3.3V
2.5V
standard
standard
3.3V
1.1 Features
The features of the S1F81100 include the following:
ꢀInput voltage:
ꢀRegulator:
VIN
3.3V to 5.5V (if at least either VCC2 or VCC3 is 3.3V) (Note 1)
2.8V to 5.5V (if both VCC2 and VCC3 are 2.5V or lower)
Note 1: When VIN falls to around 3.3V, output falls below 3.3V.
4-channel
CH-1 (VCC1): PWM controller
High-speed synchronized rectification type PWM controller
(Connected to an external component to configure a switching regulator.)
Features include a fast response circuit using a current/voltage returning system, more compact external
components thanks to a fast clock, and a sub-regulator (mask options).
Output voltage
1.5/1.4/1.3/1.2/1.1/1.0/0.9/0.8V
Select one value from above via the I2C controller.
Accuracy: within ±5%
Output current
Main
Sleep mode
Operating mode Max.: 500mA
Sub [mask options] Max.: 20mA
OFF
CH-2 (VCC2): PWM controller
High-speed synchronized rectification type PWM controller
(Connected to an external component to configure a switching regulator.)
Features include a fast response circuit using a current/voltage returning system, a short-circuit-proof circuit,
more compact external components thanks to a fast clock, and a sub-regulator.
Output voltage
3.3/2.5/1.8V: One is to be selected from the mask options (1.8V is under development).
Accuracy: within ±5%
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S1F81100 Technical Manual
Output current
Main
Sub
Deep Sleep mode
Operating mode
Max.: 10mA
OFF
Max.: 1A
CH-3 (VCC3): PWM controller
High-speed synchronized rectification type PWM controller
(Connected to an external component to configure a switching regulator.)
Features include a fast response circuit using a current/voltage returning system, a short-circuit-proof circuit,
more compact external components thanks to a fast clock, and a sub-regulator.
Output voltage
3.3/2.5/1.8V: One is to be selected from the mask options (1.8V is under development).
Accuracy: within ±5%
Output current
Main
Sub
Deep Sleep mode
Operating mode
Max.: 10mA
OFF
Max.: 1A
CH-4 (VCC4): Series regulator
Low power consumption type series regulator
Output voltage
Output current
1.5/1.4/1.3/1.2/1.1/1.0/0.9/0.8V…Same voltage as in CH-1 setting
Sleep mode OFF
Operating mode 20mA (@VCC3 = 3.3V), 5mA (@VCC3 = 2.5V)
Typ.: 0.7µA(@VIN = 4.0V)
ꢀShutdown current:
ꢀCurrent consumption:
Normal mode 2mA(Typ.)
Sleep mode
100µA(Typ.)
ꢀExternal interface:
Built-in interfaces in the I2C controller (SCL, SDA and AD_EN; for the
slave function only).
ꢀOutput voltage detecting function: 1 channel (nVCC_FLT)
The output of power good circuit will be LOW if one of CH1 to CH3
output is out of defined value.
ꢀInput voltage detecting function: 1 channel (nBAT_FLT)
The LOW output is applied if the detected input voltage fails to comply
with the specs.
ꢀResetting function:
ꢀSleep function:
1 channel (XRST(I),nRESET(O))
1 channel (PWR_EN,WUP)
1.2 Block Diagram
The following is a block diagram of the S1F81100.
[****]
[****]
[****]
****
: Input Power Terminal
: Backup Power Terminal
: GND Terminal
: VIN Level I/O Terminal
: VCC1 Level I/O Terminal
: VCC2 Level I/O Terminal
: VCC3 Level I/O Terminal
: VCC4 Level I/O Terminal
: BATT_VCC Level I/O Terminal
: Analog Terminal
****
****
****
****
****
****
Fig.1.2.1 Notation of Pin Voltage Levels in Fig.1.2.2.
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[VIN
]
[VIN1
]
[VSS
]
V
CC1
CH-1
PWM cont.
Series Reg.
Power-Good
Soft start
Err. Dtct.
etc.
CLKIN
FB1M
SW1OH
SW1OL
SSCAP1
OSC
SDA
SCL
[VSS1
]
AD_EN
P03
[VIN2
]
P02
V
CC2
CH-2
P01
PWM cont.
Series Reg.
Power-Good
Soft start
Err. Dtct.
etc.
P00
FB2M
SW2OH
SW2OL
SSCAP2
XRST
Reset
Cont.
nRESET
[VSS2
]
V
Dtct.
IN
nBAT_FLT
nVCC_FLT
[VIN3
]
V
CC3
CH-3
VOUT
Dtct.
PWM cont.
Series Reg.
Power-Good
Soft start
Err. Dtct.
etc.
FB3M
SW3OH
SW3OL
SSCAP3
PWR_EN
WUP
Sleep
Cont.
Int. Power
Reg.
V
D1
[VSS3
]
V
CC4
Ref. Power
Reg.
V
REF
CH-4
FB4
XSDWN
XTEST0
BATT_VCC
[VBAK
Test
Cont.
Backup
Switch
]
Fig.1.2.2 S1F81100 Block Diagram
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S1F81100 Technical Manual
1.3 Package Dimensions and Pin Assignment
[QFP12-48]
9±0.4
7±0.1
9±0.4
36
25
37
24
INDEX
48
13
1
12
+0.1
0.5
0.18
-0.05
0.125±0.05
0°
10°
0.5±0.2
1
Unit: mm
Fig.1.3.1 QFP12-48 Package Diagram
Table 1.3.1 QFP12-48 Pin Assignment
Pin #
1
2
3
4
5
6
7
8
Pin #
13
14
15
16
17
18
19
20
21
22
23
24
Pin #
25
26
27
28
29
30
31
32
33
34
35
36
Pin #
37
38
39
40
41
42
43
44
45
46
47
48
Pin name
FB3M
SW3OL
VSS3
VCC1
VIN1
SW1OH
FB1M
SW1OL
VSS1
Pin name
FB4
VCC4
VIN
XRST
XTEST0
XSDWN
AD_EN
TCLK(N.C.)
CLKIN
VSS
Pin name
VD1
Pin name
XPOR(N.C.)
VBAK
P02
P03
VCC2
VIN2
SW2OH
FB2M
SW2OL
VSS2
VCC3
VIN3
BATT_VCC
PWR_EN
WUP
nRESET
nBAT_FLT
nVCC_FLT
P00
9
10
11
12
P01
SCL
SDA
SSCAP3
SSCAP2
SSCAP1
TIREF(N.C.)
VREF
SW3OH
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S1F81100 Technical Manual
[QFN7-48]
7
6.75
+0.18
0.42
−0.18
13
24
12
25
1
36
48
37
0.5
Fig.1.3.2 QFN7-48 Package Diagram
Table 1.3.2 QFN7-48 Pin Assignment
Pin #
1
Pin #
13
Pin #
25
Pin #
37 XPOR(N.C.)
Pin name
FB3M
Pin name
FB4
Pin name
VD1
Pin name
2
3
4
5
6
7
8
9
SW3OL
VSS3
VCC1
VIN1
SW1OH
FB1M
SW1OL
VSS1
SSCAP3
SSCAP2
SSCAP1
14
15
16
17
18
19
VCC4
VIN
XRST
XTEST0
XSDWN
AD_EN
26
27
28
29
30
31
VBAK
38
39
40
41
42
P02
P03
VCC2
BATT_VCC
PWR_EN
WUP
nRESET
nBAT_FLT 43
VIN2
SW2OH
FB2M
SW2OL
VSS2
VCC3
VIN3
20 TCLK(N.C.) 32
21
22
23 TIREF(N.C.) 35
24
nVCC_FLT
P00
44
45
46
47
48
CLKIN
VSS
33
34
10
11
12
P01
SCL
SDA
VREF
36
SW3OH
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S1F81100 Technical Manual
1.4 Pin Descriptions
Table 1.4.1(a) Pin Descriptions
[Power supply/controlling pins]
Pin name
VIN
I/O
Level
Function
Voltage (+) input pin
Voltage (-) input pin
VSS
Interface power supply input (Short-circuited to VCC2 outside
IC)
VBAK
VD1
VREF
Internal constant voltage output pin
Reference voltage output pin
Interface power supply (Short-circuited to VCC2 outside IC)
Output voltage detection result output pin
Input voltage detection result output pin
System reset signal output pin
Sleep state setting input pin
Sleep state flag output pin
BATT_VCC
nVCC_FLT
nBAT_FLT
nRESET
PWR_EN
WUP
O
O
O
I
O
I
BATT_VCC
BATT_VCC
BATT_VCC
BATT_VCC
BATT_VCC
VCC2
CLKIN
External clock input pin
XRST
I
VIN
Resetting input pin
XTEST0
XSDWN
P00 to 01
P02 to 03
SCL
I
I
VIN
Testing input pin
Ultra-power-saving mode setting input pin
General-purpose I/O pin
VIN
I/O
I/O
I
I/O
I
VCC2
VIN
General-purpose I/O pin
VCC2
I2C clock input pin
SDA
AD_EN
VCC2
I2C data I/O pin
VIN
I2C Address enabling input pin
[CH-1 Related Pins]
Pin name
VIN1
I/O
Function
Voltage (+) input pin
SW1OH
SW1OL
SSCAP1
FB1M
VCC1
VSS1
O
O
P-ch power MOS transistor drive signal output pin
N-ch power MOS transistor drive signal output pin
CH-1 soft start setting pin
Output current feedback input pin
Output voltage feedback input pin [sub-regulator output pin]
Voltage (-) input pin
I
I
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Table 1.4.1(b) Pin Description
[CH-2 Related Pins]
Function
Pin name
VIN2
I/O
Voltage (+) input pin
SW2OH
SW2OL
SSCAP2
FB2M
VCC2
VSS2
O
O
P-ch power MOS transistor drive signal output pin
N-ch power MOS transistor drive signal output pin
CH-2 soft start setting pin
Output current feedback input pin
Output voltage feedback input pin [sub-regulator output pin]
Voltage (-) input pin
I
I
[CH-3 Related Pins]
Function
Voltage (+) input pin
Pin name
VIN3
I/O
SW3OH
SW3OL
SSCAP3
FB3M
VCC3
VSS3
O
O
P-ch power MOS transistor drive signal output pin
N-ch power MOS transistor drive signal output pin
CH-3 soft start setting pin
Output current feedback input pin
Output voltage feedback input pin [sub-regulator output pin]
Voltage (-) input pin
I
I
[CH-4 Related Pins]
Function
VCC4 voltage output pin
Feedback input pin
Pin name
VCC4
I/O
O
I
FB4
Notes: The following pins are dedicated to test use. Always indicate as N.C. when using.
Operation without the indication of N.C. cannot be guaranteed.
XPOR, TCLK, TIREF
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S1F81100 Technical Manual
1.5 Mask Options
This section describes the mask options. These can be combined freely according to the user’s needs.
Refer to the following chapter for further information on each mask options.
[No.1] CH-2(VCC2) Output voltage
ꢁ 1. 3.3V
ꢂ 2. 2.5V
ꢂ 3. 1.8V (under development)
[No.2] CH-3(VCC3) Output voltage
ꢁ 1. 3.3V
ꢂ 2. 2.5V
ꢂ 3. 1.8V (under development)
[No.3] Sleep mode one-touch recovery function
ꢁ 1. Disable
ꢂ 2. Enable
[No.4] Sleep mode Ch-2 main regulator operation
ꢂ 1. ON
ꢁ 2. OFF
[No.5] Sleep mode Ch-3 main regulator operation
ꢂ 1. ON
ꢁ 2. OFF
[No.6] Deep Sleep mode Ch-2 sub-regulator operation
ꢂ 1. Enable (CH-2 sub-regulator, ON in Deep Sleep mode)
ꢁ 2. Disable (CH-2 sub-regulator, OFF in Deep Sleep mode) *1
[No.7] CH-1(VCC1) Sub-regulator function
ꢁ 1. Disable
ꢂ 2. Enable
ꢁ is for standard specification.
*1 In the Deep Sleep mode, CH-2 output stops and VCC2 potential lowers down to the GND level. For this
reason, once the unit enters the Deep Sleep mode, it can be restored from this mode only by LOW level
input via the XRST pin. When power is externally supplied to VCC2 (CH-2) in the Deep Sleep mode,
input via PWR_EN is also accepted.
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2. INPUT VOLTAGE AND INITIAL RESET
This chapter describes the input voltage specifications and the initial reset specifications of the S1F81100.
2.1 Input Voltage
The S1F81100 requires power supply for its operation and internally generates internal constant voltage VD1
and internal reference voltage VREF from its main battery. The external interface I/O voltage BATT_VCC and
VBAK pins are required to be short-circuited to the VCC2 outside the S1F81100.
This section describes the detailed specifications for each.
V
V
V
V
IN
V
D1
IN1
IN2
IN3
Regulator
Other
Peripheral
Circuits
(oscillation, I2C
digital circuit
etc.)
VD1
Main
Battery
CH-1
CH-2
CH-3
CH-4
VSS1
VSS2
VSS3
VSS
VCC1
VCC2
VCC3
VCC4
BATT_VCC
VBAK
Fig.2.1.1 Power Supply System Block Diagram
2.1.1 Main Battery <VIN>
The input voltage range of the S1F81100’s main battery is as follows:
3.3 to 5.5V
2.8 to 5.5V
If at least either VCC2 or VCC3 is 3.3 V.
If both VCC2 and VCC3 are 2.5V or lower.
The S1F81100 is activated if a single power supply with the voltage of the above range is provided between VIN
and VSS and generates 4-channel output voltage as well as constant voltage VD1 for the internal circuits.
2.1.2 Sub-Battery <VBAK>
Short-circuit the VBAK pin of the S1F81100 to the VCC2 outside the S1F81100.
2.1.3 Constant Voltage for Internal Circuits <VD1>
The S1F81100 generates constant voltage VD1 for the internal circuits from its main battery, eliminating the
need for external input of such voltage. To stabilize the voltage, connect a 0.1µF external capacitor to the VD1
pin.
Notes: Driving an external load with internal constant voltage VD1 is not allowed.
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S1F81100 Technical Manual
2.1.4 Reference Voltage for Internal Circuits <VREF>
The S1F81100 generates reference voltage VREF for the internal circuits from its main battery. Voltage VREF is
used as the reference voltage for operations of the internal circuits such as the PWM controller, and is generated
in the S1F81100. This voltage does not have to be input externally.
To stabilize the output voltage, connect a 0.1µF external capacitor to the VREF pin.
While the LOW level is input to the XRST pin, VREF voltage is at the same potential as VIN.
Notes: Driving an external load with internal reference voltage VREF is not allowed.
2.1.5 Voltage for External Interface Pins <BATT_VCC>
The S1F81100 is equipped with the following external interface pins (which are provided for interface to the
external processor):
nVCC_FLT
nBAT_FLT
PWR_EN
WUP
(Output) Output voltage level detecting pin
(Output) Input voltage level detecting pin
(Input) Sleep state setting pin
(Output) Sleep state output pin
nRESET
(Output) Reset output pin
Short-circuit the power BATT_VCC for driving the above interface pins to the VCC2 outside the S1F81100.
Fig.2.1.5.2 shows the external connection diagram.
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CH-2
Regulator
V
CC2
VBAK
BATT_VCC
nVCC_FLT
nBAT_FLT
PWR_EN
WUP
S1F81100
nRESET
Fig.2.1.5.1 The Internal Configuration of BATT_VCC Pin
CH-2
Regulator
V
CC2
BAK
VIN
V
VIN1
VIN2
VIN3
BATT_VCC
nVCC_FLT
nBAT_FLT
PWR_EN
WUP
V
SS
VSS1
VSS2
VSS3
S1F81100
nRESET
Fig.2.1.5.2 External Connection Diagram of BATT_VCC and VBAK Pins
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2.2 Initial Reset
The S1F81100 requires initial reset to initialize its circuits. The following is the initial reset factor:
(1) External initial reset via the XRST pin.
Initial reset initializes the internal circuit of the IC. To initialize the circuits, be sure to perform one of these
actions.
During the initial reset period, the LOW level signal is output from the nRESET pin.
Fig.2.2.1 shows the initial reset circuit diagram.
XRST
nRESET
Counter
Circuit
Power Good
Circuit
Input Voltage
Detection
Circuit
Fig.2.2.1 Initial Reset Circuit Diagram
2.2.1 Reset Input Pin <XRST>
Initial reset can be performed by externally setting the reset (XRST) input pin to LOW level (VSS). After this,
the internal circuits stay in the initial reset state until outputs of all the four channels are activated.
Keep the XRST pin at LOW level for a period of 50µs or longer so that initial resetting can be performed.
Notes: While the LOW level is input to the XRST pin, VREF voltage must be set to the same voltage as VIN.
2.2.2 Reset Output Pin <nRESET>
The S1F81100 can output a reset signal to external devices via the nRESET pin.
The nRESET signal starts outputting the LOW level signal as soon as the S1F81100 unit has entered the initial
reset state, and keeps the LOW level (initial reset state) until all output voltages of the four channels are
activated. When all the output voltages are activated and the input level of the XRST pin attains the HIGH
level (VIN level), the output level of the reset output signal nRESET becomes HIGH (BATT_VCC, VCC2 level).
After the input voltage is turned ON, the nRESET signal maintains the LOW level for around 60 ms after all 4
channels are activated.
2.3 Test Pin <XTEST0>
This pin is used for testing ICs before shipping. In normal operation, XTEST0 should be connected to VIN.
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3. REGULATOR AND OPERATION
The S1F81100 has a regulator with 4 channels (CH-1, CH-2, CH-3 and CH-4) optimally configured for Intel’s
PXA250/210 processors.
CH-1, CH-2 and CH-3 are mounted with PWM controller as a main regulator. PWM controllers can output
stable voltage by configuring a switching regulator connecting external power MOS transistor and coil, etc.
Moreover, each is equipped with a series regulator as a sub (backup) regulator. The current consumption of the
system is controllable based on the load condition by simply setting the sub-regulator to operate when the load
is light.
CH-4 is a series regulator and can output voltage independently.
This chapter provides detailed descriptions of each regulator.
CH-1 (VCC1)
CORE power (VCC) for PXA250/210
Select 1 value from 1.5/1.4/1.3/1.2/1.1/1.0/0.9/0.8V: I2C controller
Main regulator: PWM controller
Sleep mode: OFF, Operating load: 500mA (Max.), Maximum conversion efficiency: about 80%.
Sub-regulator: series regulator [Select available/unavailable in mask options]
CH-2 (VCC2)
Peripheral power (VCCQ) for PXA250/210
3.3/2.5/1.8V: Select 1 value from mask options.
Main regulator: PWM controller
Deep Sleep mode: OFF, Operating load: 1A (Max.), Maximum conversion efficiency: about 90%.
Sub-regulator: series regulator
CH-3 (VCC3)
Memory power (VCCN) for PXA250/210
3.3/2.5/1.8V: Select 1 value from mask options.
Main regulator: PWM controller
Deep Sleep mode: OFF, Operating load: 1A (Max.), Maximum conversion efficiency: about 90%.
Sub-regulator: series regulator
CH-4 (VCC4)
PLL power (PLL_VCC) for PXA250/210
1.5/1.4/1.3/1.2/1.1/1.0/0.9/0.8V (Output value same with the VCC1 set value)
Series regulator
Sleep mode: OFF, Operating load: 20mA (Max.) (@VCC3 = 3.3V)
5mA (Max.) (@VCC3 = 2.5V)
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3.1 CH-1 (VCC1) Output Voltage
This section describes CH-1, a variable output type PWM controller. Fig.3.1.1 shows CH-1’s internal and
external configurations.
S1F81100
V
CC1
IN1
Power
Good
Mask Option
V
Sub-regulator
(backup)
TP1
SW1OH
-
-
+
CL1
Error
AMP
CMP.
FB1M
SW1OL
PWM
Waveform
Drive Circuit
TN1
SD1
CC1
VSS1
PG1
POFF1
LMD1
Power
Manager
V
S1n
Output
Voltage
Control
Circuit
SSCAP1
Soft Start
CS1
Fig.3.1.1 CH-1 Regulator Configuration
3.1.1 Main Regulator (PWM Controller)
The main regulator of CH-1 is a variable output type PWM controller. External components can be connected
to it to form a switching regulator to allow constant voltage to be generated and output from input voltage VIN
(VIN1) and internal constant voltage VD1.
[Configuration of CH-1 Switching Regulator]
Synchronized rectification type switching regulator.
Clock
Approximately 1 MHz (when the internal oscillator circuit is used)
Required external components: P-ch power MOS transistor
TP1
TN1
SD1
CL1
N-ch power MOS transistor
Schottky diode
Coil: 10µH
Stabilizing capacitor (100µF) CC1
Capacitor for soft start CS1
The output value is variable; it can be externally set via the output voltage value selected with one of the VS17
to 10 registers of the I2C controller.
See section 5.2 for details of the VS17 to 10 register.
3.1.2 Sub-Regulator (Backup Regulator)
CH-1 can mount series regulator as a sub-regulator from mask options.
Output value is the same with the main regulator set value.
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Sub-regulator of CH-1 is generated from VCC3 voltage. Therefore, sub-regulator of CH-1 is not activated when
CH-3 is in power OFF state.
3.1.3 Light-Load Mode Function
This function is enabled only when use of sub-regulator of CH-1 is selected from mask options.
In normal operation (normal mode), the main regulator and the sub-regulator are both operating. During
operation of the application, some conditions do not require a large load current. In this case, the mode can be
switched to [Light-load mode].
In light-load mode, the main regulator is OFF and only the sub-regulator is ON. Therefore, the current
consumed by the main regulator can be restrained, effectively saving power for the application.
Switching between the normal and light-load mode is optional in the application. The switching methods of the
2 modes are as follows:
[Switching from normal to light-load mode]
To switch from normal to light-load mode, set the value of the LMD1 register to “1” via the I2C controller.
Consequently, the main regulator of CH-1 is turned OFF and only the sub-regulator operates. Only the
voltage of the sub-regulator is outputted.
[Switching from light-load to normal mode]
To switch from light-load to normal mode, set the value of the LMD1 register to “0” via the I2C controller.
Fig.3.1.3.1 shows the normal and light-load states and the switching method.
Notes: The sub-regulator is not activate when CH-3 is in power OFF state since the sub-regulator of CH-1 is
generated from VCC3.
[CH-1]
Normal Mode
Light-load Mode
From Normal to Light-load
Set LMD1 register to 1 via
I2C.
Main Regulator
Main Regulator
ON
OFF
Sub-Regulator
Sub-Regulator
From Light-load to Normal
Set LMD1 register to 0 via
I2C.
ON
ON
Fig.3.1.3.1 Switching between normal/light-load mode in CH-1
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3.1.4 Soft Start Function
With a capacitor connected to the SSCAP1 pin, CH-1 provides a soft start function that adjusts the rise time of
the power when it is turned on. After a lapse of soft start time, voltage output of CH-1 starts Fig.3.1.4.1
shows the relation between the soft start time and the soft start capacitor capacity (CS1). When voltage output
of CH-1 is used as CORE power supply for the PXA250/210 (XScaleTM) processor, the CORE voltage must rise
to 10 ms, Max. after the PWR_EN input attains the HIGH level. For this reason, 0.01µF is recommended as
the Max. CS1.
Soft Start Time v. s. CSn (Typ.)
CSn [µF]
Fig.3.1.4.1 The Relation between the Soft Start Time and the Soft Start Capacitor Capacity (CS1).
3.1.5 Output Voltage Setting Function
Output voltage of CH-1 can be selected from eight values via the I2C controller externally. The optimal output
voltage can be set according to the operations of the driving device while the application is operating.
See Table.3.1.5.1 for voltages that can be set.
After the input voltage rises and after the initial reset signal is input from the XRST pin, 1.5V is applied.
There are 2 methods of changing the voltage value:
(1) Consecutive transition: Changes the voltage value while in normal mode via I2C.
(2) Step transition: Changes the voltage value after transition to Sleep mode and then canceling it.
The following describes the respective operation.
ꢀConsecutive transition
S1F81100 can change voltage value by consecutive transition by following the procedures below.
1 Rewrite the VS17 to 10 register value via the I2C controller and set a new voltage value.
2 Write “0” in the XC1TRG register via the I2C controller.
3 The VS17 to 10 register value is loaded to CH-1 regulator at this point and CH-1 output voltage changes.
When conducting consecutive transition, CH-1 output voltage value is controllable only via I2C controller.
See section 5.2 for details of the VS17 to 10 and XC1TRG registers.
ꢀStep transition
S1F81100 can change voltage value by step transition by following the procedures below:
1 Rewrite the VS17 to 10 register value via the I2C controller and set a new voltage value.
2 The PWR_EN pin is externally controlled to the LOW level to set the S1F81100 unit to Sleep state.
3 After the unit enters the Sleep state, the S1F81100 unit sets the WUP pin output to the HIGH level.
4 After the WUP pin is externally detected, the PWR_EN pin is set back to the HIGH level, and the S1F81100
is instructed to cancel the Sleep state.
5 The S1F81100 starts recovering from the Sleep state.
6 The WUP signal attains the LOW level.
7 When returning to the normal state, VCC1 attains the new voltage value.
If no new voltage value is set in step 1 above (that is, if the specified voltage is the same as the previous value),
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the WUP signal level does not attain the HIGH level in step 3 above.
See section 5.2 for details of the VS17 to 10 register.
Notes: When transitioning to Sleep state without changing the voltage value (without rewriting the VS17 to 10
register value), setting the PWR_EN pin to LOW does not change the output level of the WUP pin.
The example of controlling the CH-1 output voltage by step transition is shown below.
Connect with a processor mounted with master function of the I2C controller and control the output voltage by
software control.
Fig.3.1.5.1 shows the example of connection with the Intel’s mobile processor PXA250/210. Only the signals
related to changing of CH-1 output voltage is shown in the diagram.
Fig.3.1.5.2 shows a timing chart illustrating the CH-1 output voltage control.
Table.3.1.5.2 describes the procedures of software control from the processor side. By setting and conducting
software control on the controller side following the procedure in the table, VCC1 voltage output value of
S1F81100 is changed.
Table 3.1.5.1 VS17 to 10 Set Value and VCC1 Output Voltage Corresponding Table
VS17 to 10
VCC1
VS17 to 10
VCC1
11111*** B
11110*** B
11101*** B
11100*** B
11011*** B
11010*** B
11001*** B
11000*** B
10111*** B
10110*** B
10101*** B
10100*** B
10011*** B
10010*** B
10001*** B
10000*** B
Setting inhibited
Setting inhibited
Setting inhibited
Setting inhibited
Setting inhibited
Setting inhibited
Setting inhibited
Setting inhibited
Setting inhibited
Setting inhibited
Setting inhibited
Setting inhibited
1.5V
01111*** B
01110*** B
01101*** B
01100*** B
01011*** B
01010*** B
01001*** B
01000*** B
00111*** B
00110*** B
00101*** B
00100*** B
00011*** B
00010*** B
00001*** B
00000*** B
1.2V
1.2V
1.1V
1.0V
0.9V
0.8V
0.8V
0.8V
0.8V
0.8V
0.8V
0.8V
0.8V
0.8V
0.8V
0.8V
1.5V
1.4V
1.3V
PXA250/210
S1F81100
V
CC
VCC1
SDA
SCL
SDA
SCL
PWR_EN
GP[n]
PWR_EN
WUP
(Note: GP[n] indicates general-purpose input port.)
Fig.3.1.5.1 Connection example and PXA250/210 (only parts related to VCC1 control)
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VS17 to 10
A
B
[Digital]
PWR_EN
[Digital]
WUP
[Digital]
less than 1
µs
less than 1µs
nVCC_FLT
[Digital]
less than 1 s
µ
less than 1 s
µ
A
VCC1
B
ꢃ The values in the chart are all typical values for reference.
Fig.3.1.5.2 CH-1 Output Voltage Control Timing on Step Transition
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Table 3.1.5.2 Software Control Procedure for Changing VCC1 Output Voltage
Processor
ex. PXA250/210
Power IC
S1F81100
Status
Operation
Operation
(software/hardware control)
Normal Operation State
Normal
Operation
PWR_EN Pin Output: HIGH
Level
Voltage Output VCC1/VCC4 Output turned ON.
WUP Pin Output: LOW level
[Setting]
Enable input interruption of
GP[n].
c I2C Communication
[Software Control]
I2C
Rewrites the VS17 to VS10
register of the power supply IC
via the I2C controller and sets
the new voltage value.
Command
d Start transition to Sleep Transition to Starts transition to Sleep State.
PWR_EN
Signal
(PWR_EN Pin Control) Sleep
[Software Control]
L
Sets the output of PWR_EN pin
to LOW Level to transit to Sleep
state.
e CORE Voltage OFF
Sleep
Voltage Output VCC1/VCC4 Output OFF.
X
Sets the output of WUP pin to HIGH
level at the same time.
WUP
Signal
H
f Sleep State Cancellation Sleep
Receives interruption signal at
PWR_EN
Signal
Start
Cancellation GP[n] pin and starts cancellation
of Sleep state.
H
[Software (Hardware) Control]
Sets the output of PWR_EN pin
to HIGH level to cancel Sleep.
g CORE Voltage Output
Normal
Operation
Voltage Output VCC1/VCC4 Output ON.
Outputs the newly set voltage value
ON
from this point.
WUP
Signal
Sets output of the WUP pin to LOW
level at the same time.
L
Normal Operation State
Normal
Operation
PWR_EN Pin Output: HIGH
Level
Voltage Output VCC1/VCC4 Output ON.
WUP Pin Output: LOW Level
3.1.6 Power OFF Function
The voltage output of CH-1 can be turned off (powered off) via the I2C controller.
Writing “1” in the POFF1 register assigned to the I2C controller’s register causes the CH-1 output to be turned
off (powered off) and pulled down internally.
The POFF1 register value attains “0” again through one of the following steps, and then voltage output is turned
ON (powered on).
(1) Write “0” in the POFF1 register via the I2C controller.
(2) Perform initial reset.
(3) Turn the input level of the PWR_EN pin to LOW once to cause the Sleep state, then assign the HIGH level
again to the PWR_EN pin to allow recovery from the Sleep state.
See section 5.2 for details of the POFF1 register.
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3.1.7 Power Good Function
CH-1 has a Power Good function. The Power Good function refers to a function that monitors the output
voltage value inside the S1F81100 unit and determines if it is normal or not. If a state approximately 10% or
more below the typical output voltage exceeds approximately 10ms, it is determined to be “abnormal output.”
The result of the Power Good judgement can be read via the PG1 plug (read-only) of the I2C controller.
Moreover, it can be monitored by output level of nVCC_FLT pin.
The Power Good function can be deactivated by writing “0” in the VFLT register on the I2C controller.
See section 5.2 for details of the PG1 flag and VFLT registers.
See section 6.2 for details of the nVCC_FLT pin.
3.1.8 CH-1 (VCC1) Mask Options of Output Voltage
The following items are provided as mask options related to CH-1 output voltage.
[No.7] CH-1 Sub-regulator function
ꢂ 1. Disable
ꢂ 2. Enable
The mask options can be used to enable/disable the CH-1 sub-regulator function.
During operation, if a state which does not require a large load current for CH-1 exists, select “Enable” and if
not, select “Disable”
3.1.9 CH-1 (VCC1) Output Voltage Proof Function
The CH-1 output is provided with a built-in output proof function. When output voltage is continuously
reduced by 10% of the set output voltage approx. 110ms or more, the CH-1 switching regulator circuit operation
stops. The output voltage reduction detection circuit serves as the CH-1 power good detection circuit as well.
Output proof detection time: 110 ± 20 [ms]
Restore from the short-circuit proof mode is possible by input via the RESET pin (XRST).
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3.2 CH-2 (VCC2) Output Voltage
This section describes CH-2, a PWM controller. Fig.3.2.1 shows CH-2’s internal and external configurations.
S1F81100
V
V
CC2
IN2
Power
Good
Sub-
regulator(backup)
TP2
SW2OH
-
-
+
CL2
Error
AMP
CMP.
FB2M
SW2OL
PWM
Waveform
Drive Circuit
TN2
SD2
CC2
V
SS2
PG2
POFF2
LMD2
Power
Manager
SSCAP2
Soft Start
CS2
Fig.3.2.1 CH-2 Regulator Configuration
3.2.1 Main Regulator (PWM Controller)
The main regulator of CH-2 is a PWM controller. External components can be connected to it to form a
switching regulator to allow a constant voltage to be generated and output from input voltage VIN (VIN2) and
internal constant voltage VD1.
[Configuration of CH-2 Switching Regulator]
Synchronized rectification type switching regulator.
Clock
Approximately 1 MHz (when the internal oscillator circuit is used)
Required external components: P-ch power MOS transistor
TP2
TN2
SD2
CL2
N-ch power MOS transistor
Schottky diode
Coil: 10µH
Stabilizing capacitor (100µF) CC2
Capacitor for soft start
CS2
The output value is fixed to that set from the mask options.
3.2.2 Sub-Regulator (Backup Regulator)
CH-2 has a series regulator which serves as its sub-regulator.
For output value, a value approximately 0.1V lower than the value set of the main regulator is outputted.
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3.2.3 Light-Load Mode Function
In normal operation (normal mode), the main regulator and the sub-regulator are both operating. During
operation of the application, some conditions do not require a large load current. In this case, the mode can be
switched to [Light-load mode].
In light-load mode, the main regulator is OFF and only the sub-regulator is on. Therefore, the current consumed
by the main regulator can be restrained, effectively saving power for the application.
Switching between the normal and light-load mode is optional in the application. The switching methods of the
2 modes are as follows:
[Switching from normal to light-load mode]
To switch from the normal to the light-load mode, set the value of the LMD2 register to “1” via the I2C
controller. Consequently, the main regulator of the CH-2 is turned OFF and only the sub-regulator operates.
Only the voltage of the sub-regulator is outputted.
[Switching from light-load to normal mode]
There are 2 methods to switch from light-load to normal mode.
(1) Set LMD2 register to “0” via I2C controller.
(2) Use the automatic switching function by overload detection of the sub-regulator.
The above automatic switching function is a function which automatically turns on the main regulator and
switches to the normal mode when overload was detected in the sub-regulator caused by the increase of the
load current (exceeding approximately 30mA) during the light -load mode.
Fig.3.2.3.1 shows the normal and light-load modes and the switching method.
Notes: For the output voltage value of the sub-regulator, a voltage about 0.1 V lower than the value selected
from the mask options is output.
[CH-2]
Normal Mode
Light-load Mode
From Normal to Light-load
Set LMD2 register to 1 via
I2C.
Main Regulator
Main Regulator
ON
OFF
Sub-Regulator
Sub-Regulator
From Light-load to Normal
(1) Set LMD2 register to 0
via I2C.
ON
ON
(2) Use the auto-switching
function by over load
detection.
Fig.3.2.3.1 Switching between Normal/Light-load Mode in CH-2
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3.2.4 Soft Start Function
With a capacitor connected to the SSCAP2 pin, CH-2 provides a soft start function that adjusts the rise time of
the power when it is turned on. This function effectively works to prevent a system malfunction that may occur
due to rush current when the power is activated. Fig.3.2.4.1 shows the relation between the soft start time and
the soft start capacitor capacity (CS2).
Soft Start Time v. s. CSn (Typ.)
CSn [µF]
Fig.3.2.4.1 The Relation between the Soft Start Time and the Soft Start Capacitor Capacity (CS2).
3.2.5 Short-Circuit Proof Function
The S1F81100 is provided with a built-in output proof function. When output voltage is continuously reduced
below the detected value approx. 110ms or more, the CH-2 switching regulator circuit operation stops.
Restore from the short-circuit proof mode is possible by input via the reset pin (XRST). For further
information about it, see 3.2.6.
Output reduction detection CH-2 output set value
Output reduction detected value
2.3V ± 0.2V
3.3V
2.5V
1.9V ± 0.2V
Output proof detection time 110 ± 20 [ms]
Notes: Take short-circuit proof countermeasures other than above to increase the security of the application.
3.2.6 Power OFF Function
The voltage output of CH-2 can be turned off (powered off) via the I2C controller.
Writing “1” in the POFF2 register assigned to the I2C controller’s register causes the CH-2 output to be turned
off (powered off) and pulled down internally.
Moreover, as mentioned in section 3.2.5, when short-circuit proof function was activated and CH-2 voltage
output was turned off, this register is automatically rewritten to “1” in the IC.
The POFF2 register value attains “0” again through one of the following steps, and then voltage output is turned
ON.
(1) Perform initial reset.
See section 5.2 for details of the POFF2 register.
Notes: When CH-2 voltage output is turned OFF, I2C controller cannot be used.
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3.2.7 Power Good Function
CH-2 has a Power Good function. The Power Good function refers to a function that monitors the output
voltage value inside the S1F81100 unit and determines if it is normal or not. If a state approximately 10% or
more below the typical output voltage exceeds approximately 10ms, it is determined to be “abnormal output.”
The result of the Power Good judgement can be read via the PG2 flag (read-only) of the I2C controller.
Moreover, it can be monitored by output level of nVCC_FLT pin.
The Power Good function can be deactivated by writing “0” in the VFLT register on the I2C controller.
See section 5.2 for details of the PG2 flag and VFLT registers.
See section 6.2 for details of the nVCC_FLT pin.
3.2.8 CH-2 (VCC2) Mask Options Concerning Output Voltage
The following items are provided as mask options related to CH-2 output voltage.
[No.1] CH-2(VCC2) Output voltage
ꢂ 1. 3.3V
ꢂ 2. 2.5V
ꢂ 3. 1.8V (under development)
One CH-2 output voltage value is selectable from 3.3V, 2.5V and 1.8V from mask options.
[No.4] Sleep mode CH-2 main regulator operation
ꢂ 1. ON
ꢂ 2. OFF
The ON/OFF operation of CH-2 main regulator in Sleep mode is selectable from mask options.
Selecting “Operation ON” if a large load current is required for CH-2 during Sleep mode and “Operation OFF”
if a large load current is not required and restraining power consumption during Sleep mode as much as possible
increases operating efficiency.
When the LMD2 register is previously set at “1,” the main regulator in Sleep mode will be in “Operation OFF”
state regardless of this mask option.
See section 5.2 for details of the LMD2 register.
[No.6] Deep Sleep mode CH-2 sub-regulator operation
ꢂ 1. Enable (CH-2 sub-regulator, ON in Deep Sleep mode)
ꢂ 2. Disable (CH-2 sub-regulator, OFF in Deep Sleep mode)
The ON/OFF operation of CH-2 sub-regulator in the Deep Sleep mode is selectable from mask options.
Selecting “OFF” stops CH-2 output and reduces the VCC2 potential down to the GND level. For this reason,
once the unit enters the Deep Sleep mode, it can be restored from this mode only by LOW level input via the
XRST pin. When power is externally supplied to VCC2 (CH-2) in the Deep Sleep mode, input via PWR_EN is
also accepted.
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3.3 CH-3 (VCC3) Output Voltage
This section describes CH-3, a PWM controller. Fig.3.3.1 shows CH-3’s internal and external configurations.
S1F81100
V
CC3
IN3
Power
Good
V
Sub-regulator
(backup)
TP3
SW3OH
-
-
+
CL3
Error
AMP
CMP.
FB3M
SW3OL
PWM
Waveform
Drive Circuit
TN3
SD3
CC3
VSS3
PG3
POFF3
LMD3
Power
Manager
SSCAP3
Soft Start
CS3
Fig.3.3.1 CH-3 Regulator Configuration
3.3.1 Main Regulator (PWM Controller)
The main regulator of CH-3 is a PWM controller. External components can be connected to it to form a
switching regulator to allow a constant voltage to be generated and output from input voltage VIN (VIN3) and
internal constant voltage VD1.
[Configuration of CH-3 Switching Regulator]
Synchronized rectification type switching regulator.
Clock
Approximately 1 MHz (when the internal oscillator circuit is used)
Required external components: P-ch power MOS transistor
TP3
TN3
SD3
CL3
N-ch power MOS transistor
Schottky diode
Coil: 10µH
Stabilizing capacitor (100µF) CC3
Capacitor for soft start
CS3
The output value is fixed to that set from the mask options.
3.3.2 Sub-Regulator (Backup Regulator)
CH-3 has a series regulator which serves as its sub-regulator.
For output value, a value approximately 0.1V lower than the value set of the main regulator is outputted.
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3.3.3 Light-Load Mode Function
In normal operation (normal mode), the main regulator and the sub-regulator are both operating. During
operation of the application, some conditions do not require a large load current. In this case, the mode can be
switched to [Light-load mode].
In light-load mode, the main regulator is OFF and only the sub-regulator is on. Therefore, the current consumed
by the main regulator can be restrained, effectively saving power for the application.
Switching between the normal and light-load mode is optional in the application. The switching methods of the
2 modes are as follows:
[Switching from normal to light-load mode]
To switch from the ordinary to the light-load mode, set the value of the LMD3 register to “1” via the I2C
controller. Consequently, the main regulator of the CH-3 is turned OFF and only the sub-regulator operates.
Only the voltage of the sub-regulator is outputted.
[Switching from light-load to normal mode]
There are 2 methods to switch from light-load to normal mode.
(1) Set LMD3 register to “0” via I2C controller.
(2) Use the automatic switching function by overload detection of the sub-regulator.
The above automatic switching function is a function which automatically turns on the main regulator and
switches to the normal mode when overload was detected in the sub-regulator caused by the increase of the
load current (exceeding approximately 30mA) during the light-load mode.
Fig.3.3.3.1 shows the normal and light-load modes and the switching method.
Notes: For the output voltage value of the sub-regulator, a voltage about 0.1V lower than the value selected
from the mask options is output.
[CH-3]
Normal Mode
Light-load Mode
From Normal to Light-load
Set LMD3 register to 1 via
I2C.
Main Regulator
Main Regulator
ON
OFF
Sub-Regulator
Sub-Regulator
From Light-load to Normal
(1) Set LMD3 register to 0
via I2C.
ON
ON
(2) Use the auto-switching
function by over load
detection.
Fig.3.3.3.1 Switching between normal/light-load mode in CH-3
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3.3.4 Soft Start Function
With a capacitor connected to the SSCAP3 pin, CH-3 provides a soft start function that adjusts the rise time of
the power when it is turned on. This function effectively works to prevent a system malfunction that may occur
due to rush current when the power is activated. Fig.3.3.4.1 shows the relation between the soft start time and
the soft start capacitor capacity (CS3).
Soft Start Time v. s. CSn (Typ.)
CSn [µF]
Fig.3.3.4.1 The Relation between the Soft Start Time and the Soft Start Capacitor Capacity (CS3).
3.3.5 Short-Circuit Proof Function
The S1F81100 is provided with a built-in output proof function. When output voltage is continuously reduced
below the detected value approx. 110ms or more, the CH-2 switching regulator circuit operation stops.
Restore from the short-circuit proof mode is possible by input via the reset pin (XRST). For further
information about it, see 3.2.6.
Output reduction detection CH-2 output set value
Output reduction detected value
2.3V ± 0.2V
3.3V
2.5V
1.9V ± 0.2V
Output proof detection time 110 ± 20 [ms]
Notes: Take short-circuit proof countermeasures other than above to increase the security of the application.
3.3.6 Power OFF Function
The voltage output of CH-3 can be turned off (powered off) via the I2C controller.
Writing “1” in the POFF3 register assigned to the I2C controller’s register causes the CH-3 output to be turned
off (powered off) and pulled down internally.
Moreover, as mentioned in section 3.3.4, when short-circuit proof function was activated and CH-3 voltage
output was turned off, this register is automatically written over to “1” in the IC.
The POFF3 register value attains “0” again through one of the following steps, and then voltage output is turned
on.
(1) Perform initial reset.
(2) Write “0” in the POFF3 register via the I2C controller.
See section 5.2 for details of the POFF3 register.
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3.3.7 Power Good Function
CH-3 has a Power Good function. The Power Good function refers to a function that monitors the output
voltage value inside the S1F81100 unit and determines if it is normal or not. If a state approximately 10% or
more below the typical output voltage exceeds approximately 10ms, it is determined to be “abnormal output.”
The result of the Power Good judgement can be read via the PG3 flag (read-only) of the I2C controller.
Moreover, it can be monitored by output level of nVCC_FLT pin.
The Power Good function can be deactivated by writing “0” in the VFLT register on the I2C controller.
See section 5.2 for details of the PG3 flag and VFLT registers.
See section 6.2 for details of the nVCC_FLT pin.
3.3.8 CH-3 (VCC3) Mask Options Concerning Output Voltage
The following items are provided as mask options related to CH-3 output voltage.
[No.2] CH-3(VCC3) Output voltage
ꢂ 1. 3.3V
ꢂ 2. 2.5V
ꢂ 3. 1.8V (under development)
One CH-3 output voltage value is selectable from 3.3V, 2.5V and 1.8V from mask options.
[No.5] Sleep mode CH-3 main regulator operation
ꢂ 1. ON
ꢂ 2. OFF
The ON/OFF operation of CH-3 main regulator in Sleep mode is selectable from mask options.
Selecting “Operation ON” if a large load current is required for CH-3 during Sleep mode and “Operation OFF”
if a large load current is not required and restraining power consumption during Sleep mode as much as possible
increases operating efficiency.
When setting LMD3 register to “1” previously, the main regulator in Sleep mode will be in “Operation OFF”
state regardless of this mask options.
See section 5.2 for details of the LMD3 register.
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3.4 CH-4 (VCC4) Output Voltage
This section describes CH-4, a series regulator. Fig.3.4.1 shows CH-4’s internal and external configurations.
S1F81100
FB4
VCC4
Power
Manager
POFF4
Fig.3.4.1 CH-4 Regulator Configuration
3.4.1 Main Regulator (Series Regulator)
CH-4 is a push/pull type series regulator that generates constant voltage via CH-3’s output voltage VCC3.
Short-circuit the VCC4 and FB4 pins outside the IC and use after mounting the following required components.
The following lists the required components.
Required external components: Capacitor
22µF
CH-4 output voltage value is the same with the voltage value set in CH-1.
CH-4 output is turned off in the following conditions:
(1) When CH-3 is turned off
(2) When set to Sleep mode (depends on the mask options).
(3) When set to Deep Sleep mode
(4) When “1” was written in POFF4 register via the I2C controller (see section 3.4.2)
3.4.2 Power OFF Function
The voltage output of CH-4 can be turned OFF (powered OFF) via the I2C controller.
Writing “1” in the POFF4 register assigned to the I2C controller’s register causes the CH-4 output to be turned
off (powered off) and pulled down internally.
The POFF4 register value attains “0” again through one of the following steps, and then voltage output is turned
on.
(1) Perform initial reset.
(2) Turn the input level of the PWR_EN pin to LOW once to cause the Sleep state, then assign the HIGH level
again to the PWR_EN pin to allow recovery from the Sleep state.
(3) Write “0” in the POFF4 register via the I2C controller.
See the section 5.2 for details of the POFF4 register.
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3.5 Output Timing of Regulator on Initial Startup
Describes about the regulator output after the initial startup (input voltage power-on).
CH-2 and CH-3 are the first ones to rise after input voltage (VIN) power-on.
After the Power Good function of each CH has determined that their output values are within the “specified
range” for CH-2 and CH-3, CH-1 and CH-4 voltages start to rise.
Subsequently, if the Power Good function determines that the output value is within the “specified range” for
CH-1 (CH-4 does not have a Power Good function), the output voltage determining function considers the
voltage to be “normal output voltage.”
Then, set the output level of nVCC_FLT pin to HIGH.
The initial reset state in the IC cancels in approximately 60ms. At the same time, set the output level of
nRESET pin to HIGH and instruct reset cancellation to the external processor, etc.
See section 6.2 for output voltage determining function.
See section 2.2 for initial reset.
Fig.3.5.1 shows a timing chart illustrating the initial startup.
VIN
VCC2/VCC3
70ms
VCC1/VCC4
5ms
nVCC_FLT
[Digital]
less than 1µs
nRESET
[Digital]
60ms
ꢃ The values in the diagram are all typical values for approximation.
Fig.3.5.1 Initial Startup Timing
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4. OPERATION MODES
The SIF81100 provides the following operation modes (operation statuses).
(1) Normal mode
(2) Sleep mode
(3) Deep Sleep mode
(4) Ultra-Power-Saving mode
The Normal mode refers to a state in which the IC operates normally.
Each of the other three modes can be set using the control external to the IC or the control via the I2C controller.
Because each of these three modes ensures power saving as compared to the Normal mode, it is possible to
develop low-power consumption type products by efficiently set a mode when the application is operating.
This chapter describes the Sleep, Deep Sleep and Ultra-Power-Saving modes in detail.
4.1 Description of Each Operation Mode
The S1F81100 enters the Sleep or Deep Sleep mode when the PWR_EN pin is set to LOW during operation.
The switching between Sleep and Deep Sleep modes is accomplished by the EDS register in the I2C controller.
The S1F81100 enters the Ultra-Power-Saving mode when the input level of the XSDWN pin is set to LOW.
In these modes, a part or all of the voltage outputs and IC’s internal circuits can be turned OFF. Thus, using
the mode appropriate for each individual situation allows the S1F81100 to deliver power saving performance.
Table 4.1.1 shows the ON/OFF states of the internal circuits in each mode.
Table 4.1.1 Regulator Operations in Each Mode
Normal
mode
ON
Deep Sleep
mode
Ultra-Power-
Saving mode
OFF
Sleep mode
CH-1 Main
CH-2 Main
Sub
PWM
controller
PWM
controller
Series
regulator
PWM
controller
Series
regulator
OFF
OFF
ON
ON
ON
ON
ON
ON
ON or OFF
ꢃ Mask Option -2
ON
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF or ON
ꢃ Mask Option -4
OFF
CH-3 Main
Sub
ON or OFF
ꢃ Mask Option -3
ON
OFF
OFF
ON
CH-4 Main
Series
regulator
OFF
ON
Others
(analog/logic)
ꢃ For Mask Option -2, see Section 4.2.4. (Option 4)
ꢃ For Mask Option -3, see Section 4.2.4. (Option 5)
ꢃ For Mask Option -4, see Section 4.3.4. (Option 6)
4.2 Sleep Mode
The S1F81100 enters the Sleep mode when the PWR_EN pin is set to LOW during operation. In the Sleep
mode, CH-1 is turned OFF. In this mode the power consumed by the S1F81100 is lower compared to the
Normal mode.
4.2.1 Transitioning to and Canceling the Sleep Mode
This section describes how to transition to and cancel the Sleep mode.
The timing chart for transitioning to and canceling the Sleep mode varies depending on whether or not CH-1
output voltage change is made. See sections 4.2.2 and 4.2.3.
ꢀTransitioning to Sleep Mode
To transition to the Sleep mode, set the EDS register to 0 (default) and input level of the PWR_EN pin to LOW
using the I2C controller in the Normal mode.
When the S1F81100 enters the Sleep mode,
CH-1: Voltage output is turned OFF.
CH-2: Depending on the mask option setting, the main regulator is turned OFF.
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CH-3: Depending on the mask option setting, the main regulator is turned OFF.
CH-4: Voltage output is turned OFF.
In the Sleep mode, current consumption is reduced due to deactivation of CH-1. Therefore, setting the unit to
enter the Sleep mode via application software when VCC1 voltage is no longer required contributes to higher
efficiency of the unit as the current consumption of the entire system is reduced.
ꢀCanceling Sleep Mode
To cancel the Sleep mode, set the input level of the PWR_EN pin to HIGH.
In the Sleep mode, the internal register holds the same settings as ones before a transition to the Sleep mode.
When the Sleep mode is canceled, the S1F81100 is restored to the same state as it was before a transition to the
Sleep mode.
4.2.2 Transitioning to and Canceling the Sleep Mode When CH-1 Voltage Change is Made
As described in Section 4.1, to change the CH-1 output voltage using the step transition, it is required to
transition to and cancel the Sleep mode after setting the VS17 to 10 register.
This involves the software and hardware control as described in Section 3.1.5. Control the software and
hardware on your application following the description in Table 3.1.5.2.
Fig.4.2.2.1 shows its timing chart.
See section 5.2 for details of the VS17 to 10 register.
VS17 to 10
[Digital]
A
B
PWR_EN
[Digital]
WUP
[Digital]
less than 1
µ
s
µ
less than 1 s
nVCC_FLT
[Digital]
less than 1
µs
less than 1µs
A
V
CC1
B
ꢃ The values in the figure indicate the typical values that serve as guide.
Fig.4.2.2.1 Sleep Mode Control Timing when Changing CH-1 Output Voltage Using Step Transition
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4.2.3 Transitioning to and Canceling the Sleep Mode When CH-1 Voltage Change is not Made
A transition to Sleep mode not aiming at changing the CH-1 output voltage (VS17 to 10 register value not
changed) does not involve the change in the WUP signal in contrast to the conditions under which the output
voltage change is made.
Fig.4.2.3.1 shows its timing chart.
Table 4.2.3.1 shows the flow for controlling the software. Follow that flow to control the software on your
application.
VS17 to 10
[Digital]
A
PWR_EN
[Digital]
WUP
[Digital]
nVCC_FLT
[Digital]
less than 1
µs
less than 1µs
V
CC1
A
A
ꢃ The values in the figure indicate the typical values that serve as guide.
Fig.4.2.3.1 Sleep Mode Control Timing when CH-1 Voltage Change is not Made
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Table 4.2.3.1 Steps for Controlling Software When the VCC1 Output Voltage Change is not Made
Processor
ex. PXA250/210
Power supply IC
S1F81100
Status
Operation
(software/hardware-controlled)
Operation
Normal operation state
Normal
operation
PWN_EN pin output: HIGH level Voltage output VCC1/VCC4 outputs turned ON.
WUP pin output: LOW level
[Setting]
Enable the input interrupt of the
GP[n] pin.
[Software control]
Rewrites the VS17 to VS10
c I2C communication
I2C
command
register of the power supply IC
via the I2C controller and sets
the new voltage value.
d Start transitioning to
Sleep
Transition to Start transition to Sleep.
Sleep
PWR_EN
signal
(PWR_EN pin control)
[Software control]
Sets the output of PWR_EN pin
to LOW Level to transit to Sleep
state.
L
e CORE voltage OFF
Sleep
Voltage output VCC1/VCC4 outputs OFF.
X
(WUP pin held LOW.)
(Stay in Sleep until an interrupt
occurs.)
[Interrupt occurred!]
f Sleep State Cancellation Sleep
Start canceling Sleep.
PWR_EN
signal
Start
Cancellation
[Software (hardware)control]
Sets the output of PWR_EN pin
to HIGH level to cancel Sleep.
H
g CORE voltage output
Normal mode
Voltage output VCC1/VCC4 outputs ON.
ON
Normal operation state
Normal mode PWR_EN pin output: HIGH level Voltage output VCC1/VCC4 outputs ON.
WUP pin output: LOW level
4.2.4 Mask Options Associated with the Sleep Mode
The S1F81100 provides the following mask options that are associated with the Sleep mode.
[No.3] One-touch recovery function for the Sleep mode
ꢂ 1. Disable
ꢂ 2. Enable
This mask option can be used to enable/disable the one-touch recovery function.
The one-touch recovery function enables the S1F81100 unit to recover from the Sleep or Deep Sleep mode to
the Normal mode by inputting a LOW-level signal to the P02 pin when the input level of the PWR_EN pin is
held at LOW with the S1F81100 set in the Sleep or Deep Sleep mode.
This function works effectively, for example, when the sub-battery is exhausted after maintaining the
application in the Deep Sleep mode for a long period of time and it is no longer possible to set the PWR_EN pin
to HIGH.
See section 5.2 for details of the IOP02 register.
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Fig.4.2.4.1 outlines the one-touch recovery function.
Note: To use the one-touch recovery function, you must set the P02 port to “INPUT” using the IOP02 register.
In addition, you must set the input level to HIGH before entering the Sleep mode.
Normal Mode
Sleep Mode
Normal Mode
PWR_EN
[Digital]
P02
[Digital]
Even though PWR_EN is kept LOW level
input, sleep mode is canceled by one-
touch recovery function.
nVCC_FLT
[Digital]
V
CC1
Fig.4.2.4.1 Description of One-Touch Recovery Function
[No.4] CH-2 main regulator operation for the Sleep mode
ꢂ 1. ON
ꢂ 2. OFF
This mask option can be used to turn the CH-2 main regulator for the Sleep mode ON or OFF.
The mask option works effectively by selecting ON when the CH-2 requires a large load current in the Sleep
mode or selecting OFF when the CH-2 does not require a large load current and the power consumption during
the Sleep mode should be reduced as low as possible.
Setting the LMD2 register to 1 forces the main regulator to turn OFF during the Sleep mode independently of
this mask option.
See section 5.2 for details of the LMD2 register.
[No.5] CH-3 main regulator operation for the Sleep mode
ꢂ 1. ON
ꢂ 2. OFF
This mask option can be used to turn the CH-3 main regulator for the Sleep mode ON or OFF.
The mask option works effectively by selecting On when the CH-3 requires a large load current in the Sleep
mode or selecting OFF when the CH-2 does not require a large load current and the power consumption during
the Sleep mode should be reduced as low as possible.
Setting the LMD3 register to 1 forces the main regulator to turn OFF during the Sleep mode independently of
this mask option.
See section 5.2 for details of the LMD3 register.
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4.3 Deep Sleep Mode
The S1F81100 enters the Deep Sleep mode when the PWR_EN pin is set to LOW during operation with the
EDS register set to “1”. In the Deep Sleep mode, CH-1 to CH-4 are turned OFF. In this mode the power
consumed by the S1F81100 is significantly lower compared to the Sleep mode.
4.3.1 Transitioning to and Canceling the Deep Sleep Mode
This section describes how to transition to and cancel the Deep Sleep mode.
Fig.4.3.1.1 shows a timing chart when transitioning to and canceling the Deep Sleep mode.
ꢀTransitioning to Deep Sleep Mode
To transition to the Deep Sleep mode, set the EDS register to “1” and input level of the PWR_EN pin to LOW
using the I2C controller in the Normal mode.
When the S1F81100 enters the Deep Sleep mode,
CH-1: Voltage output is turned OFF.
CH-2: Voltage output is turned OFF.
Depending on the mask option setting, the sub-regulator is turned on.
CH-3: Voltage output is turned OFF.
CH-4: Voltage output is turned OFF.
In the Deep Sleep mode, CH-1 to CH-4 are turned OFF, thereby current consumption is less than that for the
Sleep mode. Therefore, setting the unit to enter the Deep Sleep mode via application software when all
voltage output are no longer required contributes to reduction of current consumption of the entire system,
resulting in higher efficiency of the unit. The unit can be restored from the Deep Sleep mode by LOW level
input via the XRST pin.
ꢀCanceling Deep Sleep Mode
When the VCC2 (CH-2) is powered by the sub-regulator or external power supply in the Deep Sleep mode, this
mode can be canceled by setting the input level of the PWR_EN pin to HIGH.
When it is canceled, the S1F81100 is restored to the same state as it was before a transition to the Deep Sleep
mode.
It can be also canceled by the LOW level input to the XRST pin. In this case, each register in the S1F81100
will be initialized.
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VS17 to 10
[Digital]
A
PWR_EN
[Digital]
WUP
[Digital]
nVCC_FLT
[Digital]
µ
less than 1 s
µ
less than 1 s
V
V
CC1/VCC4
CC2/VCC3
A
A
ꢃ The values in the figure indicate the typical values that serve as guide.
Fig.4.3.1.1 Deep Sleep Mode Control Timing
4.3.2 Mask Options Associated with the Deep Sleep Mode
The S1F81100 provides the following mask options that are associated with the Deep Sleep mode.
[No.3] One-touch recovery function for the Sleep mode
ꢂ 1. Disable
ꢂ 2. Enable
See section 4.2.2.
(In the Deep Sleep mode, the S1F81100 operates in the same way as in the Sleep mode.)
[No.6] CH-2 sub-regulator operation for the Deep Sleep mode
ꢂ 1. Enable (CH-2 sub-regulator, ON in Deep Sleep mode)
ꢂ 2. Disable (CH-2 sub-regulator, OFF in Deep Sleep mode)
The ON/OFF operation of CH-2 sub-regulator in the Deep Sleep mode is selectable from mask options.
Selecting “OFF” stops CH-2 output and reduces the VCC2 potential down to the GND level. For this reason,
once the unit enters the Deep Sleep mode, it can be restored from this mode only by LOW level input via the
XRST pin. When power is externally supplied to VCC2 (CH-2) in the Deep Sleep mode, input via PWR_EN is
also accepted.
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4.4 Ultra-Power-Saving Mode
The S1F81100 provides an Ultra-Power-Saving mode. This mode stops the functions of the entire IC
functionality to minimize power consumption. The current consumption in this mode is on the order of a few
microamperes. This mode is useful for shipping the product or for maintaining applications what are not to be
used for a long period of time.
To set the Ultra-Power-Saving mode, set the input level of the XSDWN pin to LOW. Maintaining the input
level at LOW allows the S1F81100 to stay in the Ultra-Power-Saving mode.
To recover from the Ultra-Power-Saving mode, follow the procedures below.
(1) Set the input level of the XRST pin to LOW.
(2) Set the input level of the XSDWN pin to HIGH.
(3) Set the input level of the XRST pin to HIGH.
Setting the XSDWN pin back to HIGH with the XRST pin held HIGH, the IC’s internal circuitry becomes
unstable. Thus, this input state should not be used.
Fig.4.4.1 shows a timing chart when transitioning to and canceling the Ultra-Power-Saving mode.
XSDWN
[Digital]
･･･
･･･
･･･
･･･
XRST
[Digital]
Ultra-
Power-
Saving
mode
Unstable
state
Ultra-Power-Saving
mode
Normal
mode
Normal mode
Reset
Reset
Fig.4.4.1 Timing for Transitioning and Canceling the Ultra-Power-Saving Mode
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5. I2C CONTROLLER
Being a system power supply IC, the S1F81100 is equipped with an I2C controller having a slave function for
enhancing operability for operation from external devices. Sending specified commands to the I2C controller
enables data inside the IC to be read and written, allowing detailed setting of the regulators and auxiliary
circuits.
This section provides detailed descriptions of the I2C controller.
5.1 Description
The I2C controller refers to the controller complying with the standard two-wire system serial interface
specifications advocated by Phillips. S1F81100 products are licensed by Phillips.
This section describes its communications mechanism.
5.1.1 Basic Specifications
The basic specifications of the I2C controller mounted on the S1F81100 are as follows:
Address:
000100xB (Bit length: 7 bits. LSB: Can be set with the AD_EN pin.) )
Transmission speed: Maximum 400 kHz
Pins used
SDA:
SCL:
Data I/O pin
Clock input pin
AD_EN: Address enabling pin (LSB Select pin)
Voltage level
(SDA, SCL)
(AD_EN)
VCC2 level
VIN level
Reading/writing in the register assigned to the I2C controller enables this IC to be externally configured with
detailed settings or updated operating conditions and to be subject to operation control as well as internal state
monitoring.
The function of the I2C controller of the S1F81100 is limited to the slave function. Thus, control is only possible
externally, from the master side.
Note: While VCC2 is OFF, the I2C controller cannot be used.
5.1.2 Start and Stop Conditions
In the transmission procedure involving the I2C controller, it is necessary to raise the controller-specific
conditions, Start and Stop, upon starting and stopping communications respectively. Fig.5.1.2.1 shows a chart of
these timings.
Fig.5.1.2.1 Start and Stop Conditions for I2C Controller
1) When SCL is at HIGH, SDA turns from HIGH to LOW.
This forms a Start condition.
2) When SCL is at HIGH, SDA turns from LOW to HIGH.
This forms a Stop condition.
Since this model only provides the slave function, the above Start or Stop conditions cannot be generated on
this controller. Be sure to generate them on the master side.
Both the Start and Stop conditions can be generated at a desired timing.
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5.1.3 Data Transfer (command format)
Fig.5.1.3.1 shows the command format for data transmission.
Transmit/
Receive
1 byte
Transmit/
Receive
1 byte
Transmit/
Receive
1 byte
Transmit/
Receive
1 byte
Start
Stop
Data-X0H
SDA(DATA)
Address
Data-X1H
Data-X5H
.....
. . . . .
SDA(ACK)
SCL
. . . .
. . . .
. . . .
. . . .
. . . .
Start
condition
Stop
condition
Fig.5.1.3.1 S1F81100 Command Format for I2C Controller
Fig.5.1.3.2 shows a detailed chart of command sending/receiving timings.
D7
[A6]
D6
[A5]
D5
[A4]
D4
[A3]
D3
[A2]
D2
[A1]
D1
[A0]
D0
[R/W]
SDA(DATA)
SDA(ACK)
SCL
1
2
3
4
5
6
7
8
9
ꢄ
Fig.5.1.3.2 Send and Receive Single Byte Timing
ꢀStarting Transmission
Generating the Start condition described above from the master side starts transmission.
ꢀSlave Address
After a Start condition is generated, the slave address should be specified and sent from the master side. This
slave address is composed of seven bits and is assigned a unique value for each IC. For the S1F81100, a 7-bit
slave address (000100xB) is assigned by Philips. The LSB is specified by the input level of the AD_EN pin.
When AD_EN = 0: The slave address is set to 0001000B.
When AD_EN = 1: The slave address is set to 0001001B.
This allows the AD_EN pin to be used as an Enable pin for the I2C.
The slave address must be input from the master side starting with the MSB (A6). The address is stored in the
slave (S1F81100) at the falling edge of the clock input in SCL. See section 4.1.3.2.
ꢀRead/Write Specification Bit
Immediately after the slave address has been specified, a bit to specify the transmission direction follows that
indicates either read or write. The relationship between the bit value and the transmission direction is as
follows:
Bit value “0”: Receiving from the master (S1F81100)
(write).
Bit value “1”: Transmitting from the slave (S1F81100) (read).
The read/write specification bit is input from the master side following the LSB (A0). This bit is stored in the
S1F81100 at the rising edge of the clock input in SCL. See section 5.1.3.2.
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ꢀACK Signal after Transferring Slave Address and Read/Write Specification Bit
When the slave address and read/write specification bit is transferred from the master, the slave (S1F81100)
checks the following:
Transfer format
Slave address value
When they are properly stored, the slave sends an ACK (active LOW) to the master. This ACK output timing is
synchronized with the rising edge of the clock input in SCL. See section 5.1.3.2.
When ACK is output, the S1F81100 considers that transfer of the slave address and read/write specification bit
has completed.
ꢀControl Address, Control Data and ACK Signal
Upon completion of transfer of the slave address and read/write specification bit, the slave (S1F81100) starts a
control data read or write.
The operation varies depending on the read/write specification bit. If “read” is specified, internal data is output
(read)from the slave (S1F81100) to the master. If “write” is specified, data is input (written)from the master to
the slave (S1F81100).
Control data transfer starts from the X0H control address (see Table 5.2.1). For the sequence of data and data
read timing, see Fig.5.1.3.2.
When transmission of X0H is successfully completed, the ACK signal should be sent from the master to the
slave (S1F81100) for “read” and from the S1F81100 to the master for “write.”
When an ACK is output, the single-byte (X0H) data transfer terminates.
After this, the control address is automatically incremented on the S1F81100, then transfer of X1H starts.
The subsequent byte transfer takes place in the same fashion; the control address is incremented sequentially
upon completion of each one byte.
After the last X5H control address is transferred, the control address returns to X0H and data transfer starts
again.
To successfully terminate the transmission via the I2C bus, it is required to use the following command format
as well as to generate the Stop condition.
For a read: The last ACK to be sent from the slave to the master can be either ACK (SDA LOW) or non-ACK
(SDA HIGH).
For a write: The last ACK to be sent from the master to the slave must be non-ACK (SDA HIGH).
ꢀTerminating Transmission
Generating the Stop condition described above from the master side terminates transmission.
Transmission cannot be successfully terminated unless the last ACK for both read and write operations
conforms to the command format.
Note: Data transfer continues looping until a Stop condition is issued from the master side. So be sure to
generate a Stop condition on the master side when the transmission terminates.
5.1.4 Behavior During Malfunction Conditions
The following describes typical malfunctions along with the conditions that cause them.
[Case 1] A Stop condition has started before transmission starts.
The I2C controller does not operate.
[Case 2] Transmission has started with a Start condition but a Start condition is generated again during the
transmission (that is, before generation of a Stop condition).
Transmission start from the beginning, that is, from specification of the slave address, then jumps to the X0H
control address to start the rest of the transmission.
[Case-3] When an ACK (SDA LOW) is issued from the master at the timing of ACK for a read operation, the
S1F81100 continues the read operation. At the end of the read operation, be sure to transmit a non-ACK
(SDA HIGH). If the read operation is terminated with an ACK transmitted (SCL stopped), the S1F81100 is
no longer able to generate a Start condition since transmission fails to terminate successfully. In such a case,
activate the clock (SCL) once to generate a non-ACK to get the unit back to normal.
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5.2 Control Address & Control Data List
The I2C controller of the S1F81100 has the control addresses and control data (registers/flags) listed in Table
5.2.1.
Table 5.2.1 Control Address/Data for I2C
Addr.
X0H
X1H
X2H
X3H
X4H
X5H
Register
Comment
D7
VS17
R/W
1
D6
VS16
R/W
0
D5
VS15
R/W
0
D4
D3
VS13
R/W
0
D2
VS12
R/W
1
D1
VS11
R/W
1
D0
VS10
R/W
0
Name
R/W
Init
VS14
R/W
1
VCC1 voltage control
Name
R/W
Init
RT17
R/W
1
RT16
R/W
1
RT15
R/W
1
RT14
R/W
1
RT13
R/W
1
RT12
R/W
1
RT11
R/W
1
RT10
R/W
1
General-purpose
register
Name XEECKH
RT26
R/W
1
RT25
R/W
1
XC1TRG EOSH
LMD1 POFF1
PG1
R
VCC1 setup register
R/W
Init
R/W
1
W
R/W
1
R/W
0
R/W
0
Name
R/W
Init
EDS
R/W
0
RT36
R/W
1
RT35
R/W
1
RT34
R
RT33
R/W
1
RT32
R
POFF4
R/W
0
VCC4 setup register
and other controls
R
1
1
Name EBFT
LMD3 POFF3
PG3
R
EVFT
R/W
1
LMD2 POFF2
PG2
R
VCC2/VCC3 setup
registers and other
controls
R/W
Init
R/W
1
R/W
0
R/W
0
R/W
0
R/W
0
Name IOP03 DTP03 IOP02 DTP02 IOP01 DTP01 IOP00 DTP00 General-purpose
I/O port control
R/W
Init
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
The following describes the respective registers.
VS17 to VS10 VCC1 output voltage setting register
Default: VS17 to VS10 = 096H = 10010110B
1.5V
This is the VCC1 output voltage setting register for CH-1.
The S1F81100 allows the user to select from eight output values, 1,5, 1.4, 1.3, 1.2, 1.1, 1.0, 0.9 and 0.8 V. The
output voltage value can be modified programmably based on the 8-bit register value specified with VS17 to
VS10.
Example:
(1) Setting for 1.3 V output:
130D =10000010B =082H:
(2) Setting for 1.1 V output:
110D =01101110B=06EH:
(3) Setting for 1.0 V output:
100D =01100100B =064H:
(4) Setting for 0.8 V output:
080D =01010000B =050H:
With VS17 to VS10 set to 082H, VCC1 = 1.3V.
With VS17 to VS10 set to 06EH, VCC1 = 1.1V.
With VS17 to VS10 set to 064H, VCC1 = 1.0V.
With VS17 to VS10 set to 050H, VCC1 = 0.8V.
If values other than the above examples are set for VS17 to VS10, the output value follows Table 5.2.1.
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Table 5.2.1 VS17 to VS10 Settings and VCC1 Output Voltage
VS17 to 10
VCC1
VS17 to 10
VCC1
11111*** B
11110*** B
11101*** B
11100*** B
11011*** B
11010*** B
11001*** B
11000*** B
10111*** B
10110*** B
10101*** B
10100*** B
10011*** B
10010*** B
10001*** B
10000*** B
Setting inhibited
Setting inhibited
Setting inhibited
Setting inhibited
Setting inhibited
Setting inhibited
Setting inhibited
Setting inhibited
Setting inhibited
Setting inhibited
Setting inhibited
Setting inhibited
1.5V
01111*** B
01110*** B
01101*** B
01100*** B
01011*** B
01010*** B
01001*** B
01000*** B
00111*** B
00110*** B
00101*** B
00100*** B
00011*** B
00010*** B
00001*** B
00000*** B
1.2V
1.2V
1.1V
1.0V
0.9V
0.8V
0.8V
0.8V
0.8V
0.8V
0.8V
0.8V
0.8V
0.8V
0.8V
0.8V
1.5V
1.4V
1.3V
An asterisk (*) in the table indicates an optional value.
As shown in Table 5.2.1, the S1F81100 decodes the upper five bits (VS17 to VS13), ignoring the lower three
bits (VS12 to VS10). The lower three bits can, therefore, be used as a general-purpose register.
POFFn (n=1 to 4): CH-n Power OFF control register
1
0
Output OFF (Power OFF)
Output ON (Power ON) (Default)
These are the registers for ON/OFF control of the CH-1 to CH-4 regulators. If these registers are set to “0,”
output is disabled even during normal operation.
If the PWR_EN pin is assigned the LOW level (set to the Sleep state) when these registers are set to “0,” they
are automatically initialized to enable voltage output when recovering from the Sleep state.
When a short-circuit protection function operates on the CH-2 (or CH-3), a “1” is written into the POFF2 (or
POFF3) register, turning the output OFF.
See sections 3.1.6, 3.2.6, 3.3.6 and 3.4.2 for details of the Power OFF function.
The POFFn registers are read/write-enabled.
PGn (n = 1 to 3): CH-n Power Good detecting flag
1
0
Within the specified range.
Outside the specified range.
This flag indicates the Power Good detection result for each of the CH-1 to CH-3 regulators.
If the flag value turns to “0,” the “0” level is maintained until this register is read once by the I2C controller.
After the register is read, the level turns to “1.” Thus, the register can determine which output is abnormal when
the nVCC_FLT pin output drops to “0.”
The Power Good function operates even on an unstable state (including voltage output rise or fall for each CH).
This may cause the PGn to misinterpret an output as “0” (outside the specified range) to be written into the flag.
It is, therefore, required to read the PGn flag twice or more before using the Power Good function. At the initial
startup, this must be done.
See sections 3.1.7, 3.2.7 and 3.3.7 for details of the Power Good function.
The PGn flag is read only.
LMDn (n=2, 3): Mode Select (Normal or Light-Load mode) register
1
0
Light-Load mode
Normal mode (Default)
These are the registers for selecting whether the main (PWM controller) or the sub-controller (backup LDO) is
to be used for each of the CH-2 and CH-3 regulators.
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State “0” (Normal mode) that provides a high output current is effective when a high load current is required.
State “1” puts the S1F81100 in the Light-Load mode. This significantly reduces the operating current
consumption of the S1F81100 unit. Furthermore, greater efficiency is achieved by setting this state in an
operating mode that does not require a high load current.
If overload detection activates the automatic switching function, this register automatically turns to “0.”
See sections 3.2.3 and 3.3.3 for details of the Normal and Light-Load modes, respectively.
The LMDn registers are read/write-enabled.
LMD1
(*When CH-1 sub-regulator is set to OFF by the mask option.)
CH-1 Power OFF control register
1
0
Output OFF.
Output ON. (Default)
This register operates similarly to the POFF1 register.
See section 3.1.6 for details of the Power OFF function.
The LMD1 register is read/write-enabled.
(*When CH-1 sub-regulator is set to On by the mask option.)
Mode Select (Normal or Light-Load mode) register
1
0
Light-Load mode
Normal mode (Default)
This is the register for selecting whether the Normal or Light-Load mode is to be used for the CH-1 regulator.
State “0” (Normal mode) that provides a high output current is effective when a high load current is required.
State “1” puts the S1F81100 in the Light-Load mode. This significantly reduces the operating current
consumption of the S1F81100 unit. Furthermore, greater efficiency is achieved by setting this state in an
operating mode that does not require a high load current.
If overload detection activates the automatic switching function, this register automatically turns to “0.”
See section 3.1.3 for details of the Normal and Light-Load modes.
The LMD1 register is read/write-enabled.
EDS
Deep Sleep mode setting register
Deep Sleep mode enabled.
Deep Sleep mode disabled (Default)
1
0
This is for specifying if the Deep Sleep mode is to be used or not.
If the LOW level is input for the RWR_EN pin with this register set to “1,” the S1F81100 transits to the Deep
Sleep mode and the voltage outputs from VCC1 through VCC4 are all switched OFF. This function is effectively
used to control the power consumption to a level even lower than that in the Sleep mode.
The “0” state is equivalent to the ordinary Sleep mode.
The EDS register is read/write-enabled.
EBFT
Input voltage determining function activating register
Input voltage determining function enabled. (Default)
Input voltage determining function disabled.
1
0
This is the register for enabling/disabling the input voltage determining function.
When set to “1,” this register activates input voltage determining function, enabling it to monitor if the input
voltage is within the specified range or not. If it is detected to be within the range, the outputs from the
nBAT_FLT pins will be at the HIGH level, and if it is outside the range, the outputs will be LOW.
When set to “0,” this register deactivates the input voltage determining function, and the outputs from the
nBAT_FLT pins will always be HIGH.
See section 6.3 for details of the input voltage determining function.
The EBFT register is read/write-enabled.
EVFT
Output voltage determining function activating register
Output voltage determining function enabled. (Default)
Output voltage determining function disabled.
1
0
This is the register for enabling/disabling the output voltage determining function (Power Good).
When set to “1,” this register activates the CH-1 to CH-3 regulators’ Power Good function, enabling them to
detect if the respective output voltages are within the specified range or not. If all are within the range, the
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outputs from the nVCC_FLT pins will be at the HIGH level, and if the output voltage from one or more of CH-1
to CH -3 is outside the range, the outputs will be LOW.
When set to “0,” this register deactivates the Power Good function, and the outputs from the nVCC_FLT pins
will always be HIGH.
See section 6.2 for details of the output voltage determining function.
The EVFT register is read/write-enabled.
XEECKH
External clock input enabling register
External clock input disabled. (Default)
External clock input enabled.
1
0
This is the register for enabling/disabling the external clock input.
When set to “1,” this register specifies the clock (approx. 1 MHz) generated by CR oscillation inside the
S1F81100 to be used as the reference clock. The reference clock is used as the operating clock for the PWM
controller.
When set to “0,” this register enables an external clock to be input from the CLKIN pin, making it possible for
the external clock to be used as the reference.
See section 6.1 for details of the external clock.
The XEECKH register is read/write-enabled.
EOSH
Internal oscillator circuit activating register
Oscillator circuit enabled. (Default)
Oscillator circuit disabled.
1
0
This is the register for activating/deactivating the S1F81100’s internal oscillator circuit.
If the register is set for disabling the oscillator circuit, the value of the current consumed by the S1F81100 can
be lowered. Note, however, that this setting eliminates the reference clock and disables operation. Therefore,
it is necessary to set the XEECKH register to “0” and input the external clock from the CLKIN pin prior to
setting it to “0.”
See section 6.1 for details of the oscillator circuit.
The EOSH registers are read/write-enabled.
IOP0n (n=0 to 3) P0n port I/O setting registers
1
0
Output
Input (Default)
These are the registers for setting the I/O properties of the P0n pins (general-use ports).
The pins function as input pins when the relevant register is set to “0,” and as output pins when set to “1.”
See section 6.4 for the P0n pins.
The IOP0n registers are read/write-enabled.
DTP0n (n=0 to 3) P0n port data registers
1
0
HIGH
LOW
These are the P0n pin data registers.
If the IOP0n registers are set to “input,” the P0n pin output levels can be read from these registers. If the IOP0n
registers are set to “output,” data set for these registers are output from the P0n pins.
See section 6.4 for the P0n pins.
The DTP0n registers are read/write-enabled.
XC1TRG
CH-1 voltage change register
No Change
Trigger Change
1
0
This is the register that directs a voltage change for the CH-1 regulator.
When this bit is set to 0 by the I2C controller, the values set in VS17 to VS10 registers are loaded into the CH-1
regulator. If the values currently output to the CH-1 differ from those set in the VS17 to VS10 registers, the
output voltage value is changed.
When it is set to “1”, those values are not loaded and a voltage change is not performed.
See section 3.1.5 for details of the voltage change trigger,
The XC1TRG register is read only.
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6. AUXILIARY FUNCTIONS AND OPERATIONS
The S1F81100 has the following auxiliary functions that can be set via the I2C controller.
1. Oscillator circuit/clock selecting function
2. Output voltage determining function
3. Input voltage determining function
4. General-purpose I/O ports
The following provides detailed descriptions of these functions.
6.1 Oscillator Circuit/Clock Selecting Function
The oscillator circuit generates the clock required for operations of the PWM controllers of CH-1 to CH-3. This
is a CR oscillator circuit that does not require external components, and internally generates approximately 1
MHz clock (Typ.).
This circuit also provides the clock selecting function. The XEECKH register in the I2C controller can be used
to select the clock from the internally generated clock and the clock externally input from the CLKIN pin. As
the CLKIN voltage level is VCC2, the clock cannot be externally selected with CH-2 output set OFF.
With the external clock selected, the S1F81100’s internal oscillator circuit can be deactivated. This way, power
consumption on the IC can be reduced. This setting can also be selected using the EOSH register of the I2C
controller.
Fig.6.1.1 is its circuit diagram.
CLKIN
XEECKH
EOSH
Reference clock
Oscillator
circuit
Fig.6.1.1 Clock Selecting Function Block Diagram
See section 5.2 for details of the XEECKH and EOSH registers.
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6.2 Output Voltage Determining Function
The S1F81100 has an output voltage determining function. This function exposes the reversed value of the
output level of the nVCC_FLT pin to the external devices when at least one of the regulators’ Power Good
circuits for CH-1 to CH-3 is determined to be “outside the specified range” during its operation.
For the nVCC_FLT pins, the output level will be as follows:
If the voltage is normal:
If the voltage is abnormal:
HIGH level
LOW level
For the nVCC_FLT pins, the voltage level will be BATT_VCC.
For determining the output voltages of the respective regulators, see sections 3.1.7, 3.2.7, and 3.3.7.
With this function, external components can detect the output level of this pin so that the application can be set
to the Sleep mode, etc. as required.
It is also possible to enable or disable this function by using the EVFT register of the I2C controller.
Fig.6.2.1 shows a block diagram of the output voltage determining function.
S1F81100
EVFT
PG1
PG2
Power Good
(CH-1)
nVCC_FLT
Power Good
(CH-2)
Power Good
(CH-3)
PG3
Fig.6.2.1 Output Determining Function Block Diagram
See section 5.2 for details of the EVFT register.
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6.3 Input Voltage Determining Function
The S1F81100 has an input voltage determining function. This function internally determines on the IC the
voltage input to the VIN pin and exposes the reversed value of the output level of the nBAT_FLT pin to the
external devices when the input value is determined to be “outside the specified range.”
For the nBAT_FLT pins, the output level will be as follows:
If the voltage is normal:
If the voltage is abnormal:
HIGH level
LOW level
For the nBAT_FLT pins, the voltage level will be BATT_VCC.
With this function, external components can detect the output level of this pin so that the application can be set
to the Sleep mode, etc. as required.
It is also possible to enable or disable this function by using the EBFT register of the I2C controller.
Fig.6.3.1 shows a block diagram of the input voltage determining function.
S1F81100
EBFT
nBAT_FLT
Input voltage
determining circuit
Fig.6.3.1 Input Voltage Detecting Function Block Diagram
See section 5.2 for details of the EBFT register.
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6.4 General-Purpose I/O Ports
The S1F81100 has four general-purpose I/O ports, P00 to P03. Fig.6.4.1 shows the configuration of the
general-purpose I/O ports.
IOP0n
P0n
DTP0n
Fig.6.4.1 General-purpose I/O Port Block Diagram
6.4.1 Description
With the IOP00 to IOP03 registers of the I2C controller, you can select the I/O properties of the respective pins.
Similarly, with the DTP00 to DTP03 registers, input data of the P00 to P03 ports can be read or output data can
be set for these pins.
See section 5.2 for details of the IOP00 to IOP03 and DTP00 to DTP03 registers.
When these pins are set to “input,” the pull-up resistance installed on the pin functions to set the HIGH level
input state even in the disconnected state.
If these ports are set to “output”, the complementary output specifications are applied.
The voltage levels of the P00 to P03 ports are as follows:
P00 and P01:
P02 and P03:
VCC2 level
VIN level
Note: P00 and P01 pins do not function with the CH-2 set to OFF.
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6.4.2 Mask Options Associated with the General-Purpose I/O Ports
The S1F81100 provides the following mask options that are associated with the general-purpose I/O ports.
[No.3] One-touch recovery function for the Sleep mode
ꢂ 1. Disable
ꢂ 2. Enable
This mask option can be used to enable/disable the one-touch recovery function.
The one-touch recovery function enables the S1F81100 unit to recover from the Sleep or Deep Sleep mode to
the Normal mode by inputting a LOW-level signal to the P02 pin when the input level of the PWR_EN pin is
held at LOW with the S1F81100 set in the Sleep or Deep Sleep mode.
This function works effectively, for example, when the sub-battery is exhausted after maintaining the
application in the Deep Sleep mode for a long period of time and it is no longer possible to set the PWR_EN pin
to HIGH.
See section 5.2 for details of the IOP02 register.
Fig.6.4.2.1 outlines the one-touch recovery function.
Note: To use the one-touch recovery function, you must set the P02 port to “INPUT” using the IOP02 register.
In addition, you must set the input level to HIGH before entering the Sleep mode.
Normal Mode
Sleep Mode
Normal Mode
PWR_EN
[Digital]
P02
[Digital]
Even though PWR_EN is kept LOW level
input, sleep mode is canceled by one-
touch recovery function.
nVCC_FLT
[Digital]
V
CC1
Fig.6.4.2.1 Outline of One-Touch Recovery Function
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7. BASIC EXTERNAL CONNECTION DIAGRAMS
VCC
VCCQ
VCCN
PLL_VCC
*1
CH-1
CH-2
CH-3
*
1
*1
PWR_EN
nVDD_FAULT
nBAT_FAULT
GP(n)
PWR_EN
nVCC_FLT
nBAT_FLT
WUP
FB4
VCC4
CC4
nRESET
nRESET
SSCAP1
SSCAP2
SSCAP3
CS3 CS2 CS1
VCC2
VCC2
BATT_VCC
VBAK
CLKIN
SDA
SCL
SDA
SCL
VIN
XSDWN
XTEST0
AD_EN
VD1
VREF
BAT1 CP1
P03
P02
P01
P00
+
CR1 CD1
VSS
XRST
Ext. Reset
Controller
[For *1 in figure, see Fig.7.2.]
Fig.7.1 Basic External Connection Diagram (1)
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V
CCn
For CH-n
(n=1 to 3)
V
INn
TPn
TNn
SWnOH
FBnM
CLn
V
CCn
+
CCn +
SWnOL
CP0n
SDn
V
SSn
Fig.7.2 Basic External Connection Diagram (2)
Table 7.1 External Component List (for reference)
Symbol
Components
Choke-type coil
P-ch power MOS transistor
N-ch power MOS transistor
Schottky diode
Capacitor
Parameter
10µH
Coments
CL1 to 3
TP1 to 3
TN1 to 3
SD1 to 3
CC1 to 3
CC4
*1
*2
*3
*4
*5
100µF
22µF
Capacitor
CS1
CS2 to 3
CD1
Capacitor
Capacitor
Capacitor
0.0068µF
0.01µF
0.1µF
CR1
Capacitor
0.1µF
CP1
Capacitor
100µF
CP01 to 03 Capacitor
47µF
BAT1
Lithium battery
(2.8)3.3 to 5.5V
(Recommended Components)
*1 SUMIDA/CR43-100(@Imax=500mA), SUMIDA/CR54-100(@Imax=1A)
*2 SANYO/CPH6315, HITACHI/HAT1043M
*3 SANYO/CPH6415, HITACHI/HAT2053M
*4 HITACHI/HRW0702A(@Imax=500mA), SANYO/SBS004, TOSHIBA/CMS06(@Imax=1A)
*5 NEC-TOKIN/ESVB20J107M
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8. ELECTRICAL CHARACTERISTICS
ꢀAbsolute maximum ratings
Parameter
Input voltage (1)
Input voltage (2)
Input voltage (3)
Allowable total output
current
Symbol
VIN
Applicable
Rating
Unit
V
V
VIN
*1
*2
-0.5 to +7.0
-0.5 to +4.5
-0.5 to +7.0
VI2
VI3
V
10
mA
Σ IVIN
Operating temperature
Storage temperature
Topr
Tstg
-40 to +85
-65 to +150
°C
°C
Soldering
temperature/time
Tsol
260°C, 10s
Allowable package loss
PD
250
mW
*1: VD1
*2: All pins except for input voltages (1) and (2).
ꢀRecommended operating range
Parameter
Input voltage
range
Symbol
VIN,VIN1,VIN2,
VIN3
Condition
3.3V output is selected for either
CH-2 or CH-3.
Min.
3.3
Typ.
Max. Unit
5.5
V
Output of less than 2.5V is selected
for both CH-2 and CH-3.
2.8
5.5
V
Rev.1.4
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53
S1F81100 Technical Manual
ꢀRegulator characteristics
[CH-1 characteristics]
(Conditions applied unless otherwise specified)
VIN=VIN1=VIN2=VIN3=4V, VSS=VSS1=VSS2=VSS3=0V, VBAK=3V,
VCC2=3.3V, VCC3=3.3V, CS1=0.01µF, IOUT1=100mA, Ta=25°C
Parameter
Symbol
Condition
Min.
Typ.
Max.
Unit
ꢅNormal operation (main and sub regulators)
Output voltage
VCC1
VCC1=0.8V
VCC1=0.9V
VCC1=1.0V
VCC1=1.1V
VCC1=1.2V
VCC1=1.3V
VCC1=1.4V
VCC1=1.5V
0.76
0.86
0.95
1.05
1.14
1.24
1.33
1.43
15
0.80
0.90
1.00
1.10
1.20
1.30
1.40
1.50
40
0.84
0.95
1.05
1.16
1.26
1.37
1.47
1.58
65
V
IS1H
VSW1On=0.9･VIN1
mA
Output current with
SW1OH and SW1OL
pins held HIGH
IS1LH
VSW1OH=0.1･VIN1
VSW1OL=0.1･VIN1
-90
-55
-65
-45
2.5
5
-40
-35
5.0
15
mA
mA
Output current with
SW1OH pin held LOW
IS1LL
Output current with
SW1OL pin held LOW
Input stability
Load stability
dVCC1-input
dVCC1-load
dVCC1/dTa･VCC1
VPG1
2.8V<VIN1<5.5V, IOUT1=100mA
VCC1=1.5V
10µA<IOUT1<500mA
VCC1=1.5V
IOUT1=100mA, -40°C<Ta<+85°C
VCC1=1.5V
VCC1=0.8V
VCC1=0.9V
VCC1=1.0V
VCC1=1.1V
VCC1=1.2V
mV
mV
Output voltage
temperature coefficient
-500
-430
ppm/°C
V
Power Good detection
voltage
0.68
0.77
0.85
0.94
1.02
1.11
1.19
1.28
0.72
0.81
0.90
0.99
1.08
1.17
1.26
1.35
80
0.76
0.86
0.95
1.05
1.14
1.24
1.33
1.43
VCC1=1.3V
VCC1=1.4V
VCC1=1.5V
VCC1=1.5V
Maximum conversion
efficiency
EFF1
%
V
IOUT1=500mA
ꢅ Sub-regulators only
Output voltage
VCC1L
VCC1=0.8V
VCC1=0.9V
VCC1=1.0V
VCC1=1.1V
VCC1=1.2V
VCC1=1.3V
VCC1=1.4V
VCC1=1.5V
1.8V<VCC3<5.5V, IOUT1=2mA
VCC1=1.5V
10µA<IOUT1<20mA
VCC1=1.5V
0.76
0.86
0.95
1.05
1.14
1.24
1.33
1.43
0.80
0.90
1.00
1.10
1.20
1.30
1.40
1.50
12
0.84
0.95
1.05
1.16
1.26
1.37
1.47
1.58
22
Input stability
Load stability
dVCC1L-input
dVCC1L-load
mV
mV
1
5
Output voltage
temperature coefficient
dVCC1/dTa･VCC1
IOUT1=2mA, -40°C<Ta<+85°C
VCC1=1.5V
-500
-430
ppm/°C
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[CH-2 characteristics]
(Conditions applied unless otherwise specified)
VIN=VIN1=VIN2=VIN3=4V, VSS=VSS1=VSS2=VSS3=0V, VBAK=3V,
VCC1=1.5V, VCC3=3.3V, CS2=0.1µF, IOUT2=100mA, Ta=25°C
Parameter
Symbol
Condition
Min.
Typ.
Max.
Unit
ꢅ Normal operation (main and sub regulators)
Output voltage
VCC2
VCC2=1.8V
VCC2=2.5V
VCC2=3.3V
1.71
2.38
3.14
15
1.80
2.50
3.30
40
1.89
2.63
3.47
65
V
IS2H
VSW2On=0.9･VIN2
mA
Output current with
SW2OH and SW2OL
pins held HIGH
IS2LH
VSW2OH=0.1･VIN2
VSW2OL=0.1･VIN2
-90
-55
-65
-45
40
-40
-35
100
mA
mA
mV
Output current with
SW2OH pin held LOW
IS2LL
Output current with
SW2OL pin held LOW
Input stability
dVCC2-input
VCC2=3.3V
3.4<VIN2<5.5V,IOUT2=300mA
Any other conditions except
VCC2=3.3V
2.8<VIN2<5.5V,IOUT2=300mA
10µA<IOUT2<1A
40
100
30
mV
Load stability
dVCC2-load
10
mV
Output voltage
temperature coefficient
Maximum duty ratio
Short circuit detection
voltage
dVCC2/dTa･VCC2
IOUT2=100mA, -40°C<Ta<+85°C
-500
100
-430
ppm/°C
MaxDuty2
VSHRT2
%
V
0.3
1
Short circuit detection
time
Power Good detection
voltage
TSHRT2
VPG2
ms
V
VCC2=1.8V
VCC2=2.5V
VCC2=3.3V
VCC3=3.3V
IOUT2=600mA
1.53
2.13
2.81
1.62
2.25
2.97
90
1.71
2.38
3.14
Maximum conversion
efficiency
EFF2
%
V
ꢅ Sub-regulators only
Output voltage
VCC2L
VCC2=1.8V
VCC2=2.5V
VCC2=3.3V
3.3V<VIN2<5.5V, IOUT2=2mA
10µA<IOUT2<10mA
IOUT2=2mA, -40°C<Ta<+85°C
1.61
2.28
3.04
1.70
2.40
3.20
7
12
-430
1.79
2.53
3.37
12
Input stability
Load stability
Output voltage
dVCC2L-input
dVCC2L-load
dVCC2/dTa･VCC2
mV
mV
ppm/°C
35
-500
14
temperature coefficient
Overload detection
current
30
mA
Rev.1.4
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S1F81100 Technical Manual
[CH-3 characteristics]
(Conditions applied unless otherwise specified)
VIN=VIN1=VIN2=VIN3=4V, VSS=VSS1=VSS2=VSS3=0V, VBAK=3V,
VCC1=1.5V, VCC2=3.3V, CS3=0.1µF, IOUT3=100mA, Ta=25°C
Parameter
Symbol
Condition
Min.
Typ.
Max.
Unit
ꢅ Normal operation (main and sub regulators)
Output voltage
VCC3
VCC3=1.8V
VCC3=2.5V
VCC3=3.3V
1.71
2.38
3.14
15
1.80
2.50
3.30
40
1.89
2.63
3.47
65
V
IS3H
VSW3On=0.9･VIN3
mA
Output current with
SW3OH and SW3OL
pins held HIGH
IS3LH
VSW3OH=0.1･VIN3
VSW3OL=0.1･VIN3
-90
-55
-65
-45
40
-40
-35
100
100
mA
mA
mV
mV
Output current with
SW3OH pin held LOW
IS3LL
Output current with
SW3OL pin held LOW
Input stability
dVCC3-input
VCC3=3.3V
3.4V<VIN3<5.5V, IOUT3=300mA
Any other conditions except
VCC3=3.3V
40
2.8V<VIN3<5.5V, IOUT3=300mA
10µA<IOUT3<1A
Load stability
dVCC3-load
10
30
mV
Output voltage
temperature coefficient
Maximum duty ratio
Short circuit detection
voltage
dVCC3/dTa･VCC3
IOUT3=100mA, -40°C<Ta<+85°C
-500
100
-430
ppm/°C
MaxDuty3
VSHRT3
%
V
0.3
1
Short circuit detection
time
Power Good detection
voltage
TSHRT3
VPG3
ms
V
VCC3=1.8V
VCC3=2.5V
VCC3=3.3V
VCC3=3.3V
IOUT3=600mA
1.53
2.13
2.81
1.62
2.25
2.97
90
1.71
2.38
3.14
Maximum conversion
efficiency
EFF3
%
V
ꢅ Sub-regulators only
Output voltage
VCC3L
VCC3=1.8V (IOUT3=2mA)
VCC3=2.5V (IOUT3=2mA)
VCC3=3.3V (IOUT3=2mA)
3.3V<VIN3<5.5V, IOUT3=2mA
10µA<IOUT3<10mA
1.61
2.28
3.04
1.70
2.40
3.20
7
1.79
2.53
3.37
12
Input stability
Load stability
dVCC3L-input
dVCC3L-load
mV
mV
12
35
Output voltage
temperature coefficient
dVCC3/dTa･VCC3
IOUT2=2mA, -40°C<Ta<+85°C
-500
14
-430
ppm/°C
Overload detection
current
30
mA
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S1F81100 Technical Manual
[CH-4 characteristics]
(Conditions applied unless otherwise specified)
VIN=VIN1=VIN2=VIN3=4V, VSS=VSS1=VSS2=VSS3=0V, VBAK=3V,
VCC1=1.5V, VCC2=3.3V, VCC3=3.3V, IOUT4=2mA, Ta=25°C
Parameter
Output voltage
Symbol
Condition
Min.
0.76
0.86
0.95
1.05
1.14
1.24
1.33
1.43
Typ.
0.80
0.90
1.00
1.10
1.20
1.30
1.40
1.50
12
Max.
0.84
0.95
1.05
1.16
1.26
1.37
1.47
1.58
22
Unit
V
VCC4
VCC4=0.8V
VCC4=0.9V
VCC4=1.0V
VCC4=1.1V
VCC4=1.2V
VCC4=1.3V
VCC4=1.4V
VCC4=1.5V
Input stability
Load stability
dVCC4-input
1.8V<VCC3<5.5V, IOUT4=2mA
VCC4=1.5V
mV
mV
dVCC4-load
10µA<IOUT4<20mA
VCC4=1.5V
1
5
Output voltage
temperature coefficient
dVCC4/dTa･VCC4
IOUT4=2mA, -40°C<Ta<+85°C
VCC4=1.5V
-500
-430
ppm/°C
Rev.1.4
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57
S1F81100 Technical Manual
ꢀMiscellaneous characteristics
[I/O characteristics]
(Conditions applied unless otherwise specified)
VIN=VIN1=VIN2=VIN3=4V, VSS=VSS1=VSS2=VSS3=0V, VBAK=3V, VCC2=2.5V,
VBAT=VCC2, BATT_VCC=VCC2, Ta=25°C
Parameter
HIGH-level input voltage
Symbol
VIH1
VIH2
VIH3
VIH4
VIH5
VIH6
VIL1
VIL2
VIL3
VIL4
VIL5
VIL6
IIH1
IIH2
IIH3
IIH4
IIH5
IIH61
IIH62
IIL1
IIL2
IIL3
Pin name
PWR_EN
P00,P01,CLKIN
SCL,SDA
AD_EN,P02,P03
XRST
XSDWN
PWR_EN
P00,P01,CLKIN
SCL,SDA
AD_EN,P02,P03
XRST
XSDWN
PWR_EN
P00,P01,CLKIN
SCL,SDA
AD_EN,P02,P03
XRST
XSDWN
XSDWN
PWR_EN
P00,P01,CLKIN
SCL,SDA
AD_EN,P02,P03
XRST
Condition
Min.
0.8･VBAT
0.8･VCC2
0.8･VCC2
0.8･VIN
0.9･VIN
0.9･VIN
Typ.
Max.
VBAT
VCC2
VCC2
VIN
VIN
VIN
0.2･VBAT
0.2･VCC2
0.2･VCC2
0.2･VIN
0.1･VIN
0.1･VIN
Unit
V
V
V
V
V
V
V
V
V
V
V
V
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
mA
LOW-level input voltage
HIGH -level input current
0
0
0
0
0
0
VIH1=VBAT
-0.5
-0.5
-0.5
-0.5
-0.5
-0.5
-4
5
5
0
8
0
0
0
0
0
VIH2=VCC2
VIH3=VCC2
VIH4=VIN
VIH5=VIN
VIH6=VIN
VIH6=0.8･VIN
VIL1=VSS
VIL2=VSS
VIL3=VSS
VIL4=VSS
0
-2.5
7.5
7.5
-1
10
10
0.5
16
16
1.2
3
LOW -level input current
IIL4
IIL5
IIL6
IOH1
12
12
0.7
2
VIL5=VSS
VIL6=VSS
VOH1=0.9･VBAT
8
0.2
1
XSDWN
HIGH -level output
current
WUP,nVCC_FLT,
nBAT_FLT,nRESET
P00,P01
SDA
P02,P03
WUP,nVCC_FLT,
nBAT_FLT,nRESET
P00,P01
SDA
P02,P03
IOH2
IOH3
IOH4
IOL1
VOH2=0.9･VCC2
VOH3=0.9･VCC2
VOH4=0.9･VIN
VOL1=0.1･VBAT
1
0
3
2
3
0.5
6
mA
µA
mA
mA
4.5
-2.5
LOW -level output
current
-4
-1
IOL2
IOL3
IOL4
VOL2=0.1･VCC2
VOL3=0.1･VCC2
VOL4=0.1･VIN
-4
-30
-8
-2.5
-15
-6
-1
-5
-4
mA
mA
mA
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[Current consumption characteristics]
(Conditions applied unless otherwise specified)
VIN=VIN1=VIN2=VIN3=4V, VSS=VSS1=VSS2=VSS3=0V, VBAK=3V,
VCC1=VCC4=1.5V, VCC2=2.5V, VCC3=3.3V, Ta=25°C
Parameter
In Normal mode
Symbol
Condition
IOUT1=1µA, IOUT2=1µA
IOUT3=1µA, IOUT4=1µA
IOUTB=1µA
Min.
Typ.
2
Max.
Unit
mA
Iexe
3
CH-1,2,3: Main regulator turned ON
IOUT2=1µA, IOUT3=1µA
IOUTB=1µA
CH-2,3: Main regulator turned ON
IOUT2=1µA, IOUT3=1µA
IOUTB=1µA
In Sleep mode (1)
In Sleep mode (2)
In Deep Sleep mode
Isleep1
Isleep2
Ids
1.4
100
50
2
mA
µA
µA
130
70
CH-2,3: Main regulator turned OFF
IOUTB=1µA
[Miscellaneous characteristics]
(Conditions applied unless otherwise specified)
VIN=VIN1=VIN2=VIN3=4V, VSS=VSS1=VSS2=VSS3=0V, VBAK=3V,
VCC1=VCC4=1.5V, VCC2=2.5V, VCC3=3.3V, VD1=2.2V, Ta=25°C
Parameter
BATT_VCC output
voltage
Symbol
Condition
Min.
Typ.
Max.
Unit
VBAT
IOUTB=1mA
In Normal and Sleep modes
In Deep Sleep mode
VCC2
VBAK
2.80
V
V
V
Input voltage abnormal
detection voltage
Built-in oscillator circuit
frequency response
Input frequency
VSVD
fOSH
fCLK
2.65
0.8
2.95
1.2
1
1
MHz
MHz
0.8
1.2
ꢀNOTES
ꢆ Use of the S1F81100 under conditions beyond the absolute maximum rating may cause malfunction or
permanent damage to it. Although the S1F81100 may temporarily operate as intended, such use can
significantly impair the reliability.
ꢆ The characteristics are not guaranteed if the S1F81100 is used outside the recommended operating range.
ꢆ Radiation-resistant design has not been provided for this chip.
ꢆ Although the S1F81100 is inherently short circuit proof, we recommend that you provide an overcurrent
protection to enhance application safety.
Rev.1.4
EPSON
59
S1F81100 Technical Manual
˜Examples of Main Characteristics (typical values)
– Current consumption vs. input voltage (Iexe) (Isleep1) (Isleep2) (Ids) (Istop)
VIN (V)
VIN (V)
(
m
A)
(mA)
VIN (V)
VIN (V)
(mA)
VIN (V)
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ꢆ Output voltage vs. input voltage (Light-Load mode)
(CH-2/CH-3: For 2.5V output)
CH2 input stability (LDO) @ sample No.1
3
2.8
2.6
2.4
2.2
2
1.8
1.6
1.4
1.2
1
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VIN (V)
(CH-2/CH-3: For 3.3V output)
CH3 input stability (LDO) @ sample No.8
4.00
3.80
3.60
3.40
3.20
3.00
2.80
2.60
2.40
2.20
2.00
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VIN (V)
Rev.1.4
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S1F81100 Technical Manual
(CH-1/CH-4: For 1.1V output)
CH4 input stability (LDO) @ sample No.1
2.000
1.800
1.600
1.400
1.200
1.000
0.800
0.600
0.400
0.200
0.000
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VCC3 (V)
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˜Examples of Transient Response Characteristics (typical values)
– Output voltage rising waveform
(CH-1: For 1.1V output)
CH1 starting waveform 100mA load
Ch1 cycle
No cycle
Ch1 frequency
No cycle
– Load fluctuation
(CH-1: For 1.1V output)
Load response
Load response
250mA load --> No load
No load --> 300mA load
Ch1 cycle
No cycle
Ch 1 cycle
Low resolution
Ch 1 frequency
Ch1frequency
No cycle
Low resolution
No load
No load
L
I =300mA
L
I =250mA
(CH-2: For 2.5V output)
Load response
300mA load --> No load
Load response
No load --> 300mA
Ch1 frequency
Ch1 frequency
Low resolution
Insufficient
amplitute
No load
L
I =300mA
No load
L
I =300mA
Rev.1.4
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S1F81100 Technical Manual
ꢀReference Data (typical values)
ꢆ Conversion efficiency vs. output current
(CH-1: Conversion efficiency vs. load current)
S1F81100 VCC1 efficiency v.s. Iload
100
90
80
70
60
50
40
30
20
10
0
at VCC1=0.8V
at VCC1=1.2V
at VCC1=1.5V
0
100
200
300
400
500
600
700
Iload [mA]
[Measured Condition]
VIN=3.6V, VSS=0V, Ta=25°C
P-ch Power MOS (TP1): SANYO/CPH6315
N-ch Power MOS (TN1): SANYO/CPH6415
Schottky Diode (SD1): SANYO/SBS004
Coil (CL1): SUMIDA/CR43-100
Capacitor (CC1): NEC-TOKIN/ESVB20J107M
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ꢆ Conversion efficiency vs. output current
(CH-2 and CH-3: Conversion efficiency vs. load current)
S1F81100 VCCn efficiency v.s. Iload
100
90
80
70
60
50
40
30
20
10
0
at VCCn=3.3V
at VCCn=2.5V
0
200
400
600
800
1000
1200
Iload [mA]
[Measured Condition]
VIN=3.6V, VSS=0V, Ta=25°C
P-ch Power MOS (TPn): SANYO/CPH6315
N-ch Power MOS (TNn): SANYO/CPH6415
Schottky Diode (SDn): SANYO/SBS004
Coil (CLn): SUMIDA/CR54-100
Capacitor (CCn): NEC-TOKIN/ESVB20J107M
Note: n=2,3
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9. PACKAGE
<QFP12-48>
9±0.4
7±0.1
9±0.4
36
25
37
24
INDEX
48
13
1
12
+0.1
0.5
0.18
-0.05
0.125±0.05
0°
10°
0.5±0.2
1
Unit: mm
Fig.9.1 QFP12-48 Package
66
EPSON
Rev.1.4
S1F81100 Technical Manual
<QFN7-48>
7
6.75
+0.18
−0.18
0.42
13
24
12
25
36
1
48
37
0.5
Fig.9.2 QFN7-48 Package
Rev.1.4
EPSON
67
S1F81100 Technical Manual
10. PAD LAYOUT
F8110D0**
unit: mm
Fig.10.1 Pad Layout
68
EPSON
Rev.1.4
S1F81100 Technical Manual
Table 10.1 Pad Coordinates
(Unit: µm)
Pad #
Pad Name
X
Y
Pad #
Pad Name
X
Y
1
2
3
4
5
6
7
8
9
VBAK
1336
1557
38 (DUMMY PAD)
-926
-1557
(DUMMY PAD)
BATT_VCC
PWR_EN
(DUMMY PAD)
WUP
nRESET
nBAT_FLT
nVCC_FLT
587
470
356
238
124
39 (DUMMY PAD)
40 SW3OL
41 (DUMMY PAD)
42 VSS3
43 VCC1
44 VIN1
45 (DUMMY PAD)
46 SW1OH
47 FB1M
48 SW1OL
49 (DUMMY PAD)
50 VSS1
51 (DUMMY PAD)
52 SSCAP3
53 SSCAP2
54 SSCAP1
55 (DUMMY PAD)
-813
-695
-500
-383
-152
-11
127
268
410
550
663
781
894
1012
1128
1243
1520
7
-107
-224
-338
-453
-571
-684
-807
-1144
-1289
-1520
10 (DUMMY PAD)
11 P00
12 P01
13 (DUMMY PAD)
14 SCL
15 SDA
16 (DUMMY PAD)
17 XPOR(N.C.)
18 (DUMMY PAD)
1324
1211
-1321
19 P02
20 P03
21 VCC2
22 VIN2
23 (DUMMY PAD)
24 SW2OH
25 FB2M
26 SW2OL
27 (DUMMY PAD)
28 VSS2
29 (DUMMY PAD)
30 VCC3
31 VIN3
1071
889
405
263
126
56 (DUMMY PAD)
57 FB4
58 VCC4
-1203
-1090
-859
-741
-628
-510
-397
-263
-149
-32
82
200
340
486
627
744
858
59 VIN
60 (DUMMY PAD)
61 (DUMMY PAD)
62 (DUMMY PAD)
63 XRST
64 XTEST0
65 XSDWN
66 (DUMMY PAD)
67 AD_EN
68 TCLK(N.C.)
69 CLKIN
70 (DUMMY PAD)
71 VSS
72 TIREF(N.C.)
-16
-156
-287
-403
-516
-634
-862
-980
-1093
-1211
-1324
-1557
32 (DUMMY PAD)
33 (DUMMY PAD)
34 SW3OH
35 (DUMMY PAD)
-1273
-1160
-1042
36 (DUMMY PAD)
37 FB3M
73 VREF
74 VD1
975
1440
Rev.1.4
EPSON
69
S1F81100 Technical Manual
11. TERMINAL EQUIVALENT CIRCUIT
S1F81100 I/O Terminal equivalent Circuit [Input]
BATT_VCC BATT_VCC
(PAD)
(PAD)
(PAD)
PWR_EN
VCC2
VCC2
SCL,CLKIN
VIN
VIN
XRST,AD_EN
XTEST0,XSDWN
Fig.11.1(a) Terminal Equivalent Circuit
70
EPSON
Rev.1.4
S1F81100 Technical Manual
S1F81100 I/O Terminal equivalent Circuit [Output]
BATT_VCC (VCC2
)
(PAD)
S1F81100 I/O Terminal equivalent Circuit [I/O]
V
CC2
(CTRL)
(PAD)
P00,P01,SDA
V
IN
(CTRL)
(PAD)
P02,P03
Fig.11.1(b) Terminal Equivalent Circuit
Rev.1.4
EPSON
71
S1F81100 Technical Manual
APPENDIX SELECTION OF PWM CONTROLLER’S EXTERNAL
COMPONENTS
This section provides information regarding the selection of external components for the PWM controller to
configure the switching regulators with respect to the CH-1, CH-2 and CH-3 in the S1F81100. Please use the
information in this section as a basis of component selection.
Note: For details of the specifications of the recommended components listed below, see their documents.
ꢀInput capacitors (CP01, CP02, CP03)
The key selection criteria for the input capacitors is their allowable ripple current values included in their
specification values.
First, the maximum load current on your application should be determined before selecting a capacitor with an
allowable ripple current specification value that is at least equal to or greater than the determined maximum
load current.
ꢀPower MOS transistors (TP1, TP2, TP3, TN1, TN2, TN3)
Select Power MOS transistors that have low on-resistance and small gate capacity for both P- and N-channels.
Higher on-resistance means greater power loss in the power MOS transistors when the switching regulator in
operation, which can impair conversion efficiency. The greater the gate capacity, the higher the charge and
discharge power when the switching regulator in operation, which can also impair conversion efficiency.
ꢀSchottky diodes (SD1, SD2, SD3)
Select a Schottky diode that has forward current capability equal to or greater than the maximum load current
value on your application or has a low forward voltage.
ꢀCoils (inductors) (CL1, CL2, CL3)
Select a coil with a low dc-resistance and a large rated current.
Larger dc-resistance means greater power loss in the inductors when the switching regulator in operation, which
can impair conversion efficiency.
To prevent the inductors from being saturated, it is required to select a rated current that is far greater than the
current value to use. If an inductor saturates, the ripple current increased, which may cause the outputs to
become unstable. We, therefore, recommend that you select the rated current approximately twice the load
current value on the application.
The recommended inductance is 10 µH.
ꢀRegulator output capacitors (CC1, CC2, CC3)
For a regulator output capacitor, an aluminum or tantalum capacitor of approximately 100µF.
Due to the internal circuit configurations, use of a low ESR capacitor may not ensure that the S1F81100
provides normal voltage outputs. We, therefore, recommend that you select a capacitor that has approximately
200 mΩ of ESR. (To solve such output anomalies, an improved component is under development)
ꢀExamples of Component Selection
Type
Maker
SANYO
HITACHI
SANYO
Model Number
CPH6315
HAT1043M
CPH6415
P-ch
power MOS transistor
N-ch
power MOS transistor
HITACHI
HITACHI
SANYO
HAT2053M
HRW0702A
SBS004
Schottky diode
TOSHIBA
SUMIDA
CMS06
Inductor
CR43-100
CR54-100
CR75-100
ESV20J107M
Regulator output capacitor
NEC TOKIN
72
EPSON
Rev.1.4
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HEADQUARTERS
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Phone: +65-6337-7911
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Phone: +44-(0)1344-381700
FAX: +44-(0)1344-381701
ELECTRONIC DEVICES MARKETING DIVISION
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1 Avenue de l’ Atlantique, LP 915 Les Conquerants
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Phone: +33-(0)1-64862350
FAX: +33-(0)1-64862355
Phone: +81-(0)42-587-5816
FAX: +81-(0)42-587-5624
BARCELONA BRANCH OFFICE
Barcelona Design Center
Edificio Testa, Avda. Alcalde Barrils num. 64-68
ED International Marketing Department
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Phone: +81-(0)42-587-5814
FAX: +81-(0)42-587-5117
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Phone: +34-93-544-2490
FAX: +34-93-544-2491
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Livingston West Lothian, EH54 7EG, SCOTLAND
Phone: +44-1506-605040
FAX: +44-1506-605041
S1F81100
Technical Manual
SEIKO EPSON CORPORATION
ELECTRONIC DEVICES MARKETING DIVISION
EPSON Electronic Devices Website
http://www.epsondevice.com/
First issue September, 2002
H
Printed March, 2003 in Japan
A
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