SED1221DXA [SEIKO]
16X60 DOTS DOT MAT LCD DRVR AND DSPL CTLR, UUC165, DIE-165;
| 型号： | SED1221DXA |
| 厂家： | 
SEIKO EPSON CORPORATION |
| 描述： | 16X60 DOTS DOT MAT LCD DRVR AND DSPL CTLR, UUC165, DIE-165 CD |
| 文件： | 总50页 (文件大小：398K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SED1220
• Built-in CR oscillation circuit (C and R contained)
• Accepts external clock input
• High-speed MPU interface
Affords interface with both 68/80 system MPUs
Affords interface through 4 bits and 8 bits
• Affords serial interface
OVERVIEW
SED1220 is a dot matrix LCD controller/driver for
character display. Using 4bits data, 8bits data or serial
data being provided from the micro computer, it displays
up to 36 characters, 4 user defined characters and up to
120 symbols.
Up to 256 types of built-in character generator ROMs are
prepared. Each character font is consisted of 5 × 8 dots.
It also contains the RAM for displaying 4 user defined
characters each font consisting of 5 × 8 dots. It is symbol
register allows character display with high degree of
freedom. This handy equipment can be operated with
minimum power consumption with its low power
consumption design, standby and sleeping mode.
• Character font consists of 5 × 8 dots
1
• Duty ratio
1/26 (SED1220D**)
1/18 (SED1221D**, SED1222D**)
2
• Simplified command setting
• Built-in power circuit for driving liquid crystal
Power amplifier circuit, power regulation circuit and
voltage followers × 4
• Built-in electronic volume function
• Low power consumption
80 µA max.
(In normal operation, including
operating current of the power
supply).
(In standby mode for displaying
static icon).
FEATURES
• Built-in data display RAM – 36 characters + 4 user
defined characters + 120 symbols.
• CG ROM (For up to 256 characters), CG RAM (for 4
characters) and symbol register (for 120 symbols).
• No. of display digit and lines
20 µA max.
5 µA max.
(In sleeping mode when display
is turned off).
< In normal mode >
(12 digits + 4 segments for signal) × 3 lines + 120
• Power supply
1
VDD - VSS
VDD - V5
–2.4 V ~ –3.6 V
–4.0 V ~ – 6.0 V
symbols + 5 static symbols (SED1220D**)
(12 digits + 4 segments for signal) × 2 lines + 120
2
• Temperature range for wide range operation
Ta = –30 ~ 85°C
• CMOS process
symbols + 5 static symbols (SED1221D**)
12 digits × 2 lines + 120 symbols + 5 static symbols
3
(SED1222D**
(12 digits + 4 segments for signal) × 2 lines + 120
symbols + 10 static symbols (SED122AD**)
< In standby mode >
5 static symbols
5 static symbols
5 static symbols
10 static symbols
)
• Shipping style
4
Chip (Al pad product)
Chip (Au bump product)
TCP
SED1222D*A
SED122 D*B
*
SED122 T**
*
1
• This unit does not employ radiation protection design
2
3
4
EPSON
4–1
SED1220
BLOCK DIAGRAM
LCD power circuit
Oscillator
Timing generatinon circuit
Refresh address counter
DD RAM
symbol
register
CG ROM
CG RAM
Address counter
Input buffer
MPU interface
4–2
EPSON
SED1220
CHIP SPECIFICATION
SED1220D /1221D /122AD
**
**
**
146
74
73
147
63
62
56
55
165
54
1
:DUMY PAD
:PAD
SED122 D**
*
↑
Digits prepared for CGROM pattern changes
Chip size:
Pad pitch:
7.70 × 2.77 mm
100 µm (Minimum)
Chip thickness (for reference): 625 ± 25 µm (SED122 D*A)
*
(SED122 D*B)
*
1) A1 pad specifications
Pad size on Y side:
75 µm × 135 µm
135 µm × 75 µm
Pad size on X side:
2) Au bump specifications
Bump size on Y side:
Bump size on X side:
Bump height (for reference)
69 µm × 129 µm
129 µm × 69 µm
22.5 µm ± 5.5 µm
<Fuse Pines>
1) Al pad. pad size
2) Au bump
Bump size
86 µm × 75 µm
80 µm × 69 µm
EPSON
4–3
SED1220
SED1222D
**
108
52
. . . . . . . . .
109
51
y
41
40
x
Top View
34
33
125
. . .
. . . . . . . . .
. . .
12
27
1
11
28
32
: PAD
SED1222D**
↑
Digits prepared for CGROM pattern changes
Chip size:
Pad pitch:
7.70 × 2.77 mm
124 µm (Minimum)
Chip thickness (for reference): 625 ± 50 µm (SED1222D*A)
1) A1 pad specifications
Pad size on Y side:
90 µm × 96 µm
96 µm × 90 µm (PAD. No. 1 ~ 11, 28 ~ 32, 52 ~ 108)
175 µm ×135 µm (PAD. No. 12 ~ 27)
Pad size on X side:
<Fuse Pines>
1) Al pad. pad size
86 µm × 75 µm
4–4
EPSON
SED1220
<SED1220D /1221D >
** **
Unit: µm
PAD
COORDINATES
PAD
COORDINATES
No.
Name
X
Y
No.
Name
X
Y
1
2
3
4
5
6
7
8
9
NC
NC
NC
A0
WR
CS
D7
D6
D5
D4
D3
D2
D1
–3700
–3600
–3500
–3252
–3132
–3012
–2892
–2772
–2652
–2532
–2412
–2292
–2172
–2052
–1836
–1736
–1556
–1456
–1276
–1176
–996
–896
–716
–616
–436
–336
–156
–56
–1204
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
VDD
(FSA)
(FSB)
(FSC)
(FS0)
(FS1)
(FS2)
(FS3)
VDD
COMSA
COMS1
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
NC
NC
NC
SEGS1
SEGS2
SEG1
SEG2
SEG3
SEG4
SEG5
3670
3603
–910
–796
–696
–596
–496
–396
–296
–196
–82
61
203
303
403
503
603
703
803
903
1003
1204
3603
3670
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
D0
VDD
VDD
VSS
VSS
V5
V5
V4
V4
V3
V3
V2
V2
V1
V1
V0
V0
VR
VR
VOUT
VOUT
CAP2–
CAP2–
CAP2+
CAP2+
CAP1–
CAP1–
CAP1+
CAP1+
VSS
VSS
VDD
VDD
CK
VS1
P/S
I/F
RES
NC
NC
NC
3670
3700
3600
3500
3319
3219
3119
3019
2919
2819
2719
2619
2519
2419
2319
2219
2119
2019
1919
1819
1719
1619
1519
1419
1319
1219
1119
1019
919
124
224
404
504
684
784
964
SEG6
SEG7
SEG8
SEG9
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
SEG16
SEG17
SEG18
SEG19
SEG20
SEG21
SEG22
SEG23
SEG24
SEG25
SEG26
SEG27
SEG28
SEG29
SEG30
1064
1244
1344
1524
1624
1804
1904
2084
2184
2364
2464
2693
2821
2949
3077
3205
3500
3600
3700
100
101
102
103
104
105
106
107
108
819
719
619
519
419
319
219
–1204
1204
(FS*)
: Being fuse adjusting pins, maintain them on floating state.
CK pins : Should be VDD when not being used.
EPSON
4–5
SED1220
PAD
COORDINATES
No.
109
Name
X
Y
SEG31
SEG32
SEG33
SEG34
SEG35
SEG36
SEG37
SEG38
SEG39
SEG40
SEG41
SEG42
SEG43
SEG44
SEG45
SEG46
SEG47
SEG48
SEG49
SEG50
SEG51
SEG52
SEG53
SEG54
SEG55
SEG56
SEG57
SEG58
SEG59
SEG60
SEGS4
SEGS5
COM24
COM23
COM22
NC
119
19
–81
–181
–281
–381
–481
–581
–681
1204
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
–781
–881
–981
–1081
–1181
–1281
–1381
–1481
–1581
–1681
–1781
–1881
–1981
–2081
–2181
–2281
–2381
–2481
–2581
–2681
–2781
–2881
–2981
–3081
–3181
–3281
–3500
–3600
–3700
–3670
NC
NC
1204
1000
900
800
700
600
500
400
300
COM21
COM20
COM19
COM18
COM17
COM16
COM15
COM14
COM13
COM12
COM11
COM10
COM9
COMS2
SEGSA
SEGSB
SEGSC
SEGSD
SEGSE
200
100
0
–100
–200
–300
–433
–533
–633
–733
–833
–3670
4–6
EPSON
SED1220
<SED1222D >
**
Unit: µm
PAD
COORDINATES
PAD
COORDINATES
No.
Name
X
Y
No.
Name
X
Y
1
2
3
4
5
6
7
8
9
A0
WR
CS
D7
D6
D5
D4
D3
D2
D1
D0
VDD
VSS
V5
V4
V3
V2
V1
V0
VR
VOUT
CAP2–
CAP2+
CAP1–
CAP1+
VSS
VDD
CK
VS1
P/S
I/F
RES
VDD
(FSA)
(FSB)
(FSC)
(FS0)
(FS1)
(FS2)
(FS3)
VDD
COMSA
COMS1
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
SEG1
SEG2
SEG3
–3312
–3180
–3048
–2916
–2784
–2652
–2520
–2388
–2256
–2124
–1992
–1786
–1506
–1226
–946
–666
–386
–106
174
–1228
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
SEG4
SEG5
SEG6
SEG7
SEG8
3100
2976
2852
2728
2604
2480
2356
2232
2108
1984
1860
1736
1612
1488
1364
1240
1116
992
1228
SEG9
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
SEG16
SEG17
SEG18
SEG19
SEG20
SEG21
SEG22
SEG23
SEG24
SEG25
SEG26
SEG27
SEG28
SEG29
SEG30
SEG31
SEG32
SEG33
SEG34
SEG35
SEG36
SEG37
SEG38
SEG39
SEG40
SEG41
SEG42
SEG43
SEG44
SEG45
SEG46
SEG47
SEG48
SEG49
SEG50
SEG51
SEG52
SEG53
SEG54
SEG55
SEG56
SEG57
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
–1228
–1204
868
744
620
496
372
248
124
454
734
1014
1294
1574
1854
2134
2414
2692
2836
2980
3124
3268
3694
3603
0
–1204
–1228
–124
–248
–372
–496
–620
–744
–868
–992
–1116
–1240
–1364
–1488
–1612
–1736
–1860
–1984
–2108
–2232
–2356
–2480
–2604
–2728
–2852
–2976
–3100
–3224
–3348
–3472
–1228
–919
–796
–696
–596
–496
–396
–296
–196
–73
63
199
323
447
571
695
819
943
1067
1191
1228
1228
1228
3603
3694
100
101
102
103
104
105
106
107
108
3694
3472
3348
3224
1228
(FS*)
: Being fuse adjusting pins, maintain them on floating state.
CK pins : Should be VDD when not being used.
EPSON
4–7
SED1220
PAD
COORDINATES
No.
109
Name
X
Y
SEG58
SEG59
SEG60
COM16
COM15
COM14
COM13
COM12
COM11
COM10
COM9
COMS2
SEGSA
SEGSB
SEGSC
SEGSD
SEGSE
–3694
1191
1067
943
819
695
571
447
323
119
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
75
–49
–173
–335
–459
–583
–707
–831
–3694
4–8
EPSON
SED1220
<SED122AD >
**
Unit: µm
PAD
COORDINATES
PAD
COORDINATES
No.
Name
X
Y
No.
Name
X
Y
1
2
3
4
5
6
7
8
9
NC
NC
NC
A0
WR
CS
D7
D6
D5
D4
D3
D2
D1
–3700
–3600
–3500
–3252
–3132
–3012
–2892
–2772
–2652
–2532
–2412
–2292
–2172
–2052
–1836
–1736
–1556
–1456
–1276
–1176
–996
–896
–716
–616
–436
–336
–156
–56
–1204
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
VDD
(FSA)
(FSB)
(FSC)
(FS0)
(FS1)
(FS2)
(FS3)
VDD
COMSA
COMS1
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
NC
NC
NC
SEGS1
SEGS2
SEG1
SEG2
SEG3
SEG4
SEG5
3670
3603
–910
–796
–696
–596
–496
–396
–296
–196
–82
61
203
303
403
503
603
703
803
903
1003
1204
3603
3670
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
D0
VDD
VDD
VSS
VSS
V5
V5
V4
V4
V3
V3
V2
V2
V1
V1
V0
V0
VR
VR
VOUT
VOUT
CAP2–
CAP2–
CAP2+
CAP2+
CAP1–
CAP1–
CAP1+
CAP1+
VSS
VSS
VDD
VDD
CK
VS1
P/S
I/F
RES
NC
NC
NC
3670
3700
3600
3500
3319
3219
3119
3019
2919
2819
2719
2619
2519
2419
2319
2219
2119
2019
1919
1819
1719
1619
1519
1419
1319
1219
1119
1019
919
124
224
404
504
684
784
964
SEG6
SEG7
SEG8
SEG9
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
SEG16
SEG17
SEG18
SEG19
SEG20
SEG21
SEG22
SEG23
SEG24
SEG25
SEG26
SEG27
SEG28
SEG29
SEG30
1064
1244
1344
1524
1624
1804
1904
2084
2184
2364
2464
2693
2821
2949
3077
3205
3500
3600
3700
100
101
102
103
104
105
106
107
108
819
719
619
519
419
319
219
–1204
1204
(FS*)
: This is a fuse adjusting terminal. Set it to floating state.
CK pins : Set it to VDD when not used.
EPSON
4–9
SED1220
PAD
COORDINATES
No.
109
Name
X
Y
SEG31
SEG32
SEG33
SEG34
SEG35
SEG36
SEG37
SEG38
SEG39
SEG40
SEG41
SEG42
SEG43
SEG44
SEG45
SEG46
SEG47
SEG48
SEG49
SEG50
SEG51
SEG52
SEG53
SEG54
SEG55
SEG56
SEG57
SEG58
SEG59
SEG60
SEGS4
SEGS5
NC
119
19
–81
–181
–281
–381
–481
–581
–681
1204
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
–781
–881
–981
–1081
–1181
–1281
–1381
–1481
–1581
–1681
–1781
–1881
–1981
–2081
–2181
–2281
–2381
–2481
–2581
–2681
–2781
–2881
–2981
–3081
–3181
–3281
–3500
–3600
–3700
–3670
NC
NC
NC
NC
NC
1204
1000
900
800
700
600
500
400
300
COM16
COM15
COM14
COM13
COM12
COM11
COM10
COM9
COMS2
SEGSA
SEGSB
SEGSC
SEGSD
SEGSE
SEGSF
SEGSG
SEGSH
SEGSI
SEGSJ
200
67
–33
–133
–233
–333
–433
–533
–633
–733
–833
–3670
4–10
EPSON
SED1220
Q’ty
DESCRIPTION OF PINS
Power Pins
Pin name
VDD
I/O
Description
Power supply Connected to logic supply. Common with MPU power terminal VCC.
Power supply 0V power terminal connected to system ground.
Power supply Multi-level power supply for liquid crystal drive.
The voltage determined in the liquid crystal cell is resistance-
divided or impedance-converted by operational amplifier, and the
resultant voltage is applied.
1
1
6
VSS
V0, V1
V2, V3
V4, V5
The potential is determined on the basis of VDD and the following
equation must be respected.
VDD = V0 ≥ V1 ≥ V2 ≥ V3 ≥ V4 ≥ V5
VDD ≥ VSS ≥ V5 ≥ VOUT
When the built-in power supply is ON, the following voltages are
given to pins V1 to V4 by built-in power circuit:
V1 = 1/5 V5
V2 = 2/5 V5
V3 = 3/5 V5
V4 = 4/5 V5
(1/4 V5)
(2/4 V5)
(3/4 V5)
(4/4 V5) voltage ratings in ( ) are for optinal choices.
VS1
O
Power supply voltage output pin for oscillating circuit, and DC/DC
source. Don’t connect this pin to an external load.
1
LCD Power Circuit Pins
Pin name
I/O
Description
Q’ty
CAP1+
O
Capacitor positive side connecting pin for boosting.
This pin connects the capacitor with pin CAP1–.
Capacitor negative side connecting pin for boosting.
This pin connects a capacitor with pin CAP+.
Capacitor positive side connecting pin for boosting.
This pin connects a capacitor with pin CAP2–.
Capacitor negative side connecting pin for boosting.
This pin connects a capacitor with pin CAP2+.
Output pin for boosting. This pin connects a smoothing capacitor
with VDD pin.
1
CAP1–
CAP2+
CAP2–
VOUT
O
O
O
O
I
1
1
1
1
1
VR
Voltage regulating pin. This pin gives a voltage between VDD and
V5 by resistance-division of voltage.
EPSON
4–11
SED1220
Pins for System Bus Connection
Pin name
D7 (SI)
D6 (SCL)
D5 ~ D0
I/O
I
Description
Q’ty
8
8-bit input data bus. These pins are connected to a 8-bit or 16-bit
standard MPU data bus.
When P/S = “Low”, the D7 and D6 pins are operated as a serial data
input and a serial clock input respectively.
P/S RES I/F D7 D6 D5 D4
“L” SI SCL
“H” “H” “H” D7 D6 D5 D4
“H” “L” “H” D7 D6 D5 D4
“H” “L” “L” D7 D6 D5 D4
RES: Indicates the active potential.
D3-D0
OPEN
D3-D0
D3-D0
OPEN
CS A0 WR
—
—
—
—
CS A0
CS A0
—
E
CS A0 WR
CS A0 WR
OPEN:Though “OPEN” is available, fixing the potential is
recommended for noise-withstnading characteristical reason.
Indicates that it can be set at either “H” or “L”, but fixing the
potential is required.
—:
A0
I
I
Usually, this pin connects the least significant bit of the MPU address
bus and identifies a data command.
0 : Indicates that D0 to D7 are a command.
1 : Indicates that D0 to D7 are display data.
In case of a 68 series MPU, initialization can be performed by
1
1
RES
changing RES
initialization can be performed by changing
. In case of an 80 series MPU,
.
A reset operation is performed by edge sensing of the RES signal.
An interface type for the 68/80 series MPU is selected by input level
after initialization.
“L” : 68 series MPU interface
“H” : 80 series MPU interface
CS
I
I
Chip select signal. Usually, this pin inputs the signal obtained by
decoding an address bus signal. At the “Low” level, this pin is
enabled.
1
1
WR
(E)
<When connecting an 80 series MPU>
Active “Low”. This pin connects the WR signal of the 80 series
MPU. The signal on the data bus is fetched at the rise of the WR
signal.
<When connecting a 68 series MPU>
Active “High”. This pin becomes an enable clock input of the 68
series MPU.
P/S
I
This pin switches between serial data input and parallel data input.
1
P/S
“High”
“Low”
Chip Select Data/Command
Data
D0~D7
SI
Serial Clock
CS
CS
A0
A0
–
SCL
IF
I
I
Interface data length select pin for parallel data input.
“High”: 8-bit parallel input
“Low”: 4-bit parallel input
When P/S = “Low”, connect this pin to VDD or VSS.
External input terminal
1
1
CK
It must be fixed to “High” when the internal oscillation circuit is used.
4–12
EPSON
SED1220
Liquid Crystal Drive Circuit Signals
Dynamic drive terminal (SED1220D**/1221D**/122AD**)
Pin name
COM1~
COM24
COMS1,
CMOS2
SEG1~
SEG60
SEGS1, 2
4, 5
I/O
Description
Q’ty
O
Common signal output pin (for characters)
24
Common signal output pin (except for characters)
CMOS1, CMOS2: Common output for symbol display
O
O
O
2
60
4
Segment signal output pin (for characters)
Segment signal output pin (except for characters)
SEGS1, SEGS2: Segment output for signal output
Dynamic drive terminal (SED1222D**)
Pin name
COM1~
COM16
COMS1,
CMOS2
SEG1~
I/O
Description
Q’ty
O
Common signal output pin (for characters)
16
Common signal output pin (except for characters)
CMOS1, CMOS2: Common output for symbol display
O
O
2
Segment signal output pin (for characters)
60
SEG60
Static drive terminal
Pin name
COMSA
I/O
O
Description
Common signal output pin (for icon)
Q’ty
1
SEGSA, B
C, D, E
F, G, H, I, J
Segment signal output pin (for icon)
SEGSF, G, H, I, J (only SED122A)
5 to
10
O
Note: For the electrode of liquid crystal display panel to be connected to the static drive terminal, we recommend
you to use a pattern in which it is separated from the electrode connected to the dynamic drive terminal.
When this pattern is too close to the other electrode, both the liquid crystal display and electrode will be
deteriorated.
EPSON
4–13
SED1220
FUNCTIONAL DESCRIPTION
MPU Interface
Selection of interface type
In the SED1220 Series, data transfer is performed through a 8-bit or 4-bit data bus or a serial data input (SI). By selecting
“High” or “Low” as P/S pin polarity, a parallel data input or a serial data input can be selected as shown in Table 1.
Table 1
P/S
“High” Parallel Input
“Low” Serial Input
Type
CS
CS
CS
A0
A0
A0
WR
WR
H, L
SI
—
SI
SCL
—
D0~D7
D0~D7
—
SCL
Parallel Input
In the SED1220 Series, when parallel input is selected (P/S = “High”), it can be directly connected to the 80 series MPU
bus or 68 series MPU bus, as shown in Table 2, if either “High” or “Low” is selected as RES pin polarity after a reset input,
because the RES pin has an MPU select function.
Selection between 8 bits and 4 bits is performed by command.
Table 2
RES input polarity
Type
68 series
80 series
A0
A0
A0
WR
E
WR
CS
CS
CS
D0~D7
D0~D7
D0~D7
↓ active
↓
active
Interface with 4-bit MPU interface
When data transfer is performed by 4-bit interface (IF = 0), an 8-bit command, data and address are divided into two parts.
CS
WR
D7 to D4
Upper (D7 to D4)
Lower (D3 to D0)
Note: When performing writing in succession, reverse a time exceeding the system cycle time (tcyc) and then
perform writing.
Serial interface (P/S = “Low”)
The serial interface consists of a 8-bit shift register and a 3-bit counter and acceptance of an SI input or SCL input is enabled
in the ship selected status (CS = “Low”).
When no chip is selected, the shift register and counter are reset to the initial status.
Serial data is input in the order of D7, D6 .... D0 from the serial data input pin (SI) at the rise of Serial Clock (SCL).
At the rising edge of the 8th serial clock, the serial data is converted into 8-bit parallel data and this data is processed.
The A0 input is used to identify whether the serial data input (SI) is display data or a command. That is, when A0 = “High”,
it is regarded as display data. When A0 = “Low”, it is regarded as a command.
The A0 input is read in and identified at the rise of the 8 x n-th clock of Serial Clock (SCL) after chip selection.
Fig. 1 shows a timing chart of the serial interface.
Regarding the SCL signal, special care must be exercised about terminal reflection and external noise due to a wire length.
We recommend the user to perform an operation check with a real machine.
We also recommend the user to periodically refresh the write status of each command to prevent a malfunction due to noise.
4–14
EPSON
SED1220
CS
SI
D7
D6
D5
D4
D3
D2
D1
D0
D7
SCL
A0
1
2
3
4
5
6
7
8
9
Fig. 1
Identification of data bus signals
The SED1220 series identifies data bus signals, as shown in Table 3, by combinations of A0 and WR (E).
Table 3
Common
68 series
80 series
Function
A0
1
0
E
1
1
WR
0
0
Writing to RAM and symbol register
Writing to internal register (command)
Chip select
The SED1220 series has a chip select pin (CS). Only when CS = “Low”, MPU interfacing is enabled.
In any status other than Chip Select, D0 to D7 and A0, WR, SI and SCL inputs are invalidated. When a serial input interface
is selected, the shift register and counter are reset.
However, the Reset signal is input regardless of the CS status.
Power Circuit
This is a low-power-consumption power circuit that generates a voltage required for liquid crystal drive.
The power circuit consists of a boosting circuit, voltage regulating circuit and voltage follower.
The power circuit incorporated in the SED1220 Series is set for a small-scale liquid crystal panel, so that its display quality
may be greatly deteriorated if it is used for a liquid crystal panel with a large display capacity.
In this case, an external power supply must be used.
A power circuit function can be selected by power control command. With this, an external power supply and a part of
the internal power supply can be used together.
Amplifying
circuit
Voltage regulat-
Voltage
follower
External
voltage input
—
Amplifying
system pin
Per specification
OPEN
ing circuit
●
×
×
●
●
×
●
●
●
×
VOUT
Note 1
Note 2
Note 3
V5 = VOUT
V1, V2, V3, V4, V5
OPEN
OPEN
×
×
Note 1: When the boosting circuit is turned off, make boosting system pins (CAP1+, CAP1-, CAP2+, CAP2-) open
and give a liquid crystal drive voltage to the VOUT pin from the outside.
Note 2: When the voltage regulating circuit is not used with the boosting circuit OFF, make the boosting system pins
open, connect between the V5 pin and VOUT pin, and give a liquid crystal drive voltage from the outside.
Note 3: When all the internal power supplies are turned off, supply liquid crystal drive voltages V1, V2, V3, V4 and
V5 from the outside, and make the CAP1+, CAP1-, CAP2+, CAP2- and VOUT pins open.
EPSON
4–15
SED1220
Voltage Tripler Circuit
If capacitors are connected between CAP+1 – CAP–1
and CAP2+,CAP2– and VSS VOUT, VDD– VSS potential
is negatively tripled and generated at VOUT terminal.
When the voltage is boosted double, open CAP2+ and
connect CAP2– to VOUT terminal.
At this time, the oscillating circuit must be operating
since the amplifying circuit utilize the signal from the
oscillation output.
VDD=0V
VDD=0V
=
=
VS1 -2V
V
S1 -2V
V
OUT=VS1=-4V
=
OUT=3VS1 -6V
V
Potential relationship of amplified voltage
Voltage regulating circuit
Amplified voltage generated at VOUT outputs liquid crystal drive voltage V5 through the voltage regulation circuit.V5
1
voltage can be obtained from the expression below by adjusting the resistors Ra and Rb within the range of
V5<VOUT.calculated by the following formula:
V0
VDD
V5 = (1 + Rb) • VREG
Ra
..............................
1
VREG
R1
Where, VREG is the constant power supply within IC.
•
+
=
VREG is maintained constantly at VREG • 2.0V.
Ra
V5
Voltage regulation of V5 output is done by connecting to
a variable register between VR, VDD and V5. It is
recommended to combine fixed registers R1 and R3 with
variable resistor R2 for fine adjustment of V5 voltage.
VR
R2
-
R3
Rb
[Sample setting on R1, R2 and R3]
• R1 + R2 + R3 = 1.2 M ohm (decided from the current
value I05 passed between VDD – V5. Where, I05≤5 µA
is supposed).
R1 = 400KΩ
R2 = 200KΩ
R3 = 600KΩ
• Variable voltage range provided by R2 is from –4V to
–6V (to be decided considering charecteristics of the
liquid crystal).
The voltage regulation circuit outputs VREG with the
temperature gradient of approximately –0.04%/°C.
Since VR terminal has high input impedance, anti-noise
measures must be considered including use of shortened
wiring distance and shield wire.
• Since VREG = 2.0V, if the electronic volume register is
set at (0, 0, 0, 0, 0), followings are derived from above
1
conditions and expression
:
4–16
EPSON
SED1220
● Voltage Regulation Circuit Using Electronic Volume
Function
The electronic volume function allows to control the
liquid crystal drive voltage V5 with the commands and
thus to adjust density of the liquid crystal display.
Liquid crystal drive voltage V5 can have one of 32
voltage values if 5-bit data is set to the electronic volume
register.
When using the electronic volume function, you need to
turn the voltage regulation circuit on using the supply
control command.
[Sample constants setting when electronic volume function is used]
V
0
...............................
V5 = (1 + Rb ) • VEV
Ra
2
V
DD
n
α
Where VEV = VREG – α
α = VREG / 150
Ra
V
REG
α
V
EV
0
+
-
V
5
V
R
Rb
No. Electronic volume register
a
V5
0
1
2
3
•
(0, 0, 0, 0, 0)
(0, 0, 0, 0, 1)
(0, 0, 0, 1, 0)
(0, 0, 0, 1, 1)
•
0
1α
2α
3α
•
Large
•
•
•
•
•
30
31
•
•
•
•
(1, 1, 1, 1, 0)
(1, 1, 1, 1, 1)
(n-1)α
nα
Small
When the electronic volume function is not used, select (0, 0, 0, 0, 0) for the electronic volume register.
EPSON
4–17
SED1220
Liquid crystal voltage generating circuit
V5 potential is resistive divided within IC to produce V1,
V2, V3 and V4 potentials required for driving the liquid
crystal. V1, V2, V3 and V4 potentials are then subject to
impedance conversion and provided to the liquid crystal
drive circuit.
The liquid crystal drive voltage is fixed to 1/5 (1/4) bias.
The liquid crystal power terminals V1 – V5 must be
externally connected with the voltage regulating capacitor
C2.
When a built-in supply is used
When voltage is doubled
When voltage is tripled
V
SS
VSS
C1
CAP1+
CAP1–
CAP1+
CAP1–
C1
C1
R3
CAP2+
CAP2–
CAP2–
V
C1
C1
OUT
VOUT
R3
R1
V
V
5
V5
R2
R2
R
VR
R1
V
DD, V0
V
DD, V0
SED1220D✽✽
SED1220D✽✽
C2
C2
C2
C2
C2
C2
V
V
V
V
V
V
1
V
V
V
V
V
V
1
C2
C2
C2
C2
C2
2
2
3
3
4
4
5
5
S1
S1
C1
Reference setting values: C1: 0.1 - 4.7 µF We recommend the user to set the optimum values to capacitors C1
C2: 0.1 µF
and C2 according to the panel size watching the liquid crystal display
and drive waveforms.
4–18
EPSON
SED1220
Example 2: When using the built-in power source
(VC, VF, P) = (1, 1, 0)
Example 3: When using the built-in power source
(VC, VF, P) = (0, 1, 0)
SED1220D
SED1220D
**
**
V
SS
V
SS
V
SS
CAP1+
CAP1-
CAP2+
CAP2-
CAP1+
CAP1-
CAP2+
CAP2-
V
OUT
V
OUT
External
power
source
R
3
1
V
V
5
V
V
5
External
power
R2
R
R
source
R
V
DD, V0
V
DD, V0
C2
C2
C2
C2
C2
C2
C2
C2
C2
C2
C2
C2
V
V
V
V
V
V
1
V
V
V
V
V
V
1
2
2
3
3
4
5
4
5
S1
S1
Reference setting values: C1: 0.47 - 4.7 µF We suggest you to determine the most appropriate capacitance values,
C2: 0.1 - 4.7 µF fitting to the panel size, for respective capacitors C1 and C2 in consideration
of the liquid crystal display and drive waveforms.
When a built-in supply is used
VSS
CAP1+
CAP1–
VOUT
V5
VR
VDD, VDD
SED1220D✽✽
V1
V2
V3
V4
V5
External
power
supply
EPSON
4–19
SED1220
Low Power Consumption Mode
Reset Circuit
SED1220 is provided with standby mode and sleep mode
for saving power consumption during standby period.
Upon activation of the RES input, this LSI will be
initialized.
● Standby Mode
● Initial State
Switching between on and off of the standby mode is
done using the power save command.
In the standby mode, only static icon is displayed.
1. Liquid crystal display output
1. Display on/off control
C = 0
B = 0
D = 0
: Cursor off
: Blink off
: Display off
COM1 ~ COM24, COMS1, COMS2 : VDD level
2. Power save
O = 0
SEG1 ~ SEG60, SEGS1, 2, 4, 5
: VDD level
: Oscillation off
: Power save off
SEGSA, B, C, D, E, F, G, H, I, J, COMSA: Can be
PS = 0
turned on by static drives.
3. Supply control
VC = 0
VF = 0
P = 0
4. System setting
Use the static icon RAM for controlling the static
icon display done with SEGSA, B, C, D, E, COMSA.
2. DD RAM, CG RAM and symbol register
Written information is saved as it is irrespective of on
or off of the stand-by mode.
: Voltage regulation circuit off
: Voltage follower off
: Amplifying circuit off
N2, N1 = 0 : 2 lines
3. Operation mode is retained the same as it was prior
to execution of the standby mode.
S = 0
CG = 0
5. Electronic volume control
: Left-hand shift
: “CGRAM” blank
The internal circuit for the dynamic display output is
stopped.
4. Oscillating circuit
Address : 28H
Data
: (0, 0, 0, 0, 0)
The oscillation circuit for the static display must be
6. Static icon
remained on.
Address : 20H
Data : (0, 0, 0, 0, 0)
Address : 21H
● Sleep Mode
To enter the sleep mode, turning off the power circuit and
oscillation circuit using the commands, and then execute
power save command. This mode helps to save power
consumption by reducing current to almost resting cur-
rent level.
Data
Address : 22H
Data
Address : 23H
: (0, 0, 0, 0, 0)
: (0, 0, 0, 0, 0)
Data
: (0, 0, 0, 0, 0)
1. Liquid crystal display output
As explained in the Section “MPU interface”, the RES
terminal connects to the reset terminal of the MPU and
initialization is being effected together with the MPU.
However, when the bus, port, etc. of the MPU maintains
high-impedance for a certain duration of time after
resetting, make the resetting input to the SED1220 after
the inputs to the SED1220 have become definite.
As the resetting signal, like explained in the Section “DC
characteristics”, active level pulses of minimum 10us or
more should be used. Normal operation status can be
obtained after 1us from the edge of the RES signal.
By making the RES terminal active, respective registers
can be cleared and the aforesaid setting state can be
obtained.
COM1 ~ COM24, COMS1, COMS2 : VDD level
SEG1 ~ SEG60, SEGS1, 2, 4, 5
: VDD level
SEGSA, B, C, D, E, F, G, H, I, J, COMSA: Clear all
the data of the static icon registers to “0”.
2. DD RAM, CG RAM and symbol register
Written information is saved at it is irrespective of on
or off the sleep mode.
3. Operation mode mode is retained the same at it was
prior to execution of the sleep mode.
All internal circuits are stopped.
4. Power circuit and oscillation circuit
Turn off the built-in supply circuit and oscillation
circuit using the power save command and supply
control command.
If initialization is not effected by the RES terminal when
the supply voltage is applied, it may go into a state where
cancellation is unworkable.
In case the built-in liquid crystal power circuit will not be
used, it becomes necessary that the RES input be active
when the external liquid crystal power is being applied.
4–20
EPSON
SED1220
COMMAND
Table 4 lists the commands. SED1220 identifies the data
C
0
0
1
1
B
Cursor display
bus signal using different combinations of A0 and WR
(E). High speed command interpretation and execution
are possible since only the internal timing is used.
0 Non-display
1 Non-display
0 Underbar cursor
1 Alternate display of display
characters in black and white.
The cursor position indicates the
position of address
•
Command Overview
Command type
Command name
A0 WR
Display control
instruction
Power control
Cusor Home
Display ON/OFF Control
Power Save
Power Control
System set
0
0
0
0
0
0
0
0
0
0
0
0
(C, B)
(0, 0)
(1, 0)
(1, 1)
System set
Address control Address Set
instruction
Data input
instruction
Data Write
1
0
f Blink
The cursor position indicates the position of address
counter.
Instruction execution duration of dependents on the
internal process time of SED1220, therefore it is neces-
sary to provide a duration larger than the system cycle
time (tCYC) between execution of two successive in-
struction.
Therefore, whenever moving the cursor, change
the address counter value using the RAM address
set command or the auto increment done by writing
the RAM data.
•
Description of Commands
(1) Cursor Home
This command presets the address counter to 30H
ISelective flashing symbol display is possible by
selecting (C, B) = (1, 0) and thus locating the
address counter to the position of the symbol register
through selecting (since the symbol is corresponding
to the character at each 5 dots).
and moves the cursor, when it is present, to the first
digit of the first line.
A0 WR D7 D6 D5 D4 D3 D2 D1 D0
0
0
0
0
0
1
*
*
*
*
(3) Power Save
This command is used to controlling the oscillation
: Don't Care
circuit and setting or resetting the sleep mode.
(2) Display ON/OFF Control
This command performs on or off of display and
cursor setting.
A0 WR D7 D6 D5 D4 D3 D2 D1 D0
Note: Symbols driven by COMSA and SEGSA – E
must be controlled through the static icon
RAM.
0
0
0
1
0
0
O
PS
: Don't Care
= 0 : Power save off (reset)
: Power save on (set)
*
*
PS
1
A0 WR D7 D6 D5 D4 D3 D2 D1 D0
0
0
0
0
1
1
C
B
D
*
O
= 0 : Oscillating circuit off (stop of
oscillation)
D
= 0 : Display off
: Display on
1
: Oscillating circuit on (oscilla
tion)
1
B
= 0 : Cursor blink off
: Cursor blink on
(4) Supply Control
1
This command is used for controlling operation of
the built-in power circuit.
Blink displays characters in black and white,
alternately. The alternating display will be repeated
with approx. 1 second interval.
A0 WR D7 D6 D5 D4 D3 D2 D1 D0
0
0
0
1
0
1
0
VC
P
VF
= 0 : Amplifying circuit off
: Amplifying circuit on
C
= 0 : Display of cursor
: Does not display
P
1
1
Following table shows relationship between B and
C registers and the cursor.
Note: The oscillation circuit must be turned on
for the amplitying circuit to be active.
EPSON
4–21
SED1220
VF
= 0 : Voltage follower off
: Voltage follower on
(6) RAM Address Set
1
This command sets addresses to write data into the
DD RAM, CG RAM and symbol register in the
address counter.
VC
= 0 : Voltage regulation circuit off
: Voltage regulation circuit on
1
When the cursor is displayed, the cursor is dis-
played at the display position corresponding to the
DD RAM address set by this command.
(5) System Set
This command is used for selecting display line,
common shift direction and use/non-use of CR
RAM.
When power on or resetting is done, execute this
command first.
A0 WR D7 D6 D5 D4 D3 D2 D1 D0
0
0
1
ADDRESS
1
2
The settable address length is ADDRESS = 00H to
7FH.
Before writing data into the RAM, set the data
write address by this command. Next, when data is
written in succession, the address is automatically
incremented.
A0 WR D7 D6 D5 D4 D3 D2 D1 D0
0
0
0
1
1
0
S
CG
N1 N2
: Don't Care
N2, N1 = 0, 0 : 2lines
N2, N1 = 0, 1 : 3lines
S
= 0 : COM left shift
= 1 : COM right shift
CG
= 0 : Use CG RAM
1
: Does not use RAM
RAM Map
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
0 0 H
1 0 H
2 0 H
3 0 H
4 0 H
5 0 H
6 0 H
7 0 H
C G R A M (0 0 H)
C G R A M (0 2 H)
C G R A M (0 1 H)
C G R A M (0 3 H)
EV Test
For signals
SI
DDRAM line 1
DDRAM line 2
DDRAM line 3
Symbol register
Symbol register
–
Unused
"
"
"
"
:Unused
:Output from SEGS1 to SEGS2, SEGS4, SEGS5
For symbol register :Output from COMS1 to COMS2.
For signals
SI
EV
:Static icon register
:Electronic volume register
Test :Test register (Do not use)
4–22
EPSON
SED1220
(7) Data Write
A0 WR D7 D6 D5 D4 D3 D2 D1 D0
RAM Address Set
1
0
DATA
Data Writing
1
2
This command writes data the DD RAM, CG RAM
or symbol register.
This command automatically increases the address
counter by +1, thus enabling continuous writing of
data.
Note: When executing
instructions in
NO
One Line Completed?
YES
succession, reserve a
time exceeding tCYC
and execute the next
instruction.
<Example of Data Writing>
Following figures illustrates an example of con-
tinuous writing of one line data to DD RAM.
EPSON
4–23
SED1220
Table 4 SED1220 Series Command List
Code
Command
Function
A0 WRD7 D6 D5 D4 D3 D2 D1 D0
(1) Cursor Home
0
0
0
0
0
0
0
0
0
1
1
1
*
*
*
*
*
Moves the cursor to the home position.
(2) Display ON/OFF
Control
C
B
D
Sets cursor ON/OFF (C), cursor blink ON//OFF (B),
and display ON/OFF (D).
C = 1 (cursor ON) 0 (cursor OFF), B = 1 (blink ON)
0 (blink OFF), D = 1 (display ON)
D = 0 (display OFF)
(3) Power Save
0
0
0
0
0
0
1
1
0
0
0
1
*
*
0 PS Sets power save ON/OFF (PS) and oscillating circuit
ON/OFF (0).
PS = 1 (power save ON) 0 (power save OFF),
0 = 1 (oscillating circuit ON) 0 (oscillating circuit
OFF)
(4) Power Control
0 VC VF P Sets voltage regulating circuit ON/OFF and boosting
circuit ON/OFF (P).
VC = 1 (voltage regulating circuit ON) 0 (voltage
regulating circuit OFF) VF = 1 (voltage follower
ON) 0 (voltage follower OFF), P = 1 (boosting
circuit ON) 0 (boosting circuit OFF)
(5) System Set
0
0
0
1
1
1
0 N2 N1 S CG Sets the use or non-use of CG RAM and shifting
direction of display line (N1, N2) and COM
CG = 1 (use of CG RAM), 0 = (Does not use
CG RAM),
M2, N1 = 0, 0 (2 lines) 0, 1 (3 lines).
S = 0 (left shift), 1 (right shift).
(6) RAM Address Set
(7) RAM Write
0
1
0
0
ADDRESS
DATA
Sets the DD RAM, CG RAM or symbol register
address.
Writes data into the DD RAM, CG RAM or symbol
register address.
(8) NOP
0
0
0
0
0
0
0
0
0
0
0
0
0
*
0
*
0
*
0
*
Non-operation command
(9) Test Mode
Command for IC chip test. Don’t use this command.
system command selects on which of CG ROM and CG
RAM they are to be used.
SED1220 CG ROM is mask ROM and compatible with
customized ROM. Contact us for its use in your system.
Product name of modified CG ROM is defined as below:
CHARACTER GENERATOR
Character Generator ROM (CG ROM)
Character Generator ROM (CG ROM)
SED1220 cntains the character generator ROM (CG
ROM) consisted of up to 256 types of characters.
Character size is 5 × 8 dots.
Tables 5 though 7 show the SED1220** character code.
Concerning the 4 characters from 00H through 03H, the
(Example) S E D 1 2 2 0 D 0 B
↑
Digit for CG ROM
pattern change
4–24
EPSON
SED1220
SED1220DA
*
Lower 4 Bit of Code
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
EPSON
4–25
SED1220
SED1220DB
*
Lower 4 Bit of Code
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
4–26
EPSON
SED1220
SED1220DG
*
Lower 4 Bit of Code
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
EPSON
4–27
SED1220
Character Generator RAM (CG ROM)
CGRAM contained in SED1220 enables user programming of character patterns for display signals with higher degrees
of freedom.
When using CGRAM, select it using the system command.
Capacity of CGRAM is 160 bits and accepts registration of any 4 5 ×8 dots patterns.
Following shows relationship between the CGRAM characters, CGRAM addresses and character code.
CGRAM data (character pattern)
Character display
Signal display
SEGS
1 2
Character code
RAM address
00H~07H
D7
D0 SEG
4 5
00H
02H
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
0
1
1
0
0
0
1
0
0
0
0
0
0
1
0
0
1
0
0
1
0
0
1
0
0
0
1
1
1
1
0
0
1
0
0
1
0
0
1
0
1
1
1
1
1
1
0
0
1
0
0
1
0
0
1
0
0
0
1
1
1
1
0
0
1
0
0
1
1
1
0
0
0
0
0
0
0
1
0
0
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
10H~17H
01H
03H
08H~0FH
18H~1FH
Unused
Character data
1: Display
0: Non-display
It is possible to set a 5 × 8 character size in this system. In this case, use the *7H/*FH RAM. Note that the *7H/*FH data
is inverted when a under-bar cursor is used.
4–28
EPSON
SED1220
Symbol Register
SED1220 contains the symbol register which enable individual symbol setting for displaying on the screen.
Capacity of the symbol register is 120 bits and is capable of displaying up to 120 symbols.
Following shows relationship between the symbol register display patterns, RAM addresses and written data.
13
1
12
13
1 2 3 4 5
56 ·
·
·
· 60
COMS1
COMS2
61 ·
·
· 65
116 ·
·120
60
SEG1 2
SEG1 2 3 4 5
RAM address
SEG56
SEGS4 5
Symbol Bits
D7
D0
5
0
1
1
6
2
7
3
8
4
9
*
*
*
*
*
*
10
60H~6BH
70H~7BH
B
0
1
56 57 58 59 60
61 62 63 64 65
66 67 68 69 70
*
*
*
*
*
*
*
*
*
B
116 117 118 119 120
*
*
*
Note: When the symbol is 1.5 times or more than the character, it is recommended to drive it using both COMS1
and COMS2.
EPSON
4–29
SED1220
up to 5 icons (SED1220/1221/1222) or 10 icons
(SED122A).
Following shows relationship between the static icons
functions, static icon RAM addresses and written data.
Static Icon Ram
SED1220 contains the static icon RAM for displaying
the static icons in addition to the dynamic icons.
Capacity of static icon RAM is 10 bits (SED1220/1221/
1222) or 20 bit (SED122A) and is capable of displaying
< SEGSA, B, C, D, E >
Static icon data
Display
Function
RAM address
20H
D7
*
D0 S E G S A B C D E
1
0
1
0
0
1
0
1
0
Display
On/Off
*
*
*
*
Blink
On/Off
21H
1
*
f BLINK
< SEGSF, G, H, I, J >
Static icon data
Display
Function
RAM address
D7
*
D0 S E G S F G H I J
1
0
1
0
0
1
0
1
0
Display
On/Off
22H
23H
*
*
*
*
Blink
On/Off
1
*
f BLINK
*: Blank
1: Display or blink on
0: Display or blink off
fBLINK: 1–2 Hz
Electronic Volume RAM (register)
SED1220 contains the electronic volume function for
controlling the liquid crystal drive voltage V5 and density
of liquid crystal display. The electronic volume function
enables to select one of 32 voltage status of the liquid
crystal drive voltage V5 by writting 5-bit data to the
electronic volume RAM.
Following shows relationship between RAM addresses
set by the electronic volume and written data.
Electronic volume data
Condi-
tion
Function
RAM address
28H
V
EV
D7
*
D0
0
Electronic
volume data
0
0
0
0
0
V
REG–0
*
*
V
REG–α
0
0
0
0
0
0
0
0
1
0
1
2
*
*
*
*
*
*
V
REG–2α
V
V
V
REG–29α
REG–30α
REG–31α
1
1
1
1
1
1
1
1
1
0
1
1
1
0
1
29
30
31
*
*
*
*
*
*
*
*
*
*
*
*
29H
For testing
*
*
*
: Blank
Note : Do not use the address “29H”. It is for testing
α = VREG/150
4–30
EPSON
SED1220
ABSOLUTE MAXIMUM RATINGS
Item
Power supply voltage (1)
Power supply voltage (2)
Power supply voltage (3)
Input voltage
Symbol
VSS
Standard value
–6.0~+0.3
Unit
V
V5, Vout
V1, V2, V3, V4
VIN
–7.0~+0.3
V
V5~+0.3
V
VSS–0.3~+0.3
VSS–0.3~+0.3
–30~+85
V
Output voltage
VO
V
Operating temperature
Topr
°C
TCP
–55~+100
Storage temperature
Tstr
°C
Bare chip
–65~+125
(VCC) VDD
(GND) VSS
V
V
DD
5
Notes: 1. All the voltage values are based on VDD = 0 V.
2. For voltages of V1, V2, V3 and V4, keep the condition of VDD ≥ V1 ≥ V2 ≥ V3 ≥ V4 ≥ V5 and VDD ≥ VSS
≥ V5 ≥ VOUT at all times.
3. If the LSI is used exceeding the absolute maximum ratings, it may lead to permanent destruction.
In ordinary operation, it is desirable to use the LSI in the condition of electrical characteristics. If the
LSI is used out of this condition, it may cause a malfunction of the LSI and have a bad effect on the
reliability of the LSI.
EPSON
4–31
SED1220
DC CHARACTERISTICS
VDD = 0 V, VSS = –3.6 V to –2.4 V, Ta = –30 to 85°C unless otherwise specified.
Item
Operatable
Data retain
Symbol
VSS
Condition
min
–3.6
–3.6
typ
–3.0
max
–2.4
–2.0
Unit Applicable pin
Power
supply
voltage (1) voltage
V
VSS
*1
Power
supply
Operatable
Operatable
V5
V1, V2
V3, V4
VIHC
VILC
ILI
–7.0
0.6×V5
V5
0.2×VSS
VSS
–4.0
VDD
0.4×V5
VDD
0.8×VSS
1.0
40
V
V
V
V
V
V5 *2
V1, V2
V3, V4
*3
voltage (2) Operatable
High-level input voltage
Low-level input voltage
Input leakage current
LC driver ON resistance
*3
VIN = VDD or VSS
–1.0
µA *3
KΩ COM,SEG
*4
RON Ta=25°C
∆V=0.1V
V5=–7.0V
20
Static current consumption
IDDQ
0.1
5.0
80
20
µA VDD
µA VDD *5
µA VDD
Dynamic current
consumption
IDD Display state V5 = –6 V without load
Standby state Oscillation ON, Power
OFF, VSS = –3V
without load
Sleep state
Oscillation OFF, Power
OFF, VSS = –3.0V
5
µA VDD
µA VDD *6
pF *3
Access state fcyc=200KHz,
VSS = –3.0V
CIN
500
8.0
130
Input pin capacity
Ta=25°C f=1MHz
5.0
Frame frequency
External clock frequency
fFR
fck
fck
Ta=25°C VSS=–3.0V
Display of 2 lines
Display of 3 lines
70
100
23.4
33.8
Hz *10
KHz *10 *11
KHz *10 *11
Reset time
Reset pulse width
Reset start time
tR
1.0
10
50
µs *7
µs *8
ns *8
tRW
tRES
Dynamic system
Input voltage
Amplified voltage
output voltage
VS1
–2.3
–6.9
–2.1
–6.3
–1.9
–5.7
V
V
*9
VOUT
VOUT
When voltage is tripled
Voltage follower
operating voltage
Reference voltage
V5
–7.0
–4.0
V
V
VREG
Ta = 25°C
–2.06
–2.0
–1.94
*1: A wide operating voltage range is guaranteed but an
abrupt voltage variation in the access status of the
MPU is not guaranteed.
*4: This is a resistance value when a voltage of 0.1 V is
applied between output pin SEGn, SEGSn, COMn or
COMSn, and each power pin (V1, V2, V3 or V4). It
is specified in the range of operating voltage (2).
RON = 0.1 V / ∆I
*2: When the voltage is Tripled, care must be paid to
supply the voltage VSS so that operating voltage of
VOUT and V5 may not be exceeded.
(∆I: Current flowing when 0.1 V is
applied between the power and output)
*3: D0 ~ D5, D6 (SCL), D7 (SI), A0, RES, CS WR (E),
P/S, IF
4–32
EPSON
SED1220
*10:The fOSC frequency of the oscillator circuit for
internal circuit drive may differ from the fBST boost-
ing clock on some models. The following provides
the relationship between the fOSC frequency, fBST
boosting clock, and fFR frame frequency.
*5: Character “
” display. This is applicable to the
case where no access is made from the MPU and the
built-in power circuit and oscillating circuit are in
operation.
fOSC = (No. of digits) × (1/Duty) × fFR
fBST = (1/2) × (1/No. of digits) × fOSC
*6: Current consumption when data is always written by
fcyc.
The current consumption in the access state is almost
proportional to the access frequency (fcyc).
When no access is made, only IDD (I) occurs.
*11:When performing the operations using an external
clock, not taking advantage of the built-in oscillation
circuit, input the waveforms indicated below.
Meanwhile, while using an external clock but when
clock inputs are not being made, fix it to “H”.
(Normal High)
*7: tR (reset time) indicates the internal circuit reset
completion time from the edge of the RES signal.
Accordingly, the SED1220 usually enters the oper-
ating state after tR.
<Incase the external clock = fosc>
• Duty = (th/tosc) × 100 = 20 ~ 30%
• fosc = 1/tosc
*8: Specifies the minimum pulse width of the RES
signal. It is reset when a signal having the pulse
width greater than tRW is entered.
V
DD
t
osc
th
Power Supply
–2.4 V
V
SS
<Incase the external clock = 4 × fosc>
• Duty = (th/tosc) × 100 = 50%
• fosc = 1/tosc
t
RES
V
V
DD
SS
RES
t
RW
tR
All signal timings are based on 20% and 80% of VSS signals.
t
h
t
osc
*9: When operating the boosting circuit, the power
supply VSS must be used within the input voltage
range.
EPSON
4–33
SED1220
TIMING CHARACTERISTICS
(1) MPU Bus Write Timing (80 series)
A0
t
AC8
t
AH8
CS
t
cyc8
t
AW8
t
CCL
WR
t
CCH
t
DS8
t
DH8
D0 to D7
[Ta = –30 to 85°C, VSS = –3.6 V to –2.4 V]
Measuring
condition
Item
Address hold time
Signal Symbol
Min.
Max.
Unit
A0, CS
tAH8
tAW8
tAC8
tCYC8
tCCL
tCCH
tDS8
tDH8
Every timing is specified
on the basis of 20% and
80% of VSS.
30
60
–
–
–
–
–
–
–
–
ns
ns
ns
ns
ns
ns
ns
ns
Address setup time
CS setup time
0
System cycle time
WR
650
150
450
100
50
Write “L” pulse width (WR)
Write “H” pulse width (WR)
Data setup time
D0 ~ D7
Data hold time
[Ta = –30 to 85°C, VSS = –3.3 V to –2.7 V]
Measuring
condition
Item
Signal Symbol
Min.
Max.
Unit
Address hold time
Address setup time
CS setup time
A0, CS
tAH8
tAW8
tAC8
tCYC8
tCCL
tCCH
tDS8
tDH8
Every timing is specified
on the basis of 20% and
80% of VSS.
10
60
–
–
–
–
–
–
–
–
ns
ns
ns
ns
ns
ns
ns
ns
0
System cycle time
Write “L” pulse width (WR)
Write “H” pulse width (WR)
Data setup time
WR
500
100
350
100
20
D0 ~ D7
Data hold time
*1: For the rise and fall of an input signal (tr and tf), set a value not exceeding 25ns (excluding RES input).
t
r
tf
V
V
SS × 0.8 [V]
SS × 0.2 [V]
*2: tCCL is specified based on an overlap period of CS and WR “L” levels.
4–34
EPSON
SED1220
(2) MPU Bus Write Timing (68 series)
A0
t
AH6
t
AC6
CS
t
EWH
t
CYC6
t
EWL
E
t
DS6
t
DH6
t
AW6
D0 to D7
[Ta = –30 to 85°C, VSS = –3.6 V to –2.4 V]
Measuring
condition
Item
Signal Symbol
Min.
Max.
Unit
Address setup time
Address hold time
CS setup time
A0, CS
tAW6
tAH6
Every timing is specified
on the basis of 20% and
80% of VSS.
60
30
–
–
–
–
–
–
–
–
ns
ns
ns
ns
ns
ns
ns
ns
tAC6
0
System cycle time
Enable “L” pulse width (WR)
Enable “H” pulse width (WR)
Data setup time
WR
tCYC6
tEWL
tEWH
tDS6
650
150
450
100
50
D0 ~ D7
Data hold time
tDH6
[Ta = –30 to 85°C, VSS = –3.3 V to –2.7 V]
Measuring
condition
Item
Signal Symbol
Min.
Max.
Unit
Address setup time
Address hold time
CS setup time
A0, CS
tAW6
tAH6
Every timing is specified
on the basis of 20% and
80% of VSS.
60
10
–
–
–
–
–
–
–
–
ns
ns
ns
ns
ns
ns
ns
ns
tAC6
0
System cycle time
Enable “L” pulse width (WR)
Enable “H” pulse width (WR)
Data setup time
WR
tCYC6
tEWL
tEWH
tDS6
500
100
350
100
20
D0 ~ D7
Data hold time
tDH6
*1: For the rise and fall of an input signal (tr and tf), set a value not exceeding 25ns (excluding RES input).
t
r
tf
V
V
SS × 0.8 [V]
SS × 0.2 [V]
*2: tEWH is specified based on an overlap period of CS “L” and E “H” levels.
EPSON
4–35
SED1220
(3) Serial Interface
t
CSS
tCSH
CS
t
SAS
tSAH
A0
t
SCYC
t
SLW
SCL
t
SHW
t
SDS
tSDH
SI
[Ta = –30 to 85°C, VSS = –3.6 V to –2.4 V]
Measuring
condition
Item
Signal Symbol
Min.
Max.
Unit
System clock cycle
SCL “H” pulse width
SCL “L” pulse width
Address setup time
Address hold time
Data setup time
SCL
tSCYC
tSHW
tSLW
tSAS
tSAH
tSDS
tSDH
tCSS
tCSH
Every timing is specified
on the basis of 20% and
80% of VSS.
1000
300
300
50
ns
ns
ns
ns
ns
ns
ns
ns
ns
A0
SI
300
50
Data hold time
50
CS-SCL time
CS
150
700
*1: For the rise and fall of an input signal (tr and tf), set a value not exceeding 25ns (excluding RES input).
t
r
tf
V
V
SS × 0.8 [V]
SS × 0.2 [V]
4–36
EPSON
SED1220
MPU INTERFACE (REFERENCE EXAMPLES)
The SED1220 Series can be connected to the 80 series MPU and 68 series MPU. When an serial interface is used, the
SED1220 Series can be operated by less signal lines.
80 Series MPU
V
CC
V
DD
A0
A0
P/S
A1 to A7
IORQ
CS
Decoder
MPU
SED1220
D0 to D7
WR
D0 to D7
WR
IF
RES
RES
V
SS
GND
RESET
RESET
RESET
68 Series MPU
V
CC
V
DD
A0
A0
P/S
A1 to A7
VMA
CS
Decoder
MPU
SED1220
D0 to D7
E
D0 to D7
E
IF
RES
RES
V
SS
GND
Serial Interface
VCC
V
DD
Port4
Port3
A0
P/S
CS
MPU
SED1220
Port1
Port2
SI
SCL
IF
RES
RES
V
SS
GND
VSS
or GND
EPSON
4–37
SED1220
INTERFACE TO LCD CELLS (REFERENCE)
12 columns by 3 lines, 5 × 8-dot matrix segments and symbols
. . . . . . . . . . . . . . . . . 12
LCD panel
1
SED 1220
static icon
COMSA
SEGSA
SEGSE
symbol
COMS1
COMS2
signal
signal
COM1
2
3
4
5
6
7
8
COM9
10
11
12
13
14
15
16
COM17
18
19
20
21
22
23
24
character
SEGS1
SEGS2
SEG1
2
3
4
5
SEG60
SEGS4
SEGS5
4–38
EPSON
SED1220
12 columns by 2 lines, 5 × 8-dot matrix segments and symbols
. . . . . . . . . . . . . . .
LCD panel
1
12
SED 1221
static icon
COMSA
SEGSA
SEGSE
symbol
COMS1
COMS2
signal
signal
COM1
2
3
4
5
6
7
8
COM9
10
11
12
13
14
15
16
character
SEGS1
SEGS2
SEG1
2
3
4
5
SEG60
SEGS4
SEGS5
EPSON
4–39
SED1220
12 columns by 2 lines, 5 × 8-dot matrix segments and symbols
• • • • • • • • • • • • • •
LCD panel
1
12
SED 1222
static icon
COMSA
SEGSA
SEGSE
symbol
COMS1
COMS2
COM1
2
3
4
5
6
7
8
COM9
10
11
12
13
14
15
16
character
SEG1
2
3
4
5
SEG60
4–40
EPSON
SED1220
12 columns by 2 lines, 5 × 8-dot matrix segments and symbols
• • • • • • • • • • • • • •
LCD Panel
Static icon
1
12
SED 122A
COMSA
SEGSA
SEGSJ
Symbol
COMS1
COMS2
Signal
Signal
COM1
2
3
4
5
6
7
8
COM9
10
11
12
13
14
15
16
Character
SEGS1
SEGS2
SEG1
2
3
4
5
SEG60
SEGS4
SEGS5
EPSON
4–41
SED1220
LIQUID CRYSTAL DRIVE WAVEFORMS (B WAVEFORMS)
V
V
V
V
V
V
DD
COM 1
1
COM 1
COM 2
COM 3
COM 4
COM 5
COM 6
COM 7
COM 8
2
3
4
5
V
V
V
V
V
V
DD
1
2
COM 2
3
COM 9
4
COM 10
COM 11
COM 12
COM 13
COM 14
COM 15
COM 16
5
V
V
V
V
V
V
DD
1
COM 3
2
3
4
5
V
V
V
V
V
V
DD
SEG 1
SEG 2
SEG 3
SEG 4
SEG 5
1
2
SEG 1
3
4
5
V
V
V
V
V
V
DD
1
2
SEG 2
3
4
5
V
V
V
V
V
V
5
4
3
COMO -SEG 1
2
1
DD
-V1
-V2
-V3
-V4
-V5
V
V
V
V
V
V
5
4
COMO -SEG 2
3
2
1
DD
-V1
-V2
-V3
-V4
-V5
4–42
EPSON
SED1220
Instruction Setup Example
(Reference Only)
(1) Initial setup
(2) Display mode
V
DD-VSS power ON
End of initialization
Power regulation
Input of RAM address setup command
Input of RAM (data) write command
Display of written data
Input of reset signal
Command status
• Static display control: Off
• Display on/off control: Off
• Power save: Off
• Power control: Off
• System setup: Off
• Electronic volume (0, 0, 0, 0, 0)
• Static icon (0, 0, 0, 0, 0)
• Others are undefined.
Waiting for 10 sec or more
Command input:
(Asterisk indicates any command sequence.)
(1) NOP command
(2) System setup command
(
) Electronic volume register setup
• Address: 28H
• Data: (
,
,
,
,
)
(
) Power save command
• PS: Off (Power save)
• O: On (Oscillation)
(5) Power control commands
• P, VF, VC: On
1)
(6) RAM address setup
(7) Data writing
1)
2)
Waiting for 20msec or more
Command input
(8) Display on/off control command
• D: On (Display)
3)
Data input
(9) Static icon control
3)
• Address: 20H
• Data: (
• Address: 21H
• Data: (
,
,
,
,
,
,
)
)
,
,
End of initialization
Notes 1) Commands (6) and (7) initialize the RAM. The display contents must first be set. The non-display area
must satisfy the following conditions (for RAM clear).
• DDRAM: Write the 20H data (character code).
• CGRAM: Write the 00H data (null data).
• Symbol register: Write the 00H data (null data).
As the RAM data is unstable during reset signal input (after power-on), null data must be written. If not,
unexpected display may result.
2) Since it is specified based on rise characteristics of the booster, power control and voltage follower
circuits, time to be set differs depending on external capacity. Be sure to set it after the external capacity
is confirmed.
3) A display of the dynamic drive series is turned on when the on command is input and the static icon is
turned on using the static icon control command.
To turn both on at the same time when the display is turned on, execute display on/off command and
static icon control within 1 frame period.
EPSON
4–43
SED1220
(3-1) Selecting the Standby mode
(3-2) Releasing the Standby mode
End of initialization
Standby mode
Normal operation
(Power Save is released and
oscillator circuit is turned ON.)
(1) Input of power save command
• PS: Off (Power save)
• O: On (Oscillation)
(2) Input of power control command
• P, VF, VC: On
(1) Input of display on/off control command
• D: Off (Display)
(2) Input of power save command
• PS: On (Power save)
2)
Waiting for 20msec or more
• O: On (Oscillation)
(3) Input of power control command
• P, VF, VC: Off
(3) Input of display on/off control command
• D: Off (Display)
Standby status
Return to normal operation (initial status).
Only static icon displayed
(4-1) Selecting the Sleep mode
(4-2) Releasing the Sleep mode
End of initialization
Sleep mode
Normal operation
(Power Save is released and
oscillator circuit is turned ON.)
(1) Input of power save command
• PS: Off (Power save)
• O: On (Oscillation)
(2) Input of power control command
• P, VF, VC: On
(1) Input of display on/off control command
• D: Off (Display)
(2) Static icon control
• Address: 20H
2)
Waiting for 20msec or more
• Data: (0, 0, 0, 0, 0)
• Address: 21H
• Data: (0, 0, 0, 0, 0)
3)
(3) Input of display on/off control command
• D: Off (Display)
(3) Input of power save command
• PS: On (Power save)
• O: Off (Oscillation)
(4) Input of power control command
• P, VF, VC: Off
3)
(4) Static icon control
• Address: 20H
• Data: (
• Address: 21H
• Data: (
,
,
,
,
,
,
)
)
,
,
Enter the Sleep mode.
Return to normal operation (initial status).
4–44
EPSON
SED1220
Instruction Setup Example of SED1220 series
(1) Initial setup
(2) display ON “EPSON”
(3) Display ON the Icon
(4) Standby Mode sequence
(5) Releasing the Standby Mode sequence
<Diagram of SED1220Txx and LCD Panel>
Static Icon
..
. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
..
..
SED1220DAB
CHIP:REVERSE
80series MPU
EPSON
4–45
SED1220
(1) Initial setup
(1.1) VDD–VSS Power ON
(1.2) Power regulation
(1.3) Input of RESET signal
(1.4) Command Status
• Display ON/OFF
• Power save
:OFF
:OFF
• Power control
• System reset
:OFF
:OFF
• Electronic Volume
:(0, 0, 0, 0, 0)
• Static display control :OFF
• Others are undefined.
(1.5) Waiting for 10µ sec or more
(1.6) Command Input: ((*) indicates any command sequence.)
(a) System Setup command: CGRAM→Not use, 3lines, COM Left shift
A0
0
WR
0
D7
0
D6
1
D5
1
D4
0
D3
0
D2
1
D1
0
D0
0
(*) Electronic volume resister setup: Data→(0, 0, 0, 0, 0, 0)
A0
0
WR
0
D7
1
D6
0
D5
1
D4
0
D3
1
D2
0
D1
0
D0
0
1
0
0
0
0
0
0
0
0
0
(*) Power save command: PS→0, 0→1
A0
0
WR
0
D7
0
D6
1
D5
0
D4
0
D3
0/1
D2
0/1
D1
1
D0
0
(d) Power Control command: P, VF, VC→1
A0
0
WR
0
D7
0
D6
1
D5
0
D4
1
D3
0
D2
1
D1
1
D0
1
(e) (f) RAM address setup, Data writing
• RAM address setup: Set address is 30H
A0
0
WR
0
D7
1
D6
0
D5
1
D4
1
D3
0
D2
0
D1
0
D0
0
4–46
EPSON
SED1220
• Data writing: All data→20H (for 1 Line)
A0
1
WR
0
D7
0
D6
0
D5
1
D4
0
D3
0
D2
0
D1
0
D0
0
1
0
0
0
1
0
0
0
0
0
1
0
0
0
1
0
0
0
0
0
1
0
0
0
1
0
0
0
0
0
1
0
0
0
1
0
0
0
0
0
1
0
0
0
1
0
0
0
0
0
1
0
0
0
1
0
0
0
0
0
1
0
0
0
1
0
0
0
0
0
1
0
0
0
1
0
0
0
0
0
1
0
0
0
1
0
0
0
0
0
1
0
0
0
1
0
0
0
0
0
1
0
0
0
1
0
0
0
0
0
1
0
0
0
1
0
0
0
0
0
• RAM address setup: Set address is 40H
A0
0
WR
0
D7
1
D6
1
D5
0
D4
0
D3
0
D2
0
D1
0
D0
0
• Data writing: All data→20H (for 2 line)
A0
1
WR
0
D7
0
D6
0
D5
1
D4
0
D3
0
D2
0
D1
0
D0
0
1
0
0
0
1
0
0
0
0
0
1
0
0
0
1
0
0
0
0
0
1
0
0
0
1
0
0
0
0
0
1
0
0
0
1
0
0
0
0
0
1
0
0
0
1
0
0
0
0
0
1
0
0
0
1
0
0
0
0
0
1
0
0
0
1
0
0
0
0
0
1
0
0
0
1
0
0
0
0
0
1
0
0
0
1
0
0
0
0
0
1
0
0
0
1
0
0
0
0
0
1
0
0
0
1
0
0
0
0
0
1
0
0
0
1
0
0
0
0
0
• RAM address setup: Set address is 50H
A0
0
WR
0
D7
1
D6
1
D5
0
D4
1
D3
0
D2
0
D1
0
D0
0
EPSON
4–47
SED1220
• Data writing: All data →20H (for 3 Line)
A0
1
WR
0
D7
0
D6
0
D5
1
D4
0
D3
0
D2
0
D1
0
D0
0
1
0
0
0
1
0
0
0
0
0
1
0
0
0
1
0
0
0
0
0
1
0
0
0
1
0
0
0
0
0
1
0
0
0
1
0
0
0
0
0
1
0
0
0
1
0
0
0
0
0
1
0
0
0
1
0
0
0
0
0
1
0
0
0
1
0
0
0
0
0
1
0
0
0
1
0
0
0
0
0
1
0
0
0
1
0
0
0
0
0
1
0
0
0
1
0
0
0
0
0
1
0
0
0
1
0
0
0
0
0
1
0
0
0
1
0
0
0
0
0
• End of Initialization
(2) Display ON “EPSON”
(2.1) RAM address setup command: 30H
A0
0
WR
0
D7
1
D6
0
D5
1
D4
1
D3
0
D2
0
D1
0
D0
0
(2.2) Data writing command: Writing “EPSON”
A0
1
WR
0
D7
0
D6
1
D5
0
D4
0
D3
0
D2
1
D1
0
D0
1
E: 45H
P: 50H
S: 53H
O: 4FH
N: 4EH
1
0
0
1
0
1
0
0
0
0
1
0
0
1
0
1
0
0
1
1
1
0
0
1
0
0
1
1
1
1
1
0
0
1
0
0
1
1
1
0
(2.3) Waiting for 20ms or more
(2.4) Display ON/OFF control command: B, C→0, D→1
A0
0
WR
0
D7
0
D6
0
D5
1
D4
1
D3
0
D2
0
D1
0
D0
1
Display ON 5×7 Dots “EPSON”
EPSON
4–48
EPSON
SED1220
(3) Display ON The Icon: Valid in Standby mode only
(3.1) Display ON/OFF command: D→OFF
A0
0
WR
0
D7
0
D6
0
D5
1
D4
1
D3
0
D2
0
D1
0
D0
0
(3.2) Static display control command: 1 ~ 2Hz Blink
A0
0
WR
0
D7
1
D6
0
D5
1
D4
0
D3
0
D2
0
D1
0
D0
0
1
0
0
0
0
1
0
0
0
0
0
0
1
0
1
0
0
0
0
1
1
0
0
0
0
1
0
0
0
0
(3.3) Power save command: PS→ON, 0→ON
A0
0
WR
0
D7
0
D6
1
D5
0
D4
0
D3
0/1
D2
0/1
D1
1
D0
1
(3.4) Power control commands: P, VF, VC→OFF
A0
0
WR
0
D7
0
D6
1
D5
0
D4
1
D3
0
D2
0
D1
0
D0
0
Display ON the Icon
e
(4) Releasing the Standby Mode
(4.1) Power save command: PS→0, 0→1
A0
0
WR
0
D7
0
D6
1
D5
0
D4
0
D3
0/1
D2
0/1
D1
1
D0
0
(4.2) Power control commands: P, VF, VC→1
A0
0
WR
0
D7
0
D6
1
D5
0
D4
1
D3
0
D2
1
D1
1
D0
1
(4.3) Waiting for 20ms or more
(4.4) Display ON/OFF command: D→1
A0
0
WR
0
D7
0
D6
0
D5
1
D4
1
D3
0
D2
0
D1
0
D0
1
END of Releasing the Standby mode
EPSON
4–49
SED1220
4. Power Supply to Booster Circuit
SED1220 integrates a booster circuit.
The customer can select a specification of using
either the regulator output VS1 or VSS as the supply
voltage to the booster circuit.
Our standard specification is preset to the regulator
output VS1.
5. External Clock Specifications
Option List
SED1220 provides the optional functions as described in
the following. Being adaptable to the customer’s optional
demand, contact the Business Department of our company
when installed.
o
Our product name corresponding to a customer’s
option is defined as shown below:
SED1220 integrates an external clock terminal and
there are two clock specifications, f and 4×f
oscillation.
(Example) SED1220D XB
Shipping form: A (AL
pad product) or B (metal
bump product)
Either of them can be selected on your request.
Internal
External
External
oscillation clock f osc. clock 4×f osc.
Option corresponding
digit
Standard
Optional
●
●
●
×
×
●
Machine type: 0 (12 digits × 3
lines) or 1 (12 digits × 2 lines)
The standard external clock specification is set to
fOSC.
1. Specification of Character Generator ROM
(CGROM)
6. Reset Signal Input Polarity Specifications
SED1220 inputs reset signal from the reset terminal
using edge detection and I/F specification 80/68
series can be selected according to this signal level.
RES input polarity can also be selected on your
request.
SED1220 integrates a character generator ROM
which can generate a maximum of 256 type characters.
The size of these characters is composed of 5 × 7 (8)
dots.
Being a mask ROM, the SED1220 CGROM is
adaptable to the character generator ROM exclusive
for the customer, too.
RES input
polarity
Type
For our standard CGROMs, refer to the Character
Fonts Table.
Standard
68 series
80 series
Optional
80 series
68 series
2. Specification of Liquid Crystal Driver Voltage Bias
Value.
SED1220 integrates a liquid crystal diver voltage
generator circuit. Its 5-volt potential is divided into
resistance inside of IC to generate 1-V, 2-V, 3-V or
4-V potential as required for the liquid crystal driver.
Further, the 1-V, 2-V, 3-V or 4-Vpotential is converted
into impedance by a voltage follower to be supplied
to the liquid crystal driver circuit.
is set to the 68 series and
to the 80 series as
the standard RES input polarities.
7. Pad Layout Specifications of COMS1 Symbol
Terminal
On SED1220, pad layout of COMS1 symbol terminal
can be changed. COMS1 pad layout can be selected
on your request.
Either 1/5 or 1/4 bias value can be selected as
demanded by the customer.
Our standard bias value is preset to 1/5.
3. Specification of Reference Voltage of Liquid Crystal
Driver Voltage Regulation Circuit.
Standard
Optional
Pad No
Pad Name
Pad Name
SED1220 integrates a voltage regulation circuit using
a booster voltage as its power supply to generate 5V
for the liquid crystal driver via the voltage regulation
circuit.
The voltage regulation circuit integrates a reference
voltage regulator VREG.
The customer can select a specification of using
either the internal reference voltage or external VSS
reference voltage.
Our standard specification is preset to the internal
reference voltage.
65
66
67
68
69
70
71
72
73
COMS1
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COMS1
4–50
EPSON
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