SED1648DOA_技术文档

SED1648

LCD SEGMENT DRIVER

■ DESCRIPTION

The SED1648 is an 80-output dot matrix LCD segment (column) driver for driving high-capacity LCD panels

at duty cycles higher than 1/100 (up to 1/300). The LSI has a wide range of the LCD driving voltages. The

offsetbiasregulationoftheliquidcrystalpowerispossibledependingontheVDD level.Theseuniquefeatures

allow the SED1648 to interface with a variety of LCD panels. The device does not require a controller to

implement an enable daisy chain technology.

The SED1648 is used in conjunction with the SED1651 (100-output row driver) or the SED1635 (100-bit row

driver) to drive a large-capacity dot matrix LCD panel.

■ FEATURES

Low-power CMOS technology

Daisy chain enable support

•

80-bit segment (column) driver

Pin selection of the output shift direction

LCD voltage ..................................... –8 to –28V

Supply voltage ................................. 2.7 to 5.5V

Package..........................Al pad slim DIE (DOA)

High-speed 4-bit bus

Duty cycle .................................. 1/100 to 1/300

Shift clock frequency .................... 10 MHz max

Ability to adjust offset bias of the LCD source

relative to VDD

■ SYSTEM BLOCK DIAGRAM

D0 ~ D3

XSCL

LP, FR

LCD

CONTR

YSCL

YD

SED1648

80

SED1648

80

SED1651

100

160 x 200 dots

DUTY: 1/200

100

525

SED1648

■ BLOCK DIAGRAM

O0

O79

V2

V3

V0

V5

LCD Driver

80 bits

V_SS

V_DD

Level Shifter

80 bits

FR

DSPOFF

LP

Latch

80 bits

Data Register

80 bits

D3~D0

XSCL

EIO1

SHL

Enable Shift Register

EIO2

526

SED1648

■ BLOCK DESCRIPTION

Enable Shift Register

•

The enable shift register is a bidirectional shift register where the direction of the shift is selected by the SHL

input. The output of this shift register is used to store the data bus signals in the data register.

When the enable signal is in a disable state, the internal clock signal and data bus are fixed at “L”, placing

the chip in power save mode.

Whenmultiplesegmentdriversareused, theEIOterminalsofthevariousdriversarecascadeconnectedand

the EIO terminal of the first driver is connected to VDD.

The enable control circuit automatically senses when 80 bits worth of data have been received, and sends

the enable signal, thus eliminating the need for a control signal from the control LSI.

Data Register

•

This is a register to convert the data bus signal from serial to parallel using the output of the enable shift

register. Consequently, the relationships between the serial display data and the segment output is

determined independently of the shift clock input number.

Latch

•

The latch receives the contents of the data registers when triggered by the falling edge of the LP, and outputs

them to the level shifter.

Level Shifter

•

The level shifter is a level interface circuit which converts the signal voltage level from a logic circuit level to

the LC driver voltage level.

LCD Driver

•

The LCD driver outputs the LC drive voltage.

Therelationshipbetweenthedatabussignal, theACsignalFR, andthesegmentoutputvoltageisasfollows:

Data

Bus Signal

FR

Voltage

DSPOFF

O Output

H

L

V0

V5

V2

V3

V0

H

L

H

L

—

527

SED1648

■ PIN DESCRIPTION

No. of

Pins

Pin Name

O0 to O79

I/O

O

Function

Segment (column) output to drive LC.

80

Output transition occurs on falling edge of LP.

D0 to D3

XSCL

LP

I

Display data input.

4

1

2

I

Display data shift clock input (triggers on falling edge)

Display data latch pulse input (triggers on falling edge)

Enable I/O

EIO1

EIO2

I/O

This is set to input or output depending on the level of the SHL input. The

outputisresetbytheLPinput, andoncethe80-bitdatareceptioniscomplete,

the terminals automatically rise to “H”.

SHL

I

Shift direction select and EIO terminal I/O control input.

1

When the data has been input to terminals (D3, D2, ..., D0) in the order (a3,

a2, a1, a0) (b3, b2, b1, b0) ... (t3, t2, t1, t0), the relationship between the data

and the segment output is as shown in the table below:

O Output

EIO

SHL

79

a3

t0

78

a2

t1

77

a1

t2

...

2

1

0

1

2

I

L

t2

t1

t0

O

I

H

a1

a2

a3

O

Note:

The relationship between the data and the segment output is

independent of the shift clock number.

FR

I

LC drive output AC signal input

1

4

8

VDD, VSS

Power

Power source for logic: VDD : 0V VSS : –2.7 to –5.5V

V0, V2,

V3, V5

LC drive circuit power:

VDD

V5

:

0V

–8 to –28V

VDD ≥ V0 ≥ V2 ≥ 6/9 × V5

3/9 × V5 ≥ V3 ≥ V5

*1

DSPOFF

I

Forced blank input.

1

“L” level outputs are forced to the V0 level.

Total 107 (of which 5 are NC)

Note: *1. The pairs V0-V5 must each be attached to the LCD power source.

528

SED1648

■ ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings

•

Parameter

Power voltage (1)

Symbol

Condition

–7.0 to +0.3

Unit

V

VSS

V5

Power voltage (2)

Power voltage (3)

Input voltage

–30.0 to +0.3

V

V0, V2, V3

VI

V5 – 0.3 to VDD + 0.3

VSS – 0.3 to VDD + 0.3

20

V

Output voltage

VO

V

EIO output current

Operating temperature

Storage temperature 1

IO

mA

°C

TOPR

TSTG1

–40 to +85

–65 to +150

Notes:

1. All voltages are given relative to V^DD= 0V.

2. Storage temperature 1 is the recommendation for the chip itself.

3. Ensure that the relationship between V0, V2 and V3 is always as follows: V^DD≥ V0 ≥ V2 ≥ V3 ≥ V5

System Side

V

DD

CC

DD

SS

–5V

V0

V2

GND

–28V

V3

V5

4. The LSI may be permanently damaged if the logic system power is floating or VSS is less than or equal to –2.6V when

power is applied to the LC drive circuit system. Special caution must be paid to the power sequences when turning

the power on and off.

529

SED1648

Unless otherwise specified, VDD = V0 = 0V,

DC Electrical Characteristics

•

VSS = –5.0V ± 10%, Ta = –40 to 85°C

Parameter

Symbol

V^SS

Conditions

Applicable Pins

Min

–5.5

Typ

–5.0

—

Max

–2.7

Unit

V

Power voltage (1)

VSS

V5

Recommended operating

voltage

V5

V^SS= –2.7 to –5.5V

Function

–28.0

–12.0

V

Possible operating

voltage

V5

—

–8.0

V

Power voltage (2)

Power voltage (3)

Power voltage (4)

High-level input voltage

V0

V2

V3

V^IH

Recommended value

VSS = –2.7 to –5.5V

V0

V2

V3

V^DD– 2.5

3/9 × V5

V5

—

VDD

V^DD

V

6/9 × V5

—

0.2 × VSS

EIO1, EIO2,

FR, D0 ~ D3,

XSCL, SHL,

LP,DSPOFF

Low-level input voltage

V^IL

—

0.8 × VSS

V

High-level output voltage

Low-level output voltage

V^OH

V^OL

VSS =

–2.7 to

–5.5V

IOH = –0.6mA

IOL = 0.6mA

EIO1, EIO2 VDD – 0.4

—

V

VSS + 0.4

Input leakage current

I^LI

VSS ≤ VIN ≤ VDD

D0 ~ D3, LP,

FR, XSCL,

—

2.0

µA

SHL, DSPOFF

I/O leakage current

Static current

I^LI/O

I^SS

VSS ≤ VIN ≤ VDD

EIO1, EIO2

VSS

—

5.0

25

µA

V5 = –28.0 to –14.0V,

V^IH= VDD, VIL = VSS

Output resistance

RSEG

∆VON = 0.5V,

O0 ~ O79

—

1.5

1.9

KΩ

V5 = –20.0V,

V3 = 13/15 × V5,

V2 = 2/15 × V5,

V0 = V^DD, Ta = 25°C

Average operating

I^SS

VSS = –5.0V,

VSS

—

0.10

0.2

mA

consumption current (1)

VIH = VDD, VIL = VSS,

f^XSCL= 2.69MHz,

fLP = 16.8KHz,

fFR = 70Hz;

Input data: checker

pattern display, no load

V^SS= –3.0V; other

parameters are the

same as for VSS = –5V

—

0.07

0.02

0.15

0.05

Average operating

I5

V^SS= –5.0V,

V5

mA

consumption current (2)

V0 = 0.0V, V2 = –9.3V,

V3 = –18.6V,

V5 = –28.0V; other

parameters are the

same as for the I^SSitem

Input terminal capacitance

I/O terminal capacitance

C^I

Freq. = 1MHz,

Ta = 25°C, Chip alone

D0 ~ D3, LP,

FR, XSCL,

SHL, DSPOFF

—

8

pF

C^I/O

EIO1, EIO2

15

530

SED1648

AC Characteristics

Input Timing Characteristics

•

°

V_IH= 0.2 V_SS

V_IL= 0.8 V_SS

FR

t_WLH

t_DF

t_C

LP

t_LD

t_LH

XSCL

t_DS

t_DH

t_WCH

t_WCL

D3~D0

t_SUE

EIO1, 2

(IN)

VSS = –5.0 ± 0.5V, Ta = –40 to 85°C

Parameter

Symbol

t^C

Conditions

Min

100

30

Max

—

Unit

ns

XSCL frequency

—

XSCL high-level pulse width

XSCL low-level pulse width

Data setup time

t^WCH

t^WCL

t^DS

—

30

—

20

—

Data hold time

t^DH

10

—

XSCL → LP rising edge

LP → XSCL falling edge

LP high-level pulse width

Allowable FR delay

t^LD

0

—

t^LH

40

—

t^WLH

t^DF

*3

40

—

–900

35

+900

—

EIO setup time

t^SUE

VSS = –4.5 to –2.7V, Ta = –40 to 85°C

Parameter

Symbol

t^C

Conditions

VSS = –2.7V

V^SS= –3.0V

—

Min

153

133

50

Max

—

Unit

ns

*1

*2

XSCL frequency

—

XSCL high-level pulse width

XSCL low-level pulse width

Data setup time

t^WCH

t^WCL

t^DS

—

50

—

30

—

Data hold time

t^DH

—

15

—

XSCL → LP rising edge

t^LD

—

0

—

VSS = –2.7V

V^SS= –3.0V

VSS = –2.7V

V^SS= –3.0V

—

75

—

LP → XSCL falling edge

t^LH

65

—

*3

75

—

LP high-level pulse width

Allowable FR delay

EIO setup time

t^WLH

t^DF

65

—

–900

60

+900

—

VSS = –2.7V

V^SS= –3.0V

t^SUE

50

—

Notes: *1. At 6.5 MHz.

*3. tWLH specifies when LP is “H” and XSCL is “L”.

*4. The tr and tf input signals are specified at 20 ns.

*2. At 7.5 MHz.

531

SED1648

Output Timing Characteristics

°

V_IH= 0.2 V_SS

V_IL= 0.8 V_SS

FR

t_FRSD

LP

t_ER

t_LSD

XSCL

t_DCL

V_IH= 0.2 V_SS

V_OL= 0.8 V_SS

EIO1, 2

(OUT)

O n

(SEG)

Vn–0.5

Vn+0.5

VDD = –5.0 ± 0.5V, V5 = –12.0 to –28.0V

Parameter

EIO reset time

Symbol

t^ER

Conditions

Min

—

Max

90

Unit

ns

CL = 15pF (EIO)

EIO output delay time

LP → SEG output delay time

FR → SEG output delay time

tDCL

—

55

ns

t^LSD

—

200

400

ns

CL = 100pF (On)

t^FRSD

—

ns

VDD = –4.5 to –2.7V, V5 = –12.0 to –28.0V

Parameter

Symbol

t^ER

Conditions

—

Min

—

Max

150

85

Unit

ns

EIO reset time

CL = 15pF (EIO)

VSS = –2.7V

V^SS= –3.0V

—

ns

EIO output delay time

t^DCL

—

75

ns

LP → SEG output delay time

FR → SEG output delay time

t^LSD

—

400

800

ns

CL = 100pF (On)

t^FRSD

—

ns

Notes: *1. The tr and tf input signals are specified at 20 ns.

532

SED1648

Timing Diagram

•

Timing diagram (assuming 1/200 duty). (This diagram provided only as a reference.)

200

1

2

3

4

199

200

1

2

199

200

1

LP

LATCH

DATA

FR

LP

XSCL

20

1

2

3

20

1

2

3

20

1

2

3

20

1

2

3

D0 ~ D3

EIO 1

EIO 2

EIO n

1

~ 3 indicate driver cascade numbers.

LP

LATCH

DATA

L

H

L

H

FR

H

DSPOFF

V0

V2

V3

V5

533

SED1648

■ LCD DRIVING POWER

Method of Forming Each Voltage Level

•

The simplest way to obtain the voltage levels for driving the LCs is to use resistive voltage dividers between

V5 and VDD, and to drive the LCs with op amp voltage followers.

In consideration of the use of op amps, V0 (the highest electrical level) and VDD are separated and given

separate terminals.

However, when the voltage level of V0 is below VDD and the voltage difference between the two is large, the

performance of the LC output driver is reduced. Therefore, ensure that the voltage gap between V0 and VDD

is in the range of 0V – 2.5V.

When op amps are not going to be used, connect V0 to VDD.

Permanent damage may result to the LSI when there is serial resistance in the V5 or VDD power lines. This

is because the voltage drop that will occur at V5 or VDD when the signal changes will cause the power level

relationships within the LCD (i.e., VDD ≥ V0 ≥ V2 ≥V3 ≥ V5) to fail.

When a guard resistance is inserted, voltage stabilization using a capacitance is necessary.

Cautions During Power Up and Power Down

•

Because of the high voltage of the LC driving system of this LSI, if the power to the logic system is floating

or if VSS is greater than or equal to –2.6V when a high voltage is applied to the LC driving system, or if the

LC driving signal is output before the LC driving system voltage stabilizes, then too much current will flow,

causing damage to the LSI.

It is recommended that the display off function (DSPOFF) be used to keep the LCD driver output level at V0

until the LCD drive system voltage stabilizes.

Follow the sequences below during power up and power down:

Power up: Logic system on → LC drive system on (or simultaneous)

Power down: LC drive system off → Logic system off (or simultaneous)

As a way to prevent excessive current, insert a high-speed fuse or guard resistance in series with the LC

power source.

The optimal value of the guard resistance must be selected based on the capacitance of the LC cells.

V

t1

t2

V_DD

V_SS

t

t1, t2, t3 0 s

V5

Power

ON

Power

OFF

t3

V_DD

V_SS

DSPOFF

t

534

SED1648

■ EXAMPLE OF CONNECTION

Large Screen LCD Structure Diagram

•

r

R

r

+

V_SS

V5

+

–

V5 V4 V3 V2 V1 V0 V_DD

DIO1

YD

YSCL

SHL

DIO2

DIO1

640 X 200 DOT

FR

SEL

(GND)

DIO2

1/200 DUTY

DI3 = H or L

80

SED1648

V_DD

EIO1

EIO2

EIO1

EIO2

EIO1

EIO2

1

2

8

LP

XSCL

SHL

DSPOFF

DL0 ~ 3

535

SED1648

■ PAD LAYOUT

90

80

70

60

50

40

(0,0)

1

5

10

15

20

25

Chip size ..................11.93 mm × 1.45 mm

Chip thickness .........400 µm (TYP)

Al Pad Specifications (SED1648D0A)

chip edge

161u

178u

(min)

156u-a

151u-a

a

b

c

109u

165u-a

b

180u

(min)

chip edge

Pad a aperture (X, Y): ...................100 × 120 µm PAD No. 38-97

Pad b aperture (X, Y): ...................110 × 110 µm PAD No. 28-37, 98-107

Pad c aperture (X, Y): ...................110 × 110 µm PAD No. 1-27

536

SED1648

■ PAD COORDINATES

Unit: µm

Pad

No.

Pad

Name

X

Y

Pad

No.

Pad

Name

X

Y

Pad

No.

Pad

Name

X

Y

Coord.

1

EIO2

V0

–5653

–5297

–5117

–4936

–4547

–4091

–3839

–3587

–3065

–2828

–2590

–2086

–1583

–1079

1079

1583

2086

2590

3065

3587

3839

4091

4594

4984

5164

5345

5653

5814

5653

5814

5653

5814

5653

5814

5653

5814

–560

–414

–305

–196

–86

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

09

5653

5268

5090

4911

4732

4554

4375

4197

4018

3839

3661

3482

3304

3125

2946

2768

2589

2411

2232

2053

1875

1696

1518

1339

1160

982

569

73

74

045

046

047

048

049

050

051

052

053

054

055

056

057

058

059

060

061

062

063

064

065

066

067

068

069

070

071

072

073

074

075

076

077

078

079

–982

569

460

351

241

132

23

2

010

011

012

013

014

015

016

017

018

019

020

021

022

023

024

025

026

027

028

029

030

031

032

033

034

035

036

037

038

039

040

041

042

043

044

–1160

–1339

–1518

–1696

–1875

–2053

–2232

–2411

–2589

–2768

–2946

–3125

–3304

–3482

–3661

–3839

–4018

–4197

–4375

–4554

–4732

–4911

–5090

–5268

–5653

–5814

–5653

–5814

–5653

–5814

–5653

–5814

–5653

–5814

3

V2

75

76

4

V3

5

V5

77

6

V^SS

NC

SHL

NC

V^DD

DSPOFF

FR

78

7

79

80

8

9

81

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

82

83

84

85

LP

86

XSCL

D0

87

88

D1

89

D2

90

NC

D3

91

92

NC

V^SS

V5

93

94

95

V3

96

V2

97

V0

98

803

99

EIO1

O0

625

100

101

102

103

104

105

106

107

01

446

02

267

89

03

–89

–86

–195

–305

–414

04

23

05

132

–267

–446

–625

–803

06

241

07

351

08

460

537

SED1648

THIS PAGE INTENTIONALLY BLANK

538


型号：	SED1648DOA
厂家：	SEIKO EPSON CORPORATION
描述：	LIQUID CRYSTAL DISPLAY DRIVER, UUC102, SLIM, ALUMINUM PAD, DIE-102 驱动接口集成电路
文件：	总14页 (文件大小：49K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

SED1648DOA [SEIKO]

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