SED1771DOA [SEIKO]
LIQUID CRYSTAL DISPLAY DRIVER, UUC182, 11.27 X 3.79 MM, 0.25 MM HEIGHT, DIE-182;
| 型号： | SED1771DOA |
| 厂家： | 
SEIKO EPSON CORPORATION |
| 描述： | LIQUID CRYSTAL DISPLAY DRIVER, UUC182, 11.27 X 3.79 MM, 0.25 MM HEIGHT, DIE-182 驱动 接口集成电路 |
| 文件： | 总14页 (文件大小：60K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SED1770/71
CMOS LCD DRIVER
■ DESCRIPTION
The SED1770 and the SED1771 are 160-bit output LCD segment (column) analog drivers for driving high-
capacity active matrix LCD MIM- or TFT-type panels. These devices take 3-bit analog input (VA, VB, VC)
which are (R, G, B) signals, and can support duty cycle higher than 1/100 (up to 1/500). Also, the LSI features
a wide range of LCD voltages from 5 to 17V.
The device uses a high-speed daisy-chain enable system which decreases power consumption and
eliminates the need for separate enable signals for each driver.
TheSED1770/71isusedinconjunctionwiththeSED1743Fcommondriverstosupportalarge-capacityTFT/
MIM active matrix LCD panel.
■ FEATURES
Low-power, high-speed CMOS technology
Built-in high-speed sampling circuitry
Selectable output shift direction
Low output resistance
•
•
•
•
•
•
•
•
•
•
LCD driver output ................... 160 (SED1770)
162 (SED1771)
High-speed data transfer ........ 10MHz
Wide range of LCD voltage .... 5 to 17V
Supply voltage ........................ 4.5 to 5.5V
Support high-speed daisy-chain data transfer
which reduces power consumption
Package.................................. TAB (2-sided)
Al pad (DOA)
Takes 3-bit video inputs (VA, VB, VC)
•
■ SYSTEM BLOCK DIAGRAM
VA, VB, VC
XSCL
LP, FR
LCD
CONTR
YSCL
YD
SED1770/71
160
SED1770/71
160
SED1743 160
320 SEG × 480 COM
160
160
SED1743
SED1743
DUTY: 1/480
673
SED1770/71
■ BLOCK DIAGRAM
VDDH VDD VSS
SEG0
SEG1
OE
Buffer Ability
Adjust/Select
Circuit
Liquid Crystal
Driver Buffer
V
d2
d1
V
Line Memory–2
Output Transfer Buffer
Line Memory-1
LP
V
COM
V ~ V
A
C
Sampling Circuit
SHL
2 Way Shift Register
EIO1
EIO2
Enable
Control Circuit
XSCL
TEST1
TEST2
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SED1770/71
■ FUNCTIONS OF BLOCKS
Enable control circuit
•
If the enable signal is in the disable status, the internal clock signal is fixed to “L” and placed in the POWER SAVE
mode.
When using multiple segment drivers, the EIO terminals of the drivers should be cascade-connected while the
EIOterminalofthefrontdriverisconnectedtoVSS.Inthiscase,thesamplingofthefrontdriverstartsfromXSCL’s
initial rising. As the enable control circuit automatically detects that sampling of data of the portion of 160 outputs
has been finished thus automatically transferring the enable signal, the control signal by the control LSI is not
necessary.
The EIO output is reset by LP input.
Shift register
•
•
The shift register shifts the sampling signal by shift clock input. And it selects the shift direction by SHL input.
Sampling circuit
The sampling circuit samples analog input signals sequentially by means of the sampling signals from the shift
register. At this time, input/output are corresponded as follows: VA with SEG0, 3, 6 --- 159; VB with SEG1, 4, 7
---157; and VC with SEG2, 5, 8 --- 158.
Line memory - 1
•
•
The line memory-1 stores the analog data sampled by the sampling circuit.
Output transfer buffer
With the rising of LP, the output transfer buffer transfers the data of line memory-1 to line memory-2 and at the
same time switches over to another liquid crystal drive output. When LP = H, make sure that XSCL = L. While
sampling the data, make sure that LP = L. The ability of this buffer can be adjusted by Vd1.
Line memory - 2
•
•
The line memory-2 holds the voltage of the liquid crystal drive output for the period until the next switching.
Liquid crystal drive buffer
The crystal drive buffer outputs the liquid crystal drive voltage. The ability of this buffer can be adjusted by Vd2
and switched over by OE.
Buffer ability adjustment and switching circuit
•
This circuit performs two types of buffer ability adjustment and switching. The buffer abilities of both Vd1 and Vd2
reach their lowest level when they are equivalent to VDDH; the respective abilities can be increased by lowering
the electric potential, thus enabling them to cope with various liquid crystal panels.
The ability (output current) of the liquid crystal drive buffer is switched over by the OE to be used. With the time
of writing data in the panel set at OE = “H”, the large current is used to drive the buffer; after writing the data, the
small current is used to drive the buffer at OE = “L”. This not only improves the data write ability but also prevents
the leakage of the hold time, thus making it possible to save power.
675
SED1770/71
■ PIN DESCRIPTION
Terminal
Name
Number of
Terminals
Power
I/O
I/O
Function
Shift register data input/output;
VDD
~
EIO1
EIO2
Connected to the lower-stage EIO in cascade connection;
Changes at XSCL’s rising edge
2
VSS
Clock signal input;
XSCL
LP
I
I
↑
↑
1
1
Shift register operation at rising and falling edges
Display data latch signal input; switches the output data at rising edge.
Liquid crystal drive buffer ability switching signal input:
H: Large current drive
OE
I
↑
1
L: Small current drive
Shift direction select signal input of shift register
SHL
H
EIO1
Input
EIO2
Output
Input
SEG Output
SHL
I
I
↑
↑
1
2
2
01-> 1 -> 2 --- -> 158 -> 159
159 -> 158 -> --- -> 2 -> 1 -> 0
L
Output
TEST1
TEST2
Test input: Normally L.
Pulldown is not built in.
Buffer ability adjustment input:
The buffer ability for output transfer and that for liquid crystal drive
can be varied by the voltage applied to the terminal.
Vd1: Output transfer buffer ability adjustment
VDDH
~
Vd1
Vd2
I
I
VSS
Vd2: Liquid crystal drive buffer ability adjustment
VA
VB
VC
Analog signal input:
↑
↑
3
Inputs image signals (R, G, and B).
Liquid crystal drive segment output:
SEG0
~
Outputs the level, based on the analog signal input
(VA, VB and VC) data as a sample holder.
The input/output are corresponded as
O
160
SEG159*
...
...
...
.
VA ->SEG0, 3, 6 , VB -> SEG1, 4, 7 , VC -> SEG2, 5, 8
Sample hold reference voltage input;
Reference power of the sample hold circuit;
To input the central electric potential of the analog signal
input (VA, VB, VC) is the standard.
VCOM
I
↑
1
VDDH
VDD
VSS
P
P
Power supply for high voltage LCD drive circuit.
Power supply for logic circuit.
—
—
2
1
LSI’s common GND:
P
—
3
Shall be externally connected among VSS terminals.
(*) In the case of SED1771DOA, this is up to 162 outputs and
SEG 162, and the number of terminals increases by two.
Total: 183
(NC 3)
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SED1770/71
■ ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
•
(VSS=0V)
Parameter
Supply voltage (1)
Supply voltage (2)
Input voltage *1
Symbol
VDD
Rating
Unit
V
–0.3 to +7.0
VDDH
VID
–0.3 to +25.0
–0.3 to VDD+0.3
–0.3 to VDDH+0.3
–65 to +150
V
V
Input voltage *2
VIA
V
Storage temperature
Operating temperature
Tstg
°C
°C
Topr
–20 to +75
Notes: 1. Applies to EIO1, EIO2, XSCL, LP, OE, SHL, TEST1, and TEST2.
2. Applies to VA, VB, VC, Vd1, Vd2, and VCOM.
DC Characteristics
•
(VSS=0V, VDD=5V±10%, VDDH=15V, and Ta= –20 to +75°C unless otherwise noted)
Applicable
Signal
VDD
Rating
Typ
—
Parameter
Symbol
Condition
Unit
Min
4.5
Max
5.5
Supply voltage (1)
Supply voltage (2)
“H” input voltage
VDD
VDDH
VIH
V
V
VDDH
VDD
—
17.0
VDD
0.2•VDD
8.0
0.8•VDD
VSS
—
V
*1
*2
“L” input voltage
VIL
—
V
Input terminal capacity
Input leak current
“H” output voltage
“L” output voltage
Input/output
CID
ILID
VOH
VOL
Ta = 25°
—
—
pF
µA
V
0 < VI < VDD
IOH = –0.4mA
IOL = 0.4mA
—
—
2.0
VDD–0.4
VSS
—
VDD
0.4
—
V
EIO1
EIO2
CI/O
Ta = 25°C
—
—
15.0
pF
terminal capacity
Input/output leak current
Analog input voltage
Analog input capacity
Between-output
ILI/O
Vvideo
CIA
0 < VI < VDD
—
—
—
—
15.0
VDDH–1.5
80
µA
V
VA, VB, VSS+1.5
VC
—
pF
dVO
MAX – MIN = 100
mV
SEG 0
~
voltage deviation
Input/output gain
Gv
IOH
IOL
95
—
—
—
—
—
0.1
0.1
—
105
—
—
5
%
SEG 161
“1” output current
“0” output current
Current consumption (1)
Current consumption (2)
*3
*4
*5
*5
mA
mA
mA
mA
IDD
—
—
IDDH
—
15
Notes: 1. EIO1, EIO2, XSCL, LP, OE, SHL, TEST1, TEST2
2. XSCL, LP, OE, SHL, TEST1, TEST2
3. Vd2 = 12V, Vvideo = 13V, OE = H
4. Vd2 = 12V, Vvideo=2V, OE=H
5. fXSCL = 10MHz, 1H = 63.5µs, Vvideo=+2~+13V, TOE (OE=H) = 10µs, without load
677
SED1770/71
AC Characteristics
•
VSS = 0V, VDD = 5V±10%, VDDH = 15V, and Ta = –20 to +75°C unless otherwise noted.
Input Timing Characteristics
°
tWLH
90%
10%
LP
tLD
tC
tLH
XSCL
tSUE
tWCH
tWCL
EIO
Rating
Typ
—
Parameter
Symbol
Condition
Unit
Min
100
40
40
40
2.5
1
Max
—
XSCL cycle
tc
ns
ns
ns
ns
µs
µs
ns
XSCL “H” pulse width
XSCL “L” pulse width
XSCL-to-LP rise time
LP pulse width
tWCH
tWCL
tLD
—
—
—
—
—
—
tWLH
tLH
*1
—
—
LP-to-XSCL time
EIO setup time
—
—
tSUE
50
—
—
Notes: 1. Time of XSCL=L and LP=H.
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SED1770/71
Output Timing Characteristics
°
LP
XSCL
t
t
ER
DCL
10%
EIO
90%
t
LSD
90%
10%
SEGout
Rating
Typ
—
Parameter
Symbol
Condition
Unit
Min
—
Max
40
EIO output delay time
EIO output reset time
tDCL
tER
ns
ns
CL = 15pF
—
—
12.0
Variable by Vdl and Vd2
15
LP-to-SEGout delay time
tLSD
*1
—
—
µs
Notes: 1. Vd1 = Vd2 = 12V, Vvideo = 2~13V, load capacity = 100pF, OE = “H”.
679
SED1770/71
Signal Timing Example (with specifications of SHL = H, 160 outputs, 1:1 correspondence)
•
XSCL
EIO1 (in)
EIO2 (out)
SEG0
SEG1
SEG2
SEG3
SEG159
V
A
B
SEG4
SEG157
SEG158
V
V
C
Sampling is started from the rising edge of the next XSCL after EIO1 has fallen.
1H
OE
LP
EIO
Sa
VCS
SEGout
Idr
Sa : Analog switch input of the sampling circuit
VCS : Electric potential of the sampling capacitor
Idr : Size of the drive current
680
SED1770/71
■ ALUMINUM MASTER SLICE OPTIONS
On this LSI, the following switchings are available by the aluminum master slice options.
Switching of number of output pins
•
(1) 160 outputs : Outputs EIO at the time of SEG158 sampling.
At this time, the SEG160 and 161 terminals are placed in the NC status.
(2) 162 outputs : Outputs EIO at the time of SEG160 sampling.
Note: This applies if SHL = H. If SHL = L, the first output becomes SEG159 with (1), and SEG161 with (2).
Correspondence between the shift register and the sampling analog switch
•
(1) Shift registers and analog switches shall be corresponded at the ratio of 1:1.
(2) One shift register stage shall be connected with three analog switches; and the shift register shall operate
for every 3 stages.
(1) 1 : 1 Correspondence
(2) 1 : 3 Correspondence
Skip
Shift
Register
Shift
Register
3n
3n+1
3n+2
3n
3(n+1)
3(n+1)
VA
VB
VC
VA
VB
VC
Analog
Switch
Analog
Switch
3n
3n+1
3n+2
3(n+1)
3n
3n+1
3n+2
3(n+1)
SEG Output
SEG Output
[n = 0 ~53]
Correspondence with product names
SED1770DOA: Selects 160 outputs for 1) and 1:1 correspondence for 1)
SED1771DOA: Selects 162 outputs for 1) and 1:3 correspondence for 2)
•
681
SED1770/71
■ PAD LAYOUT
1
185
Y
X
(0,0)
X
Y
Die size:
11.27mm × 3.79mm
Pad pitch:
0.12mm (min)
* Metallic bump specifications
Die thickness:
0.25mm ± 0.025mm
Bump Size
X
Y
PAD No.
23, 24, 28, 29, 30, 31
Bump size A
350µm × 150µm ± 20µm
200µm × 150µm ± 20µm
95µm × 150µm ± 20µm
15, 16, 17, 18, 19, 20, 21, 22, 25, 26, 27,
32, 33, 34, 35, 36, 37
Bump size B
Bump size C
Other than above
(The X in X and Y of the bump size shall be the direction parallel to the scribe line.)
682
SED1770/71
■ PAD COORDINATES
Unit = µm
Pad
X
Pad
Pad
Y
X
Y
X
Y
Number Name
Number Name
Number Name
89
SEG51 –3540 –1699
SEG52 –3420 –1699
SEG53 –3300 –1699
SEG54 –3180 –1699
SEG55 –3060 –1699
SEG56 –2940 –1699
SEG57 –2820 –1699
SEG58 –2700 –1699
SEG59 –2580 –1699
SEG60 –2460 –1699
SEG61 –2340 –1699
SEG62 –2220 –1699
SEG63 –2100 –1699
SEG64 –1980 –1699
SEG65 –1860 –1699
SEG66 –1740 –1699
SEG67 –1620 –1699
SEG68 –1500 –1699
SEG69 –1380 –1699
SEG70 –1260 –1699
SEG71 –1140 –1699
SEG72 –1020 –1699
1
SEG148 5210
SEG149 5090
SEG150 4970
SEG151 4850
SEG152 4730
SEG153 4610
SEG154 4490
SEG155 4370
SEG156 4250
SEG157 4130
SEG158 4010
SEG159 3890
SEG160* 3770
SEG161* 3650
TEST1 3400
1699
1699
1699
1699
1699
1699
1699
1699
1699
1699
1699
1699
1699
1699
1699
1699
1699
1699
1699
1699
1699
1699
1699
1699
1699
1699
1699
1699
1699
1699
1699
1699
1699
1699
1699
1699
1699
1699
1699
1699
1699
1699
1699
1699
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
SEG7 –4490
SEG8 –4610
SEG9 –4730
SEG10 –4850
SEG11 –4970
SEG12 –5090
SEG13 –5210
SEG14 –5436
SEG15 –5436
SEG16 –5436
SEG17 –5436
SEG18 –5436
SEG19 –5436
SEG20 –5436
SEG21 –5436
SEG22 –5436
SEG23 –5436
SEG24 –5436
SEG25 –5436
SEG26 –5436
SEG27 –5436
SEG28 –5436
SEG29 –5436
SEG30 –5436
SEG31 –5436
SEG32 –5436
SEG33 –5436
1699
1699
1699
1699
1699
1699
1699
1343
1223
1103
983
90
2
91
3
92
4
93
5
94
6
95
7
96
8
97
9
98
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
863
743
623
503
OE
LP
3150
2900
2650
2400
2150
1900
383
263
XSCL
SHL
EIO2
EIO1
143
23
–97
–217
–337
–457
–577
–697
–817
–937
TEST2 1650
SEG73 –900
SEG74 –780
SEG75 –660
SEG76 –540
SEG77 –420
SEG78 –300
SEG79 –180
–1699
–1699
–1699
–1699
–1699
–1699
–1699
–1699
–1699
–1699
–1699
–1699
–1699
–1699
–1699
–1699
–1699
–1699
–1699
–1699
–1699
–1699
VSS
VDDH
Vd1
1270
830
440
Vd2
190
VCOM
VSS
–60
–450
–890
–1330
–1770
–2150
–2400
–2650
–2900
–3150
–3400
SEG34 –5436 –1057
SEG35 –5436 –1177
SEG36 –5436 –1297
SEG37 –5436 –1417
SEG38 –5100 –1699
SEG39 –4980 –1699
SEG40 –4860 –1699
SEG41 –4740 –1699
SEG42 –4620 –1699
SEG43 –4500 –1699
SEG44 –4380 –1699
SEG45 –4260 –1699
SEG46 –4140 –1699
SEG47 –4020 –1699
SEG48 –3900 –1699
SEG49 –3780 –1699
SEG50 –3660 –1699
VDD
VDDH
VSS
SEG80
SEG81
SEG82
SEG83
SEG84
SEG85
SEG86
SEG87
SEG88
–60
60
180
300
420
540
660
780
900
VA
(NC)
VB
(NC)
VC
(NC)
SEG0 –3650
SEG1 –3770
SEG2 –3890
SEG3 –4010
SEG4 –4130
SEG5 –4250
SEG6 –4370
SEG89 1020
SEG90 1140
SEG91 1260
SEG92 1380
SEG93 1500
SEG94 1620
683
SED1770/71
Pad
Number Name
Pad
Pad
X
Y
X
Y
X
Y
Number Name
Number Name
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
SEG95 1740
SEG96 1860
SEG97 1980
SEG98 2100
SEG99 2220
SEG100 2340
SEG101 2460
SEG102 2580
SEG103 2700
SEG104 2820
SEG105 2940
SEG106 3060
SEG107 3180
SEG108 3300
SEG109 3420
SEG110 3540
SEG111 3660
SEG112 3780
–1699
–1699
–1699
–1699
–1699
–1699
–1699
–1699
–1699
–1699
–1699
–1699
–1699
–1699
–1699
–1699
–1699
–1699
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
SEG113 3900
SEG114 4020
SEG115 4140
SEG116 4260
SEG117 4380
SEG118 4500
SEG119 4620
SEG120 4740
SEG121 4860
SEG122 4980
SEG123 5100
SEG124 5436
SEG125 5436
SEG126 5436
SEG127 5436
SEG128 5436
SEG129 5436
SEG130 5436
–1699
–1699
–1699
–1699
–1699
–1699
–1699
–1699
–1699
–1699
–1699
–1417
–1297
–1177
–1057
–937
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
SEG131 5436
SEG132 5436
SEG133 5436
SEG134 5436
SEG135 5436
SEG136 5436
SEG137 5436
SEG138 5436
SEG139 5436
SEG140 5436
SEG141 5436
SEG142 5436
SEG143 5436
SEG144 5436
SEG145 5436
SEG146 5436
SEG147 5436
–577
–457
–337
–217
–97
23
143
263
383
503
623
743
863
983
1103
1223
1343
–817
–697
(*) SEG160 and 161 become NC in the case of SED1770DOA
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SED1770/71
■ EXTERNAL PACKAGE DIMENSIONS
1.50
9.40
9.82
NCx3
NC
216–
TEST–1
OE
LP
XSCL
SHL
EIO2
EIO1
TEST–2
VSS
VDDH
NC
Vd1
Vd2
VCOM
VSS
VDD
VDDH
VSS
VA
VB
VC
216–
NC
1.00
NCx3
3.92
5.90
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