GS12281 [SEMTECH]
12G UHD-SDI Re-timing Cable Driver;
| 型号： | GS12281 |
| 厂家： | 
SEMTECH CORPORATION |
| 描述： | 12G UHD-SDI Re-timing Cable Driver |
| 文件： | 总97页 (文件大小：3874K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
GS12281
12G UHD-SDI Re-timing Cable Driver
Key Features
Applications
•
Dual non-inverted 75Ω cable interface with on-chip
termination
Next Generation 12G UHD-SDI infrastructures designed to
support UHDTV1, UHDTV2, 4K D-Cinema and 3D HFR and HDR
production image formats. Typical applications: Cameras,
Switchers, Distribution Amplifiers and Routers.
•
SMPTE ST 2082-1, ST 2081-1, ST 424, ST 292-1 and ST 259
compliant input/output
•
•
Multi-standard operation from 1Mb/s to 11.88Gb/s
In addition to standard SMPTE rates, the device also supports
re-timing of DVB-ASI at 270Mb/s, and MADI at 125Mb/s.
Description
The GS12281 is a low-power, multi-rate, re-timing cable driver
supporting rates up to 12G UHD-SDI. It is designed to receive
100Ω differential input signals, automatically recover the
embedded clock from the digital video signal and re-time the
incoming data, and transmit the re-timed signal over 75Ω coaxial
cables. The 100Ω trace input supports up to 17dB of insertion loss.
•
•
•
3D Input Signal Eye Monitor
PRBS generator and checker
Cable driver mode features:
Wide swing control
Pre-emphasis to compensate for significant insertion loss
between device output and BNC
The integrated eye monitor provides non-disruptive mission
mode analysis of the post equalized input signal. The 256x128
resolution scan matrix allows accurate signal analysis to speed up
prototyping and enable field analysis.
Automatic/manual output slew rate control
Manual or automatic re-timer bypass
Manual or automatic Mute or disable on LOS
Built in macros enable customizable cross section analysis and
quick horizontal and vertical eye opening measurements.
•
Trace equalizer features:
Integrated 100Ω, differential input termination
Automatic power down on loss of signal
Adjustable carrier detect threshold
DC-coupling from 1.2V to 2.5V CML logic
Trace equalization to compensate for up to 20” FR4 at
11.88Gb/s
With high phase consistency between scans and configurable
space and time thresholds, algorithms can be deployed in the
field to analyze long term signal quality variation (Bathtub Plot) to
reduce costly system installation debug time for intermittent
errors. The two cable drivers have highly configurable
pre-emphasis and swing controls to compensate for long trace
and connector losses. Additionally, automatic and user selectable
output slew rate control is provided for each cable driver output.
Automatic input offset compensation
•
CDR features:
The GS12281 is pin compatible with the GS12181 single input,
and the GS12182 dual input 12G UHD-SDI Multi-rate Re-timing
Cable Drivers, the GS12081 12G UHD-SDI Multi-rate Cable Driver,
as well as the GS3281 3G SDI Multi-rate Re-timing Cable Driver.
Manual or automatic rate modes
Wide Loop bandwidth control
Re-timing at the following data rates: 125Mb/s, 270Mb/s,
1.485Gb/s, 2.97Gb/s, 5.94Gb/s, and 11.88Gb/s. This
includes the f/1.001 rates.
Note: For the GS12281 to be pin compatible with the GS12182,
careful design considerations are required. Contact for your local
Semtech FAE for details.
Additional Features
•
•
•
•
•
•
•
Single 1.8V power supply for analog and digital core
2.5V or 3.3V for cable driver output supply
GSPI serial control and monitoring interface
Four configurable GPIO pins for control or status monitoring
Wide operating temperature range: -40ºC to +85ºC
Small 6mm x 4mm 40-pin QFN
Pin compatible with the GS12181, GS12182, GS12081, and
GS3281
•
Pb-free/Halogen-free/RoHS and WEEE compliant package
GS12281
Final Data Sheet
PDS-061385
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GPIO2
GPIO3
GPIO4
SDOUT
GPIO1
SCLK
SDIN
CS
Control & Status
SDO0
Signal Selector
Cable Driver
PRBS
Generator
Data:
(Retime/Bypass)
SDO0
PRBS Generator
Swing and Pre-emphasis
Control
Trace Equalizer
CDR
DDI
SDO1
Signal Selector
Cable Driver
Data:
(Retime/Bypass)
PRBS
SDO1
Checker
PRBS Generator
Swing and Pre-emphasis
Control
EYE
Monitor
GS12281 Functional Block Diagram
GS12281
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Revision History
Version
ECO
PCN
Date
Changes and/or Modifications
Updated Input Voltage Range (DDI, DDI) and Table 5-3: Control
Register Descriptions.
9
8
7
044484
043494
043023
—
—
—
February 2019
August 2018
July 2018
Updated Table 5-4.
Updated Figure 1-1, Table 1-1, Table 2-2, Section 4.9.8 and
Section 6.
6
5
041055
040340
—
—
July 2018
Updated Section 4.9.5.6, Section 4.7.5.2 and Section 5.
Updated Table 2-2, Section 4.2.2 and Section 5.
January 2018
Added Section 4.7.3, added pin compatibility to list of key
features, updated Section 6.1, updated Table 2-2 and Table 2-3.
4
3
2
037848
037303
036700
—
—
—
August 2017
June 2017
May 2017
Updated Table 2-2, Section 4.5, Table 5-3, Figure 6-1,
Section 4.9.13 and added Section 4.9.12.
Rewrite of Section 4.4, Section 4.5, Section 4.6, Section 4.7.4
Updated Table 2-2, Table 2-3, Table 5-3 and Table 5-4
Updated Table 1-1, Table 2-1, Figure 4-8, Table 4-12, Figure 6-1 as
per Errata (PDS-061434)
1
0
034008
033175
—
—
November 2016
October 2016
New Document.
Contents
1. Pin Out.................................................................................................................................................................5
1.1 GS12281 Pin Assignment ................................................................................................................5
1.2 GS12281 Pin Descriptions ...............................................................................................................6
2. Electrical Characteristics................................................................................................................................9
2.1 Absolute Maximum Ratings ...........................................................................................................9
2.2 DC Electrical Characteristics ........................................................................................................ 10
2.3 AC Electrical Characteristics ......................................................................................................... 12
3. Input/Output Circuits.................................................................................................................................. 15
4. Detailed Description.................................................................................................................................... 16
4.1 Device Description .......................................................................................................................... 16
4.1.1 Sleep Mode............................................................................................................................ 16
4.2 Trace Equalizer ................................................................................................................................. 17
4.2.1 Input Trace Equalization................................................................................................... 17
4.2.2 Carrier Detect, and Loss of Signal.................................................................................. 18
4.3 Serial Digital Re-timer (CDR) ........................................................................................................ 19
4.3.1 PLL Loop Bandwidth Control.......................................................................................... 20
4.3.2 Automatic and Manual Rate Detection....................................................................... 20
4.3.3 Lock Time ............................................................................................................................... 21
GS12281
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4.4 PRBS Checker .................................................................................................................................... 23
4.4.1 Timed PRBS Check Measurement Procedure............................................................ 23
4.4.2 Continuous PRBS Check Measurement Procedure................................................. 24
4.5 EYE Monitor ....................................................................................................................................... 27
4.5.1 Shape Scan and Measurement Time............................................................................ 28
4.5.2 Matrix-Scan and Shape-Scan Operation..................................................................... 30
4.6 PRBS Generator ................................................................................................................................ 36
4.7 Output Drivers .................................................................................................................................. 38
4.7.1 Bypassed Re-timer Signal Output Control ................................................................. 39
4.7.2 Output Driver Polarity Inversion.................................................................................... 39
4.7.3 Output Driver Data Rate Selection................................................................................ 39
4.7.4 Amplitude and Pre-Emphasis Control ......................................................................... 40
4.7.5 Output State Control Modes........................................................................................... 42
4.8 GPIO Controls .................................................................................................................................... 43
4.9 GSPI Host Interface ......................................................................................................................... 44
4.9.1 CS Pin....................................................................................................................................... 44
4.9.2 SDIN Pin .................................................................................................................................. 44
4.9.3 SDOUT Pin.............................................................................................................................. 44
4.9.4 SCLK Pin .................................................................................................................................. 46
4.9.5 Command Word 1 Description....................................................................................... 46
4.9.6 GSPI Transaction Timing................................................................................................... 48
4.9.7 Single Read/Write Access................................................................................................. 50
4.9.8 Auto-increment Read/Write Access ............................................................................. 51
4.9.9 Setting a Device Unit Address ........................................................................................ 52
4.9.10 Default GSPI Operation................................................................................................... 53
4.9.11 Clear Sticky Counts Through Four Way Handshake............................................. 54
4.9.12 Device Power Up Sequence.......................................................................................... 54
4.9.13 Host Initiated Device Reset ........................................................................................... 55
5. Register Map................................................................................................................................................... 57
5.1 Control Registers ............................................................................................................................. 57
5.2 Status Registers ................................................................................................................................ 59
5.3 Register Descriptions ..................................................................................................................... 60
6. Application Information............................................................................................................................. 93
6.1 Typical Application Circuit ........................................................................................................... 93
7. Package & Ordering Information ............................................................................................................ 94
7.1 Package Dimensions ...................................................................................................................... 94
7.2 Recommended PCB Footprint .................................................................................................... 95
7.3 Packaging Data ................................................................................................................................ 95
7.4 Marking Diagram ............................................................................................................................. 96
7.5 Solder Reflow Profiles .................................................................................................................... 96
7.6 Ordering Information ..................................................................................................................... 96
GS12281
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1. Pin Out
1.1 GS12281 Pin Assignment
40
39
38
37
36
35
34
33
32
31
30
29
VEE_DDI
RSVD
1
2
3
4
5
6
7
8
28
27
26
25
24
23
22
21
VEEO
SDO0
RSVD
SDO0
GS12281
40-pin QFN
6mm x 4mm
VCC_DDI
TERM
VCCO_0
VCCO_1
SDO1/RCO
SDO1/RCO
VEEO
DDI
DDI
VEE_DDI
9
10
11
12
13
14
15
16
17
18
19
20
Figure 1-1: GS12281 Pin Assignment
GS12281
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1.2 GS12281 Pin Descriptions
Table 1-1: GS12281 Pin Descriptions
Pin Number
Name
Type
Description
Most negative power supply connection for the Trace Equalizer.
Connect to ground.
1, 8
VEE_DDI
Power
These pins may be left floating. Please contact your Semtech FAE for
additional information on circuit compatibility with the GS12241.
2, 3, 9, 30
4
RSVD
—
Most positive power supply connection for the Trace Equalizer.
VCC_DDI
Power
Connect to 1.8V and decouple to ground. See Section 6.1 Typical
Application Circuit for values.
Input Common Mode termination. Decouple to ground. See
Section 6.1 Typical Application Circuit for values.
5
TERM
—
Serial digital differential input. Differential CML input with internal
100Ω termination.
6, 7
DDI, DDI
Input
Chip Select input for the Gennum Serial Peripheral Interface (GSPI)
host control/status port.
1.8V CMOS input with 100kΩ pull-up.
Active-LOW input.
10
CS
Digital Input
Refer to Section 4.9.1 for more details.
Serial digital data input for the Gennum Serial Peripheral Interface
(GSPI) host control/status port.
11
12
13
SDIN
SDOUT
SCLK
Digital Input
Digital Output
Digital Input
1.8V CMOS input with 100kΩ pull-down.
Refer to Section 4.9.2 for more details.
Serial digital data output for the Gennum Serial Peripheral Interface
(GSPI) host control/status port.
1.8V CMOS output.
Refer to Section 4.9.3 for more details.
Burst-mode clock input for the Gennum Serial Peripheral Interface
(GSPI) host control/status port.
1.8V CMOS input with 100kΩ pull-down.
Refer to Section 4.9.4 for more details.
Most negative power supply for digital core logic.
Connect to ground.
14, 15
16
VSS
Power
Power
Most positive power supply connection for digital core logic.
VDD
Connect to 1.8V and decouple to ground. See Section 6.1 Typical
Application Circuit for values.
Multi-function Control/Status Input/Output 0.
Default function:
Digital
Input/Output
Direction = Output
Signal = High indicates LOS (Loss of Signal, inverse of Carrier Detect)
17
GPIO0
Pin is 1.8V CMOS I/O, please refer to GPIO0_CFG for more information
on how to configure GPIO0.
GS12281
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Table 1-1: GS12281 Pin Descriptions (Continued)
Pin Number
Name
Type
Description
Multi-function Control/Status Input/Output 1.
Default function:
Digital
Input/Output
Direction = Output
Signal = High indicates PLL is locked
18
GPIO1
Pin is 1.8V CMOS I/O, please refer to GPIO1_CFG for more information
on how to configure GPIO1.
Most negative power supply connection for the analog core.
Connect to ground.
19, 31, 37, 38
20
VEE_CORE
VCCO1P8_1
VEEO
Power
Power
Power
Most positive power supply connection for cable driver pre driver.
Connect to 1.8V and decouple to ground. See Section 6.1 Typical
Application Circuit for values.
Most negative power supply connection for the output drivers.
Connect to ground.
21, 28
Differential CML output with two internal 75Ω pull-ups.
The data signal or PRBS generator can be selected for this output. The
PRBS generator can be configured to generate a PRBS7 or a clock
pattern.
Note: If one of the two outputs is not used by the application, ensure
that it is connected to ground through a capacitor and resister. See
Section 6.1 Typical Application Circuit for values.
SDO1/RCO,
SDO1/RCO
22,23
Output
Most positive power supply connection for the SDO1/ SDO1 output
driver.
24
25
VCCO_1
VCCO_0
Power
Power
Connect to 2.5V or 3.3V and decouple to ground. See Section 6.1
Typical Application Circuit for values.
Most positive power supply connection for the SDO/SDO0 output
driver.
Connect to 2.5V or 3.3V and decouple to ground. See Section 6.1
Typical Application Circuit for values.
Differential CML output with two internal 75Ω pull-ups.
The data signal or PRBS generator can be selected for this output. The
PRBS generator can be configured to generate a PRBS7 or a clock
pattern.
26, 27
SDO0, SDO0
Output
Note: If one of the two outputs is not used by the application, ensure
that it is connected to ground through a capacitor and resistor. See
Section 6.1 Typical Application Circuit for values.
Most positive power supply connection for cable driver pre driver.
Connect to 1.8V and decouple to ground. See Section 6.1 Typical
Application Circuit for values.
29
32
VCCO1P8_0
REF_CLK
Power
Optional 27MHz reference input. 1.8V CMOS input with 100kΩ
pull-down. Connect to ground if not used.
Digital Input
GS12281
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Table 1-1: GS12281 Pin Descriptions (Continued)
Pin Number
Name
Type
Description
Multi-function Control/Status Input/Output 2.
Default function:
Digital
Input/Output
Direction = Input
Signal = Set high to put device in sleep
33
GPIO2
Pin is 1.8V CMOS I/O, please refer to GPIO2_CFG for more information
on how to configure GPIO2.
VCO filter capacitor connection. Decouple to ground. See Section 6.1
Typical Application Circuit for values.
34
35
VCO_FILT
Passive
Power
Most positive power supply connection for the analog core.
VCC_CORE
Connect to 1.8V and decouple to ground. See Section 6.1 Typical
Application Circuit for values.
Multi-function Control/Status Input/Output 3.
Default function:
Digital
Input/Output
Direction = Input
Signal = Set high to disable SDO1/SDO1
36
GPIO3
Pin is 1.8V CMOS I/O, please refer to GPIO3_CFG for more information
on how to configure GPIO3.
Loop filter capacitor connection. Connect to pin 40 through capacitor.
See Section 6.1 Typical Application Circuit for values.
39
40
LF+
LF-
Passive
Passive
Loop filter capacitor connection. Connect to pin 39 through capacitor.
See Section 6.1 Typical Application Circuit for values.
Central paddle can be connected to ground or left unconnected. Its
purpose is to provide increased mechanical stability. It is not required
for thermal dissipation. It is not commended to connect device
ground pins to the central paddle.
Tab
—
—
GS12281
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2. Electrical Characteristics
2.1 Absolute Maximum Ratings
Table 2-1: Absolute Maximum Ratings
Parameter
Value
Supply Voltage—Core (VCC_DDI, VCC_CORE,
VDD)
-0.5V to +2.2V
Supply Voltage—Output Driver (VCCO_0,
VCCO_1)
-0.5V to +3.65V
Input ESD Voltage (any pin)
2kV HBM
Storage Temperature Range (TS)
-50°C to +125°C
-0.3V to 2.6V
Input Voltage Range (DDI, DDI)
Input Voltage Range (GPIO2, GPIO3 REF_CLK) -0.3V to (VCC_CORE +0.3)V
Input Voltage Range (CS, SDIN, SCLK, VSS,
-0.3V to (VDD +0.3)V
VDD, GPIO0, GPIO1)
Solder Reflow Temperature
260°C
Note: Absolute Maximum Ratings are those values beyond which damage may occur.
Functional operation outside of the ranges shown in the AC/DC electrical characteristics
tables is not guaranteed.
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2.2 DC Electrical Characteristics
Table 2-2: DC Electrical Characteristics
TA = -40°C to +85°C, unless otherwise shown.
Parameter
Symbol
Conditions
Min
Typ
Max
Units Notes
VCC_DDI,
VCC_CORE
, VDD
Supply Voltage
1.71
1.8
1.89
V
—
2.38
3.14
2.5
3.3
2.63
3.47
V
V
—
—
Supply Voltage - Output
Driver
VCCO_0,
VCCO_1
VCCO_0 = 2.5V,
Output Swing = 800mVpp
—
—
375
390
—
—
mW
mW
1
,
Power - Mission Mode
(SDO0/SDO0 enabled
SDO1/SDO1 disabled)
PD
VCCO_0 = 2.5V,
Output Swing = 800mVpp
—
with max pre-emphasis
PD
Power - Sleep Mode
Sleep
—
—
40
23
54
34
mW
mA
—
VCCO_0 = 2.5V,
Output Swing = 800mVpp
1,4
VCCO_0 = 2.5V,
Output Swing = 800mVpp
with max pre-emphasis
,
—
—
—
—
29
24
30
20
38
33
37
28
mA
mA
mA
mA
4
1,4
4
ICCO_0
ICCO_1
,
VCCO_0 = 3.3V,
Output Swing = 800mVpp
Supply Current - Cable Driver
VCCO_0 = 3.3V,
Output Swing = 800mVpp
with max pre-emphasis
,
ICCO1P8_0
ICCO1P8_1
,
Output Swing = 800mVpp
4
CDR Locked to Rate
—
—
120
143
146
158
mA
mA
—
—
CDR Unlocked During
Rate Search
Supply Current –
Analog Core
ICC_CORE
PRBS Generator Enabled
PRBS Checker Enabled
Eye Monitor Enabled
—
—
—
60
55
50
90
94
92
mA
mA
mA
5,6
5
5
Supply Current - Trace
Equalizer
ICC_DDI
IDD
—
—
21
15
—
32
18
mA
mA
V
—
—
2
Supply Current - Digital Logic
DDI Input Common
Mode Voltage
VCMIN
0.94
2.525
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Table 2-2: DC Electrical Characteristics (Continued)
TA = -40°C to +85°C, unless otherwise shown.
Parameter
Symbol
Conditions
Min
Typ
Max
Units Notes
SDO Output Common
Mode Voltage
V
-
CCO
/2
VCMOUT
Single Ended
—
—
—
V
SDO
DDI Input Termination
Differential
—
—
100
75
—
—
Ω
Ω
—
3
SDO Output Termination
Between SDO and GND
0.65*
VDD
VIH
VIL
—
—
VDD
V
V
—
—
Input Voltage - Digital Pins
(CS, SDIN, SCLK, GPIO[0:1])
0.35*
VDD
0
0.65*
VIH
VIL
—
—
VCC_CORE
V
V
—
—
VCC_CORE
Input Voltage - Digital Pins
(GPIO[2:3])
0.35*
0
VCC_CORE
VDD -
0.45
VOH
VOL
VOH
VOL
IOH = -5mA
IOL = +5mA
IOH = -5mA
IOL = +5mA
—
—
—
—
—
0.45
—
V
V
V
V
—
—
—
—
Output Voltage - Digital Pins
(SDOUT, GPIO[0:1])
—
VCC_CORE
- 0.45
Output Voltage - Digital Pins
(GPIO[2:3])
—
0.45
Notes:
1. Pre-emphasis is disabled.
2. 0.94V is when trace EQ is DC coupled to upstream driver running from 1.2V supply, and 2.525V is when trace EQ is DC coupled to upstream driver
running from 2.5V supply.
3. Applies to both SDO0 and SDO1.
4. The specifications provided are per symbol, not a combined value.
5. Current listed is an increase to ICC_CORE when stated condition is true.
6. Selected clock source = VCO free running.
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2.3 AC Electrical Characteristics
Table 2-3: AC Electrical Characteristics
VCC_DDI, VCC_CORE, VDD = 1.8V 5ꢀ and VCCO_0, VCCO_1 = +2.5/3.3V 5ꢀ, TA = -40°C to +85°C, unless otherwise shown.
Parameter
Symbol
DRDDI
Conditions
—
Min
0.001
720
Typ
—
Max
11.88
880
Units Notes
Serial Input Data Rate
Serial Output Voltage Swing
Gb/s
—
3
VSDO
mVpp
Single Ended
800
Differential Input
Voltage Swing
VDDI
mVppd
—
200
—
800
10
12G
—
—
—
—
—
—
0.7
0.8
20
30
—
—
—
—
—
—
—
—
Inches
Inches
Inches
Inches
Inches
Inches
UI
8
8
6G
Loss Compensation (Input
Trace Equalization)
3G
60
8
—
HD
60
8
SD
60
8
MADI
60
8
12G
0.85
0.95
—
—
Intrinsic Input Jitter Tolerance
Square Wave Modulation
IIJT
MADI/SD/HD/3G/6G
UI
All rates enabled, except
MADI.
—
—
16.7
ms
5
tALOCK
PLL Lock Time – Asynchronous
PLL Lock Time – Synchronous
All rates enabled.
—
—
—
400
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
32
10
5
ms
μs
μs
ps
ps
ps
ps
ps
ps
ꢀ
5
5
5
6
6
6
6
6
6
6
6
6
6
1
1
1
1
SD
tSLOCK
HD/3G/6G/12G
SD
1000
70
40
100
20
10
5
triseSDO, tfallSDO
SDO/SDO Rise/Fall Time
HD/3G
6G/12G
SD
SDO/SDO Mismatch
in Rise/Fall Time
—
HD/3G
6G/12G
SD
SDO/SDO Eye Cross Shift
SDO/SDO Overshoot
—
—
HD/3G
8
ꢀ
6G/12G
9
ꢀ
—
10
-17
-12
-8
ꢀ
5MHz to 1.485GHz
1.485GHz to 2.97GHz
2.97GHz to 5.94GHz
5.94GHz to 11.88GHz
dB
dB
dB
dB
Output Return Loss
—
-5
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Table 2-3: AC Electrical Characteristics (Continued)
VCC_DDI, VCC_CORE, VDD = 1.8V 5ꢀ and VCCO_0, VCCO_1 = +2.5/3.3V 5ꢀ, TA = -40°C to +85°C, unless otherwise shown.
Parameter
Symbol
tOJ(125Mb/s)
tOJ(270Mb/s)
tOJ(1.485Gb/s)
tOJ(2.97Gb/s)
tOJ(5.94Gb/s)
tOJ(11.88Gb/s)
tOJ(Bypass)
Conditions
Min
—
Typ
0.015
0.03
0.03
0.04
0.05
0.08
Max
0.08
0.08
0.08
0.08
0.1
Units Notes
UIpp
UIpp
UIpp
UIpp
UIpp
UIpp
UIpp
2, 6, 9
2, 6, 9
2, 6, 9
2, 6, 9
2, 6, 9
2, 6, 9
—
—
Serial Data Output Jitter
(SDO/SDO)
BW = default,
Pattern = PRBS
—
—
—
0.16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0.13
10
0.2
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
2, 6, 7
4
Setting 0.0625x
Setting 0.125x
Setting 0.25x
kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz
MHz
MHz
kHz
kHz
MHz
MHz
MHz
20
4
BWLOOP(125Mb/s)
BWLOOP(270Mb/s)
BWLOOP(1.485Gb/s)
BWLOOP(2.97Gb/s)
BWLOOP(5.94Gb/s)
38
4
Setting 0.5x (Default)
Setting 1.0x
76
4
150
20
4
Setting 0.0625x
Setting 0.125x
Setting 0.25x
4
40
4
80
4
Setting 0.5x
160
316
110
220
440
876
1750
220
440
880
1.76
3.5
4
Setting 1.0x (Default)
Setting 0.0625x
Setting 0.125x
Setting 0.25x
4
4
4
PLL Loop Bandwidth
4
Setting 0.5x (Default)
Setting 1.0x
4
4
Setting 0.0625x
Setting 0.125x
Setting 0.25x
4
4
4
Setting 0.5x (Default)
Setting 1.0x
4
4
Setting 0.0625x
Setting 0.125x
Setting 0.25x
440
880
1.76
3.5
4
4
4
Setting 0.5x (Default)
Setting 1.0x
4
7
4
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Table 2-3: AC Electrical Characteristics (Continued)
VCC_DDI, VCC_CORE, VDD = 1.8V 5ꢀ and VCCO_0, VCCO_1 = +2.5/3.3V 5ꢀ, TA = -40°C to +85°C, unless otherwise shown.
Parameter
Symbol
Conditions
Min
—
Typ
880
1.76
3.5
7
Max
—
Units Notes
Setting 0.0625x
Setting 0.125x
Setting 0.25x
kHz
MHz
MHz
MHz
MHz
4
4
4
4
4
—
—
PLL Loop Bandwidth
(Continued)
BWLOOP(11.88Gb/s)
—
—
Setting 0.5x (Default)
Setting 1.0x
—
—
—
14
—
Notes:
1. Values achieved with Semtech evaluation board and connector.
2. Measured using a clean input source.
3. Default driver swing Setting.
4. Please see PLL_LOOP_ BANDWIDTH_ 0 for the full range of loop bandwidth settings.
5. Please see Section 4.3.3.1for the further definition on Synchronous and Asynchronous Lock Time.
6. This specification applies to SDO0/SDO0 and SDO1/SDO1.
7. For 12G and minimum trace loss.
8. Trace insertion loss was measured with FR4 material using 7 mil stripline traces using a PRBS23 signal.
9. Measured under minimal trace loss conditions.
10.Stated minimum and maximum voltages represent voltage levels at input pins.
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3. Input/Output Circuits
2
VCCO_<n>
VCCO_<n>
VCCO_<n>
VCC_DDI
VCC_DDI VCC_DDI
75Ω
75Ω
SDO
SDO
DDI
RLC
RLC
50Ω
50Ω
TERM
DDI
Note: The <n> in VCCO_<n> refers to the output power supply number. VCCO_1
is the power supply connection for SDO1/SDO1, and VCCO_0 is the power supply
connection for SDO0/SDO0.
Figure 3-1: DDI, DDI
Figure 3-2: SDO0/SDO0 and SDO1/SDO1
VDD
VDD
VDD
VDD
VDD
100kΩ
SDIN,
SCLK,
CS
REF_CLK
100kΩ
Figure 3-3: SDIN, SCLK, REF_CLK
Figure 3-4:
.
CS
VCC_IO*
VCC_IO*
VCC_IO*
VDD
VDD
1kΩ
GPIO[0:3]
100kΩ
VCC_IO*
SDOUT
Note: VCC_IO makes reference to the following power supplies and pins:
VCC_IO = VDD for GPIO[0:1]
VCC_IO = VCC_CORE for GPIO[2:3]
Figure 3-5: SDOUT
Figure 3-6: GPIO[0:3]
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4. Detailed Description
4.1 Device Description
The GS12281 is a dual output SMPTE compliant re-timing cable driver with integrated
75Ω internal terminations. It includes a 100Ω differential trace equalizer to receive the
outgoing signal from the system. The Trace Equalizer has offset correction and boost
control, which can compensate for 17dB of insertion loss at 5.94GHz. The device
includes a CDR which will lock to and retime valid SMPTE signals to produce extremely
low output jitter, even at extended trace lengths. The CDR has extensive loop
bandwidth control to enable jitter transfer optimization. To facilitate system testing, the
device also includes 3D eye monitor, PRBS7 checker and generator. The Cable Driver has
amplitude and pre-emphasis control to compensate for significant insertion loss
between device output and BNC. The pre-emphasis control is two dimensional, where
both pre-emphasis pulse amplitude and width adjustments can be made to help
optimize for interconnect mismatches such as vias and connectors.
Note: The parameters referred to within Section 4.2.1 to Section 4.2.2 are linked to their
respective registers in Table 4-1. For a complete list of registers and functions, please see
Section 5.
4.1.1 Sleep Mode
To enable low power operation, the GS12281 has manual and automatic sleep mode
control.
The default mode is automatic sleep mode on LOS (Loss of signal). The device can also
be manually put into sleep mode. When the device is in sleep mode, all the core blocks
are powered-down, except the host interface and carrier detect circuits. The cable driver
can be configured to be disabled or muted during sleep.
The CTRL_AUTO_SLEEP and CTRL_MANUAL_SLEEP parameters in register 0x3,
control the sleep mode of the device. The default value of the CTRL_AUTO_SLEEP
parameter is 1 (auto sleep). While in auto sleep mode, the CTRL_MANUAL_SLEEP
b
parameter has no effect. To enable host control of the sleep mode, set the
CTRL_AUTO_SLEEP parameter to 0 manual sleep control. To prevent the device from
b
entering sleep, set the CTRL_MANUAL_SLEEP parameter to 0 (not sleep). To manually
b
configure the device to sleep, set the CTRL_MANUAL_SLEEP parameter to 1 (sleep).
b
The device can also be manually made to sleep through the GPIO pins. The default GPIO
pin to control sleep is GPIO2 (pin 33). Drive this pin HIGH to make the device sleep.
Section 4.6 describes the PRBS generator function. If the device's PRBS generator is
intended to be used without a valid input signal, the device should be manually set to
not sleep as described above. Without a valid input signal, an LOS status will be
generated and the device will enter sleep mode and the PRBS block will be disabled. For
a description of LOS thresholds and settings, see Section 4.2.2.
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4.2 Trace Equalizer
The GS12281 features a differential input buffer with 100Ω differential input
termination, which includes a trace equalizer that can be configured to compensate for
up to 20" of 7-mil stripline of FR4 at 11.88Gb/s and up to 60" at 3Gb/s.
The differential input signal can be either DC-coupled or AC-coupled and is capable of
operation with any binary coded signal that between 1Mb/s and 11.88Gb/s.
The input circuit is compatible with industry standard CML differential transmitters
when DC coupled using industry standard 100Ω differential termination circuitry.
The trace equalizer includes an automatic input offset compensation circuit. This
reduces offset-induced data jitter in the link due to asymmetric performance of
DC-coupled upstream differential drivers. The input offset compensation circuit also
improves the input sensitivity of the trace equalizer.
Note: The parameters referred to within Section 4.2.1 to Section 4.2.2 are linked to their
respective registers in Table 4-1. For a complete list of registers and functions, please see
Section 5.
4.2.1 Input Trace Equalization
The trace equalizer can compensate for up to 17dB of insertion loss at 5.94GHz in 8
increments, which can be adjusted through the CFG_TREQ0_BOOST parameter in
control register 0x1E. The default value of CFG_TREQ0_BOOST is (2 ). Please refer to
h
Figure 4-1 for recommended boost setting.
8
7
6
boost setting 8
5
4
3
2
1
0
boost setting 7
boost setting 6
boost setting 5
boost setting 4
boost setting 3
boost setting 2
boost setting 1
boost setting 0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
Insertion Loss at 5.94GHz (dB)
Figure 4-1: GS12281 Trace EQ Boost Setting Recommendation
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By default at power up or after system reset, the trace equalizer is configured to
compensate for up to 3" of 7-mil stripline in FR4 material at high frequencies.
Note: If using input trace lengths longer than 5", use an upstream launch swing of
~800mV
ppd
4.2.2 Carrier Detect, and Loss of Signal
The trace equalizer input has a highly configurable Carrier Detection mechanism that
allows the system designer to optimize the sensitivity and hysteresis of the Carrier
Detection mechanism to meet specific system requirements.
Default settings should satisfy most applications; however, designers can modify the
following three parameters to customize the trace equalizer's carrier detection for their
application:
•
•
•
CFG_TREQ0_CD_BOOST
CFG_TREQ0_CD_ASSERT_THRESH
CFG_TREQ0_CD_DEASSERT_THRESH
The trace equalizer Carrier Detect is reported by status parameter STAT_PRI_CD in
register 0x87.
The first CD control parameter is CFG_TREQ0_CD_BOOST in register 0x1E. This
parameter determines the method and therefore the level of equalization to be used on
the input signal routed to the Carrier Detection sub-block. The default value is 0 , which
b
maximizes the level of equalization. Alternatively, the designer can choose to have this
signal equalized at the same level as the main signal routed to the CDR by setting
CFG_TREQ0_CD_BOOST to 1 . The setting of this parameter has no impact on the main
b
signal routed to the CDR.
The last two CD control parameters can be found in register 0x1F. Parameters
CFG_TREQ0_CD_ASSERT_THRESH and CFG_TRE0Q_CD_DEASSERT_THRESH set
the Carrier Detect assert and de-assert thresholds to the input signal, which also defines
the hysteresis of CD signal.
The default values of CFG_TREQ0_CD_ASSERT_THRESH and
CFG_TREQ0_CD_DEASSERT_THRESH are is 4 and 3 respectively. With the default
d
d
settings, the minimum launch swing needed to assert the carrier detect is 200mV and it
will be de-asserted when the signal level falls below 150mV.
The STAT_PRI_CD (Carrier Detect) parameter will be set to 0 and the LOS will be set to
b
1 whenever a new signal at the input does not exceed the assert threshold, or an
b
existing signal falls below the de-assert threshold. The result is that the device will not
indicate lock, and the outputs will mute (assuming Mute on LOS is left to its default value
in the CONTROL_OUTPUT_MUTE register (0x49). See Section 4.7.5 for more details.
Given a differential input trace with 17dB of insertion loss at 5.94GHz and
CFG_TREQ0_CD_BOOST = 0 , Figure 4-2 illustrates the relationship between launch
b
swing voltage, and minimum threshold setting to assert or de-asset Carrier Detect at all
rates up to threshold setting at 11.88Gb/s.
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Min Launch Swing vs. CD Threshold Setting
800
700
600
500
400
300
200
100
0
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
Carrier Detect Threshold Setting
Figure 4-2: Input Voltage Vs. Carrier Detect Threshold Setting
Table 4-1: Trace Equalizer Configuration and Status Parameters
Register Address
and Name
h
Parameter Name
Description
CFG_TREQ0_CD_DEASSERT_THRESH
CFG_TREQ0_CD_ASSERT_THRESH
CFG_TREQ0_CD_BOOST
Sets the Carrier Detect de-assert threshold.
Sets the Carrier Detect assert threshold.
Selects the boost method of the CD signal.
Sets the Trace Equalizer boost level.
1F,
TREQ0_CD_ HYSTERESIS
1E,
TREQ0_ INPUT_BOOST
CFG_TREQ0_BOOST
84,
A counter showing the number of times the primary
Carrier Detect signal changed.
STAT_CNT_PRI_CD_CHANGES
STAT_PRI_CD
STICKY_ COUNTS_0
87,
Primary carrier detection status.
CURRENT_ STATUS_1
4.3 Serial Digital Re-timer (CDR)
The GS12281 includes an integrated CDR, whose purpose is to lock to a valid incoming
signal from the trace equalizer stage and produce a lower jitter signal at the cable driver
outputs. The CDR will attempt to lock to any of the following data rates: MADI
(125Mb/s), SD-SDI (270Mb/s), HD-SDI (1.485Gb/s), 3G-SDI (2.97Gb/s), 6G-SDI (5.94Gb/s)
and 12G-SDI (11.88Gb/s). This includes the f/1.001 rates. The default settings of the
re-timer block are optimal for most applications. However, the following controls allow
the user to customize the behaviour of the re-timer: loop bandwidth control, Automatic
and Manual Rate Detection.
Note: The parameters referred to within Section 4.3.1 to Section 4.3.3.1 are linked to
their respective registers in Table 4-3. For a complete list of registers and functions,
please see Section 5.
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4.3.1 PLL Loop Bandwidth Control
The ratio of output peak-to-peak jitter to input peak-to-peak jitter of the CDR can be
represented by a low-pass jitter transfer function, with a bandwidth equal to the PLL
loop bandwidth. Although the default loop bandwidth settings for the GS12281 CDR
are ideal for most SDI signals, the GS12281 allows the user to adjust the loop bandwidth
for each MADI and SMPTE compliant rate.
Registers 0x0A through 0x0C contain the following parameters which allow the user to
configure rate dependent loop bandwidth: CFG_PLL_LBW_12G, CFG_PLL_LBW_6G,
CFG_PLL_LBW_3G, CFG_PLL_LBW_HD, CFG_PLL_LBW_SD, and
CFG_PLL_LBW_MADI. The loop bandwidth settings are defined in terms of ratios of the
nominal loop bandwidth. For each rate, where '1.0x' is the nominal loop bandwidth, the
following ratios are available: 0.0625x, 0.125x, 0.25x, 0.5x, and 1.0x. Table 2-3 provides
the specific loop bandwidths for each data rate and loop bandwidth setting. Lowering
the loop bandwidth will lower the jitter amplitude above the loop bandwidth
frequency. Although lower output jitter is desirable, the lower loop bandwidth may
reduce the device’s IJT to very high jitter that may be present outside the loop
bandwidth.
4.3.2 Automatic and Manual Rate Detection
With the default rate detect setting, the CDR will automatically attempt to lock to any of
following data rates: SD-SDI (270Mb/s), HD-SDI (1.485Gb/s), 3G-SDI (2.97Gb/s), 6G-SDI
(5.94Gb/s) and 12G-SDI (11.88Gb/s). This includes the f/1.001 rates. However, the CDR
can be configured to only lock to a single rate, by setting the
CFG_AUTO_RATE_DETECT_ENA and CFG_MANUAL_RATE parameters in register
0x06. In addition to CFG_MANUAL_RATE, with automatic rate detection enabled
(CFG_AUTO_RATE_DETECT_ENA = 1), specific rates can be excluded from the rate
detect list through the CFG_RATE_ENA_<r> rate disable mask parameter in 0x06,
where r is the rate to be disabled or enabled. For details on specific settings, please see
the RATE_ DETECT_ MODE register.
The STAT_LOCK parameter in register 0x86 will indicate that the CDR is locked when its
value is 1 and unlocked when its value is 0 . The lock status can also be monitored
b
b
externally on any GPIO pin, however it is the default mode for GPIO1, pin 18. The
STAT_DETECTED_RATE parameter in register 0x87 will indicate the data rate at which
the CDR is locked to. A value of 0 in the STAT_DETECTED_RATE parameter indicates
d
that the device is not locked, while values between 1 and 6 will indicate that the
d
d
device is locked to one of the six available rates between MADI at 125Mb/s and UHD-SDI
at 11.88Gb/s.
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Table 4-2: Detected Data Rates
STAT_DETECTED_
Detected Data Rate
RATE [2:0]
0
1
2
3
4
5
6
Unlocked
MADI (125Mb/s)
SD (270Mb/s)
HD (1.485Gb/s)
3G (2.97Gb/s)
6G (5.94Gb/s)
12G (11.88Gb/s)
If the CDR cannot lock to any of the valid rates in automatic mode or the selected rate in
manual mode, the signal can automatically be bypassed to the output. If the CDR does
lock to the incoming signal, the re-timed and bypassed (if manual bypass control
enabled) signals are available at the appropriate output. See the Section 4.7 for more
details.
4.3.3 Lock Time
4.3.3.1 Synchronous and Asynchronous Lock Time
Synchronous lock time is defined as the time it takes the device to re-lock to an existing
signal that has been momentarily interrupted or to a new signal of the same data rate
as the previous signal which has been quickly switched in.
Asynchronous lock time is defined as the time it takes the device to lock when a signal
is first applied to the serial digital inputs, or when the signal rate changes. The
asynchronous and synchronous lock times are defined in Table 2-3.
Note: To ensure synchronous lock times are met, the maximum interruption time of the
signal is 10μs for an SD-SDI signal. HD, 3G, 6G, or 12G signals must have a maximum
interruption time of 6μs. The new signal, after interruption, must have the same
frequency as the original signal but may have an arbitrary phase.
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Table 4-3: CDR Control and Status Parameters
Register Address
and Name
h
Parameter Name
Description
Enables or disables the automatic rate detection mode
of the CDR.
CFG_AUTO_RATE_DETECT_ENA
CFG_MANUAL_RATE
Select a single rate for CDR rate detection when
CFG_AUTO_RATE_DETECT_ENA is 0b.
CFG_RATE_ENA_12G
CFG_RATE_ENA_3G
CFG_RATE_ENA_6G
CFG_RATE_ENA_HD
CFG_RATE_ENA_SD
CFG_RATE_ENA_MADI
12G auto rate detection enable
3G auto rate detection enable
6G auto rate detection enable
HD auto rate detection enable
SD auto rate detection enable
MADI auto rate detection enable
06,
RATE_ DETECT_ MODE
08,
CFG_REF_CLK_MODE_MANUAL
Enables or disables external reference clock mode.
REF_CLK_ MODE
0A,
CFG_PLL_LBW_12G
CFG_PLL_LBW_6G
CFG_PLL_LBW_3G
CFG_PLL_LBW_HD
CFG_PLL_LBW_SD
CFG_PLL_LBW_MADI
Configures the Loop Bandwidth for 12G signals.
Configures the Loop Bandwidth for 6G signals.
Configures the Loop Bandwidth for 3G signals.
Configures the Loop Bandwidth for HD signals.
Configures the Loop Bandwidth for SD signals.
Configures the Loop Bandwidth for MADI signals.
PLL_LOOP_
BANDWIDTH_ 0
0B,
PLL_LOOP_
BANDWIDTH_ 1
0C,
PLL_LOOP_
BANDWIDTH_ 2
CFG_GPIO1_FUNCTION
Sets the function of GPIO1.
11,
GPIO1_CFG
CFG_GPIO1_OUTPUT_ ENA
Sets the GPIO pin as either an output or an input.
Counter showing the number of times the PLL lock
status changed.
STAT_CNT_PLL_LOCK_CHANGES
STAT_CNT_RATE_CHANGES
STAT_LOCK
85,
STICKY_ COUNTS_1
Counter showing the number of times the PLL lock rate
changed.
86,
The status of the PLL. Locked, or unlocked.
The rate at which the PLL is locked to.
CURRENT_ STATUS_0
87,
STAT_DETECTED_RATE
CURRENT_ STATUS_1
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4.4 PRBS Checker
The GS12281 includes an integrated PRBS checker, which can error check a PRBS7 signal
out of the trace equalizer input blocks.
There are two modes of operation for the PRBS checker:
•
•
Timed Mode: Used for precise measurements of up to ~3.334s.
In timed mode, the host sets the measurement time and executes the checker
operation. The device ends the PRBS error check measurement when the timer
expires, and the host reads back the measurement status and error count.
Continuous Mode: Can be used for longer measurements but with less precision in
the time interval.
In continuous mode, the host controls the starts and stops of the PRBS error
checking operation then reads back the measurement status and error count.
Note: When working with the PRBS Checker, please note the following.
•
The parameters referred to in Section 4.4.1 to Section 4.4.2 are briefly described and
linked to their respective registers in Table 4-4. For a complete list of registers and
functions, please see Section 5.
•
The PRBS generator and checker can be active at the same time, however, the
generator can not be looped back on itself for error checking.
4.4.1 Timed PRBS Check Measurement Procedure
For applications where measurement times are ~3.34s or less, the timed PRBS check
mode is the most suitable. Alternatively, to achieve precise timing for lower BER signals,
the timed PRBS check measurement can be repeated by the host and the total
measurement time and error count is determined by summing the individual
measurements.
In timed mode, the host sets the total measurement time by setting the
CFG_PRBS_CHECK_PREDIVIDER and the CFG_PRBS_CHECK_MEAS_TIME
parameters to the required values to achieve the total measurement time required by
the application.
To perform a timed PRBS measurement, please complete the following steps:
1. Set the appropriate settings within CFG_PRBS_CHECK_PREDIVIDER and
CFG_PRBS_CHECK_MEAS_TIME to achieve the total measurement time required
by the application. The TMT (total measurement time) is determined by the
following equation:
TMT = CFG_PRBS_CHECK_PREDIVIDER * (CFG_PRBS_CHECK_MEAS_TIME
*256+1) * (1/40MHz)
Note: Using the default CFG_PRBS_CHECK_PREDIVIDER setting of 0 (pre-divider
= 4) and CFG_PRBS_CHECK_MEAS_TIME setting of 3 (MEAS_TIME = 3), the TMT
(total measurement time) is ~77μs per measurement.
2. Follow the steps outlined in Figure 4-3: Timed PRBS Check Flow.
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4.4.2 Continuous PRBS Check Measurement Procedure
As previously mentioned, the maximum measurement time for a timed PRBS error
measurement is ~3.35 seconds. For links with very low error rates, this time is insufficient
to capture an adequate number of errors. For these situations, the continuous PRBS
check measurement is more appropriate.
In continuous PRBS measurement mode, the measurement can run as long as required
(assuming the device remains locked) to ensure the BER test level is met.
To perform a continuous PRBS measurement, please follow the steps outlined in the
flowchart found within Figure 4-4: Continuous PRBS Check Flow.
Table 4-4: PRBS Checker Parameter Description
Register Address
and Name
h
Parameter Name
Description
CFG_PRBS_CHECK_PREDIVIDER
CFG_PRBS_CHECK_MEAS_TIME
Selects pre-divider for PRBS check measurement timer.
50,
Selects PRBS check measurement interval for timed
measurements.
PRBS_ CHK_CFG
Selects between timed and continuous type PRBS
measurement.
CTRL_PRBS_CHECK_TIMED_CONT_B
TRL_PRBS_CHECK_START
51,
PRBS_CHK_ CTRL
Used to start and stop PRBS measurements.
PRBS error count storage location.
89,
STAT_PRBS_CHK_ERR_CNT
PRBS_ CHK_ ERR_CNT
STAT_PRBS_CHECK_STATUS
Status indication of PRBS checker.
8A,
PRBS_ CHK_STATUS
STAT_PRBS_CHECK_LAST_ABORT
Indication bit for PRBS successful completion or abort.
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Note:
The host must not change ctrl_prbs_check_start
during a PRBS timed check except as described in
this diagram. There is no capability for the host to
abort a timed PRBS check once requested.
In particular, after setting ctrl_prbs_check_start to
1 for a timed check, the host is not permitted to
write ctrl_prbs_check_start back to 0 until the
device sets stat_prbs_check_status to 2 or 3
indicating completion or abort. Behaviour is
undefined if it does so; it would lead to race
conditions in the host <-> device handshake.
Start Timed PRBS Check Measurement
Host sets
CTRL_PRBS_CHECK_TIMED_CONT_B = 1
CTRL_PRBS_CHECK_START = 1
Device clears error count
And attempts to start PRBS
checker based on lock
condition of device
Device Sets
STAT_PRBS_CHK_ERR_CNT = 0
Loss of lock occurred during measurement
or at the beginning of measurement
initiation. Error count is invalid
Resets PRBS
checker.
STAT_PRBS_CHECK_STATUS
= 3
Host sets
CTRL_PRBS_CHECK_START = 0
YES
YES
Prepares device
for next
operation
NO
NO
Device Sets
STAT_PRBS_CHECK_STATUS =
0
STAT_PRBS_CHECK_STATUS
= 1
YES
PRBS Checker is ready for new
operation
NO
Status indicates that
timer Expired, PRBS
Timed Measurement
Complete
NO
STAT_PRBS_CHECK_STATUS
= 2
Resets PRBS
checker.
YES
Host sets
CTRL_PRBS_CHECK_START = 0
NO
STAT_PRBS_CHECK_STATUS
= 0
YES
PRBS Error Check Completed
Successfully
User reads Error count from
STAT_PRBS_CHK_ERR_CNT
Figure 4-3: Timed PRBS Check Flow
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Start Continuous PRBS Check
Measurement
Device clears error count
And attempts to start PRBS
checker based on lock
condition of device
Host sets
CTRL_PRBS_CHECK_TIMED_CONT_B = 0
CTRL_PRBS_CHECK_START = 1
Device Sets
STAT_PRBS_CHK_ERR_CNT = 0
Loss of lock occurred during
measurement or at the
beginning of measurement
initiation. Error count is invalid
Resets PRBS
checker.
STAT_PRBS_CHECK_STATUS
= 3
Host sets
CTRL_PRBS_CHECK_START = 0
YES
Prepares device
for next
operation
NO
Device Sets
STAT_PRBS_CHECK_STATUS =
0
STAT_PRBS_CHECK_STATUS
= 1
NO
YES
NO
Host may terminate PRBS
measurement at anytime
by completing this action.
PRBS Checker is ready for new
operation
Host sets
CTRL_PRBS_CHECK_START
=0
YES
YES
NO
STAT_PRBS_CHECK_STATUS
= 0
YES
STAT_PRBS_CHECK_LAST_ABORT
= 1
This step is to ensure that an error did
not occur between ending the PRBS
measurement and the last polling of
STAT_PRBS_CHECK_STATUS.
NO
PRBS Error Check Completed
Successfully
User reads Error count from
STAT_PRBS_CHK_ERR_CNT
Figure 4-4: Continuous PRBS Check Flow
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4.5 EYE Monitor
The GS12281 includes an integrated eye monitor, which can scan the equalized signal
from the trace equalizer input block. The eye monitor is capable of performing a full
128h x 256v matrix-scan or simply a 4 coordinate shape-scan of the equalized signal
(See Figure 4-5).
Note: If the eye monitor will be used during normal operation of the device (cable driver
mission mode), the user must ensure that the Device Power-up Sequence in
Section 4.9.12 is completed to prevent temporary signal disturbance when enabling the
eye monitor.
Figure 4-5: Full Matrix Scan (left) and 4-Point Shape Scan (right)
The eye monitor is highly configurable, and the host can configure the offset, resolution,
sample time, and error threshold parameters to control the depth and execution time of
the scan. The EYE monitor scans the signal from the trace equalizer block. Similar to the
PRBS Checker, the eye monitor is controlled through a 4-way handshake mechanism.
The following sections outline the scan parameters and procedure to configure the eye
scan area, error threshold, and run a shape or full scan.
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4.5.1 Shape Scan and Measurement Time
0
Max Horizontal Scan Resolution
Default
128
Vertical
Offset
Start
Vertical Offset Step = 1
Phase Step = 1
Vertical
Offset Start
Vertical
Offset Stop
Phase Start
Phase Stop
Vertical Offset Step = 2
Phase Step = 1
Default
Vertical
Offset
Stop
255
0
127
Default
Default
Phase
Start
Phase
Stop
Vertical Offset Step = 4
Phase Step = 4
Figure 4-6: Eye Scan Matrix Parameters
Figure 4-6 shows a visual representation of the scan matrix and indicates the spatial
parameters that determine the scan area and resolution. Running a scan using the
default offset and step parameters, results in 32768 (128x256) samples. The number of
samples and thus, the total scan time can be reduced to meet the needs of the
application. The scan area can be reduced by reducing the span determined by the
vertical and phase start and stop offsets, or the resolution can be reduced by increasing
the step size between adjacent samples. On the right in Figure 4-6, there are three step
settings used as examples, however there are a total of nine combinations possible. See
Table 4-5 for the register addresses and parameter names of the spatial eye scan
parameters.
For example, by increasing the vertical and phase step size to 4, the resolution is
2
reduced to (1/4) , thus reducing the number of samples down to 2048 (32768x1/16).
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The vertical and horizontal scan information is useful when adjusting pre-emphasis and
equalization of a link. However, once this is accomplished, it may be sufficient to use the
eye scanner to only monitor jitter by setting the offsets to simply slice the eye at the
centre offset position, thus obtaining a simple 128 sample horizontal scan. A horizontal
eye can be configured to run in just over a millisecond.
In addition to the spatial parameters, the sample time, and thus the bit error rate
resolution for the eye scan can be adjusted; longer scans can detect finer bit error rates.
However, this proportionally increases the total scan time. The sample time in
microseconds is determined by a 32-bit time-out value split across two 16 bit registers.
See Table 4-6 for the register addresses and parameter names of the time-out eye scan
parameters.
For example, using the default spatial and temporal measurement scan parameters, the
scan time is approximately 6.6 seconds (32768 x 2 x100μs). However, by changing the
vertical and horizontal step size to 4, the scan time can be reduced to 400ms
(2048x2x100ꢁs).
The error count information can be used as is to determine the minimum inner contour
based on the measurement time. However, the basic data can be post processed to
determine things like error rate, and error threshold.
The following equations provide guidance for user post-processing:
Equation 4-1
Equation 4-2
Equation 4-3
sample1error1count
error1rate = -------------------------------------------------------------
sample1time
Contour maps can be created by defining error rate thresholds, and grouping sampled
points that fall between thresholds.
For example:
sample1time
sample1time
-----------------------------------------------------------------------
-----------------------------------------------------------------------
sample1error1threshold
error1rate1threshold11
error1rate1threshold12
Some sampling scopes provide eye maps with BER contours; similar limited BER contour
approximations can be obtained from the eye scan by using BER threshold groups.
For example:
sample1time1x1data1rate
error1rate1threshold11
sample1time1x1data1rate
error1rate1threshold12
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
sample1error1threshold
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Table 4-5: Spatial Scan Configuration Parameters
Register Address and Name
Parameter Name
Description
h
CTRL_EYE_PHASE_START
Horizontal phase start index
Horizontal phase stop index
Horizontal phase step size
Vertical offset start index
Vertical offset stop index
Vertical offset step size
5A,
EYE_MON_ SCAN_CTRL_0
CTRL_EYE_PHASE_STOP
CTRL_EYE_PHASE_STEP
5B,
EYE_MON_ SCAN_CTRL_1
CTRL_EYE_VERT_OFFSET_START
CTRL_EYE_VERT_OFFSET_STOP
CTRL_EYE_VERT_OFFSET_STEP
5C,
EYE_MON_ SCAN_CTRL_2
The next section describes the implementation of the matrix-scan and shape-scan.
4.5.2 Matrix-Scan and Shape-Scan Operation
The previous section described the parameters used to adjust the spatial and temporal
eye scan settings. Each sample of the eye scan can record up to 65536 errors. A full eye
scan would require 64KB (256 x 128 x 2 Bytes) of memory to store the data of a full scan.
The eye monitor was implemented to use device resources more efficiently by
segmenting a full scan into several partial scan segments. Each partial scans segment
can contain up to 512B of scan data.
In the case of a full matrix-scan, there are 128 partial scan segments and each partial
scan segment contains two complete scan lines (2 x 128 x 2B = 512B). In the case of a
partial matrix-scan, each scan segment contains multiple partial scan lines including
partial lines (see Figure 4-7).
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1st Partial Scan
Error Count = Max
0 <Error Count < Max
Error Count = 0
1st Partial Scan
1st
1 st
Vertical Offset Start
2nd
2nd
2nd
2nd
...
...
...
...
Last
Last
Vertical Offset Stop
128th Partial Scan
Phase Start
Phase Stop
Figure 4-7: Full Matrix Scan (left) and Partial Matrix Scan (right)
Figure 4-7 illustrates an example of an eye scan, where the sampled eye data is not
centred within the scan matrix. The eye scan data has an arbitrary centre phase relative
to the centre of the matrix which is determined when the eye monitor is powered up.
While the eye monitor remains powered, subsequent scans will maintain the same
relative phase allowing for consecutive scans to be compared for changes.
Although the scan data is not centred, a simple algorithm can be applied to the data to
shift the eye data and extract the relevant information.
In addition to the matrix-scan, the eye monitor includes a built-in function called a
shape-scan. The shape-scan returns four coordinates corresponding to the horizontal
and vertical extremes of the inner eye (See Figure 4-8).
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Error Count = Max
> error count threshold
Error Count = 0
Positive Edge
(PE)
Right Edge
(RE)
Left Edge
(LE)
Negative Edge
(NE)
Figure 4-8: 4-Point Scan Coordinates Relative to the Eye
The four points obtained from the shape-scan can be used to quickly and easily
calculate the eye height and width of the signal eye. The shape-scan alone will most
likely meet the signal analysis requirements of most applications. Alternatively, the
coordinates obtained from the shape-scan can be used to optimize the bounds of a
partial matrix-scan. The four points returned from the shape-scan are determined by the
error rate threshold set by the error threshold parameter and the time-out parameters
previously discussed.
Table 4-6: Time-out Eye Scan Parameters
Register Address and Name
Parameter Name
Description
h
56,
CFG_EYE_BER_THRESHOLD
Number of sample errors to determine fail
EYE_MON_ INT_CFG_2
54,
CFG_EYE_MON_TIMEOUT_MS
CFG_EYE_MON_TIMEOUT_LS
MSB of measurement time in microseconds
LSB of measurement time in microseconds
EYE_MON_ INT_CFG_0
55,
EYE_MON_ INT_CFG_1
This section provides a step-by-step procedure to run a matrix and shape-scan. The
shape-scan procedure is described first.
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Shape-Scan Procedure:
1. Ensure the offset and step parameters described in Table 4-5 are set to their default
values.
2. Configure the 4-point error rate threshold by setting each of the parameters listed
in Table 4-6.
3. Configure the eye monitor to run a shape-scan by setting
CTRL_EYE_SHAPE_SCAN_B to 1.
Start the scan and poll the scanner status register until the scan is complete. Please refer
to the flow diagram in Figure 4-9.
Please Note the Following:
Status = STAT_EYE_MON_STATUS
Run Shape Scan
Host powers up eye monitor and starts
Shape Scan by setting:
CTRL_EYE_MON_POWER_CTRL = 1
CTRL_EYE_MON_START = 1
Note: the host can write
ctrl_eye_mon_power_ctrl = 1 and
ctrl_eye_mon_start = 1 in the
same GSPI write, i.e. at the same
time. It is not necessary to set the
power up first.
Host reads scan status from
STAT_EYE_MON_STATUS
3
1 or 0
Status
2
Host determines Eye Width and Eye Height by reading from
the following 4 registers:
le = STAT_EYE_SHAPE_LEFT_EDGE_PHASE
re = STAT_EYE_SHAPE_RIGHT_EDGE_PHASE
pe =STAT_EYE_SHAPE_POS_EDGE_OFFSET
ne =STAT_EYE_SHAPE_NEG_EDGE_OFFSET
if pe > ne:
Scan Failed
Reset Eye Scanner
EyeHeight = (256 + ne - pe)
else:
EyeHeight = (ne - pe)
if le > re:
EyeWidtht = (128 + re - le)
else:
EyeWidtht = (re - le)
Host Resets Eye Scanner for new scan by
setting CTRL_EYE_MON_START = 0
Or power down by setting
CTRL_EYE_MON_POWER_CTRL = 0
NO
Status = 0?
Shape Scan
Complete
Figure 4-9: Shape-Scan Flow Diagram
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Matrix-Scan Procedure:
1. Set the bounds of the matrix-scan with the offset and step parameters described in
Table 4-5. The default value results in a full matrix-scan. Alternatively, the
shape-scan can be executed and the coordinates returned can be used to minimize
the scan time and data size of the scan.
2. Configure the 4-point error rate threshold by setting each of the parameters listed
in Table 4-6.
3. Configure the eye monitor to run a matrix-scan by setting
CTRL_EYE_SHAPE_SCAN_B to 0.
4. Start the scan and poll the scanner status register until the scan is complete. Please
refer to the flow diagram in Figure 4-10.
Read Eye Scan Buffer Procedure:
1. Host reads image size from STAT_EYE_IMAGE_SIZE.
Note: The matrix-scan is composed of multiple partial scan segments. The size (in
Bytes) of the last partial scan segment is stored in STAT_EYE_IMAGE_SIZE.
2. Host reads scan buffer data from register 0x6CC1 to (0x6CC1 + (size read from
STAT_EYE_IMAGE_SIZE)/2).
Address 0x6CC1 is the first header word corresponding to the last vertical offset
position in the matrix that was read.
Address 0x6CC2 is the second header word corresponding to the image size.
This value is a copy of the image size that was read from
STAT_EYE_IMAGE_SIZE.
Address 0x6CC3 to (0x6CC1 + (size read from STAT_EYE_IMAGE_SIZE)/2) is the
eye scan data.
The image data is 2 bytes per sample point.
Making reference to the Matrix shown in Figure 4-6, the eye scan data
starting at 0x6CC3 is stored in order from left to right, top to bottom, from
the last stored vertical/horizontal position in the matrix.
The number of samples contained in the scan buffer is equal to (size read from
STAT_EYE_IMAGE_SIZE - 4)/2.
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Please Note the Following:
Run Scan
- Status = STAT_EYE_MON_STATUS
- Partial = STAT_EYE_SCAN_PARTIAL_OR_FULL
YES
Status = 0?
Host powers up eye monitor and starts
Matrix Scan by setting:
CTRL_EYE_MON_POWER_CTRL = 1
CTRL_EYE_MON_START = 1
Note: the host can write
ctrl_eye_mon_power_ctrl = 1 and
ctrl_eye_mon_start = 1 in the
same GSPI write, i.e. at the same
time. It is not necessary to set the
power up first.
NO
Host reads scan status from
STAT_EYE_MON_STATUS
3
1 or 0
status
2
Host preforms
Read Buffer
Scan
Host Resets Eye Scanner for
new scan by setting
CTRL_EYE_MON_START = 0
Scan Failed
Reset Eye Scanner
Eye Scan
Data
Procedure
NO
Partial = 1?
YES
Host Resets Eye Scanner fornew scan by
setting CTRL_EYE_MON_START = 0
Or power down by setting
CTRL_EYE_MON_POWER_CTRL = 0
NO
Status = 0?
Full Eye Scan
Complete
Figure 4-10: Matrix-Scan Flow Diagram
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4.6 PRBS Generator
The GS12281 includes an integrated PRBS generator which can produce a differential
PRBS7 or a divided clock signal on either output for system testing.
Note: When working with the PRBS Generator, please note the following.
•
•
•
The PRBS generator and checker can be active at the same time, however, the
generator can not be looped back on itself for error checking.
If the application requires adjustments to the default output swing, please see
Section 4.7.4.
The parameters referred to within this section are linked to their respective
registers in Table 4-7. For a complete list of registers and functions, please see
Section 5.
To configure the PRBS generator for use, please see the following steps:
1. Select the PRBS generator as the source on the appropriate output:
To switch SDO0/SDO0 from data mode to PRBS generator mode, set
CTRL_OUTPUT0_SIGNAL_SEL = 1
To switch SDO1/SDO1 from data mode to PRBS generator mode, set
CTRL_OUTPUT1_SIGNAL_SEL = 1
2. The default device settings are configured to power-down the device on loss of
input signal. If the PRBS generator is to be used without a valid input signal, then
the following automatic setting parameters must be disabled. This must be done to
ensure device is powered up and the outputs are active for the PRBS generator.
The following settings are required for PRBS generator on either output:
CTRL_AUTO_SLEEP = 0
CTRL_MANUAL_SLEEP = 0
The following settings are required when SDO1/SDO1 is selected as PRBS
output:
CTRL_OUTPUT1_AUTO_MUTE = 0
CTRL_OUTPUT1_MANUAL_MUTE = 0
CTRL_OUTPUT1_AUTO_DISABLE = 0
CTRL_OUTPUT1_MANUAL_DISABLE = 0
CTRL_OUTPUT1_AUTO_SLEW = 0
The following settings are required when SDO0/SDO0 is selected as PRBS
output:
CTRL_OUTPUT0_AUTO_MUTE = 0
CTRL_OUTPUT0_MANUAL_MUTE = 0
CTRL_OUTPUT0_AUTO_DISABLE = 0
CTRL_OUTPUT0_MANUAL_DISABLE = 0
CTRL_OUTPUT0_AUTO_SLEW = 0
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Manually set the appropriate slew rate in CTRL_OUTPUT<n>_MANUAL_SLEW
for the rate to be selected in CTRL_PRBS_GEN_DATA_RATE
0 for SD and MADI
1 for HD and 3G
2 for 6G and 12G
Note: The <n> in the control parameter names refers to the output number.
Where output 0 is the cable driver output SDO1/SDO1 and output 1 is the cable
driver output SDO1/SDO1.
3. Set the values within the following parameters which meet the needs of the
application:
CTRL_PRBS_GEN_SIGNAL_SELECT
CTRL_PRBS_GEN_CLK_SRC
CTRL_PRBS_GEN_DATA_RATE
Note: If CTRL_PRBS_GEN_CLK_SRC was set to CDR recovered clock a valid
signal that the CDR has locked to must be present for proper operation, and
the PRBS generator will match this data rate regardless of what rate
CTRL_PRBS_GEN_DATA_RATE is set to.
CTRL_PRBS_GEN_CLK_DIVIDER
CTRL_PRBS_GEN_INVERT
4. Start the generator by setting CTRL_PRBS_GEN_ENABLE = 1.
To stop the generator at any time, set CTRL_PRBS_GEN_ENABLE = 0. If the use of the
PRBS generator is complete, revert any settings made in steps 1 and 2 to return to
normal operation.
Table 4-7: PRBS Generator Parameter Descriptions
Register Address
and Name
h
Parameter Name
Description
CTRL_AUTO_SLEEP
Set the device to auto or manual sleep.
3,
Manually set the sleep setting of the device when auto
sleep mode is turned off.
CONTROL_ SLEEP
CTRL_MANUAL_SLEEP
Selects between data or PRBS generator as the driver
source for SDO1/SDO1.
CTRL_OUTPUT1_SIGNAL_SEL
CTRL_OUTPUT0_SIGNAL_SEL
CTRL_OUTPUT1_AUTO_MUTE
CTRL_OUTPUT1_MANUAL_MUTE
CTRL_OUTPUT0_AUTO_MUTE
CTRL_OUTPUT0_MANUAL_MUTE
48,
OUTPUT_ SIG_SELECT
Selects between data or PRBS generator as the driver
source for SDO0/SDO0.
Select automatic or manual mute control for
SDO1/SDO1.
Manually set the mute control for SDO1/SDO1 when
auto mute mode is turned off.
49,
CONTROL_ OUTPUT_
MUTE
Select automatic or manual mute control for
SDO0/SDO0.
Manually set the mute control of the SDO0/SDO0 when
auto mute mode is turned off.
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Table 4-7: PRBS Generator Parameter Descriptions (Continued)
Register Address
and Name
h
Parameter Name
Description
Selects automatic or manual disable control for
SDO1/SDO1.
CTRL_OUTPUT1_AUTO_DISABLE
CTRL_OUTPUT1_MANUAL_DISABLE
CTRL_OUTPUT0_AUTO_DISABLE
CTRL_OUTPUT0_MANUAL_DISABLE
CTRL_OUTPUT0_AUTO_SLEW
Manually set the disable control of the SDO1/SDO1
when auto disable mode is turned off.
4A,
CONTROL_ OUTPUT_
DISABLE
Selects automatic or manual disable control for
SDO0/SDO0.
Manually set the disable control of the SDO0/SDO0
when auto disable mode is turned off.
Selects auto or manual slew rate selection for
SDO0/SDO0.
Manually set the slew rate for SDO0/SDO0 when auto
slew mode is turned off.
CTRL_OUTPUT0_MANUAL_SLEW
CTRL_OUTPUT1_AUTO_SLEW
4B,
CONTROL_ OUTPUT_
SLEW
Selects auto or manual slew rate selection for
SDO1/SDO1.
Manually set the slew rate for SDO1/SDO1 when auto
slew mode is turned off.
CTRL_OUTPUT1_MANUAL_SLEW
Selects between setting the output of the PRBS
generator to being a clock or a PRBS test signal.
CTRL_PRBS_GEN_SIGNAL_SELECT
CTRL_PRBS_GEN_CLK_SRC
CTRL_PRBS_GEN_CLK_DIVIDER
CTRL_PRBS_GEN_INVERT
Selects the clock source used by the PRBS generator.
If a clock is selected as the PRBS output signal, this
parameter sets the divide ratio of the clock.
52,
PRBS_GEN_ CTRL
Allows the polarity of the PRBS signal to be inverted.
If a PRBS test signal is selected as the output signal, this
parameter sets the data rate of the PRBS7 signal.
CTRL_PRBS_GEN_DATA_RATE
CTRL_PRBS_GEN_ENABLE
Used to enable or disable the PRBS generator.
4.7 Output Drivers
The GS12281 features two independently configurable output drivers (see Figure 3-2),
with data (re-timed or bypassed) available on both outputs. The two drivers provide
highly configurable amplitude and pre-emphasis control. The signal on the outputs can
be inverted to help with signal polarity when layout requires trace inversion. The PRBS
generator is available on both outputs. The LOS (Loss of Signal) status from the equalizer
stage can be used to automatically mute or disable the outputs on their assertion. The
Loss of Lock status from the CDR block can be used to mute the outputs. The cable
drivers can be configured to mute or disable during sleep. The sleep control modes
takes precedence over the manual or automatic LOS and Loss of Lock output control
modes.
Note: The <n> in the control parameter names refers to the output number. Output 0 is
the cable driver output SDO0/SDO0 and output 1 is the cable driver output SDO1/SDO1.
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4.7.1 Bypassed Re-timer Signal Output Control
With the default power-up settings, the GS12281 outputs will automatically switch to
the bypassed signal (non-re-timed) whenever the PLL is unlocked. Alternatively, manual
re-timer bypass may be configured by setting the CTRL_OUTPUT<n>_RETIMER_
AUTO_BYPASS and CTRL_OUTPUT<n>_RETIMER_MANUAL_BYPASS parameters in
register 0x4C to 0 and 1 respectively via the host interface, in which case the PLL will
b
b
remain bypassed for all rates.
The re-timer bypass function, manual or automatic, does not affect the input
equalization function of the device.
If both outputs are manually disabled, then the device will power down the CDR block
and features of the re-timer such as rate detect and lock detect will no longer be
accessible in this mode.
4.7.2 Output Driver Polarity Inversion
While in data mode, the signal polarity may be inverted at the outputs through the
CTRL_OUTPUT<n>_ DATA_ INVERT parameters in register 0x48. This may be useful to
compensate for an inverted upstream signal or to facilitate board signal routing. To
invert the polarity of either of the two output drivers, write 1 to control parameter
b
CTRL_OUTPUT<n>_DATA_ INVERT.
4.7.3 Output Driver Data Rate Selection
By default, the GS12281 uses the output driver and slew rate group settings for the data
rate to which the CDR is locked.
When the CDR is unlocked it will use the 6G/12G rate group:
CFG_OUTPUT<n>_CD_UHD_DRIVER_SWING
CFG_OUTPUT<n>_CD_UHD_PREEMPH_WIDTH
CFG_OUTPUT<n>_CD_UHD_PREEMPH_AMPL
CFG_OUTPUT<n>_CD_UHD_PREEMPH_PWRDWN
If required, manual selection of the output driver and slew rate group is possible using
the following steps:
1. Set CTRL_OUTPUT<n>_AUTO_SLEW = 0
2. Set CTRL_OUTPUT<n>_MANUAL_SLEW to the desired rate group. The slew rate
options are as follows:
0 = SD/MADI
1 = HD/3G
2 = 6G/12G
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4.7.4 Amplitude and Pre-Emphasis Control
The two output drivers offer very granular amplitude and pre-emphasis control. For
optimal loss compensation, both the pre-emphasis pulse amplitude and the
pre-emphasis pulse width can be independently configured on both output drivers.
This extra flexibility provides a mechanism to better shape the pre-emphasis gain to
match the frequency loss response of interconnect composed of trace, connector and
via losses. The swing and pre-emphasis can be independently configured for specific
data rates.
Note: The parameters referred to within this section are linked to their respective
registers in Table 4-8. For a complete list of registers and functions, please see Section 5.
The output swing can be configured for the following three rate groups:
CFG_OUTPUT<n>_CD_SD_DRIVER_SWING (MADI and SD)
CFG_OUTPUT<n>_CD_HD_DRIVER_SWING (HD and 3G)
CFG_OUTPUT<n>_CD_UHD_DRIVER_SWING (6G and 12G)
The output pre-emphasis can be configured for the following two rate groups:
CFG_OUTPUT<n>_CD_HD_PREEMPH_WIDTH (HD and 3G)
CFG_OUTPUT<n>_CD_HD_PREEMPH_AMPL (HD and 3G)
CFG_OUTPUT<n>_CD_UHD_PREEMPH_WIDTH (6G and 12G)
CFG_OUTPUT<n>_CD_UHD_PREEMPH_AMPL (6G and 12G)
The output driver swing and pre-emphasis will use the rate specific swing configuration
when the CDR is locked to that rate. The default swing setting is ~800mVpp single
ended into an external 75Ω load, and is adjustable in each of the output swing
parameters listed above. Applications where maximum output swing and pre-emphasis
range are desired, it is recommended that the output supplies VCCO_0 and VCCO_1 be
connected to a 3.3V supply. For most applications with short trace between GS12281
and output BNC, 2.5V power supply can be used.
4.7.4.1 Pre-Emphasis Optimization
The goal of pre-emphasis is to open the eye at the downstream receiver as much as
possible. This means minimizing ISI jitter while meeting sufficient inner eye amplitude
to meet a receiver's input sensitivity. The cable driver has the additional requirement to
meet the SMPTE output specification.
The GS12281 has a high level of precision for pre-emphasis control, which allows for fine
optimization of any loss channel. The default cable driver settings should meet SMPTE
output specification for most applications with short (1 to 2 inch) trace between the
GS12281 and the output BNC. However, the pre-emphasis values may be adjusted to
produce a better-looking eye. It is difficult to provide guidance regarding dB, as a 12G
eye diagram looks different depending on the video test equipment used. The designer
must optimize for their targets.
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Table 4-8: Output Swing and Pre-Emphasis Control Parameters
Register Address
and Name
h
Parameter Name
Description
2B/29,
OUTPUT_ PARAM_CD_
SD_3/
OUTPUT_ PARAM_CD_
SD_1
Output amplitude configuration parameter.
CFG_OUTPUT<n>_CD_
SD_DRIVER_SWING
<n> = 0: For SD and MADI rates on SDO0.
<n> = 1: For SD and MADI rates on SDO1.
2D/2F
OUTPUT_ PARAM_
CD_HD_1/
OUTPUT_ PARAM_
CD_HD_3
Output amplitude configuration parameter.
CFG_OUTPUT<n>_CD_
HD_DRIVER_SWING
<n> = 0: For HD and 3G rates on SDO0.
<n> = 1: For HD and 3G rates on SDO1.
Output pre-emphasis pulse width configuration parameter.
CFG_OUTPUT<n>_CD_HD_
PREEMPH_WIDTH
<n> = 0: For HD and 3G rates on SDO0.
<n> = 1: For HD and 3G rates on SDO1.
2C/2E
OUTPUT_ PARAM_
CD_HD_0/
OUTPUT_ PARAM_
CD_HD_2
Output pre-emphasis power down configuration parameter.
CFG_OUTPUT<n>_CD_HD_
PREEMPH_PWRDWN
<n> = 0: For HD and 3G rates on SDO0.
<n> = 1: For HD and 3G rates on SDO1.
Output pre-emphasis pulse amplitude configuration parameter.
CFG_OUTPUT<n>_CD_HD_
PREEMPH_AMPL
<n> = 0: For HD and 3G rates on SDO0.
<n> = 1: For HD and 3G rates on SDO1.
31/33
OUTPUT_ PARAM_
CD_UHD_1/
OUTPUT_ PARAM_
CD_UHD_3
Output amplitude configuration parameter.
CFG_OUTPUT<n>_CD_UHD_
DRIVER_SWING
<n> = 0: For 6G and 12G rates on SDO0.
<n> = 1: For 6G and 12G rates on SDO1.
Output pre-emphasis pulse width configuration parameter.
CFG_OUTPUT<n>_CD_UHD_
PREEMPH_WIDTH
<n> = 0: For 6G and 12G rates on SDO0.
<n> = 1: For 6G and 12G rates on SDO1.
30/32
OUTPUT_ PARAM_
CD_UHD_0/
OUTPUT_ PARAM_
CD_UHD_2
Output pre-emphasis power down configuration parameter.
CFG_OUTPUT<n>_CD_UHD_
PREEMPH_PWRDWN
<n> = 0: For 6G and 12G rates on SDO0.
<n> = 1: For 6G and 12G rates on SDO1.
Output pre-emphasis pulse amplitude configuration parameter.
CFG_OUTPUT<n>_CD_UHD_
PREEMPH_AMPL
<n> = 0: For 6G and 12G rates on SDO0.
<n> = 1: For 6G and 12G rates on SDO1.
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4.7.5 Output State Control Modes
The GS12281 provides several output state control modes to meet specific application
requirements. The cable driver has the following three output modes: operational,
muted, disabled, or balanced. During non-sleep, if the control modes are configured
such that multiple output modes are enabled, the priorities of the control modes from
highest to lowest are the following: balanced, disabled, and then muted.Section 4.7.5.1
through Section 4.7.5.3 describe how to configure the output control modes that are
enabled during non-sleep. If the device enters sleep, either manually or automatically,
the sleep output control modes take precedence over the non-sleep control modes. The
default cable driver configuration is for it to be disabled during sleep; however the cable
driver can be configured to mute during sleep by setting the
CFG_SLEEP_OUTPUT<n>_MUTE parameter in register 0x5 to 1 .
b
4.7.5.1 Output Mute Control Mode
Each of the outputs on the GS12281 have independent mute control modes, which can
be configured through the host interface.
The following are the four output mute control modes:
1. The outputs automatically mute on LOS (default).
2. The outputs automatically mute on LOS and during rate search.
3. The outputs never mute.
4. The outputs are always muted.
The first mute control mode is the default power-up configuration for both output
drivers (the CTRL_OUTPUT<n>_AUTO_MUTE control parameter in register 0x49 is set
to 1 ). In this mode, the outputs will automatically mute on the assertion of LOS. In
b
addition to mute on LOS, with auto mute control mode configured, setting the
CTRL_OUTPUT<n>_AUTO_MUTE_DURING_RATE_SEARCH control parameter in
register 0x49 to 1 , will configure the outputs to also mute when the device loses lock
b
and begins to rate search.
The outputs can be manually configured to never mute by setting both the
CTRL_OUTPUT<n>_AUTO_MUTE and CTRL_OUTPUT<n>_MANUAL_MUTE control
parameters in register 0x49 to 0 . Alternatively, the outputs can be manually configured
b
to always be muted by setting the CTRL_OUTPUT<n>_AUTO_MUTE and
CTRL_OUTPUT<n>_ MANUAL_MUTE control parameters to 0 and 1 respectively.
b
b
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4.7.5.2 Output Disable Control Mode
Each of the outputs on the GS12281 also have independent disable control modes,
which can be configured through the host interface.
The following are the three output disable control modes:
1. The outputs are never disabled (default).
2. The outputs are automatically disabled on LOS.
3. The outputs are always disabled.
The first disable control mode is the default power-up configuration for both output
drivers (the CTRL_OUTPUT<n>_AUTO_DISABLE and
CTRL_OUTPUT<n>_MANUAL_DISABLE control parameters in register 0x4A are both
set to 0 ). In this mode, the outputs will never disable. By setting the
b
CTRL_OUTPUT<n>_AUTO_DISABLE control parameter in register 0x4A to 1 , the
b
outputs will automatically disable on the assertion of LOS.
The output can be manually disabled by leaving the
CTRL_OUTPUT<n>_AUTO_DISABLE control parameter set to 0 and setting the
b
CTRL_OUTPUT<n>_MANUAL_DISABLE control parameter to 1 .
b
The disable control mode takes precedence over the output mute control mode.
4.7.5.3 Output Balanced Control Mode
The GS12281 has a feature designed to facilitate reliable Output Return Loss (ORL)
measurement while the device is still powered. The device can be put into a BALANCE
mode which prevents the outputs from toggling while ORL is being measured.
BALANCE mode can be enabled through the host interface, by setting control
parameter CTRL_OUTPUT<n>_ BALANCED in register 4D to 1 . This control mode
b
takes precedence over both the output mute and output disable control modes.
4.8 GPIO Controls
There are four configurable GPIO pins which can independently be configured as inputs
or outputs. Each GPIO has a default function which can be re-configured through the
host interface.
If there is a conflict between the internal register configuration of a given device
function and the logic-level applied to a GPIO pin that is configured to control that same
device function, the GPIO logic-level takes precedence over the internal register
configuration. The logic HIGH and LOW levels of the GPIO[3:0] pin to which LOS is
connected are specified by the EIA/JESD8-5A standard for 1.8V operation.
For a list of available functions and configuration details of GPIO[3:0], please refer to the
GPIO Configuration registers in Section 5.
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4.9 GSPI Host Interface
The GS12281 is configured via the Gennum Serial Peripheral Interface (GSPI).
The GSPI host interface is comprised of a serial data input signal (SDIN pin), serial data
output signal (SDOUT pin), an active-LOW chip select (CS pin) and a burst clock (SCLK
pin).
The GS12281 is a slave device, so the SCLK, SDIN and CS signals must be sourced by the
application host processor.
All read and write access to the device is initiated and terminated by the application
host processor.
4.9.1 CS Pin
The Chip Select pin (CS) is an active-LOW signal provided by the host processor to the
GS12281.
The HIGH-to-LOW transition of this pin marks the start of serial communication to the
GS12281.
The LOW-to-HIGH transition of this pin marks the end of serial communication to the
GS12281.
Each device may use its own separate Chip Select signal from the host processor or up
to 32 devices may be connected to a single Chip Select when making use of the Unit
Address feature.
Only those devices whose Unit Address matches the UNIT ADDRESS in GSPI Command
Word 1 will respond to communication from the host processor (unless the B’CAST ALL
bit in GSPI Command Word 1 is set to 1).
4.9.2 SDIN Pin
The SDIN pin is the GSPI serial data input pin of the GS12281.
The 32-bit Command and 16-bit Data Words from the host processor or from the SDOUT
pin of other devices are shifted into the device on the rising edge of SCLK when the CS
pin is LOW.
4.9.3 SDOUT Pin
The SDOUT pin is the GSPI serial data output of the GS12281.
All data transfers out of the GS12281 to the host processor or to the SDIN pin of other
connected devices occur from this pin.
By default at power up or after system reset, the SDOUT pin provides a non-clocked path
directly from the SDIN pin, regardless of the CS pin state, except during the GSPI Data
Word portion for read operations from the device. This allows multiple devices to be
connected in Loop-Through configuration.
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For read operations, the SDOUT pin is used to output data read from an internal
Configuration and Status Register (CSR) when CS is LOW. Data is shifted out of the
device on the falling edge of SCLK, so that it can be read by the host processor or other
downstream connected device on the subsequent SCLK rising edge.
4.9.3.1 GSPI Link Disable Operation
It is possible to disable the direct SDIN to SDOUT (Loop-Through) connection by writing
a value of 1 to the GSPI_LINK_DISABLE bit in CONTROL_REG. When disabled, any data
appearing at the SDIN pin will not appear at the SDOUT pin and the SDOUT pin is HIGH.
Note: Disabling the Loop-Through operation is temporarily required when initializing
the Unit Address for up to 32 connected devices.
The time required to enable/disable the Loop-Through operation from assertion of the
register bit is less than the GSPI configuration command delay as defined by the
parameter t
(4 SCLK cycles).
cmd_GSPI_config
Table 4-9: GSPI_LINK_DISABLE Bit Operation
Bit State
Description
0
1
SDIN pin is looped through to the SDOUT pin
Data appearing at SDIN does not appear at SDOUT, and SDOUT pin is HIGH.
SDIN pin
Configuration and
Status Register
SDOUT pin
GSPI_LINK
_DISABLE
High-Z
BUS_THROUGH_
ENABLE
CS pin
Figure 4-11: GSPI_LINK_DISABLE Operation
4.9.3.2 GSPI Bus-Through Operation
Using GSPI Bus-Through operation, the GS12281 can share a common PCB trace with
other GSPI devices for SDOUT output.
When configured for Bus-Through operation, by setting
GSPI_BUS_THROUGH_ENABLE bit to 1, the SDOUT pin will be high-impedance when
the CS pin is HIGH.
When the CS pin is LOW, the SDOUT pin will be driven and will follow regular read and
write operation as described in Section 4.9.3.
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Multiple chains of GS12281 devices can share a single SDOUT bus connection to host by
configuring the devices for Bus-Through operation. In such configuration, each chain
requires a separate Chip Select (CS).
SDIN pin
Configuration and
Status Register
SDOUT pin
GSPI_LINK
_DISABLE
High-Z
BUS_THROUGH_
ENABLE
CS pin
Figure 4-12: GSPI_BUS_THROUGH_ENABLE Operation
4.9.4 SCLK Pin
The SCLK pin is the GSPI serial data shift clock input to the device, and must be provided
by the host processor.
Serial data is clocked into the GS12281 SDIN pin on the rising edge of SCLK. Serial data
is clocked out of the device from the SDOUT pin on the falling edge of SCLK (read
operation). SCLK is ignored when CS is HIGH.
The maximum interface clock rate is 27MHz.
4.9.5 Command Word 1 Description
All GSPI accesses are a minimum of 48 bits in length (two 16-bit Command Words
followed by a 16-bit Data Word) and the start of each access is indicated by the
HIGH-to-LOW transition of the chip select (CS) pin of the GS12281.
The format of the Command Words and Data Word are shown in Figure 4-13.
Data received immediately following this HIGH-to-LOW transition will be interpreted as
a new Command Word.
4.9.5.1 R/W bit—B15 Command Word 1
This bit indicates a read or write operation.
When R/W is set to 1, a read operation is indicated, and data is read from the register
specified by the ADDRESS field of the Command Word.
When R/W is set to 0, a write operation is indicated, and data is written to the register
specified by the ADDRESS field of the Command Word.
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4.9.5.2 B'CAST ALL—B14 Command Word 1
This bit is used in write operations to configure all devices connected in Loop-Through
and Bus-Through configuration with a single command.
When B’CAST ALL is set to 1, the following Data Word (AUTOINC = 0) or Data Words
(AUTOINC = 1) are written to the register specified by the ADDRESS field of the
Command Words (and subsequent addresses when AUTOINC = 1), regardless of the
setting of the UNIT ADDRESS(es).
When B’CAST ALL is set to 0, a normal write operation is indicated. Only those devices
that have a Unit Address matching the UNIT ADDRESS field of Command Word 1 write
the Data Word to the register specified by the ADDRESS field of the Command Words.
4.9.5.3 EMEM—B13 Command Word 1
The EMEM bit must be set to 1 in Command Word 1. When EMEM is set to 1, a 23-bit
address split between Command Word 1 and Command Word 2 is used to access the
registers in this device.
4.9.5.4 AUTOINC—B12 Command Word 1
When AUTOINC is set to 1, Auto-Increment read or write access is enabled.
In Auto-Increment Mode, the device automatically increments the register address for
each contiguous read or write access, starting from the address defined in the ADDRESS
field of the Command Word.
The internal address is incremented for each 16-bit read or write access until a
LOW-to-HIGH transition on the CS pin is detected.
When AUTOINC is set to 0, single read or write access is required.
Auto-Increment write must not be used to update values in CONTROL_REG.
4.9.5.5 UNIT ADDRESS—B11:B7 Command Word 1
The 5 bits of the UNIT ADDRESS field of the Command Word are used to select one of 32
devices connected on a single chip select in Loop-Through or Bus-Through
configurations.
Read and write accesses are only accepted if the UNIT ADDRESS field matches the
programmed DEV_UNIT_ADDRESS in CONTROL_REG.
By default at power-up or after a device reset, the DEV_UNIT_ADDRESS is set to 00 .
h
4.9.5.6 ADDRESS—B6:B0 Command Word 1 and B15:B0 Command Word 2
The Command and Data Word formats are shown in Figure 4-13 and Figure 4-14. As an
example of the command word structure, reading register 0x90 from a device with unit
address 3, that has AUTOINC = 0, and B’CAST ALL = 0 would be structured as follows:
•
•
Command word 1: 1010 0001 1000 0000 (0xA180)
Command word 2: 0000 0000 1001 0000 (0x90)
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Command Words
MSB
R / W
LSB
UNIT ADDRESS
UA2
ADDRESS[22:16]
A19
B’CAST
ALL
EMEM
A13
AUTOINC
A12
UA4
A11
UA3
A10
UA1
UA0
A22
A6
A21
A5
A20
A4
A18
A2
A17
A1
A16
ADDRESS[15:0]
A8 A7
A15
A14
A9
A3
D3
A0
D0
Data Word
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D2
D1
Figure 4-13: Command and Data Word Format
Command Word 1
MSB
R / W
LSB
UNIT ADDRESS
UA2
ADDRESS[22:16]
A19
B’CAST
ALL
EMEM
AUTOINC
UA4
UA3
UA1
UA0
A22
A21
A20
A18
A17
A16
23-bit CSR address field.
5-bit UNIT ADDRESS field providing up to
32 devices to be connected on a single CS.
Auto increment read/write access when set.
Single read write access when reset.
Extended memory mode. When set, the extended memory mode is
enabled. When reset, normal GSPI addressing is enabled.
When set, the UNIT ADDRESS field is ignored and
all data accesses are actioned by the device.
When reset, the Unit Address is used to
manage data accesses in the device.
Read access when this bit is set.
Write access when this bit is reset.
Command Word 2
ADDRESS[15:0]
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Figure 4-14: Command Word 1 and Command Word 2 Details
Note: Please see Section 4.9.5.6 ADDRESS—B6:B0 Command Word 1 and B15:B0
Command Word 2 for an example of the command word structure.
4.9.6 GSPI Transaction Timing
tcmd_GSPI_config
tcmd
t9
SCLK
CS
X
SDIN
X
SDOUT
t0
t1
t2
t4
t7
SCLK
CSb
t3
t8
R/W
BCST
EMEM
Auto_Inc
UA4
UA3
UA2
UA1
UA0
A22
A21
A20
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
SDIN
SDOUT
R/W
BCST
EMEM
Auto_Inc
UA4
UA3
UA2
UA1
UA0
A22
A21
A20
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
D15
D14
D13
D
12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
SDIN signal is looped out on SDOUT
Write Mode
t5
t9
SCLK
CSb
t6
R/W
RSV
EMEM
Auto_Inc
UA4
UA3
UA2
UA1
UA0
A22
A21
A20
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
SDIN
SDOUT
R/W
RSV
EMEM
Auto_Inc
UA4
UA3
UA2
UA1
UA0
A22
A21
A20
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Read Data is output on SDOUT
SDIN signal is looped out on SDOUT
Read Mode
Figure 4-15: GSPI External Interface Timing
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Table 4-10: GSPI Timing Parameters
Equivalent
SCLK
Parameter
Symbol
Min
Typ
Max
Units
Cycles
SCLK Frequency
—
t0
—
—
—
—
—
1
—
1.7
—
—
—
50
—
—
—
—
27
—
—
60
—
—
—
—
MHz
ns
CS LOW Before SCLK Rising Edge
SCLK Period
t1
t2
37
ns
SCLK Duty Cycle
40
ꢀ
t3
Input Data Setup Time
SCLK Idle Time – Write
SCLK Idle Time – Read
Inter–Command Delay Time
2.3
ns
t4
1/SCLK
138
115
ns
t5
—
3
ns
tcmd
ns
Inter–Command Delay Time (after
GSPI configuration write)
1
4
139
1.3
0
—
—
—
—
6.4
—
ns
ns
ns
tcmd_GSPI_conf
t6
t7
SDOUT After SCLK Falling Edge
—
—
CS HIGH After Final SCLK Falling
Edge
t8
t9
Input Data Hold Time
CS HIGH Time
—
—
1.2
58
—
—
—
—
ns
ns
SDIN to SDOUT Combinatorial
Delay
—
—
—
—
—
—
—
—
3.4
ns
# of
Max chips daisy-chained at max
SCLK frequency (26 MHz)
When host clocks in SDOUT
data on falling edge of SCLK
compatible
Semtech
devices
8
Max frequency for 32
daisy-chained devices
When host clocks in SDOUT
data on falling edge of SCLK
7.5
MHz
Note:
1. tcmd_GSPI_conf inter-command delay must be used whenever modifying CONTROL_REG register at address 0x00.
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4.9.7 Single Read/Write Access
Single read/write access timing for the GSPI interface is shown in Figure 4-16 to
Figure 4-20.
When performing a single read or write access, one Data Word is read from/written to
the device per access. Each access is a minimum of 48-bits long, consisting of two
Command Words and a single Data Word. The read or write cycle begins with a
HIGH-to-LOW transition of the CS pin. The read or write access is terminated by a
LOW-to-HIGH transition of the CS pin.
The maximum interface clock rate is 27MHz and the inter-command delay time
indicated in the figures as t , is a minimum of 3 SCLK clock cycles. After modifying
cmd
values in CONTROL_REG, the inter-command delay time, t
, is a minimum
cmd_GSPI_config
of 4 SCLK clock cycles.
For read access, the time from the last bit of Command Word 2 to the start of the data
output, as defined by t , corresponds to no less than 4 SCLK clock cycles at 27MHz.
5
t
cmd
SCLK
CS
COMMAND WORD 1
COMMAND WORD 1
COMMAND WORD 2
COMMAND WORD 2
DATA WORD
DATA WORD
X
X
COMMAND WORD 1
COMMAND WORD 1
SDIN
SDOUT
Figure 4-16: GSPI Write Timing—Single Write Access with Loop-Through Operation (default)
t
cmd
SCLK
CS
SDIN
COMMAND WORD 2
COMMAND WORD 1
DATA WORD
X
COMMAND WORD 1
SDOUT
Figure 4-17: GSPI Write Timing—Single Write Access with GSPI Link-Disable Operation
t
cmd
SCLK
CS
COMMAND WORD 2
COMMAND WORD 2
COMMAND WORD 1
COMMAND WORD 1
DATA WORD
DATA WORD
X
High-z
COMMAND WORD 1
COMMAND WORD 1
SDIN
High-Z
SDOUT
Figure 4-18: GSPI Write Timing—Single Write Access with Bus-Through Operation
SCLK
t
5
CS
COMMAND WORD 1
COMMAND WORD 1
COMMAND WORD 2
COMMAND WORD 2
SDIN
DATA WORD
SDOUT
Figure 4-19: GSPI Read Timing—Single Read Access with Loop-Through Operation (default)
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SCLK
t
5
CS
SDIN
COMMAND WORD
COMMAND WORD
1
1
COMMAND WORD
COMMAND WORD
2
2
High-z
X
DATA WORD
SDOUT
Figure 4-20: GSPI Read Timing—Single Read Access with Bus-Through Operation
4.9.8 Auto-increment Read/Write Access
Auto-increment read/write access timing for the GSPI interface is shown in Figure 4-21
to Figure 4-25.
Auto-increment mode is enabled by the setting the AUTOINC bit of Command Word 1.
In this mode, multiple Data Words can be read from/written to the device using only one
starting address. Each access is initiated by a HIGH-to-LOW transition of the CS pin, and
consists of two Command Words and one or more Data Words. The internal address is
automatically incremented after the first read or write Data Word, and continues to
increment until the read or write access is terminated by a LOW-to-HIGH transition of
the CS pin.
Note: Writing to CONTROL_REG using Auto-increment access is not allowed.
The maximum interface clock rate is 27MHz and the inter-command delay time is a
minimum of 3 SCLK clock cycles.
For read access, the time from the last bit of the second Command Word to the start of
the data output of the first Data Word as defined by t will be no less than 4 SCLK cycles
5
at 27MHz. All subsequent read data accesses will not be subject to this delay during an
Auto-Increment read.
SCLK
CS
SDIN
COMMAND WORD 1
COMMAND WORD 1
COMMAND WORD 2
COMMAND WORD 2
DATA 1
DATA 1
DATA 2
DATA 2
SDOUT
Figure 4-21: GSPI Write Timing—Auto-Increment with Loop-Through Operation (default)
SCLK
CS
COMMAND WORD 1
COMMAND WORD 2
DATA 1
DATA 2
SDIN
SDOUT
Figure 4-22: GSPI Write Timing—Auto-Increment with GSPI Link Disable
Operation
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SCLK
CS
SDIN
COMMAND WORD 2
COMMAND WORD 2
COMMAND WORD 1
COMMAND WORD 1
DATA 1
DATA 1
DATA 2
DATA 2
High-Z
SDOUT
Figure 4-23: GSPI Write Timing—Auto-Increment with Bus-Through Operation
SCLK
t
5
CS
SDIN
COMMAND WORD 1
COMMAND WORD 1
COMMAND WORD 2
COMMAND WORD 2
SDOUT
DATA 1
DATA 2
Figure 4-24: GSPI Read Timing—Auto-Increment Read with Loop-Through Operation (default)
SCLK
t
5
CS
SDIN
COMMAND WORD 1
COMMAND WORD 1
COMMAND WORD 2
COMMAND WORD 2
High-z
SDOUT
X
DATA 1
DATA 2
Figure 4-25: GSPI Read Timing—Auto-Increment Read with Bus-through Operation
4.9.9 Setting a Device Unit Address
Multiple (up to 32) GS12281 devices can be connected to a common Chip Select (CS) in
Loop-Through or Bus-Through operation.
To ensure that each device selected by a common CS can be separately addressed, a
unique Unit Address must be programmed by the host processor at start-up as part of
system initialization or following a device reset.
Note: By default at power up or after a device reset, the DEV_UNIT_ADDRESS of each
device is set to 0 and the SDINSDOUT non-clocked loop-through for each device is
h
enabled.
These are the steps required to set the DEV_UNIT_ADDRESS of devices in a chain to
values other than 0:
1. Write to Unit Address 0 selecting CONTROL_REG (ADDRESS = 0), with the
GSPI_LINK_DISABLE bit set to 1 and the DEV_UNIT_ADDRESS field set to 0. This
disables the direct SDINSDOUT non-clocked path for all devices on chip select.
2. Write to Unit Address 0 selecting CONTROL_REG (ADDRESS = 0), with the
GSPI_LINK_DISABLE bit set to 0 and the DEV_UNIT_ADDRESS field set to a
unique Unit Address. This configures DEV_UNIT_ADDRESS for the first device in
the chain. Each subsequent such write to Unit Address 0 will configure the next
device in the chain. If there are 32 devices in a chain, the last (32nd) device in the
chain must use DEV_UNIT_ADDRESS value 0.
3. Repeat step 2 using new, unique values for the DEV_UNIT_ADDRESS field in
CONTROL_REG until all devices in the chain have been configured with their own
unique Unit Address value.
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Note: t
delay must be observed after every write that modifies
cmd_GSPI_conf
CONTROL_REG.
All connected devices receive this command (by default the Unit Address of all devices
is 0), and the Loop-Through operation will be re-established for all connected devices.
Once configured, each device will only respond to Command Words with a
UNIT ADDRESS field matching the DEV_UNIT_ADDRESS in CONTROL_REG.
Note: Although the Loop-Through and Bus-Through configurations are compatible
with previous generation GSPI enabled devices (backward compatibility), only devices
supporting Unit Addressing can share a chip select. All devices on any single chip select
must be connected in a contiguous chain with only the last device's SDOUT connected
to the application host processor. Multiple chains configured in Bus-Through mode can
have their final SDOUT outputs connected to a single application host processor input.
4.9.10 Default GSPI Operation
By default at power up or after a device reset, the GS12281 is set for Loop-Through
Operation and the internal DEV_UNIT_ADDRESS field of the device is set to 0.
Figure 4-26 shows a functional block diagram of the Configuration and Status Register
(CSR) map in the GS12281.
At power-up or after a device reset, DEV_UNIT_ADDRESS = 00h
[15]
R/W
[14]
[13]
[12]
[11:7]
[6:0]
bits
BCAST
ALL
Auto
Inc
Unit Address
32 devices
Register Address
Upper 7 bits
EMEM
COMMAND 1
[15:0]
bits
COMMAND 2
Lower 16 bits of Register Address
[15:0]
bits
Compare
DATA
Data to be written / Read Data
[4:0]
[15]
[14]
[12:5]
bits
[13]
Read/Write
GSPI_BUS_
THROUGH
_ENABLE
GSPI_LINK
_DISABLE
Reg 0
RESERVED
DEV_UNIT_ADDRESS
RESERVED
Configuration and Status Registers
Figure 4-26: Internal Register Map Functional Block Diagram
The steps required for the application host processor to write to the Configuration and
Status Registers via the GSPI, are as follows:
1. Set Command Word 1 for write access (R/W = 0); set Auto Increment; set the Unit
Address field in the Command Word 1 to match the configured
DEV_UNIT_ADDRESS which will be zero after power-up. Set the Register Address
bits in Command Word 1 to match the upper 7 bits of the register address to be
accessed. Set the bits in Command Word 2 to match the lower 16 bits of the register
address to be accessed. Write Command Word 1 and Command Word 2.
2. Write the Data Word to be written to the first register.
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3. Write the Data Word to be written to the next register in Auto Increment mode, etc.
Read access is the same as the above with the exception of step 1, where the Command
Word 1 is set for read access (R/W = 1).
Note: The UNIT ADDRESS field of Command Word 1 must always match
DEV_UNIT_ADDRESS for an access to be accepted by the device. Changing
DEV_UNIT_ADDRESS to a value other than 0 is only required if multiple devices are
connected to a single chip select (in Loop-Through or Bus-Through configuration).
4.9.11 Clear Sticky Counts Through Four Way Handshake
There are three sticky counters that keep count of changes in status of primary carrier
detect, rate changes, and lock changes. The counters can be read from the following
three parameters in register 0x84 and 0x85: STAT_CNT_PRI_CD_CHANGES,
STAT_CNT_RATE_CHANGES, and STAT_CNT_PLL_LOCK_CHANGES. The counters
saturate at 255 (0xFF) and must be cleared before additional status changes can be
counted. The following four way handshake procedures clears the counters.
1. Poll STAT_CLEAR_COUNTS_STATUS parameter until equal to 0 (idle), then set
CTRL_CLEAR_COUNTS = 1 (clear sticky counts).
2. Poll STAT_CLEAR_COUNTS_STATUS parameter until equal to 2 (cleared), then
reset CTRL_CLEAR_COUNTS to 0.
The device will now reset STAT_CLEAR_COUNTS_STATUS to 0 (idle) and the clearing
process can be repeated at any time.
4.9.12 Device Power Up Sequence
If all power supplies cannot be guaranteed to power up simultaneously, ensure that
VCC_DDI powers up first. Please note that there is no minimum time requirement
between power supply initializations after VCC_DDI is energized.
Note: Please check with your local FAE (field applications engineer), as some devices
may need updated configuration settings. If a configuration file has been provided by
the FAE, see the timing information in the Serial Routing and Distribution Product
Configuration Loading Procedure Application Note (PDS-061176).
4.9.12.1 Power-Up Timing Sequence
The following timing sequence must be observed after power-up when no external
configuration loading is required. See Figure 4-27 for the timing requirements of Steps
1 and 2 below.
Step 1 – No GSPI Access Allowed
a) Device supply reaches 90ꢀ of target. POR (Power On Reset) is activated.
b) Internal blocks reset, default device configuration boot-up begins.
c) Default device configuration boot-up process.
Step 2 – GSPI Access Allowed
a) Host sets EYE_MON_INT_CFG_3 (register address 0x57) to 0x8006.
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b) If there are multiple devices on the GSPI chain, the host should configure the unit
address of each device. See Section 4.9.9 for further information on unit addressing.
c) Host sets custom application specific settings.
d) Normal operation begins.
5.11 ms – no GSPI Access Allowed
GSPI Access Allowed
All blocks reset.
After Completion of Reset, device
automatically initiates default
configuration boot-up.
Eye Monitor
Reset:
Host
writes 0x8006
to register 0x57
at unit address
0.
Normal Operation Begins.
Host must reconfigure the unit addresses of
devices that were reset to 0.
After which, host may read/write any
register of a specific device on the chain, or
use broadcast write to concurrently write a
command to all devices on the GSPI chain.
All devices that
received reset
command will
have their unit
address reset to
0.
Command will
be broadcast to
all devices that
were reset.
Device Blocks
Resetting.
Device
Configuration
Booting.
Application Defined GSPI Read/Write
Access.
GSPI Access..
110 μs
5 ms
Host writes
0xAD00 to
Internal Reset
Sequence
Complete.
Default
Configuration
Boot-Up
Eye
Monitor
Reset.
Register 0x007F
to reset device.
Host may reset
all devices by
using broadcast
mode.
Complete.
Figure 4-27: Power-Up Sequence.
4.9.13 Host Initiated Device Reset
The GS12281 includes a reset function accessible via the device's host interface, which
reverts all internal logic and register values to their default values.
The device can be reset with a single write of AD00 to the RESET_CONTROL bits of the
h
CONTROL_RESET register, which will assert and de-assert the device reset within the
duration of the GSPI write access Data Word.
The device can be placed and held in reset by writing AA00 to the RESET_CONTROL
h
bits of the CONTROL_RESET register. Subsequent writes of DD00 to the
h
RESET_CONTROL bits will de-assert device reset.
The current state of user-initiated device reset can be read from the RESET_CONTROL
bits of CONTROL_RESET register.
While in reset, host interface access to any other register will not be functional and all
logic and configuration registers will be in reset state. While in reset, output behaviour
is undefined. The digital logic and registers within the device will exit the reset state 5ms
after device reset is de-asserted.
The following timing sequence must be observed to initiate a device reset.
Note: Please check with your local FAE (field applications engineer), as some devices
may need updated configuration settings. If a configuration file has been provided by
the FAE, see the timing information in the Serial Routing and Distribution Product
Configuration Loading Procedure Application Note (PDS-061176).
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4.9.13.1 Host Initiated Device Reset Timing Sequence
The following timing sequence must be observed after a Host Initiated Device Reset
when no external configuration loading is required. See Figure 4-28 for the timing
requirements of the Steps 1 to 3 below.
Step 1 – GSPI Access Allowed
a) Host writes 0xAD00 to register 0x007F to reset selected devices, or all devices using
broadcast.
Step 2– No GSPI Access Allowed
a) Internal blocks reset, default device configuration boot-up begins.
b) Default device configuration boot-up completes.
Step 3 – GSPI Access Allowed
a) Host sets EYE_MON_INT_CFG_3 (register address 0x57) to 0x8006.
b) If there are multiple devices on the GSPI chain, host must reconfigure unit address
of each device that was reset. See Section 4.9.9 for further information on unit
addressing.
c) Host sets custom application specific settings.
d) Normal operation begins.
5.11 ms – No GSPI Access Allowed
GSPI Access Allowed
All blocks reset.
After Completion of Reset, device
automatically initiates default
configuration boot-up.
Eye Monitor
Reset:
Host
writes 0x8006
to register 0x57
at unit address
0.
Normal Operation Begins.
Host must reconfigure the unit addresses of
devices that were reset to 0.
After which, the host may read/write any
register of specific device on the chain, or
use broadcast write to concurrently write a
command to all devices on the GSPI chain.
All devices that
received reset
command will
have their unit
address reset to
0.
Command will
be broadcast to
all devices that
were reset.
Device Blocks
Resetting.
Device
Configuration
Booting.
Application Defined GSPI Read/Write
Access.
GSPI Access.
110 μs
5 ms
Host writes
0xAD00 to
Internal Reset
Sequence
Complete.
Default
Configuration
Boot-Up
Eye
Monitor
Reset.
Register 0x007F
to reset device.
Host may reset
all devices by
using broadcast
mode.
Complete.
Figure 4-28: Host Initiated Device Reset Timing Sequence.
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5. Register Map
The host interface on the GS12281 provides users complete control of key features such
as GPIO configuration, PLL loop bandwidth settings, re-time parameters, carrier
detection, trace equalization, bypass modes, output swing controls, mute functions,
pre-emphasis control and many others.
It also includes a wide selection of Status registers which allow the user to read back
several key metrics of information from the GS12281 to add more flexibility to their
designs. Section 5.1 to Section 5.3 cover each Control and Status register in detail.
5.1 Control Registers
d
Table 5-1: Control Registers
GSPI
Address
Register Name
R/W
h
0
1
CONTROL_ REG
DEVICE_ID
RW
RO
2
RSVD
RW
RW
RW
RW
RW
RW
RW
7F
3
CONTROL_ RESET
CONTROL_ SLEEP
MISC_CNTRL
MISC_CFG
4
5
6
RATE_ DETECT_ MODE
RSVD
7
CDR Configuration
8
9
REF_CLK_ MODE
RW
RW
RW
RW
RW
RW
FACTORY_ CDR_ PARAMETERS
PLL_LOOP_ BANDWIDTH_ 0
PLL_LOOP_ BANDWIDTH_ 1
PLL_LOOP_ BANDWIDTH_ 2
RSVD
0A
0B
0C
0D to 0F
GPIO Configuration
10
11
12
13
GPIO0_CFG
RW
RW
RW
RW
GPIO1_CFG
GPIO2_CFG
GPIO3_CFG
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Table 5-1: Control Registers (Continued)
GSPI
Address
Register Name
R/W
h
Equalizer Configuration
14 to 1D
1E
RSVD
RW
RW
RW
RW
TREQ0_ INPUT_BOOST
TREQ0_CD_ HYSTERESIS
RSVD
1F
20 to 25
Output Configuration
26 to 27
28
RSVD
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
OUTPUT_ PARAM_CD_ SD_0
OUTPUT_ PARAM_CD_ SD_1
OUTPUT_ PARAM_CD_ SD_2
OUTPUT_ PARAM_CD_ SD_3
OUTPUT_ PARAM_ CD_HD_0
OUTPUT_ PARAM_ CD_HD_1
OUTPUT_ PARAM_ CD_HD_2
OUTPUT_ PARAM_ CD_HD_3
OUTPUT_ PARAM_ CD_UHD_0
OUTPUT_ PARAM_ CD_UHD_1
OUTPUT_ PARAM_ CD_UHD_2
OUTPUT_ PARAM_ CD_UHD_3
RSVD
29
2A
2B
2C
2D
2E
2F
30
31
32
33
34 to 47
Output Control
48
OUTPUT_ SIG_SELECT
RW
RW
RW
RW
RW
RW
RW
49
CONTROL_ OUTPUT_ MUTE
CONTROL_ OUTPUT_ DISABLE
CONTROL_ OUTPUT_ SLEW
CONTROL_ RETIMER_ BYPASS
CONTROL_ BALANCED_ MODE
RSVD
4A
4B
4C
4D
4E to 4F
Test Functions
50
51
52
PRBS_ CHK_CFG
PRBS_CHK_ CTRL
PRBS_GEN_ CTRL
RW
RW
RW
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Table 5-1: Control Registers (Continued)
GSPI
Address
Register Name
R/W
h
53
54
RSVD
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
EYE_MON_ INT_CFG_0
EYE_MON_ INT_CFG_1
EYE_MON_ INT_CFG_2
EYE_MON_ INT_CFG_3
RSVD
55
56
57
58 to 59
5A
EYE_MON_ SCAN_CTRL_0
EYE_MON_ SCAN_CTRL_1
EYE_MON_ SCAN_CTRL_2
EYE_MON_ SCAN_CTRL_3
5B
5C
5D
Internal Only Configuration
5E to 7E RSVD
RW
5.2 Status Registers
Table 5-2: Status Registers
GSPI
Address
Register Name
R/W
h
80
81
82
83
84
85
86
87
88
89
8A
8B
8C
RSVD
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
VERSION_0
VERSION_1
VERSION_2
STICKY_ COUNTS_0
STICKY_ COUNTS_1
CURRENT_ STATUS_0
CURRENT_ STATUS_1
RSVD
PRBS_ CHK_ ERR_CNT
PRBS_ CHK_STATUS
EYE_MON_ SCAN_ SIZE_OUTPUT
EYE_MON_ SHAPE_ OUTPUT_0
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Table 5-2: Status Registers (Continued)
GSPI
Address
Register Name
R/W
h
8D
8E
EYE_MON_ SHAPE_ OUTPUT_1
EYE_MON_ SHAPE_ OUTPUT_2
EYE_MON_ SHAPE_ OUTPUT_3
EYE_MON_ STATUS
RW
RW
RW
RW
RW
8F
90
91 to BF
RSVD
5.3 Register Descriptions
Table 5-3: Control Register Descriptions
Reset
Value
Register
Name
Bit
Slice
Address
Parameter Name
R/W
Description
h
h
Device Configuration And Control
RSVD
15
R/W
0
Reserved - do not modify.
0 = Enable loop-through. SDIN pin is
looped through to the SDOUT pin.
GSPI_LINK_DISABLE
14
R/W
0
1 = Disable loop-through. Data
appearing at SDIN does not appear at
SDOUT, and SDOUT pin is HIGH.
CONTROL_
REG
0
GSPI_BUS_THROUGH_
ENABLE
0 = Disable bus-through mode
1 = Enable bus-through mode
13
R/W
R/W
0
0
RSVD
12:5
Reserved - do not modify.
Device address programmed by
application. See Section 4.9.9 for further
information
DEV_UNIT_ADDRESS
4:0
R/W
0
This register contains the device’s
identification, including revision.
Contact the local technical sales
representative for more details.
1
2
DEVICE_ID
RSVD
DEVICE_VERSION
RSVD
15:0
15:0
RO
—
0
R/W
Reserved - do not modify.
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Table 5-3: Control Register Descriptions (Continued)
Reset
Value
Register
Name
Bit
Slice
Address
Parameter Name
R/W
Description
h
h
Device Reset, Reverts all internal logic
and register values to defaults.
Write Values:
AA00h = Asserts device reset
DD00h = De-assert device reset
AD00h = Assert/de-assert device reset in
a single write
CONTROL_
RESET
7F
RESET_CONTROL
15:0
R/W
DD00
Read Values:
AA00h = User-initiated reset is asserted
DD00h = User-initiated reset is
de-asserted
See Section 4.9.13 for further
information
RSVD
15:2
1
R/W
R/W
0
0
Reserved - do not modify.
Sleep manual mode control:
0 = Never Sleep
1 = Always Sleep
CTRL_MANUAL_SLEEP
Controls sleep mode when auto sleep
(CTRL_AUTO_SLEEP) is disabled.
CONTROL_
SLEEP
Sleep auto mode control:
0 = Disable auto sleep mode
1 = Enable auto sleep mode
3
If CTRL_AUTO_SLEEP = 0 (manual sleep
mode), then CTRL_MANUAL_SLEEP
controls sleep.
CTRL_AUTO_SLEEP
0
R/W
1
If CTRL_AUTO_SLEEP = 1 (auto sleep
mode), sleep is automatically entered
on loss of signal.
RSVD
15:1
0
R/W
R/W
0
0
Reserved - do not modify.
Clear sticky counts control register.
0 = no action
1 = clear sticky counts.
4
MISC_CNTRL
Part of a four way handshake with
STAT_CLEAR_COUNTS_STATUS. See
Section 4.9.11 for more details on
implementing the four way handshake
for this operation.
CTRL_CLEAR_COUNTS
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Table 5-3: Control Register Descriptions (Continued)
Reset
Value
Register
Name
Bit
Slice
Address
Parameter Name
RSVD
R/W
Description
h
h
15:4
R/W
0
Reserved - do not modify.
Controls whether cable driver (SDO1) is
muted or disabled (powered down)
during sleep:
CFG_SLEEP_
OUTPUT1_MUTE
3
R/W
0
0 = disable (power down) output during
sleep.
1 = mute output during sleep.
5
MISC_CFG
Controls whether cable driver (SDO0) is
muted or disabled (powered down)
during sleep:
CFG_SLEEP_
OUTPUT0_MUTE
2
R/W
R/W
0
0
0 = disable (power down) output during
sleep.
1 = mute output during sleep.
RSVD
1:0
Reserved - do not modify.
CDR Configuration
RSVD
15:14
R/W
0
1
Reserved - do not modify.
12G auto rate detection enable:
0 = Disable rate
CFG_RATE_ENA_12G
13
R/W
1 = Enable rate
6G auto rate detection enable:
0 = Disable rate
1 = Enable rate
CFG_RATE_ENA_6G
CFG_RATE_ENA_3G
CFG_RATE_ENA_HD
CFG_RATE_ENA_SD
12
11
10
9
R/W
R/W
R/W
R/W
1
1
1
1
3G auto rate detection enable:
0 = Disable rate
1 = Enable rate
RATE_
DETECT_
MODE
6
HD auto rate detection enable:
0 = Disable rate
1 = Enable rate
SD auto rate detection enable:
0 = Disable rate
1 = Enable rate
MADI auto rate detection enable:
0 = Disable rate
1 = Enable rate
CFG_RATE_ENA_MADI
RSVD
8
R/W
R/W
0
0
7:5
Reserved - do not modify.
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Table 5-3: Control Register Descriptions (Continued)
Reset
Value
Register
Name
Bit
Slice
Address
Parameter Name
R/W
Description
h
h
Manual rate selection. The CDR will only
lock to the selected rate if
CFG_AUTO_RATE_DETECT_ENA = 0:
0 = Reserved - do not use.
1 = MADI
2 = SD
CFG_MANUAL_RATE
4:1
R/W
0
3 = HD
4 = 3G
5 = 6G
6 = 12G
7 = Reserved - do not modify.
RATE_
DETECT_
MODE
6
Set or disable auto rate detection mode
for the CDR.
(Continued)
(Continued)
0 = Disable auto rate detection
1 = Enable auto rate detection
When automatic rate detection is
disabled
CFG_AUTO_RATE_DETE
CT_ENA
0
R/W
1
(CFG_AUTO_RATE_DETECT_ENA = 0),
the rate is set by CFG_MANUAL_RATE.
Note: If using manual rate selection, the
host should set CFG_MANUAL_RATE to
1 through 6 first, then set
CFG_AUTO_RATE_ENA = 0.
7
RSVD
RSVD
RSVD
15:0
15:2
R/W
R/W
3
0
Reserved - do not modify.
Reserved - do not modify.
Manual external reference mode
selection:
0 = External reference clock mode
1 = Referenceless mode
CFG_REF_CLK_MODE_
MANUAL
1
R/W
1
Controls reference clock mode when
CFG_REF_CLK_MODE_AUTO = 0.
Automatic external reference selection
mode.
0 = Disable auto mode
1 = Enable auto mode
REF_CLK_
MODE
8
In auto mode, the device automatically
switches to reference clock mode when
the reference clock is detected. When
auto mode is disabled, reference clock
mode is controlled by
CFG_REF_CLK_MODE_
AUTO
0
R/W
1
CFG_REF_CLK_MODE_MANUAL.
Note: Once the device has been
switched to external reference mode,
either manual or automatically, it can
not be manually set back to
referenceless mode unless it is followed
by a device reset.
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Semtech
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Rev.9
Proprietary & Confidential
PDS-061385
February 2019
Table 5-3: Control Register Descriptions (Continued)
Reset
Value
Register
Name
Bit
Slice
Address
Parameter Name
RSVD
R/W
Description
h
h
15:4
3:2
R/W
R/W
7
0
Reserved - do not modify.
Set to 3 when using a PRBS7 signal or
h
similar repetitive short pattern.
PHASE_MODE
CFG_MIN_LBW
FACTORY_
CDR_
PARAMETERS
9
To maximize loop bandwidth of PLL and
consequently IJT of CDR, set this
parameter to 0.
1
R/W
0
RSVD
RSVD
0
R/W
R/W
0
0
Reserved - do not modify.
Reserved - do not modify.
15:13
Configure PLL loop bandwidth in terms
of ratio to nominal loop bandwidth 'x'
(see Table 2-3).
11.88Gb/s (12G) loop bandwidth
setting:
0x00 = Reserved - do not use
0x01 = 0.0625x
0x02 = 0.125x
0x03 = 0.1875x
0x04 = 0.25x
0x05 = 0.3125x
0x06 = 0.375x
0x07 = 0.4375x
0x08 = 0.5x
CFG_PLL_LBW_12G
12:8
R/W
8
0x09 = 0.5625x
0x0A = 0.625x
0x0B = 0.6875x
0x0C = 0.75x
PLL_LOOP_
BANDWIDTH_
0
0A
0x0D = 0.8125x
0x0E = 0.875x
0x0F = 0.9375x
0x10 to 0x1B = Reserved - do not use
0x1C = 1.0x (nominal)
0x1D = 1.0625x
0x1E = 1.125x
0x1F = 1.1875x
RSVD
7:5
4:0
R/W
R/W
0
8
Reserved - do not modify.
Configure 5.94Gb/s (6G) PLL loop
bandwidth in terms of ratio to nominal
loop bandwidth 'x' (see Table 2-3).
See CFG_PLL_LBW_12G parameter for
available settings.
CFG_PLL_LBW_6G
GS12281
Final Data Sheet
64 of 97
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PDS-061385
February 2019
Table 5-3: Control Register Descriptions (Continued)
Reset
Value
Register
Name
Bit
Slice
Address
Parameter Name
RSVD
R/W
Description
h
h
15:13
12:8
7:5
R/W
0
Reserved - do not modify.
Configure 2.97Gb/s (3G) PLL loop
bandwidth in terms of ratio to nominal
loop bandwidth 'x' (see Table 2-3).
See CFG_PLL_LBW_12G parameter for
available settings.
CFG_PLL_LBW_3G
RSVD
R/W
R/W
R/W
R/W
R/W
R/W
R/W
8
PLL_LOOP_
BANDWIDTH_
1
0B
0
Reserved - do not modify.
Configure 1.485Gb/s (HD) PLL loop
bandwidth in terms of ratio to nominal
loop bandwidth 'x' (see Table 2-3).
See CFG_PLL_LBW_12G parameter for
available settings.
CFG_PLL_LBW_HD
RSVD
4:0
8
15:13
12:8
7:5
0
Reserved - do not modify.
Configure 270Mb/s (SD) PLL loop
bandwidth in terms of ratio to nominal
loop bandwidth 'x' (see Table 2-3).
See CFG_PLL_LBW_12G parameter for
available settings.
CFG_PLL_LBW_SD
RSVD
1C
0
PLL_LOOP_
BANDWIDTH_
2
0C
Reserved - do not modify.
Configure 125Mb/s (MADI) PLL loop
bandwidth in terms of ratio to nominal
loop bandwidth 'x' (see Table 2-3).
See CFG_PLL_LBW_12G parameter for
available settings.
CFG_PLL_LBW_MADI
4:0
8
0D
RSVD
RSVD
RSVD
RSVD
15:0
15:0
R/W
R/W
8
0
Reserved - do not modify.
Reserved - do not modify.
0E to 0F
GS12281
Final Data Sheet
65 of 97
Semtech
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Rev.9
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PDS-061385
February 2019
Table 5-3: Control Register Descriptions (Continued)
Reset
Value
Register
Name
Bit
Slice
Address
Parameter Name
R/W
Description
h
h
GPIO Configuration
RSVD
15:9
R/W
0
1
Reserved - do not modify.
GPIO0 buffer mode control.
0 = GPIO pin is configured as an input
(tri-stated / high impedance).
CFG_GPIO0_
OUTPUT_ENA
8
R/W
1 = GPIO pin is configured as an output.
Function select for GPIO0 pin.
GPIO0 output functions:
0x00 = Output driven LOW
0x01 = Output driven HIGH
0x02 = PLL lock status (HIGH — PLL
locked)
0x03 to 0x7F = Reserved - do not use.
0x80 = LOS equivalent to inverse of
STAT_PRI_CD (Default mode for GPIO0)
0x81 = carrier detect status
(STAT_PRI_CD)
0x82 = Sleep mode status (HIGH —
Device in sleep mode)
0x83 = HIGH for SD, LOW for all other
rates.
0x84 = Rate detected [0]
10
GPIO0_CFG
0x85 = Rate detected [1]
0x86 = Rate detected [2]
CFG_GPIO0_FUNCTION
7:0
R/W
80
Note: To have full rate range using the
GPIO rate detect function, one GPIO pin
must be used for each Rate Detect
bit[2:0]. Please see Table 4-2: Detected
Data Rates for the indication values.
0x87 to 0xFF = Reserved - do not use.
GPIO0 input functions:
0x00 to 0x80 = Reserved - do not use.
0x81 = SDO0 disable control (HIGH —
disable)
0x82 = SDO1 disable control (HIGH —
disable)
0x83 to 0x84 = Reserved - do not
modify.
0x85 = Retimer bypass enable (HIGH —
Bypass enabled)
0x86 = Sleep control (HIGH — Sleep)
0x87 to 0xFF = Reserved - do not use.
GS12281
Final Data Sheet
66 of 97
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PDS-061385
February 2019
Table 5-3: Control Register Descriptions (Continued)
Reset
Value
Register
Name
Bit
Slice
Address
Parameter Name
RSVD
R/W
Description
h
h
15:9
R/W
0
Reserved - do not modify.
GPIO1 buffer mode control.
See GPIO0_CFG:
CFG_GPIO0_OUTPUT_ENA parameter
for description and available settings.
Default mode: Output
CFG_GPIO1_
OUTPUT_ENA
8
R/W
1
11
GPIO1_CFG
Function select for GPIO1 pin.
See GPIO0_CFG:
CFG_GPIO0_FUNCTION parameter for
description and available settings.
Default Function: 0x02 = PLL lock status
CFG_GPIO1_
FUNCTION
7:0
15:9
8
R/W
R/W
R/W
2
0
0
RSVD
Reserved - do not modify.
GPIO2 buffer mode control.
See GPIO0_CFG:
CFG_GPIO0_OUTPUT_ENA parameter
for description and available settings.
Default mode: Input
CFG_GPIO2_
OUTPUT_ENA
12
GPIO2_CFG
Function select for GPIO2 pin.
See GPIO0_CFG:
CFG_GPIO2_FUNCTION
RSVD
7:0
15:9
8
R/W
R/W
R/W
86
0
CFG_GPIO0_FUNCTION parameter for
description and available settings.
Default Function: 0x86 = Sleep control
Reserved - do not modify.
GPIO3 buffer mode control.
See GPIO0_CFG:
CFG_GPIO0_OUTPUT_ENA parameter
for description and available settings.
Default mode: Input
CFG_GPIO3_
OUTPUT_ENA
0
13
GPIO3_CFG
Function select for GPIO3 pin.
See GPIO0_CFG:
CFG_GPIO0_FUNCTION parameter for
description and available settings.
Default Function: 0x82 = SDO1 disable
control (HIGH disable)
CFG_GPIO3_FUNCTION
7:0
R/W
82
GS12281
Final Data Sheet
67 of 97
Semtech
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Rev.9
Proprietary & Confidential
PDS-061385
February 2019
Table 5-3: Control Register Descriptions (Continued)
Reset
Value
Register
Name
Bit
Slice
Address
Parameter Name
R/W
Description
h
h
Trace Equalizer Configuration
14
15
16
17
18
19
1A
1B
1C
1D
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:5
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
303
0
Reserved - do not modify.
Reserved - do not modify.
Reserved - do not modify.
Reserved - do not modify.
Reserved - do not modify.
Reserved - do not modify.
Reserved - do not modify.
Reserved - do not modify.
Reserved - do not modify.
Reserved - do not modify.
Reserved - do not modify.
4002
1
50
1
14
1
4
0
0
Trace equalizer boost setting for TEQ
(Trace Equalizer):
0 = Bypass equalization stage
1 to 8 = 1 to 17dB of insertion loss at
5.94GHz (see Figure 4-1).
Bypass is the minimum boost setting;
boost 8 is maximum boost setting.
CFG_TREQ0_BOOST
4:1
R/W
2
TREQ0_
INPUT_BOOST
1E
Selects boost level applied to DDI input
signal for carrier detection function
only.
0 = Sets to boost 8 (See Figure 4-1)
1 = Use CFG_TREQ0_BOOST setting
CFG_TREQ0_
CD_BOOST
0
R/W
R/W
0
0
RSVD
15:8
Reserved - do not modify.
Sets assert threshold for trace equalizer
carrier detect
0 to15d, where 0 is minimum threshold
and 15d is maximum threshold (see
Figure 4-2).
CFG_TREQ0_CD_
ASSERT_THRESH
7:4
3:0
R/W
R/W
4
3
TREQ0_CD_
HYSTERESIS
1F
Sets deassert threshold for trace
equalizer carrier detect
0 to15d, where 0 is minimum threshold
and 15d is maximum threshold (see
Figure 4-2).
CFG_TREQ0_CD_
DEASSERT_THRESH
20
21
22
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
15:0
15:0
15:0
R/W
R/W
R/W
3
F
Reserved - do not modify.
Reserved - do not modify.
Reserved - do not modify.
3FF
GS12281
Final Data Sheet
68 of 97
Semtech
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PDS-061385
February 2019
Table 5-3: Control Register Descriptions (Continued)
Reset
Value
Register
Name
Bit
Slice
Address
Parameter Name
R/W
Description
h
h
Output Configuration
23 to 27
RSVD
RSVD
RSVD
15:0
R/W
R/W
0
0
Reserved - do not modify.
Reserved - do not modify.
15:13
Configure the MADI/SD rate
pre-emphasis pulse width on cable
driver output1 (SDO1).
CFG_OUTPUT1_CD_
SD_PREEMPH_WIDTH
Range: 0 to 15d.
12:8
7
R/W
R/W
R/W
3
0
1
Adjust the pre-emphasis pulse width to
better match the channel loss response
shape.
RSVD
Reserved - do not modify.
Power down the MADI/SD rate
pre-emphasis on cable driver output1
(SDO1).
0 = Pre-emphasis driver powered up
(pre-emphasis enabled).
OUTPUT_
PARAM_CD_
SD_0
28
CFG_OUTPUT1_CD_
SD_PREEMPH_
PWRDWN
6
1 = Pre-emphasis driver powered down
(pre-emphasis disabled).
Configure the MADI/SD rate
pre-emphasis amplitude on cable driver
output1 (SDO1).
CFG_OUTPUT1_CD_
SD_PREEMPH_AMPL
Range: 0 to 15d.
5:0
R/W
R/W
0
0
Adjust the pre-emphasis pulse
amplitude to better match the channel
loss at Nyquist.
RSVD
15:14
Reserved - do not modify.
Configure the MADI/SD rate amplitude
on cable driver output1 (SDO1) in
~28mVpp steps.
Functional Range = 9d to 31d
Precision Range = 20d to 26d
Default value = 23d (~800mVpp
)
OUTPUT_
PARAM_CD_
SD_1
CFG_OUTPUT1_CD_
SD_DRIVER_SWING
29
13:8
R/W
17
Note: In auto slew mode (CTRL_
OUTPUT1_AUTO_SLEW=1), the slew
rate is determined by the rate at which
the CDR is locked. If the CDR is
unlocked, the slew will default to
6G/12G Slew. See Table 2-3 for Rise/Fall
Times, and Section 4.7.3 for more details
on output driver selection.
RSVD
7:0
R/W
A0
Reserved - do not modify.
GS12281
Final Data Sheet
69 of 97
Semtech
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PDS-061385
February 2019
Table 5-3: Control Register Descriptions (Continued)
Reset
Value
Register
Name
Bit
Slice
Address
Parameter Name
RSVD
R/W
Description
h
h
15:13
12:8
7
R/W
0
3
0
1
Reserved - do not modify.
Configure the MADI/SD rate
pre-emphasis pulse width on cable
driver output0 (SDO0).
CFG_OUTPUT0_CD_
SD_PREEMPH_WIDTH
Range: 0 to 15d.
R/W
R/W
R/W
Adjust the pre-emphasis pulse width to
better match the channel loss response
shape.
RSVD
Reserved - do not modify.
Power down the MADI/SD rate
pre-emphasis on cable driver output0
(SDO0).
0 = Pre-emphasis driver powered up
(pre-emphasis enabled).
OUTPUT_
PARAM_CD_
SD_2
2A
CFG_OUTPUT0_CD_
SD_PREEMPH_
PWRDWN
6
1 = Pre-emphasis driver powered down
(pre-emphasis disabled).
Configure the MADI/SD rate
pre-emphasis amplitude on cable driver
output0 (SDO0).
CFG_OUTPUT0_CD_
SD_PREEMPH_AMPL
Range: 0 to 15d.
5:0
R/W
R/W
0
0
Adjust the pre-emphasis pulse
amplitude to better match the channel
loss at Nyquist.
RSVD
15:14
Reserved - do not modify.
Configure the MADI/SD rate amplitude
on cable driver output 0 (SDO0) in
~28mVpp steps.
Functional Range = 9d to 31d
Precision Range = 20d to 26d
Default value = 23d (~800mVpp
)
OUTPUT_
PARAM_CD_
SD_3
CFG_OUTPUT0_CD_
SD_DRIVER_SWING
2B
13:8
R/W
17
Note: In auto slew mode (CTRL_
OUTPUT0_AUTO_SLEW=1), the slew
rate is determined by the rate at which
the CDR is locked. If the CDR is
unlocked, the slew will default to
6G/12G Slew. See Table 2-3 for Rise/Fall
Times, and Section 4.7.3 for more details
on output driver selection.
RSVD
7:0
R/W
A0
Reserved - do not modify.
GS12281
Final Data Sheet
70 of 97
Semtech
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Rev.9
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PDS-061385
February 2019
Table 5-3: Control Register Descriptions (Continued)
Reset
Value
Register
Name
Bit
Slice
Address
Parameter Name
RSVD
R/W
Description
h
h
15:13
12:8
7
R/W
0
8
0
0
Reserved - do not modify.
Configure the HD/3G rate pre-emphasis
pulse width on cable driver output1
(SDO1).
CFG_OUTPUT1_CD_
HD_PREEMPH_WIDTH
Range: 0 to 15d.
R/W
R/W
R/W
Adjust the pre-emphasis pulse width to
better match the channel loss response
shape.
RSVD
Reserved - do not modify.
Power down the HD/3G rate
pre-emphasis on cable driver output1
(SDO1)
0 = Pre-emphasis driver powered up
(pre-emphasis enabled).
OUTPUT_
PARAM_
CD_HD_0
2C
CFG_OUTPUT1_CD_
HD_PREEMPH_
PWRDWN
6
1 = Pre-emphasis driver powered down
(pre-emphasis disabled).
Configure the HD/3G rate pre-emphasis
amplitude on cable driver output1
(SDO1).
CFG_OUTPUT1_CD_
HD_PREEMPH_AMPL
Range: 0 to 15d.
5:0
R/W
R/W
5
0
Adjust the pre-emphasis pulse
amplitude to better match the channel
loss at Nyquist.
RSVD
15:14
Reserved - do not modify.
Configure the HD/3G rate amplitude on
cable driver output 1 (SDO1) in
~26mVpp steps.
Functional Range = 9d to 31d
Precision Range = 22d to 28d
Default value = 25d (~800mVpp
)
OUTPUT_
PARAM_
CD_HD_1
CFG_OUTPUT1_CD_
HD_DRIVER_SWING
2D
13:8
R/W
19
Note: In auto slew mode (CTRL_
OUTPUT1_AUTO_SLEW=1), the slew
rate is determined by the rate at which
the CDR is locked. If the CDR is
unlocked, the slew will default to
6G/12G Slew. See Table 2-3 for Rise/Fall
Times, and Section 4.7.3 for more details
on output driver selection.
RSVD
7:0
R/W
80
Reserved - do not modify.
GS12281
Final Data Sheet
71 of 97
Semtech
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Rev.9
Proprietary & Confidential
PDS-061385
February 2019
Table 5-3: Control Register Descriptions (Continued)
Reset
Value
Register
Name
Bit
Slice
Address
Parameter Name
RSVD
R/W
Description
h
h
15:13
12:8
7
R/W
0
Reserved - do not modify.
Configure the HD/3G rate pre-emphasis
pulse width on cable driver output0
(SDO0).
CFG_OUTPUT0_CD_
HD_PREEMPH_WIDTH
Range: 0 to 15d
R/W
R/W
R/W
8
Adjust the pre-emphasis pulse width to
better match the channel loss response
shape.
RSVD
Reserved - do not modify.
Power down the HD/3G rate
pre-emphasis on cable driver output0
(SDO0)
0 = Pre-emphasis driver powered up
(pre-emphasis enabled).
OUTPUT_
PARAM_
CD_HD_2
2E
CFG_OUTPUT0_CD_
HD_PREEMPH_
PWRDWN
6
0
1 = Pre-emphasis driver powered down
(pre-emphasis disabled).
Configure the HD/3G rate pre-emphasis
amplitude on cable driver output0
(SDO0).
CFG_OUTPUT0_CD_
HD_PREEMPH_AMPL
Range: 0 to 15d.
5:0
R/W
R/W
5
0
Adjust the pre-emphasis pulse
amplitude to better match the channel
loss at Nyquist.
RSVD
15:14
Reserved - do not modify.
Configure the HD/3G rate amplitude on
cable driver output 0 (SDO0) in
~26mVpp steps.
Functional Range = 9d to 31d
Precision Range = 22d to 28d
Default value = 25d (~800mVpp
)
OUTPUT_
PARAM_
CD_HD_3
CFG_OUTPUT0_CD_
HD_DRIVER_SWING
2F
13:8
R/W
19
Note: In auto slew mode (CTRL_
OUTPUT0_AUTO_SLEW=1), the slew
rate is determined by the rate at which
the CDR is locked. If the CDR is
unlocked, the slew will default to
6G/12G Slew. See Table 2-3 for Rise/Fall
Times, and Section 4.7.3 for more details
on output driver selection.
RSVD
7:0
R/W
80
Reserved - do not modify.
GS12281
Final Data Sheet
72 of 97
Semtech
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Rev.9
Proprietary & Confidential
PDS-061385
February 2019
Table 5-3: Control Register Descriptions (Continued)
Reset
Value
Register
Name
Bit
Slice
Address
Parameter Name
RSVD
R/W
Description
h
h
15:13
12:8
7
R/W
0
4
0
0
Reserved - do not modify.
Configure the 6G/12G rate
pre-emphasis pulse width on cable
driver output1 (SDO1).
Range: 0 to 15d.
Adjust the pre-emphasis pulse width to
better match the channel loss response
shape.
Note: In auto slew mode (CTRL_
OUTPUT1_AUTO_SLEW=1), the slew
rate is determined by the rate at which
the CDR is locked. If the CDR is
unlocked, the slew will default to
6G/12G Slew. See Table 2-3 for Rise/Fall
Times, and Section 4.7.3 for more details
on output driver selection.
CFG_OUTPUT1_CD_
UHD_PREEMPH_
WIDTH
R/W
R/W
R/W
RSVD
Reserved - do not modify.
Power down the 6G/12G rate
pre-emphasis on cable driver output1
(SDO1)
0 = Pre-emphasis driver powered up
(pre-emphasis enabled).
1 = Pre-emphasis driver powered down
(pre-emphasis disabled).
Note: In auto slew mode (CTRL_
OUTPUT1_AUTO_SLEW=1), the slew
rate is determined by the rate at which
the CDR is locked. If the CDR is
unlocked, the slew will default to
6G/12G Slew. See Table 2-3 for Rise/Fall
Times, and Section 4.7.3 for more details
on output driver selection.
OUTPUT_
PARAM_
CD_UHD_0
30
CFG_OUTPUT1_CD_
UHD_PREEMPH_
PWRDWN
6
Configure the 6G/12G rate
pre-emphasis amplitude on cable driver
output1 (SDO1).
Range: 0 to 15d.
Adjust the pre-emphasis pulse
amplitude to better match the channel
loss at Nyquist.
CFG_OUTPUT1_CD_
UHD_PREEMPH_AMPL
5:0
R/W
4
Note: In auto slew mode (CTRL_
OUTPUT1_AUTO_SLEW=1), the slew
rate is determined by the rate at which
the CDR is locked. If the CDR is
unlocked, the slew will default to
6G/12G Slew. See Table 2-3 for Rise/Fall
Times, and Section 4.7.3 for more details
on output driver selection.
GS12281
Final Data Sheet
73 of 97
Semtech
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Rev.9
Proprietary & Confidential
PDS-061385
February 2019
Table 5-3: Control Register Descriptions (Continued)
Reset
Value
Register
Name
Bit
Slice
Address
Parameter Name
RSVD
R/W
Description
h
h
15:14
R/W
0
Reserved - do not modify.
Configure the 6G/12G rate amplitude on
cable driver output1 (SDO1) in ~23mVpp
steps.
Functional Range = 9d to 31d
Precision Range = 24d to 30d
Default value = 27d(~800mVpp
)
CFG_OUTPUT1_CD_
UHD_DRIVER_
SWING
OUTPUT_
PARAM_
CD_UHD_1
31
13:8
R/W
1B
Note: In auto slew mode (CTRL_
OUTPUT1_AUTO_SLEW=1), the slew
rate is determined by the rate at which
the CDR is locked. If the CDR is
unlocked, the slew will default to
6G/12G Slew. See Table 2-3 for Rise/Fall
Times, and Section 4.7.3 for more details
on output driver selection.
RSVD
RSVD
7:0
R/W
R/W
40
0
Reserved - do not modify.
Reserved - do not modify.
15:13
Configure the 6G/12G rate
pre-emphasis pulse width on cable
driver output0 (SDO0).
Range: 0 to 15d.
Adjust the pre-emphasis pulse width to
better match the channel loss response
shape.
CFG_OUTPUT0_CD_
UHD_PREEMPH_
WIDTH
OUTPUT_
PARAM_
CD_UHD_2
32
12:8
R/W
R/W
4
0
Note: In auto slew mode (CTRL_
OUTPUT0_AUTO_SLEW=1), the slew
rate is determined by the rate at which
the CDR is locked. If the CDR is
unlocked, the slew will default to
6G/12G Slew. See Table 2-3 for Rise/Fall
Times, and Section 4.7.3 for more details
on output driver selection.
RSVD
7
Reserved - do not modify.
GS12281
Final Data Sheet
74 of 97
Semtech
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Rev.9
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PDS-061385
February 2019
Table 5-3: Control Register Descriptions (Continued)
Reset
Value
Register
Name
Bit
Slice
Address
Parameter Name
R/W
Description
h
h
Power down the 6G/12G rate
pre-emphasis on cable driver output0
(SDO0)
0 = Pre-emphasis driver powered up
(pre-emphasis enabled).
1 = Pre-emphasis driver powered down
(pre-emphasis disabled).
CFG_OUTPUT0_CD_
UHD_PREEMPH_
PWRDWN
6
R/W
0
Note: In auto slew mode (CTRL_
OUTPUT0_AUTO_SLEW=1), the slew
rate is determined by the rate at which
the CDR is locked. If the CDR is
unlocked, the slew will default to
6G/12G Slew. See Table 2-3 for Rise/Fall
Times, and Section 4.7.3 for more details
on output driver selection.
OUTPUT_
PARAM_
CD_UHD_2
(Continued)
32
(Continued)
Configure the 6G/12G rate
pre-emphasis amplitude on cable driver
output0 (SDO0).
Range: 0 to 15d.
Adjust the pre-emphasis pulse
amplitude to better match the channel
loss at Nyquist.
CFG_OUTPUT0_CD_
UHD_PREEMPH_AMPL
5:0
R/W
R/W
4
0
Note: In auto slew mode (CTRL_
OUTPUT0_AUTO_SLEW=1), the slew
rate is determined by the rate at which
the CDR is locked. If the CDR is
unlocked, the slew will default to
6G/12G Slew. See Table 2-3 for Rise/Fall
Times, and Section 4.7.3 for more details
on output driver selection.
RSVD
15:14
Reserved - do not modify.
Configure the 6G/12G rate amplitude on
cable driver output 0 (SDO0) in
~23mVpp steps.
Functional Range = 9d to 31d
Precision Range = 24d to 30d
Default value = 27d (~800mVpp
)
OUTPUT_
PARAM_
CD_UHD_3
CFG_OUTPUT0_CD_
UHD_DRIVER_SWING
33
13:8
R/W
1B
Note: In auto slew mode (CTRL_
OUTPUT0_AUTO_SLEW=1), the slew
rate is determined by the rate at which
the CDR is locked. If the CDR is
unlocked, the slew will default to
6G/12G Slew. See Table 2-3 for Rise/Fall
Times, and Section 4.7.3 for more details
on output driver selection.
RSVD
RSVD
7:0
R/W
R/W
40
Reserved - do not modify.
Reserved - do not modify.
34
RSVD
15:0
201
GS12281
Final Data Sheet
75 of 97
Semtech
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Rev.9
Proprietary & Confidential
PDS-061385
February 2019
Table 5-3: Control Register Descriptions (Continued)
Reset
Value
Register
Name
Bit
Slice
Address
Parameter Name
RSVD
R/W
Description
h
h
35
36
37
38
39
3A
3B
3C
3D
3E
3F
40
41
42
43
44
45
46
47
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
1170
201
Reserved - do not modify.
Reserved - do not modify.
Reserved - do not modify.
Reserved - do not modify.
Reserved - do not modify.
Reserved - do not modify.
Reserved - do not modify.
Reserved - do not modify.
Reserved - do not modify.
Reserved - do not modify.
Reserved - do not modify.
Reserved - do not modify.
Reserved - do not modify.
Reserved - do not modify.
Reserved - do not modify.
Reserved - do not modify.
Reserved - do not modify.
Reserved - do not modify.
Reserved - do not modify.
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
1170
201
1170
201
1170
342
1C90
342
1C90
340
850
340
850
342
1C90
342
1C90
GS12281
Final Data Sheet
76 of 97
Semtech
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Rev.9
Proprietary & Confidential
PDS-061385
February 2019
Table 5-3: Control Register Descriptions (Continued)
Reset
Value
Register
Name
Bit
Slice
Address
Parameter Name
R/W
Description
h
h
Output Control
RSVD
15:4
R/W
10
0
Reserved - do not modify.
Controls optional signal polarity
inversion on cable driver output0
(SDO0) when data is selected
CTRL_OUTPUT0_
DATA_INVERT
3
R/W
(CTRL_OUTPUT0_SIGNAL_SEL = 0).
Controls optional signal polarity
inversion on cable driver output1
(SDO1) when data is selected
CTRL_OUTPUT1_
DATA_INVERT
2
1
R/W
R/W
0
0
(CTRL_OUTPUT1_SIGNAL_SEL = 0).
OUTPUT_
SIG_SELECT
48
Select between Data and PRBS
generator on output0 (SDO0).
0 = Data
CTRL_OUTPUT0_
SIGNAL_SEL
1 = PRBS generator output (PRBS7 or
divided version of PRBS generator clock)
Select between data or PRBS generator
on output1 (SDO1).
0 = Data
1 = PRBS generator output (PRBS7 or
divided version of PRBS generator clock)
CTRL_OUTPUT1_
SIGNAL_SEL
0
R/W
R/W
0
0
RSVD
15:6
Reserved - do not modify.
Selects if device is auto muted during
rate search, based on loss of lock at the
input.
1= Mutes SDO1 when CDR is not locked
to the applied signal.
CTRL_OUTPUT1_
AUTO_MUTE_DURING_
RATE_SEARCH
5
R/W
0
0= Device does not auto mute.
Note: If passing non-standard rates
through the device or using the PRBS
generator, set this parameter to 0.
Selects if device is auto muted during
rate search, based on loss of lock at the
input.
CONTROL_
OUTPUT_
MUTE
49
1= Mutes SDO0 when CDR is not locked
to the applied signal.
CTRL_OUTPUT0_
AUTO_MUTE_DURING_
RATE_SEARCH
4
3
R/W
R/W
0
0
0= Device does not auto mute.
Note: If passing non-standard rates
through the device or using the PRBS
generator, set this parameter to 0.
Controls mute for cable driver output1
(SDO1) when auto mute
(CTRL_OUTPUT1_AUTO_MUTE = 0) is
disabled.
CTRL_OUTPUT1_
MANUAL_MUTE
0 = Unmute output driver
1 = Mute output driver.
GS12281
Final Data Sheet
77 of 97
Semtech
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Rev.9
Proprietary & Confidential
PDS-061385
February 2019
Table 5-3: Control Register Descriptions (Continued)
Reset
Value
Register
Name
Bit
Slice
Address
Parameter Name
R/W
Description
h
h
Select automatic or manual mute
control for cable driver output1 (SDO1)
0 = Disable auto mute mode
1 = Enable auto mute mode
CTRL_OUTPUT1_
AUTO_MUTE
2
1
0
R/W
1
0
1
If CTRL_OUTPUT1_AUTO_MUTE = 0,
then CTRL_OUTPUT1_MANUAL_MUTE
controls mute for SDO1.
Controls mute for cable driver output0
(SDO0) when auto mute
(CTRL_OUTPUT0_AUTO_MUTE = 0) is
disabled.
CONTROL_
OUTPUT_
MUTE
CTRL_OUTPUT0_
MANUAL_MUTE
49
R/W
R/W
(Continued)
(Continued)
0 = Unmute output driver
1 = Mute output driver.
Select automatic or manual mute
control for cable driver output0 (SDO0)
0 = Disable auto mute mode
1 = Enable auto mute mode
CTRL_OUTPUT0_
AUTO_MUTE
If CTRL_OUTPUT0_AUTO_MUTE = 0,
then CTRL_OUTPUT0_MANUAL_MUTE
controls mute for SDO0.
RSVD
15:4
3
R/W
R/W
0
0
Reserved - do not modify.
Controls disable for cable driver output1
(SDO1) when auto disable
(CTRL_OUTPUT1_AUTO_DISABLE = 0) is
disabled.
CTRL_OUTPUT1_
MANUAL_DISABLE
0 = Enable output driver
1 = Disable (power down) output driver.
Select automatic or manual disable
control for cable driver output1 (SDO1)
CONTROL_
OUTPUT_
DISABLE
4A
0 = Disable auto disable mode
CTRL_OUTPUT1_
AUTO_DISABLE
1 = Enable auto disable mode
2
1
R/W
R/W
0
0
If CTRL_OUTPUT1_AUTO_DISABLE = 0,
then
CTRL_OUTPUT1_MANUAL_DISABLE
controls mute for SDO1.
Controls disable for cable driver output0
(SDO0) when auto disable
(CTRL_OUTPUT0_AUTO_DISABLE = 0) is
disabled.
CTRL_OUTPUT0_
MANUAL_DISABLE
0 = Enable output driver
1 = Disable (power down) output driver.
GS12281
Final Data Sheet
78 of 97
Semtech
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Rev.9
Proprietary & Confidential
PDS-061385
February 2019
Table 5-3: Control Register Descriptions (Continued)
Reset
Value
Register
Name
Bit
Slice
Address
Parameter Name
R/W
Description
h
h
Select automatic or manual disable
control for cable driver output0 (SDO0)
0 = Disable auto disable mode
1 = Enable auto disable mode
CONTROL_
OUTPUT_
DISABLE
CTRL_OUTPUT0_
AUTO_DISABLE
4A
(Continued)
0
R/W
0
If CTRL_OUTPUT0_AUTO_DISABLE = 0,
then
(Continued)
CTRL_OUTPUT0_MANUAL_DISABLE
controls mute for SDO0.
RSVD
15:11
10:9
R/W
R/W
0
2
Reserved - do not modify.
Selects slew rate for cable driver
output1 (SDO1) when auto
slew rate is disabled.
CTRL_OUTPUT1_
MANUAL_SLEW
0 = SD/MADI slew
1 = HD/3G slew
2 = 6G/12G slew
Selects between auto or manual slew
rate selection for cable driver output1
(SDO1).
0 = Disable auto slew rate selection.
1 = Enable auto slew rate selection.
CTRL_OUTPUT1_
AUTO_SLEW
8
R/W
1
This may be necessary when device is
passing an unsupported rate, or when
using the PRBS generator when the
device is not locked to an input signal.
RSVD
7:3
2:1
R/W
R/W
0
2
Reserved - do not modify.
CONTROL_
OUTPUT_
SLEW
Selects slew rate for cable driver
output0 (SDO0) when auto
slew rate is disabled.
4B
CTRL_OUTPUT0_
MANUAL_SLEW
0 = SD/MADI slew
1 = HD/3G slew
2 = 6G/12G slew
Selects between auto or manual slew
rate selection for cable driver output0
(SDO0).
0 = Disable auto slew rate selection.
1 = Enable auto slew rate selection.
This may be necessary when device is
passing an unsupported rate, or when
using the PRBS generator when the
device is not locked to an input signal.
CTRL_OUTPUT0_
AUTO_SLEW
0
R/W
1
Note: In auto-mode, the slew rate is
determined by the rate at which the
CDR is locked. If the CDR is unlocked,
the slew will default to 6G/12G Slew (see
Table 2-3 for Rise/Fall Times).
GS12281
Final Data Sheet
79 of 97
Semtech
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Rev.9
Proprietary & Confidential
PDS-061385
February 2019
Table 5-3: Control Register Descriptions (Continued)
Reset
Value
Register
Name
Bit
Slice
Address
Parameter Name
RSVD
R/W
Description
h
h
15:4
3
R/W
0
Reserved - do not modify.
Controls retimer bypass for cable driver
output1 (SDO1), when auto mode is
disabled
(CTRL_OUTPUT1_RETIMER_AUTO_BYPA
SS = 0).
CTRL_OUTPUT1_
RETIMER_MANUAL_
BYPASS
R/W
R/W
R/W
0
0 = Disable retimer bypass
1 = Enable retimer bypass
Selects between auto and manual
control of retimer bypass for cable
driver output1 (SDO1)
CTRL_OUTPUT1_
RETIMER_AUTO_
BYPASS
2
1
1
0
0 = Disable auto mode
1 = Enable auto mode
CONTROL_
RETIMER_
BYPASS
4C
Controls retimer bypass for cable driver
output0 (SDO0), when auto mode is
disabled
(CTRL_OUTPUT0_RETIMER_AUTO_BYPA
SS = 0).
CTRL_OUTPUT0_
RETIMER_MANUAL_
BYPASS
0 = Disable retimer bypass
1 = Enable retimer bypass
Selects between auto and manual
control of retimer bypass for cable
driver output0 (SDO0)
CTRL_OUTPUT0_
RETIMER_AUTO_
BYPASS
0
R/W
R/W
1
0
0 = Disable auto mode
1 = Enable auto mode
RSVD
15:2
Reserved - do not modify.
Enable or Disable balanced mode on
cable driver output1 (SDO1) for
powered output return loss
measurement.
CTRL_OUTPUT1_
BALANCED
1
R/W
0
0 = Disable
1 = Enable
CONTROL_
BALANCED_
MODE
4D
Enable or Disable balanced mode on
cable driver output 0 (SDO0) for
powered output return loss
measurement.
CTRL_OUTPUT0_
BALANCED
0
R/W
R/W
0
0
0 = Disable
1 = Enable
4E to 4F
RSVD
RSVD
15:0
Reserved - do not modify.
GS12281
Final Data Sheet
80 of 97
Semtech
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Rev.9
Proprietary & Confidential
PDS-061385
February 2019
Table 5-3: Control Register Descriptions (Continued)
Reset
Value
Register
Name
Bit
Slice
Address
Parameter Name
R/W
Description
h
h
Diagnostic Control Features
RSVD
15
R/W
0
0
Reserved - do not modify.
Adjusts the phase of the clock to the
PRBS checker:
0 = 0
1 = 90
2 = 180
3 = 270
CFG_PRBS_CHECK_
PHASEADJUST
14:13
R/W
Note: A setting of 0 is ideal for most
applications. Adjustment is not
expected.
Optionally inverts the retimed data at
the input to the PRBS checker:
CFG_PRBS_CHECK_
INVERT
12
R/W
0
0 = no inversion
1 = data inverted
PRBS_
CHK_CFG
50
Selects pre-divider for PRBS check
measurement timer:
setting = pre-divider value
0 = 4
1 = 8
2 = 16
3 = 32
4 = 64
CFG_PRBS_CHECK_
PREDIVIDER
11:8
R/W
0
5 = 128
6 = 256
7 = 512
8 = 1024
9 = 2048
Selects PRBS check measurement
interval for timed measurements.
See Section 4.4.1 for more details.
CFG_PRBS_CHECK_
MEAS_TIME
7:0
R/W
3
GS12281
Final Data Sheet
81 of 97
Semtech
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PDS-061385
February 2019
Table 5-3: Control Register Descriptions (Continued)
Reset
Value
Register
Name
Bit
Slice
Address
Parameter Name
RSVD
R/W
Description
h
h
15:9
R/W
0
0
0
Reserved - do not modify.
Selects between timed and continuous
PRBS check mode.
CTRL_PRBS_CHECK_
TIMED_CONT_B
8
R/W
R/W
0 = Selects continuous PRBS check
mode.
1 = Selects timed PRBS check mode.
RSVD
7:1
Reserved - do not modify.
PRBS_CHK_
CTRL
51
Set to 1 by host to start a timed
operation.
Set to 0 by host after completion or
abort of the operation (by the device
due to loss of lock) to tell the device that
PRBS result has been read by the host.
CTRL_PRBS_CHECK_
START
0
R/W
R/W
0
0
See Section 4.4 for more details on PRBS
checker function.
RSVD
15:10
Reserved - do not modify.
Selects whether the PRBS generator is
enabled or not:
0 = PRBS Generator disabled
1 = PRBS Generator enabled
Note: enabling the PRBS generator does
not automatically override other device
modes such as auto-sleep,
CTRL_PRBS_GEN_
ENABLE
9
R/W
0
auto-output-mute,auto-output-disable,
etc. These continue to function
normally. The user/host may need to
adjust those settings to ensure the part
will output the PRBS signal.
PRBS_GEN_
CTRL
52
Select output signal from PRBS
generator as either PRBS7 or divided
clock (divided version of the PRBS
generator clock source):
CTRL_PRBS_GEN_
SIGNAL_SELECT
8
R/W
R/W
1
0
0 = clock divider (using ratio set by
CTRL_PRBS_GEN_CLK_DIVIDER)
1 = PRBS7
Selects clock source for PRBS generator:
0 = VCO (free running)
1 = Reserved
2 = Reserved
CTRL_PRBS_GEN_
CLK_SRC
7:6
3 = Data reference PLL (CDR recovered
clock)
GS12281
Final Data Sheet
82 of 97
Semtech
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Rev.9
Proprietary & Confidential
PDS-061385
February 2019
Table 5-3: Control Register Descriptions (Continued)
Reset
Value
Register
Name
Bit
Slice
Address
Parameter Name
R/W
Description
h
h
Selects clock divider ratio for when host
selects divided clock to output on PRBS
generator
(CTRL_PRBS_GEN_SIGNAL_SELECT = 0):
CTRL_PRBS_GEN_
CLK_DIVIDER
5:4
R/W
0
0
0 = divide by 2
1 = divide by 4
2 = divide by 8
3 = divide by 16
Controls optional inversion of the
generated PRBS pattern:
CTRL_PRBS_GEN_
INVERT
3
R/W
0 = true sense
1 = inverted
Select PRBS7 data rate when PRBS clock
source not recovered clock
(CTRL_PRBS_GEN_CLK_SRC ≠ 3)
0 = Reserved - do not use.
1 = MADI
PRBS_GEN_
CTRL
(Continued)
52
(Continued)
2 = SD
3 = HD
4 = 3G
5 = 6G
6 = 12G
7 = Reserved - do not use.
CTRL_PRBS_GEN_
DATA_RATE
2:0
R/W
6
If CTRL_PRBS_GEN_CLK_SRC = 3, then
CTRL_PRBS_GEN_DATA_RATE setting
has no effect and the CDR rate is used
(based on automatic rate detection or
manual rate selection).
Additionally, if the device is locked to an
input signal, only the same rate can be
selected for the PRBS generator.
53
54
RSVD
RSVD
15:0
15:0
R/W
R/W
0
0
Reserved - do not modify.
CFG_EYE_MON_TIMEOUT[31:16]. Most
significant 16 bits of the measurement
time. This is the time spent measuring
bit errors at each point in the eye scan,
i.e. the time to measure one point in the
eye. Units are in microseconds. The Eye
Scanner scans each point twice and
there is some overhead, so the actual
measurement time is twice the number
entered.
CFG_EYE_MON_
TIMEOUT_MS
EYE_MON_
INT_CFG_0
GS12281
Final Data Sheet
83 of 97
Semtech
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Rev.9
Proprietary & Confidential
PDS-061385
February 2019
Table 5-3: Control Register Descriptions (Continued)
Reset
Value
Register
Name
Bit
Slice
Address
Parameter Name
R/W
Description
h
h
CFG_EYE_MONT_TIMEOUT[15:0] Least
significant 16 bits of the measurement
time.
CFG_EYE_MON_
TIMEOUT_LS
EYE_MON_
INT_CFG_1
55
15:0
15:0
R/W
64
64
See CFG_EYE_MON_ TIMEOUT_MS
Threshold of bit error counts to define
good vs bad points in eye for shape
scan.
CFG_EYE_BER_
THRESHOLD
EYE_MON_
INT_CFG_2
56
R/W
R/W
See Section 4.5 for further details.
The vertical offset slice that will be used
for eye shape queries.
Offset values: 0 to 255d.
CFG_EYE_DEFAULT_
VERT_OFFSET
15:8
80
0 represents the most negative slice
since 128d is the 0V slice level and 255d
is the most positive slice level.
Default is 128d
EYE_MON_
INT_CFG_3
57
RSVD
7:3
2
R/W
R/W
0
0
Reserved - do not modify.
Eye monitor initialization bit. Set HIGH
during Device Power-Up Sequence. See
Section 4.9.12 for details.
CFG_EYE_INIT_RESET
RSVD
RSVD
RSVD
RSVD
1:0
15:0
15:0
15
R/W
R/W
R/W
R/W
2
D982
100
0
Reserved - do not modify.
Reserved - do not modify.
Reserved - do not modify.
Reserved - do not modify.
58
59
RSVD
RSVD
Starting phase offset.
Valid range is 0 to 127d.
CTRL_EYE_PHASE_
START
14:8
7
R/W
R/W
0
0
Reset value must be used for shape
scan.
EYE_MON_
SCAN_CTRL_0
5A
RSVD
Reserved - do not modify.
Phase offset limit. Valid range is 0 to
127d. CTRL_EYE_PHASE_STOP must be
greater or equal to
CTRL_EYE_PHASE_START. Reset value
must be used for shape scan.
CTRL_EYE_PHASE_
STOP
6:0
R/W
7F
GS12281
Final Data Sheet
84 of 97
Semtech
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Rev.9
Proprietary & Confidential
PDS-061385
February 2019
Table 5-3: Control Register Descriptions (Continued)
Reset
Value
Register
Name
Bit
Slice
Address
Parameter Name
RSVD
R/W
Description
h
h
15
R/W
0
Reserved - do not modify.
Unsigned value for phase step size.
Valid values are 1,2, and 4.
Reset value must be used for shape
scan.
CTRL_EYE_PHASE_
STEP
14:8
R/W
1
Behaviour is undefined for other values.
In order to use a step size of 2 or 4,
CTRL_EYE_PHASE_START and
CTRL_EYE_PHASE_STOP must be set to
their default values.
EYE_MON_
SCAN_CTRL_1
5B
RSVD
7
R/W
R/W
0
0
Reserved - do not modify.
Starting voltage offset.
Valid range is 0 to 255d.
CTRL_EYE_VERT_
OFFSET_START
6:0
Voltage offset limit.
Valid range is 0 to 255d.
CTRL_EYE_VERT_OFFSET_STOP must be
greater or equal to
CTRL_EYE_VERT_
OFFSET_STOP
CTRL_EYE_VERT_OFFSET_START. Reset
value must be used for shape scan.
In order to use a step size of 2 or 4,
CTRL_EYE_VERT_ OFFSET_START and
CTRL_EYE_VERT_ OFFSET_STOP must
be set to their default values.
15:8
R/W
FF
EYE_MON_
SCAN_CTRL_2
5C
RSVD
7
R/W
R/W
0
1
Reserved - do not modify.
Unsigned value for voltage offset step
size.
Valid values are 1,2, and 4.
Behaviour is undefined for other values.
CTRL_EYE_VERT_
OFFSET_STEP
6:0
GS12281
Final Data Sheet
85 of 97
Semtech
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PDS-061385
February 2019
Table 5-3: Control Register Descriptions (Continued)
Reset
Value
Register
Name
Bit
Slice
Address
Parameter Name
RSVD
R/W
Description
h
h
15:9
R/W
0
0
0
Reserved - do not modify.
Selects whether the eye monitor should
perform an eye scan or eye shape
capture:
CTRL_EYE_SHAPE_
SCAN_B
8
R/W
R/W
0 = Selects eye scan (new or continued).
1 = Selects eye shape capture.
RSVD
7:2
Reserved - do not modify.
Power control for the eye monitor:
0 = Power down the eye monitor
1 = Power up the eye monitor
Host is permitted to change this any
time between eye scans (but not
between partial eye scans).
CTRL_EYE_MON_
POWER_CTRL
1
R/W
0
EYE_MON_
SCAN_CTRL_3
5D
This must be set to 1 to run an eye scan.
Behaviour is undefined if host sets
CTRL_EYE_MON_START = 1 without
setting this bit to 1.
Part of a four way handshake with
STAT_EYE_MON_STATUS:
0 = Set by host to tell the device to clear
the status bit.
1 = Set by host only in order to
begin/continue an eye scan or start an
eye shape capture.
CTRL_EYE_MON_START
0
R/W
—
0
See Section 4.5 for more details on
implementing the four way hand shake
for this operation.
5E to 5F
60 to 7E
RSVD
RSVD
RSVD
RSVD
15:0
—
—
Reserved.
Factory Settings
15:0
—
Reserved.
GS12281
Final Data Sheet
86 of 97
Semtech
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PDS-061385
February 2019
Table 5-4: Status Register Descriptions
Register
Name
Bit
Slice
Reset
Value
Address
Parameter Name
RSVD
R/W
Description
80
RSVD
15:0
15:0
RO
—
Reserved.
This register contains the first part of
the device configuration version. Please
contact your local technical sales
representative for more details.
81
82
83
VERSION_0
VERSION_1
VERSION_2
STAT_CONFIG_VER0
STAT_CONFIG_VER1
STAT_HW_VERSION
RO
RO
RO
—
This register contains the second part of
the device configuration version. Please
contact your local technical sales
representative for more details.
15:0
15:0
—
—
This register contains the devices
identification, including revision. Please
contact your local technical sales
representative for more details.
Count of primary carrier detection
status changes since last cleared.
The count saturates at 255d (0xFF).
See Section 4.9.11 for procedure to clear
the counts.
STAT_CNT_PRI_CD_
CHANGES
15:8
7:0
RO
RO
RO
—
—
—
STICKY_
84
COUNTS_0
RSVD
Reserved.
Count of PLL rate changes since last
cleared.
The count saturates at 255d (0xFF).
See Section 4.9.11 for procedure to clear
the counts.
STAT_CNT_RATE_
CHANGES
15:8
STICKY_
COUNTS_1
85
Count of PLL lock status changes since
last cleared.
The count saturates at 255d (0xFF).
See Section 4.9.11 for procedure to clear
the counts.
STAT_CNT_PLL_
LOCK_CHANGES
7:0
RO
—
GS12281
Final Data Sheet
87 of 97
Semtech
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Proprietary & Confidential
PDS-061385
February 2019
Table 5-4: Status Register Descriptions (Continued)
Register
Name
Bit
Slice
Reset
Value
Address
Parameter Name
RSVD
R/W
Description
15
RO
—
Reserved
Clear counts status:
0 = Idle
1 = Reserved
2 = Indicates device has cleared the
sticky counts
3 = Reserved.
STAT_CLEAR_COUNTS_
STATUS
14:13
RO
—
Part of a four-way handshake with
CTRL_CLEAR_COUNTS.
See Section 4.9.11 for more details on
implementing the four way handshake
for this operation.
PLL lock status:
0 = PLL is unlocked
1 = PLL is locked
STAT_LOCK
12
RO
—
Sleep status:
0 = Device is not in sleep
1 = Device is currently in sleep
STAT_SLEEP
RSVD
11
RO
RO
—
—
10:8
Reserved
Cable driver output1 (SDO1) output
status:
0 = Mission Cable Driver SD/MADI slew
CURRENT_
STATUS_0
86
rate
1 = Mission Cable Driver HD/3G slew
rate
STAT_OUTPUT1_MODE
7:4
RO
—
2 = Mission Cable Driver 6G/12G slew
rate
3 = Reserved
4 = Reserved
5 = Balanced
6 = Mute
7 = Disabled
cable driver output0 (SDO0) output
status:
0 = Mission Cable Driver SD/MADI slew
rate
1 = Mission Cable Driver HD/3G slew
rate
STAT_OUTPUT0_MODE
3:0
RO
—
2 = Mission Cable Driver 6G/12G slew
rate
3 = Reserved
4 = Reserved
5 = Balanced
6 = Mute
7 = Disabled
GS12281
Final Data Sheet
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Rev.9
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February 2019
Table 5-4: Status Register Descriptions (Continued)
Register
Name
Bit
Slice
Reset
Value
Address
Parameter Name
R/W
Description
Cable driver output1 (SDO1) disable
status:
0 = SDO1 is not disabled
1 = SDO1 is disabled
STAT_OUTPUT1_
DISABLE
15
14
13
12
RO
—
—
—
—
Cable driver output0 (SDO0) disable
status:
0 = SDO0 is not disabled
1 = SDO0 is disabled
STAT_OUTPUT0_
DISABLE
RO
RO
RO
Cable driver output1 (SDO1) mute
status:
0 = SDO1 is not muted
1 = SDO1 is muted
STAT_OUTPUT1_
MUTE
Cable driver output0 (SDO0) mute
status:
0 = SDO0 is not muted
STAT_OUTPUT0_
MUTE
1 = SDO0 is muted
Cable driver output1 (SDO1) re-timer
status:
0 = Retimer path to SDO1 is not
bypassed
1 = Retimer path to SDO1 is bypassed
STAT_OUTPUT1_
RETIMER_BYPASS
11
10
RO
RO
—
—
CURRENT_
STATUS_1
87
Cable driver output0 (SDO0) re-timer
status:
0 = Retimer path to SDO0 is not
STAT_OUTPUT0_
RETIMER_BYPASS
bypassed
1 = Retimer path to SDO0 is bypassed
RSVD
9
8
7
RO
RO
RO
—
—
—
Reserved
Primary carrier detection status.
0 = Primary carrier is not detected
1 = Primary carrier is detected
STAT_PRI_CD
RSVD
Reserved
The current slew rate of cable driver
output1 (SDO1):
0 = SD/MADI slew
1 = HD/3G slew
2 = 6G/12G slew
STAT_OUTPUT1_
SLEW_RATE
6:5
4:3
RO
RO
—
—
The current slew rate of cable driver
output0 (SDO0):
0 = SD/MADI slew
STAT_OUTPUT0_
SLEW_RATE
1 = HD/3G slew
2 = 6G/12G slew
GS12281
Final Data Sheet
89 of 97
Semtech
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Rev.9
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PDS-061385
February 2019
Table 5-4: Status Register Descriptions (Continued)
Register
Name
Bit
Slice
Reset
Value
Address
Parameter Name
R/W
Description
Rate at which the CDR is locked.
0 = Unlocked
1 = MADI (125Mb/s)
2 = SD (270Mb/s)
3 = HD (1.485Gb/s)
4 = 3G (2.97Gb/s)
5 = 6G (5.94Gb/s)
6 = 12G (11.88Gb/s)
7 = Reserved
CURRENT_
STATUS_1
(Continued)
87
STAT_DETECTED_RATE
2:0
RO
—
(Continued)
88
89
RSVD
RSVD
15:0
15:0
RO
RO
RO
—
—
—
Reserved
PRBS checker error count. Cleared to 0
at the start of a measurement. Updated
by the device on completion of a
measurement. Value is undefined in
case of abort due to loss of CDR lock
(STAT_PRBS_CHECK_LAST_ABORT = 1).
PRBS_
CHK_
ERR_CNT
STAT_PRBS_CHK_
ERR_CNT
RSVD
15:10
Reserved
0 = Normal
1 = No data transitions were seen
during the previous PRBS check. This bit
is set to 1 to indicate that the input data
was all 0's during a PRBS check. When
that happens, the error count will be
zero when in fact there was no valid
PRBS pattern.This bit is updated by the
device on completion of a
STAT_PRBS_CHECK_
NODATA
9
RO
—
measurement. It retains its value until
the next PRBS check operation is
requested. Value is undefined in case of
abort
PRBS_
CHK_STATUS
8A
(STAT_PRBS_CHECK_LAST_ABORT = 1).
Value does not increment during a
measurement until it completes.
PRBS abort status.
0 = Normal.
1 = PRBS check was aborted due to loss
of lock or sleep.
This bit retains its value until the next
PRBS operation is requested.
STAT_PRBS_CHECK_
LAST_ABORT
8
RO
RO
—
—
RSVD
7:2
Reserved
GS12281
Final Data Sheet
90 of 97
Semtech
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Rev.9
Proprietary & Confidential
PDS-061385
February 2019
Table 5-4: Status Register Descriptions (Continued)
Register
Name
Bit
Slice
Reset
Value
Address
Parameter Name
R/W
Description
Status for PRBS checker:
0 = PRBS check idle; ready for new
operation.
1 = PRBS check timed or continuous
operation in progress.
2 = PRBS check timed operation
completed (success)
PRBS_
CHK_STATUS
(Continued)
STAT_PRBS_CHECK_
STATUS
3 = PRBS check timed or continuous
operation aborted (error) Part of a four
way handshake with
8A
(Continued)
1:0
RO
—
CTRL_PRBS_CHECK_START
(Section 4.4). Abort will be reported if
loss of lock or sleep occurred during a
PRBS check operation or those
conditions existed when the operation
was requested by the host.
EYE_MON_
SCAN_
The size in bytes of the last partial scan
segment.
8B
8C
STAT_EYE_IMAGE_SIZE
15:0
15:8
RO
RO
—
—
SIZE_OUTPUT
Left Edge Voltage Offset returned from
shape scan.
Offset values 0 to 255d, 0 represents
most negative voltage, 127d is 0V 255d
is most positive voltage.
STAT_EYE_SHAPE_
LEFT_EDGE_OFFSET
EYE_MON_
SHAPE_
OUTPUT_0
Left Edge Phase returned from shape
scan.
Phase values 0 to 127d.
STAT_EYE_SHAPE_
LEFT_EDGE_PHASE
7:0
15:8
7:0
RO
RO
RO
RO
RO
—
—
—
—
—
Positive (top) Edge Voltage Offset
returned from shape scan.
Offset values 0 to 255d, 0 represents
most negative voltage, 127d is 0V 255d
is most positive voltage.
STAT_EYE_SHAPE_
POS_EDGE_OFFSET
EYE_MON_
SHAPE_
OUTPUT_1
8D
Positive (top) Edge Phase returned from
shape scan.
Phase values 0 to 127d.
STAT_EYE_SHAPE_
POS_EDGE_PHASE
Right Edge Voltage Offset returned
from shape scan.
Offset values 0 to 255d, 0 represents
most negative voltage, 127d is 0V 255d
is most positive voltage.
STAT_EYE_SHAPE_
RIGHT_EDGE_OFFSET
15:8
7:0
EYE_MON_
SHAPE_
OUTPUT_2
8E
Right Edge Phase returned from shape
scan.
Phase values 0 to 127d.
STAT_EYE_SHAPE_
RIGHT_EDGE_PHASE
GS12281
Final Data Sheet
91 of 97
Semtech
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Proprietary & Confidential
PDS-061385
February 2019
Table 5-4: Status Register Descriptions (Continued)
Register
Name
Bit
Slice
Reset
Value
Address
Parameter Name
R/W
Description
Negative (bottom) Edge Voltage Offset
returned from shape scan.
Offset values 0 to 255d, 0 represents
most negative voltage, 127d is 0V 255d
is most positive voltage.
STAT_EYE_SHAPE_
NEG_EDGE_OFFSET
15:8
RO
—
EYE_MON_
SHAPE_
OUTPUT_3
8F
Negative (bottom) Edge Phase returned
from shape scan.
Phase values 0 to 127d.
STAT_EYE_SHAPE_
NEG_EDGE_PHASE
7:0
RO
RO
—
—
RSVD
15:9
Reserved
Full scan status:
0 = Full scan complete.
1 = Partial scan complete.
On completion of an eye monitor eye
scan (CRTL_EYE_SHAPE_SCAN_B = 0),
indicates whether the eye monitor
completed the full scan or a partial scan.
Undefined for eye shape scan
STAT_EYE_SCAN_
PARTIAL_OR_FULL
8
RO
RO
—
—
(CTRL_EYE_SHAPE_SCAN_B = 1).
RSVD
7:2
Reserved
EYE_MON_
STATUS
Eye monitor status:
0 = Eye monitor idle; ready for new
90
operation
1 = Eye monitor operation in progress
2 = Eye monitor operation completed
(success)
3 = Eye monitor operation aborted
(error). Part of a four way handshake
with CTRL_EYE_MON_START, see
Section 4.5 for procedure. Abort will be
reported by device if loss of lock or
sleep occurred during an eye monitor
operation or those conditions existed
when the operation was requested by
the host.
STAT_EYE_MON_
STATUS
1:0
RO
—
—
91 - BF
RSVD
RSVD
15:0
—
Reserved
GS12281
Final Data Sheet
92 of 97
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February 2019
6. Application Information
6.1 Typical Application Circuit
VCC1V8
VCC1V8
29
470nF
10μF
100nF
10μF
40
39 38
37
36
35
34
33
32 31
30
1
2
3
VEE_DDI
28
VEEO
RSVD
RSVD
4.7μF
4.7μF
27
26
SDO0
75Ω
SDO0
VCC1V8
Note: Pins 24/25 both
require a 100nF capacitor
VCC3V3
25
24
VCC_DDI
TERM
DDI
4
5
VCCO_0
VCCO_1
GS12281
1μF
2x 100nF
Note: The device central paddle is not an electrical
connection. Refrain from connecting device pins to
the central paddle.
4.7μF
4.7μF
100nF
23
22
SDO1/RCO
75Ω
6
7
8
IN
IN
SDO1/RCO
VEEO
21
DDI
VEE_DDI
9
10
11
12
13 14
15
16
17
18
19
20
VCC1V8
100nF
VCC1V8
100nF
Figure 6-1: Typical Application Circuit
Note 1: 4.7μF AC-coupling capacitors are required on SDO0/SDO0 and SDO1/RCO
SDO1/RCO.
Note 2: It is recommended that separate filtered supplies are used for the following
three groups: (VCC_DDI, VCC_CORE), (VCCO1P8_0, VCCO1P8_1, VDD), (VCCO_0,
VCCO_1). Multiple devices can share the same filtered supply plane. Contact your local
technical representative for layout recommendations to achieve optimal performance.
Note 3: Existing designs with pin 30 connected to ground through a 10μF capacitor may
be left unchanged. This capacitor may be populated or removed at the designer's
discretion, with no impact on device performance.
GS12281
Final Data Sheet
93 of 97
Semtech
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PDS-061385
February 2019
7. Package & Ordering Information
7.1 Package Dimensions
DIMENSIONS
A
D
MILLIMETERS
MIN NOM MAX
0.80 0.90 1.00
B
E
DIM
A
0.05
0.02
A1 0.00
A2
(0.02)
0.15
b
0.20 0.25
5.95 6.00 6.05
PIN 1
INDICATOR
D
(LASER MARK)
D1 3.45 3.60 3.70
3.95 4.00 4.05
E
E1 1.43 1.58 1.68
e
L
N
0.40 BSC
0.30 0.40 0.50
40
aaa
bbb
0.08
0.10
A
SEATING
PLANE
aaa C
C
A1
A2
D1
LxN
E/1
E1
2
1
N
bxN
0.30 x 45°
e/2
bbb
C A B
e
D/2
NOTES:
1. CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES).
2. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS.
3. DIMENSION OF LEAD WIDTH APPLIES TO TERMINAL AND IS MEASURED BETWEEN
0.15 to 0.30mm FROM THE TERMINAL TIP.
Figure 7-1: Package Dimensions
GS12281
Final Data Sheet
94 of 97
Semtech
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Rev.9
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PDS-061385
February 2019
7.2 Recommended PCB Footprint
0.20
0.60
Pin #1
3.60
0.40
5.20
Figure 7-2: Recommended PCB Footprint
7.3 Packaging Data
Table 7-1: Packaging Data
Parameter
Value
Package Type
6mm x 4mm 40-pin QFN
Moisture Sensitivity Level
3
Junction to Air Thermal Resistance, j-a (at zero airflow)
Junction to Board Thermal Resistance, j-b
Junction to Case Thermal Resistance, j-c
40.0°C/W
32.0°C/W
36.0°C/W
<1.0°C/W
Yes
Junction-to-Top Characterization Parameter, Psi,
Pb-free and RoHS compliant
GS12281
Final Data Sheet
95 of 97
Semtech
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PDS-061385
February 2019
7.4 Marking Diagram
Pin 1
Indicator
XXXX - Last 4 digits of Assembly lot
E3 - Pb-free & Green indicator
YYWW - Date Code
GS12281
XXXXE3
YYWW
Figure 7-3: Marking Diagram
7.5 Solder Reflow Profiles
Temperature
60-150 sec.
20-40 sec.
260°C
250°C
3°C/sec max
217°C
6°C/sec max
200°C
150°C
25°C
Time
60-180 sec. max
8 min. max
Figure 7-4: Maximum Pb-free Solder Reflow Profile
7.6 Ordering Information
Table 7-2: Ordering Information
Minimum Order
Part Number
Format
Quantity
GS12281-INE3
GS12281-INTE3
GS12281-INTE3Z
490
250
Tray
Tape and Reel
Tape and Reel
2500
GS12281
Final Data Sheet
96 of 97
Semtech
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Rev.9
Proprietary & Confidential
PDS-061385
February 2019
IMPORTANT NOTICE
Information relating to this product and the application or design described herein is believed to be reliable, however such information is
provided as a guide only and Semtech assumes no liability for any errors in this document, or for the application or design described herein.
Semtech reserves the right to make changes to the product or this document at any time without notice. Buyers should obtain the latest relevant
information before placing orders and should verify that such information is current and complete. Semtech warrants performance of its
products to the specifications applicable at the time of sale, and all sales are made in accordance with Semtech’s standard terms and conditions
of sale.
SEMTECH PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS,
DEVICES OR SYSTEMS, OR IN NUCLEAR APPLICATIONS IN WHICH THE FAILURE COULD BE REASONABLY EXPECTED TO RESULT IN PERSONAL
INJURY, LOSS OF LIFE OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE. INCLUSION OF SEMTECH PRODUCTS IN SUCH APPLICATIONS IS
UNDERSTOOD TO BE UNDERTAKEN SOLELY AT THE CUSTOMER’S OWN RISK. Should a customer purchase or use Semtech products for any such
unauthorized application, the customer shall indemnify and hold Semtech and its officers, employees, subsidiaries, affiliates, and distributors
harmless against all claims, costs damages and attorney fees which could arise.
The Semtech name and logo are registered trademarks of the Semtech Corporation. All other trademarks and trade names mentioned may be
marks and names of Semtech or their respective companies. Semtech reserves the right to make changes to, or discontinue any products
described in this document without further notice. Semtech makes no warranty, representation or guarantee, express or implied, regarding the
suitability of its products for any particular purpose. All rights reserved.
© Semtech 2019
Contact Information
Semtech Corporation
200 Flynn Road, Camarillo, CA 93012
Phone: (805) 498-2111, Fax: (805) 498-3804
www.semtech.com
GS12281
Final Data Sheet
97 of 97
Semtech
Rev.9
97Proprietary & Confidential
PDS-061385
February 2019
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