GS6150-INTE3Z_技术文档

GS6150

GS6150 Multi-Rate 6G UHD-SDI

Reclocker

Gennum Products

Key Features

Applications

•

SMPTE ST 2081, ST 424, ST 292, and

ST 259-C compliant

•

SMPTE ST 2081, SMPTE ST 424,

SMPTE ST 292, SMPTE ST 259-C coaxial cable serial

digital interfaces

•

Supports retiming data at rates of 125Mb/s, 270Mb/s,

1.485 and 1.485/1.001Gb/s, 2.97 and 2.97/1.001Gb/s,

5.94 and 5.94/1.001Gb/s

•

EN50083-9 DVB-ASI interfaces

MADI standard

•

Supports retiming of DVB-ASI signals

Automatic or Manual Rate Selection

Description

Detected rate indication in Auto Mode

4:1 input selector patented technology

Option of two reclocked data outputs

The GS6150 is a low-power, multi-rate serial digital

reclocker designed to automatically recover the embedded

clock from a digital video signal and re-time the incoming

video data.

•

Four configurable GPIO pins with ability to output

device status, including:

The GS6150 will recover the embedded clock signal and re-

time the data from 6G UHD-SDI signals compliant with

SMPTE ST 2081. In addition, it can also re-time SMPTE ST

259-C, SMPTE ST 292, SMPTE ST 424 or DVB-ASI compliant

digital video signals as well as MADI audio streams.

Lock Detect

Loss of Signal (LOS)

Low/High bit-rate indication for slew-rate control of

SDI cable drivers

•

On-chip 100Ω differential input and output

termination

The GS6150 features four high-speed differential signal

inputs feeding a 4:1 input selector. Input termination is on-

chip for seamless matching to 100Ω differential

transmission lines. The input selector is a component of a

video switching system with tightly constrained timing

requirements.

Bypass support for rates up to 5940Mb/s

Manual Bypass function

Configurable automatic Bypass when not locked

•

Option to use external reference or operate

referenceless

The GS6150 includes programmable trace equalization to

compensate for high-frequency losses associated with

board-level interconnect.

Cascading reference buffer supports multiple

reclockers using a single reference source

Two CML outputs interface seamlessly to devices with a

CML input reference between 1.2V and 2.5V.

Input signal equalization and output signal

de-emphasis to compensate for trace dielectric losses

Programmable output swing and de-emphasis provide

flexibility in managing signal integrity of the output signals.

•

Single power supply operation at 1.8V

130mW typical power consumption (150mW with

second output enabled)

The GS6150 can operate in either automatic rate detection

or manual rate selection mode. In auto mode the device

will automatically detect and lock onto incoming data

signals at any supported rate.

•

Pb-free and RoHS compliant

Operating temperature range: -40°C to 85°C

GS6150

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The device can operate without an external 27MHz

frequency reference. For applications which require rapid

signal lock, an external 27MHz reference may be used to set

the VCO frequency when not locked to the input signal. The

presence of an external reference crystal is automatically

detected by the device.

A four-wire serial Gennum Serial Peripheral Interface (GSPI)

facilitates configuration and status monitoring of the

device. Multiple GS6150 devices can be daisy-chained

together with a single 4-pin connection to the host system.

This device is Pb-free, and the encapsulation compound

does not contain halogenated flame retardant. This

component and all homogenous sub-components are

RoHS compliant.

In systems that require passing of non-supported data

rates, the GS6150 can be configured to either automatically

or manually enter a bypass mode in order to pass the signal

without reclocking.

XTAL_CLK_OUT

XTAL_CLK_IN

XTAL_BUF_OUT

LF+, LF–

XTAL

Oscillator

Buﬀer

DDO0

Reference Divide

Data Buﬀer

DDO0

Retimer

Phase

Frequency

Detector

DDI0

Selectable

Divide

Charge Pump

VCO

DDI1

Equalizer/

Data Mux

Phase Detector

DDO1

DDI2

Data

Buﬀer

DDI3

LOS

Detect

SPI

Control

Oscillator

GPIO0 GPIO1 GPIO2 GPIO3

DDI_SEL[1:0]/

STROBE

GS6150 Functional Block Diagram

GS6150

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Revision History

Version

ECO

PCN

Date

Changes and/or Modifications

Updated Table 2-2 and Table 2-3.

Updated Section 4.11 and Section 5.

Updated to Final Data Sheet.

2

024967

—

March 2015

Changed product title. Updated

Table 5-1 format. Updates

1

022115

016784

—

September 2014 throughout Table 2-2 and Table 2-3.

Added Section 4.5.5. Updated

Table 5-1.

0

December 2013

New Document

Contents

1. Pin Out.................................................................................................................................................................5

1.1 Pin Assignment ...................................................................................................................................5

1.2 Pin Descriptions ..................................................................................................................................6

2. Electrical Characteristics............................................................................................................................. 10

2.1 Absolute Maximum Ratings ........................................................................................................ 10

2.2 DC Electrical Characteristics ........................................................................................................ 10

2.3 AC Electrical Characteristics ......................................................................................................... 12

3. Input/Output Circuits.................................................................................................................................. 15

4. Detailed Description.................................................................................................................................... 17

4.1 Serial Data Inputs ............................................................................................................................. 17

4.1.1 Input Trace Equalization................................................................................................... 17

4.1.2 Input Selection ..................................................................................................................... 17

4.2 Reference Clock ................................................................................................................................ 19

4.3 Signal Monitoring ............................................................................................................................ 19

4.3.1 Loss of Signal Detection.................................................................................................... 19

4.3.2 Lock Detection .................................................................................................................... 21

4.3.3 Rate Detection...................................................................................................................... 22

4.3.4 Low/High Bit Rate Detection for Slew Rate Control ............................................... 23

4.4 Low Power Modes ........................................................................................................................... 23

4.5 Serial Data Output ........................................................................................................................... 24

4.5.1 Output Impedance ............................................................................................................. 24

4.5.2 Output Signal Interface Levels ....................................................................................... 24

4.5.3 Adjustable Output Swing................................................................................................. 24

4.5.4 Output De-emphasis.......................................................................................................... 25

4.5.5 Output Common Mode Voltage.................................................................................... 26

4.6 Output Mute, Disable, and Data Selection ............................................................................. 26

4.7 Bypass Mode ..................................................................................................................................... 27

4.8 DVB-ASI ............................................................................................................................................... 27

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4.9 Device Power Up ............................................................................................................................. 27

4.9.1 Power on Reset (POR) ........................................................................................................ 27

4.9.2 Reset Pin (RST) ...................................................................................................................... 27

4.10 GPIO Pins Configuration ............................................................................................................. 27

4.11 GSPI Host Interface ....................................................................................................................... 29

4.11.1 CS Pin..................................................................................................................................... 29

4.11.2 SDIN Pin................................................................................................................................ 29

4.11.3 SDOUT Pin ........................................................................................................................... 29

4.11.4 SCLK Pin................................................................................................................................ 31

4.11.5 Command Word Description........................................................................................ 31

4.11.6 GSPI Transaction Timing ................................................................................................ 34

4.11.7 Single Read/Write Access............................................................................................... 36

4.11.8 Auto-increment Read/Write Access........................................................................... 37

4.11.9 Setting a Device Unit Address...................................................................................... 38

4.11.10 Default GSPI Operation ................................................................................................ 39

5. Host Interface Register Map...................................................................................................................... 41

6. Typical Application Circuit ........................................................................................................................ 60

7. Package and Ordering Information ....................................................................................................... 61

7.1 Package Dimensions ...................................................................................................................... 61

7.2 Recommended PCB Footprint .................................................................................................... 62

7.3 Packaging Data ................................................................................................................................ 62

7.4 Marking Diagram ............................................................................................................................. 63

7.5 Solder Reflow Profile ...................................................................................................................... 63

7.6 Ordering Information ..................................................................................................................... 63

GS6150

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1. Pin Out

1.1 Pin Assignment

48

47

46

45

44

43

42

41

40

39

38

37

1

36

35

34

33

32

31

30

29

28

27

26

25

DDI0

GND

DDI1

GND

DDI2

GND

DDI3

GPIO0

VCC_DDO0

VEE_DDO

DDO0

2

3

4

DDO0

5

VEE_DDO

DDO1

6

GS6150 48-pin QFN (6x6mm)

7

DDO1

8

VEE_DDO

VCC_DDO1

RST

9

10

11

12

GPIO3

GPIO2

13

14

15

16

17

18

19

20

21

22

23

24

Figure 1-1: GS6150 Pin Out

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1.2 Pin Descriptions

Table 1-1: GS6150 Pin Descriptions

Pin Number

Name

Type

Description

1, 2

3, 6, 9

4, 5

DDI0, DDI0

GND

Input

Power

Input

Serial Digital Differential Input 0.

Input channel isolation. Connect to ground or leave unconnected.

Serial Digital Differential Input 1.

DDI1, DDI1

DDI2, DDI2

DDI3, DDI3

7, 8

Serial Digital Differential Input 2.

10, 11

Serial Digital Differential Input 3.

Multi-function Control/Status Input/Output 0.

Signal options are:

LOS (output; default)

LOCKED

LBR_HBR

RATE_DET0

RATE_DET1

RATE_DET2

Digital

Input/Output

LOCKED_125M

LOCKED_270M

LOCKED_1G485

LOCKED_2G97

LOCKED_5G94

RATE_CHANGE

DDO0_DISABLE

DDO1_DISABLE

12

GPIO0

This pin is configured using the GPIO0_SELECT and

GPIO0_IO_SELECT bits in the GPIO_CONTROL_REG_0 register.

Multi-function Control/Status Input/Output 1.

Signal options are:

LOS

LOCKED (output; default)

LBR_HBR

RATE_DET0

RATE_DET1

RATE_DET2

Digital

Input/Output

LOCKED_125M

LOCKED_270M

LOCKED_1G485

LOCKED_2G97

LOCKED_5G94

RATE_CHANGE

DDO0_DISABLE

DDO1_DISABLE

13

GPIO1

This pin is configured using the GPIO1_SELECT and

GPIO1_IO_SELECT bits in the GPIO_CONTROL_REG_0 register.

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Table 1-1: GS6150 Pin Descriptions (Continued)

Pin Number

Name

Type

Description

Input selection control.

DDI_SEL0/STROBE,

DDI_SEL1

14, 15

Logic Input

Used to select the high-speed input for processing through the

device. Refer to Table 4-1 for details on input selection.

Reference Crystal Pin/27MHz clock input. Connect to an external

circuit as shown in Figure 6-1: GS6150 Typical Application Circuit or

to a digital clock source (XTAL_BUF_OUT of another GS6150 or

GS6151). Connect to ground if operating referenceless.

16

17

XTAL_CLK_IN

Input

Reference Crystal Pin. Connect to a external circuit as shown in Figure

6-1: GS6150 Typical Application Circuit, or leave unconnected if

XTAL_CLK_IN is driven by an external clock source or if XTAL_CLK_IN

is connected to ground (referenceless).

XTAL_CLK_OUT

Output

Buffered clock reference output. Leave unconnected if not used to

drive 27MHz clock input of another device.

18

19

XTAL_BUF_OUT

SDIN

Output

Serial digital data input for the Gennum Serial Peripheral Interface

(GSPI) host control/status port.

Digital Input

Refer to 4.11 GSPI Host Interface for more details.

Serial digital data output for the Gennum Serial Peripheral Interface

(GSPI) host control/status port.

Digital

Output

20

21

SDOUT

SCLK

Refer to 4.11 GSPI Host Interface for more details.

Burst-mode clock input for the Gennum Serial Peripheral Interface

(GSPI) host control/status port.

Digital Input

Refer to 4.11 GSPI Host Interface for more details.

Chip select input for the Gennum Serial Peripheral Interface (GSPI)

host control/status port.

22

CS

Active-low input.

Refer to 4.11 GSPI Host Interface for more details.

Most positive power supply for the internal logic

Connect to 1.8V.

23

24

VDD_DIG

VSS_DIG

Power

Most negative power supply for the internal logic

Connect to ground.

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Table 1-1: GS6150 Pin Descriptions (Continued)

Pin Number

Name

Type

Description

Multi-function Control/Status Input/Output 2.

Signal options are:

LOS

LOCKED

LBR_HBR (output; default)

RATE_DET0

RATE_DET1

RATE_DET2

Digital

Input/Output

LOCKED_125M

LOCKED_270M

LOCKED_1G485

LOCKED_2G97

LOCKED_5G94

RATE_CHANGE

DDO0_DISABLE

DDO1_DISABLE

25

GPIO2

This pin is configured using the GPIO2_SELECT and

GPIO2_IO_SELECT bits in the GPIO_CONTROL_REG_1 register.

Multi-function Control/Status Input/Output 3.

Signal options are:

LOS

LOCKED

LBR_HBR

RATE_DET0

RATE_DET1

RATE_DET2

Digital

LOCKED_125M

LOCKED_270M

LOCKED_1G485

LOCKED_2G97

LOCKED_5G94

RATE_CHANGE

DDO0_DISABLE

DDO1_DISABLE (input; default)

26

GPIO3

Input/Output

This pin is configured using the GPIO3_SELECT and

GPIO3_IO_SELECT bits in the GPIO_CONTROL_REG_1 register.

Reset pin. If set LOW, all blocks set to default conditions and inputs/

outputs set to high impedance. If HIGH, normal operation of the

device resumes. By default, internally pulled HIGH.

27

RST

Digital Input

Most positive power supply connection for the DDO1/DDO1 output

driver. Connect to any voltage between 1.2V and 2.5V.

28

VCC_DDO1

VEE_DDO

Power

Most negative power supply connections for the output drivers.

Connect to ground.

29, 32, 35

30, 31

33, 34

DDO1, DDO1

DDO0, DDO0

Output

Differential serial data output 1.

Differential serial data output 0.

Most positive power supply connection for the DDO0/DDO0 output

driver. Connect to any voltage between 1.2V and 2.5V.

36

VCC_DDO0

Power

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Table 1-1: GS6150 Pin Descriptions (Continued)

Pin Number

Name

Type

Description

Power

Decoupling

37

RSV_37

Connect through decoupling capacitor to ground.

38

39

RSV_38

RSV_39

Power

Input

Connect to 1.8V.

Connect to ground.

Leave unconnected.

40, 41

RSV_40, RSV_41

Most positive power supply connection to the analog core

Connect to 1.8V.

42

43

44

VCC_CORE

VEE_CORE

LF+

Power

Passive

Most negative power supply connection to the analog core

Connect to ground.

Connect to LF– through C_LF

Refer to Figure 6-1: GS6150 Typical Application Circuit.

Connect to LF+ through C_LF

Refer to Figure 6-1: GS6150 Typical Application Circuit.

45

46

47

LF–

Passive

Power

External decoupling for the VCO.

VCO_FILT

VCC_CORE

Refer to Figure 6-1: GS6150 Typical Application Circuit.

Most positive power supply connection for the analog core

Connect to 1.8V.

Most negative power supply connection to the analog core

Connect to ground.

48

—

VEE_CORE

Center Pad

Power

Ground pad on bottom of package.

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2. Electrical Characteristics

2.1 Absolute Maximum Ratings

Table 2-1: Absolute Maximum Ratings

Parameter

Value

–0.5 to +2.1V_DC

Supply Voltage – Core (VCC_CORE, VDD_DIG)

Supply Voltage – Output Driver (VCC_DDO0,

VCC_DDO1)

–0.5 to +2.8V_DC

Input ESD Voltage

4kV

Storage Temperature Range (T_S)

–50ºC to +125ºC

–40ºC to +85ºC

–0.3 to (V_{CC_CORE}+ 0.3)V_DC

+260ºC

Operating Temperature Range (T_A)

Input Voltage Range (any input pin)

Solder Reflow Temperature

Note: Absolute Maximum Ratings are those values beyond which damage may occur.

Functional operation outside of the ranges shown in the AC/DC electrical characteristics tables

is not guaranteed.

2.2 DC Electrical Characteristics

Table 2-2: DC Electrical Characteristics

VCC_CORE, VDD_DIG = +1.8V 5%, T_A= –40ºC to +85ºC unless otherwise specified

Parameter

Symbol Conditions

Min

Typ

Max

Units Notes

V_{CC_CORE}

V_{DD_DIG}

,

Supply Voltage – Core

(VCC_CORE, VDD_DIG)

—

1.710

1.8

1.890

V

Supply Voltage – Output

Driver (VCC_DDO0,

VCC_DDO1)

V_{CC_DDO0}

V_{CC_DDO1}

,

1.140

—

2.625

V

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Table 2-2: DC Electrical Characteristics (Continued)

VCC_CORE, VDD_DIG = +1.8V 5%, T_A= –40ºC to +85ºC unless otherwise specified

Parameter

Symbol Conditions

Min

Typ

Max

Units Notes

Data Rate 6G,

DDO1/DDO1 disabled

—

140

185

mW

1, 2

Data Rate <6G,

DDO1/DDO1 disabled

—

130

210

170

280

Data Rate 6G,

Default Settings,

DDO1/DDO1 enabled

mW

3, 4

P_D

Power

Data Rate <6G,

Default Settings,

DDO1/DDO1 enabled

—

190

255

3, 4

5

Maximum Supply and Power

Settings

—

280

20

360

35

mW

P_SLEEP

Power (Sleep operation)

—

Power (Standby

operation)

P_STANDBY

80

110

Output Swing Register

Setting = 0000_b

—

4.8

7.5

15

7

mA

6, 7

I_{CC_DDO0}

I_{CC_DDO1}

,

Output Swing Register

Setting= 0100_b

Supply Current - Output

Driver

12

22

Output Swing Register

Setting = 1100_b

Output De-emphasis

Disabled

Data Rate 6G

—

82

74

—

mA

8

Output De-emphasis

Disabled

I_{CC_CORE}

Supply Current - Core

Data Rate 3G

Output De-emphasis Enabled

Data Rate 6G

—

90

81

—

mA

8

Output De-emphasis Enabled

Data Rate 3G

I_{CC_DIG}

Supply Current - Digital

Serial Input Termination

Serial Output Termination

External Crystal Referenced

Differential

—

75

7

12

mA

Ω

100

125

Differential

Ω

V_{CC_CORE}

- 50mV

Serial Input Common

Mode Voltage

V_CMIN

—

0.9

—

V

9, 10

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Table 2-2: DC Electrical Characteristics (Continued)

VCC_CORE, VDD_DIG = +1.8V 5%, T_A= –40ºC to +85ºC unless otherwise specified

Parameter

Symbol Conditions

Min

Typ

Max

Units Notes

0.65*

VDD_DIG

V_IH

V_IL

—

VDD_DIG

V

Input Voltage - Digital

Pins

(CS, SDIN, CLK, GPIO[0:3])

0.35*

VDD_DIG

0

—

V

VDD_DIG

– 0.45

V_OH

V_OL

I_OH= -2mA

I_OL= 2mA

Output Voltage - Digital

Pins

(SDOUT, GPIO[0:3])

—

V

—

0.45

Notes:

1. Normal operation in referenceless mode, minimum output swing with de-emphasis disabled

2. VCC_DDO0/1 = 1.2V

3. The swing is default and de-emphasis is on

4. VCC_DDO0/1 = 1.8V

5. DDO0/DDO0 and DDO1/DDO1 set to maximum swing setting, external crystal reference used

6. Consumption per enabled DDO output

7. Refer to Table 4-3 for the exact register settings for each ΔV_DDOoutput swing listed

8. For two enabled outputs

9. Maximum input voltage level = 1.8V 5%

10. Up to a maximum swing of 800mV

2.3 AC Electrical Characteristics

Table 2-3: AC Electrical Characteristics

VCC_CORE, VDD_DIG = +1.8V 5%, T_A= –40ºC to +85ºC unless otherwise specified

Parameter

Symbol

DR_BYPASS

ΔV_SDI

Conditions

Min

Typ

Max

Units

Notes

Input Data Rate (Bypass)

Input Sensitivity

Bypass mode enabled

Differential

3

—

5940

800

Mb/s

1

mV_ppd

200

Output Swing Register

Setting = 0100_b

mV_ppd

310

600

410

800

510

2

ΔV_DDO

Output Voltage Swing

Output Swing Register

Setting = 1100_b

1000

Serial Input Jitter

Tolerance

Square wave

modulation

IJT

0.8

—

50

30

UI

Referenceless

ms

With External Reference

(MADI enabled)

PLL Lock Time —

Asynchronous

t_ALOCK

With External Reference

(MADI disabled)

—

20

ms

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Table 2-3: AC Electrical Characteristics (Continued)

VCC_CORE, VDD_DIG = +1.8V 5%, T_A= –40ºC to +85ºC unless otherwise specified

Parameter

Symbol

Conditions

Min

Typ

Max

Units

Notes

Referenceless

—

10

μs

PLL Lock Time —

Synchronous

t_SLOCK

With External Reference

20% ~ 80% rising edge

into 50Ω load

t_riseDDO

—

70

ps

Serial Data (DDO0 and

DDO1) Output Rise And

Fall Time

20% ~ 80% falling edge

into 50Ω load

t_fallDDO

Rise And Fall Time

Mismatch (DDO0 and

DDO1)

—

15

ps

—

Data Rate 6G

—

10

5

%

Duty Cycle Distortion

(DDO0 and DDO1)

Data Rate < 6G

t_OJ(125Mb/s)

UI_P-P

0.02

0.03

3, 4

t_OJ(270Mb/s)

t_OJ(1485Mb/s)

t_OJ(2970Mb/s)

t_OJ(5940Mb/s)

t_OJ(BYPASS)

UI_P-P

—

0.02

0.03

0.04

0.07

0.06

0.03

0.06

0.09

0.13

0.09

BW = Nominal

PRN 2²³– 1 test pattern

Serial Data Output Jitter

Intrinsic

PLL_LOOP_BANDWIDTH

= 00001

—

37

74

—

kHz

MHz

PLL_LOOP_BANDWIDTH

= 00010

PLL_LOOP_BANDWIDTH

= 00100 (default)

BW_{LOOP(125Mb/s)}

148

296

590

80

PLL_LOOP_BANDWIDTH

= 01000

PLL_LOOP_BANDWIDTH

= 10000

PLL Loop Bandwidth

PLL_LOOP_BANDWIDTH

= 00001

PLL_LOOP_BANDWIDTH

= 00010

160

320

640

1.28

PLL_LOOP_BANDWIDTH

= 00100 (default)

BW_{LOOP(270Mb/s)}

PLL_LOOP_BANDWIDTH

= 01000

PLL_LOOP_BANDWIDTH

= 10000

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Table 2-3: AC Electrical Characteristics (Continued)

VCC_CORE, VDD_DIG = +1.8V 5%, T_A= –40ºC to +85ºC unless otherwise specified

Parameter

Symbol

Conditions

Min

Typ

Max

Units

Notes

PLL_LOOP_BANDWIDTH

= 00001

—

438

—

kHz

PLL_LOOP_BANDWIDTH

= 00010

—

875

1.75

3.5

—

kHz

MHz

kHz

PLL_LOOP_BANDWIDTH

= 00100 (default)

BW_{LOOP(1485Mb/s)}

PLL_LOOP_BANDWIDTH

= 01000

PLL_LOOP_BANDWIDTH

= 10000

7

PLL_LOOP_BANDWIDTH

= 00001

875

1.75

3.5

PLL_LOOP_BANDWIDTH

= 00010

MHz

PLL_LOOP_BANDWIDTH

= 00100 (default)

BW_{LOOP(2970Mb/s)}

PLL Loop Bandwidth

PLL_LOOP_BANDWIDTH

= 01000

7.0

PLL_LOOP_BANDWIDTH

= 10000

14.0

1.75

3.5

PLL_LOOP_BANDWIDTH

= 00001

PLL_LOOP_BANDWIDTH

= 00010

PLL_LOOP_BANDWIDTH

= 00100 (default)

BW_{LOOP(5940Mb/s)}

7.0

PLL_LOOP_BANDWIDTH

= 01000

14.0

28.0

PLL_LOOP_BANDWIDTH

= 10000

Note:

1. Edge detection method for LOS detection should be used for data rates below 20Mb/s

2. Refer to Table 4-3 for the exact register settings for each ΔV_DDOoutput swing listed

3. Jitter measured using an oscilloscope according to SMPTE RP-184

4. Accumulated jitter measured peak to peak differential over 2000 hits

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3. Input/Output Circuits

VCC_DDO0/1

VCC_CORE

3.7kΩ

50Ω

RLC

DDO

DDI

18.5kΩ

Figure 3-1: DDI0, DDI0, DDI1, DDI1, DDI2, DDI2,

DDI3, DDI3 Serial Digital Differential Inputs

Figure 3-2: DDO0, DDO0, DDO1, DDO1 Serial Digital

Differential Output

VDD_DIG VDD_DIG

VDD_DIG

SDIN,

SCLK

SDOUT

100kΩ

Figure 3-3: SDIN and SCLK

Figure 3-4: SDOUT

VDD_DIG

100kΩ

CS

RST

Figure 3-6: RST

Figure 3-5: CS

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VDD_DIG

VDD_DIG VDD_DIG

DDI_SEL0,

DDI_SEL1

XTAL_BUF_OUT

100kΩ

Figure 3-8: XTAL_BUF_OUT

Figure 3-7: DDI_SEL0/STROBE and DDI_SEL1

VDD_DIG

1kΩ

GPIO

100kΩ

VDD_DIG

Note: GPIO Interface includes pins

GPIO0, GPIO1, GPIO2, and GPIO3

Figure 3-9: General Purpose Inputs/Outputs (GPIO)

VDD_DIG

EN

VDD_DIG

246Ω

XTAL_CLK_OUT

246Ω

XTAL_CLK_IN

EN

Figure 3-10: XTAL_CLK_IN and XTAL_CLK_OUT

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4. Detailed Description

The GS6150 is a multi-standard reclocker for serial digital SDTV SDI and DVB-ASI signals

operating at 270Mb/s, HDTV SDI signals operating at 1.485Gb/s and 1.485/1.001Gb/s,

3G SDI signals operating at 2.97Gb/s and 2.97/1.001Gb/s, and 6G UHD-SDI signals

operating at 5.94Gb/s and 5.94/1.001Gb/s and MADI audio streams at 125Mb/s.

4.1 Serial Data Inputs

The GS6150 features four 100Ω terminated differential input buffers.

A serial data input signal may be connected to any of the following input pin pairs of the

device: DDI0/DDI0, DDI1/DDI1, DDI2/DDI2, and DDI3/DDI3.

By default, the self-biasing circuit at the input is enabled to allow AC coupling to

upstream devices. To enable DC coupling of the inputs, the user must disable the self-

biasing network by setting bits 4:4 through 5:5 to 0 in the register 7 :

h

DDI[0:1]_TRACE_EQ_DC_TERM_ENABLE.

In order to select DC coupling, please ensure that the output common mode of the

upstream device is in range of the input common mode voltage range shown in

Table 2-2.

The serial digital input buffer is capable of operation with any binary coded signal that

meets the input signal level requirements defined below, with any data rate between

3Mb/s and 5.94Gb/s.

4.1.1 Input Trace Equalization

The GS6150 features adjustable trace equalization to compensate for PCB trace

dielectric losses up to half the maximum supported data rate, or 3GHz. The equalization

has three settings: the LOW (default) setting is optimized for compensating the high-

frequency losses associated with 0-7dB of trace loss at 1.5GHz for data rates of

2.97Gb/s and below, and for 0-10dB of trace loss at 3GHz for 5.94Gb/s. The HIGH setting

is optimized for trace loss between 7-14dB at 1.5GHz for data rates 2.97Gb/s and below.

The 0dB or EQ_BYPASS setting may be used in systems with negligible trace loss. These

settings are selected using the DDI0_TRACE_EQ_CONTROL,

DDI1_TRACE_EQ_CONTROL, DDI2_TRACE_EQ_CONTROL and

DDI3_TRACE_EQ_CONTROL bits in the INPUT_CONTROL_REG_0 register at address 5 .

h

The default state of the device is input trace equalization on all inputs set to LOW.

4.1.2 Input Selection

The GS6150 incorporates a 4:1 input selector which allows the connection of four

independent streams of video/data.

The selector is controllable in three separate ways:

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1. The DDI_SEL0 and DDI_SEL1 pins can be used to select the input.

2. A GSPI accessible register can be used to select the input, with the state change

occurring as soon as the register value changes.

3. A GSPI accessible register can be used to select the input, with a rising edge on the

STROBE pin triggering a change to the next state.

Since these states are mutually exclusive, the DDI_SEL0 pin is shared with the STROBE

function.

In the case of using the DDI_SEL0/STROBE and DDI_SEL1 pins (#1 above) or the STROBE

pre-select method (#3 above), the input selector will switch within 1μs of the change of

state on the corresponding pin(s). This strict timing requirement is not maintained when

using GSPI register selection (#2 above).

Each of the device’s four inputs is selected as shown in Table 4-1.

Table 4-1: Pin and Register Settings for Input Selection

Register Settings

Pin Settings

Differential

High-speed

Input Selected

INPUT_SELECTION_CONTROL DDI_SELECT

DDI_SELECT

DDI_SEL0/

STROBE

DDI_SEL1

7 [9:8]

7 [11]

7 [10]

h

X0 (default)

01

X

0

1

X

0

1

0

1

LOW

HIGH

X

LOW

HIGH

LOW

HIGH

X

DDI0, DDI0

DDI1, DDI1

DDI2, DDI2

DDI3, DDI3

DDI0, DDI0

DDI1, DDI1

DDI2, DDI2

DDI3, DDI3

01

X

01

X

01

X

on LOW-to-

HIGH transition

11

0

1

0

1

0

1

X

DDI0, DDI0

DDI1, DDI1

DDI2, DDI2

DDI3, DDI3

on LOW-to-

HIGH transition

on LOW-to-

HIGH transition

on LOW-to-

HIGH transition

11

Note: ‘X’ indicates ‘Do Not Care’

The DDI_SEL0/STROBE and DDI_SEL1 pins include internal pull-downs, which pulls the

input voltage LOW if either pin is unconnected.

When using the STROBE pre-select method (#3 above), the pre-selected input buffer

and trace EQ is powered up in advance of the STROBE pulse.

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4.2 Reference Clock

The GS6150 can operate with or without an external frequency reference. For

applications requiring rapid asynchronous locking, a 27MHz reference or crystal is

required.

The PLL lock times for both referenceless and external crystal reference operation are

given in Table 2-3: AC Electrical Characteristics.

If a reference is connected to the XTAL_CLK_IN pin or a crystal is connected to the

XTAL_CLK_IN and XTAL_CLK_OUT pins of the device, it will automatically be used as the

reference frequency for rapid asynchronous lock. If XTAL_CLK_IN is not connected to a

crystal, XTAL_CLK_OUT must be left unconnected.

The XTAL_CLK_IN pin operates correctly when connected directly to the

XTAL_BUF_OUT from another GS6150, or a 27MHz output of a different device.

4.3 Signal Monitoring

The GS6150 measures and reports the following signal status and quality monitoring

parameters:

•

Loss of Signal

Lock Detection

Rate Detection

Low/High Bit Rate Detection

4.3.1 Loss of Signal Detection

LOS (Loss of Signal) detection is an active HIGH output available to the application on

any of the GPIO[3:0] multi-function status and control pins. It is selected for output using

the GPIO[3:0]_IO_SELECT and GPIO[3:0]_SELECT bits accessible in the

GPIO_CONTROL_REG_0 and GPIO_CONTROL_REG_1 registers. It is the default output of

the GPIO0 pin.

LOS indicates when the serial digital signal selected by the input selector is invalid. This

function is always active.

Two methods can be used to detect loss of signal: strength (default) and edge. Either

method can be selected with LOS_DETECTION_METHOD bits of register PLL_CONTROL.

When strength detection is used as the method of LOS detection the corresponding

GPIO pin will be HIGH (signal lost) when the input signal amplitude within a predefined

window falls below the threshold set by the bits DDI[0:3]_LOS_THRESHOLD_CONTROL

in the LOS_CONTROL_REG_1 and LOS_CONTROL_REG_2 registers. The LOS threshold

hysteresis can be set by the LOS_HYSTERESIS bits in the LOS_CONTROL_REG_0 register

at address F .

h

The corresponding GPIO pin will be LOW (signal present) when the input signal

amplitude within a predefined window is above the defined threshold.

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The method of strength detection is measurement of the average rectified differential

voltage on the input pins. The strength detection method is therefore inherently

dependent on the input signal's eye shape, particularly the rise/fall times of the input

signal relative to the data rate. Additionally, the circuit has a lower bandwidth limit of

operation (20Mb/s) below which it is recommended that the edge detection method is

used. The absolute value of the threshold can be determined for any input swings

according to Equation 4-1 below:

1.9mV × (DDI[0..3]_LOS_THRESHOLD_CONTROL ) × 53

----------------------------------------------------------------------------------------------------------------------------------------

Threshold =

Equation 4-1

(DEVICE_SPECIFIC_LOS_THRESHOLD)

where DEVICE_SPECIFIC_LOS_THRESHOLD specifies the LOS threshold value for a

100mV input swing at SD-rate specific to each device. The other rates scale according to

the fractional relationship given in Figure 4-1 and Figure 4-2 below.

60

55

50

45

40

35

30

0

20

40

60

80

100

120

Frequency (Mb/s)

Figure 4-1: LOS Threshold at 100mV Input Swing vs. Low Frequency Rates for a Nominal

DEVICE_SPECIFIC_LOS_THRESHOLD of 53

Note: Edge detection method is recommended for signals in shaded areas.

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60

55

50

45

40

35

30

SD-SDI

HD-SDI

3G-SDI

6G-SDI

0

1.485

2.97

Frequency (Gb/s)

4.455

5.94

Figure 4-2: LOS Threshold at 100mV Input Swing vs. SDI Data Rates for a Nominal

DEVICE_SPECIFIC_LOS_THRESHOLD of 53

Strength detection is unaffected by the Trace EQ settings in INPUT_CONTROL_REG_0.

When edge detection is used as the method of LOS detection the corresponding GPIO

pin will be HIGH (signal lost) when no transitions are detected on the selected input. The

corresponding GPIO pin will be LOW (signal present) when transitions are detected on

the input. The LOS status is also available through the LOS bit in the PLL_STATUS

register, and as a sticky status through the LOS_STICKY bit in the STICKY_STATUS

register at address 50 .

h

4.3.2 Lock Detection

The GS6150 lock detection circuitry outputs a LOCKED status signal which indicates that

the CDR has achieved phase lock to the incoming data stream. The LOCKED signal is an

active HIGH output available to the application on any of the GPIO[3:0] multi-function

status and control pins. It is selected for output using the GPIO[3:0]_IO_SELECT and

GPIO[3:0]_SELECT bits accessible in the GPIO_CONTROL_REG_0 and

GPIO_CONTROL_REG_1 registers. By default, LOCKED is output on GPIO1.

The LOCKED status is available from the LOCKED bit in the PLL_STATUS register, and the

LOCK_LOST_STICKY bit in the STICKY_STATUS register indicates whether lock has been

lost since the bit was last cleared.

To optimize systems with high DCD and/or high residual ISI the LOCK_SAMPLE bit of the

PD_CONTROL register should be set to 1 in conjunction with reducing the Loop

b

Bandwidth.

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4.3.2.1 Synchronous and Asynchronous Lock Time

Asynchronous lock time is defined as the time it takes the device to lock when a signal

is first applied to the serial digital inputs, or when the signal rate changes.

The synchronous lock time is defined as the time it takes the device to lock to a signal

which has been momentarily interrupted.

The asynchronous and synchronous lock times are defined in Table 2-3: AC Electrical

Characteristics.

To qualify for synchronous lock time, the maximum interruption time of the signal is

10μs for a 270Mb/s signal. 1.485Gb/s, 2.97Gb/s, and 5.94Gb/s signals, as well as their

f/1.001 components have a maximum interruption time of 6μs. The new signal, after

interruption, must have the same frequency as the original signal but can have arbitrary

phase.

4.3.3 Rate Detection

The GS6150 can be manually forced to lock to a specific supported data rate, or

automatically search for and lock to supported rates. The selection between manual and

automatic rate selection is through the FORCE_PLL_RATE and

FORCE_PLL_RATE_ENABLE bits of the PLL_CONTROL register at address 4C . By default

h

the device is set to automatically search for supported SDI rates.

When set to automatically detect supported data rates, the device repeatedly cycles

through each supported rate that is enabled through the RATE_ENABLE_5G94,

RATE_ENABLE_2G97, RATE_ENABLE_1G485, RATE_ENABLE_270M and

RATE_ENABLE_125M bits of the PLL_CONTROL register, until the device phase locks to

one of the enabled rates. If lock is lost the rate search resumes, continuously testing for

each rate in sequence until lock is regained.

The device reports the current data rate setting of the automatic rate search

state machine through the DETECTED_RATE bits in the PLL_STATUS register at address

4F . Each bit of DETECTED_RATE is also available to output through the GPIO pins,

h

selected for output using the GPIO[3:0]_IO_SELECT and GPIO[3:0]_SELECT bits

accessible in the GPIO_CONTROL_REG_0 register. The supported rates that the

DETECTED_RATE bits can output are shown in Table 4-2 below.

Table 4-2: Automatic Rate Detection - Supported Data Rates

DETECTED_RATE

Data Rate

000

001

010

011

100

125Mb/s – MADI

270Mb/s – SD

1.485Gb/s – HD

2.97Gb/s – 3G

5.94Gb/s – 6G

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4.3.4 Low/High Bit Rate Detection for Slew Rate Control

A status output named LBR_HBR is provided to control the slew rate selection input of

a downstream SDI cable driver. It can be connected to the SD_EN input of drivers such

as the GS6080 or GS6081 using the Semtech recommended application circuit.

When this signal is HIGH, the data rate is 270Mb/s (SD) or 125Mb/s (MADI). This signal is

LOW for all other supported data rates, and when the GS6150 is operating in Bypass

Mode or any time the device is not locked.

The LBR_HBR output signal is available to the application on any of the GPIO[3:0]

multifunction status and control pins. It is selected for output using the

GPIO[3:0]_IO_SELECT and GPIO[3:0]_SELECT bits accessible in the

GPIO_CONTROL_REG_0 and GPIO_CONTROL_REG_1 registers. By default, LBR_HBR is

output on GPIO2.

4.4 Low Power Modes

The device can be programmed via the GSPI to operate in two different low power

modes. SLEEP mode has minimum power consumption at the expense of recovery time

upon de-assertion of the FORCE_PWRDN_SLEEP bit. STANDBY mode has higher power

consumption relative to SLEEP mode but minimizes time to return to operation on de-

assertion of the FORCE_PWRDN_STANDBY bit. The features affected by each mode are

outlined below.

SLEEP mode:

•

LOS detection remains functional

The GSPI remains functional

The reference oscillator remains functional

STANDBY mode:

•

LOS detection remains functional

The GSPI remains functional

The reference oscillator remains functional

The VCO and PLL remains functional so as to minimize the lock time when a signal is detected

The rate detector remains set to the last valid data rate. On detection of a signal, the

last valid rate is tested first by the rate detect state machine

The device can be programmed to automatically enter into SLEEP or STANDBY mode

when LOS is asserted by programming the AUTO_PWRDN_DISABLE bit in the

PWRDN_CONTROL register at address 17 . The AUTO_PWRDN_MODE bit in the same

h

register selects which mode, SLEEP or STANDBY, is entered into upon assertion of LOS.

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4.5 Serial Data Output

The GS6150 has two current-mode differential output drivers, each capable of driving

up to 1V differential into an external 100Ω differential load.

pp

The output drivers operate with any binary coded signal with supported data rates up

to 5.94Gb/s. This is applicable to both the serial data (DDO, DDO) and serial data (DDO1,

DDO1) outputs of the device.

4.5.1 Output Impedance

Each of the GS6150’s output buffers include two on-chip, 50Ω termination resistors.

4.5.2 Output Signal Interface Levels

The serial digital outputs operate within specification with an output CML power supply

of 1.2V to 2.5V.

4.5.3 Adjustable Output Swing

Through the GSPI, the output swing can be set in the range from approximately

230mV

to 930mV

in 45mV

increments, when the outputs are terminated with

ppd

50Ω loads. For the exact values, please see Table 4-3 below.

The output swing for each data rate is controlled using the bits in the

DRIVER_CONTROL_REG_3, DRIVER_CONTROL_REG_4, DRIVER_CONTROL_REG_5, and

DRIVER_CONTROL_REG_6 registers at addresses 1C through 1F .

h

The device automatically adjusts the swing setting depending on the state of the device

(i.e. detected rate, bypass mode, or mute). There are separate register controls for mute,

bypass and each data rate.

Table 4-3: Serial Digital Output Swing Settings

Register Setting

(See Note 1)

Min

Typ

Max

Units

0000_b

175

205

245

280

310

345

380

420

230

275

325

370

410

460

510

560

290

345

405

460

510

575

640

700

mV

0001_b

0010_b

0011_b(default)

0100_b

0101_b

0110_b

0111_b

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Table 4-3: Serial Digital Output Swing Settings (Continued)

Register Setting

(See Note 1)

Min

Typ

Max

Units

1000_b

455

490

530

565

600

630

670

700

605

655

705

755

800

840

890

930

760

820

mV

1001_b

1010_b

880

1011_b

945

1100_b

1000

1050

1110

1160

1101_b

1110_b

1111_b

Note:

1. Applicable registers that can be programmed with the values shown above are DDO0_SWING_1G485,

DDO0_SWING_270M, DDO0_SWING_125M, DDO0_SWING_BYPASS, DDO0_SWING_MUTE,

DDO0_SWING_5G94, DDO0_SWING_2G97, DDO1_SWING_1G485, DDO1_SWING_270M,

DDO1_SWING_125M, DDO1_SWING_BYPASS, DDO1_SWING_MUTE, DDO1_SWING_5G94, and

DDO1_SWING_2G97

4.5.4 Output De-emphasis

The GS6150 features adjustable output de-emphasis to compensate for PCB dielectric

trace loss. Each output can be independently set to a different de-emphasis setting for

each detected rate through controls found in the DRIVER_CONTROL_REG_1 and

DRIVER_CONTROL_REG_2 registers.

The effect of de-emphasis, illustrated in Figure 4-3, is to attenuate the swing of bits that

do not follow a bit transition (V ). The swing of bits that do follow a bit transition (V

)

DE

nom

is set by the output swing registers found in Section 4.5.3 and do not depend on the

de-emphasis settings.

Nominal

Swing (V_nom

De-emphasized

Swing (V_DE)

)

Data Pattern

0

1

0

De-emphasis = 20 x log₁₀(V_nom/ V_DE)

Figure 4-3: De-emphasis Waveform

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The default de-emphasis settings for each rate are given in the register descriptions for

DRIVER_CONTROL_REG_1 and DRIVER_CONTROL_REG_2 in Table 5-1. De-emphasis is

disabled on both outputs in Bypass mode, when the output is muted, or when the

device is not locked.

4.5.5 Output Common Mode Voltage

The output common mode voltage level (V

) is a function of the output voltage

) and how the transmission line is

CMOUT

swing, the output driver supply voltage (V

CC_DDO

terminated. If the outputs are terminated through 50Ω resistors to a voltage V

TERM

equal to V

, as shown in Figure 4-5 below, the output common mode voltage is

CC_DDO

given by the following expression:

ΔV

DDO

-------------------

V

= V

–

Equation 4-2

Equation 4-3

CMOUT

CC_DDO

4

If the differential outputs are terminated across a 100Ω resistor, as shown in Figure 4-4

below, the output common mode voltage is given by the following expression:

ΔV

DDO

2

V

= V

–

-------------------

CMOUT

CC_DDO

GS6150

VCC_DDO

V_TERMV_TERM

50Ω

50Ω 50Ω

50Ω

DDO

100Ω

Figure 4-4: 100Ω Parallel Output Termination

Figure 4-5: 50Ω Termination to V

TERM

4.6 Output Mute, Disable, and Data Selection

The GS6150 outputs can each be individually muted using the DDO0_MUTE and

DDO1_MUTE bits in the DRIVER_CONTROL_REG_0 register at address 19 .

h

Each output can also be independently disabled through either register or GPIO control.

When disabled each pin of the output is pulled to V

. Register

CC_DDO

DRIVER_CONTROL_REG_0 contains both register based disable bits (DDO0_DISABLE,

DDO1_DISABLE) and bits for selection between register and GPIO control

(DDO0_DISABLE_SELECT, DDO1_DISABLE_SELECT). For GPIO control refer to

Section 4.10.

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By default DDO0, DDO0 is enabled/disabled through register control and set to enabled.

DDO1, DDO1 is enabled/disabled through GPIO3 and set to output data.

4.7 Bypass Mode

In CDR Bypass mode, the GS6150 passes the input data to the outputs, bypassing the

retiming functionality.

There are two bits in the control registers that control the bypass function:

MANUAL_BYPASS and AUTO_BYPASS in the RECLOCKER_BYPASS register at address

20 . The MANUAL_BYPASS bit is inactive (set to 0) by default. The AUTO_BYPASS bit is

h

active (set to 1) by default, and places the GS6150 reclocker into bypass mode when the

PLL is not locked to a data rate. The bypass function does not affect the trace

equalization function of the device.

Note: If MANUAL_BYPASS is active, it overrides the AUTO_BYPASS bit setting.

4.8 DVB-ASI

The GS6150 has the ability to reclock DVB-ASI signals at 270Mb/s. All relevant settings

and control registers that apply to SD-SDI signals at 270Mb/s are also compatible with

DVB-ASI signals at 270Mb/s.

4.9 Device Power Up

4.9.1 Power on Reset (POR)

The GS6150 features an on-chip power-on-reset that places all registers and internal

state machines into their known, default states when the chip is powered up.

4.9.2 Reset Pin (RST)

When the RST pin is set LOW, all functional blocks are set to their default conditions and

high-speed data and digital functionality is suspended. When it is set HIGH, normal

operation of the device resumes 0.5ms after the LOW-to-HIGH transition of the signal.

This pin is not required at power up and may be left unconnected.

4.10 GPIO Pins Configuration

The GS6150 has four GPIO pins that can each be configured as outputs for various

internal status signals, or as inputs to disable either output-driver through pin control.

The bits GPIO[0:3]_IO_SELECT are used to configure the GPIO pins as outputs (0) or

inputs (1). The signals that are output or input on the GPIO pins are selected on

GPIO_CONTROL_REG_0 and GPIO_CONTROL_REG_1. The signals that can be output on

the GPIO pins are listed in Table 4-4 below.

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Table 4-4: GPIO Status Outputs

GPIO[0:3]_SELECT

Parameter

Description

Loss of signal indication - High when there is no detected

signal on the selected DDI input

0000

LOS

Phase lock indication - High when the CDR has phase-

locked to a valid input signal

0001

0010

LOCKED

LBR_HBR

Low bit-rate/High bit-rate - High when the part is locked to

the SD data rate; low for all other data rates and in bypass.

0101

0110

0111

RATE_DET0

RATE_DET1

RATE_DET2

Rate Detect - Three bits used in conjunction that represent

the data rate detected by the rate search state machine.

Refer to Table 4-2 for rate encoding details.

High when the rate search state machine is locked to a

MADI data rate (125Mb/s)

1000

1001

1010

1011

1100

LOCKED_125M

LOCKED_270M

LOCKED_1G485

LOCKED_2G97

LOCKED_5G94

High when the rate search state machine is locked to an SD

data rate (270Mb/s)

High when the rate search state machine is locked to an HD

data rate (1.485Gb/s)

High when the rate search state machine is locked to a 3G

data rate (2.97Gb/s)

High when the rate search state machine is locked to a 6G

data rate (5.94Gb/s)

When a change in the data rate is detected by the rate

search state machine, the RATE_CHANGE signal is pulsed

high for a duration of 37ns

1101

RATE_CHANGE

The signals that can be input on the GPIOs are listed in Table 4-5 below.

Table 4-5: GPIO Signal Inputs

GPIO[0:3]_SELECT

Parameter

Description

0000

0001

DDO0_DISABLE

DDO1_DISABLE

Disables serial data output 0 (DDO0, DDO0)

Disables serial data output 1 (DDO1, DDO1)

By default, the GPIO pins are configured to the following parameters:

GPIO0: LOS (output)

GPIO1: LOCKED (output)

GPIO2: LBR_HBR (output)

GPIO3: DDO1_DISABLE (input)

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4.11 GSPI Host Interface

The GS6150 is controlled via the Gennum Serial Peripheral Interface (GSPI).

The GSPI host interface is comprised of a serial data input signal (SDIN pin), serial data

output signal (SDOUT pin), an active-low chip select (CS pin) and a burst clock (SCLK

pin).

The GS6150 is a slave device, therefore the SCLK, SDIN and CS signals must be sourced

by the application host processor.

All read and write access to the device is initiated and terminated by the application

host processor.

It is strongly recommended to connect the GSPI pins of the GS6150 to a host/system

processor/controller or FPGA to facilitate optimization of the device to meet specific

application requirements. Modification of many device settings is only facilitated

through the GSPI of the GS6150, and is not available on external pins.

4.11.1 CS Pin

The Chip Select pin (CS) is an active-low signal provided by the host processor to the

GS6150.

The high-to-low transition of this pin marks the start of serial communication to the

GS6150.

The low-to-high transition of this pin marks the end of serial communication to the

GS6150.

There is an option for each device to use a separate unique Chip Select signal from the

host processor or for up to 32 devices to be connected to a single Chip Select when

making use of the Unit Address feature.

Only those devices whose Unit Address matches the UNIT ADDRESS in the GSPI

Command Word will respond to communication from the host processor (unless the

B’CAST ALL bit in the GSPI Command Word is set to 1).

4.11.2 SDIN Pin

The SDIN pin is the GSPI serial data input pin of the GS6150.

The 16-bit Command and Data Words from the host processor or from the SDOUT pin

of other devices are shifted into the device on the rising edge of SCLK when the CS pin

is low.

4.11.3 SDOUT Pin

The SDOUT pin is the GSPI serial data output of the GS6150.

All data transfers out of the GS6150 to the host processor or to the SDIN pin of other

connected devices occur from this pin.

By default at power up or after system reset, the SDOUT pin provides a non-clocked path

directly from the SDIN pin, regardless of the CS pin state, except during the GSPI Data

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Word portion for read operations to the device. This allows multiple devices to be

connected in Loop-Through configuration.

For read operations, the SDOUT pin is used to output data read from an internal

Configuration and Status Register (CSR) when CS is LOW. Data is shifted out of the

device on the falling edge of SCLK, so that it can be read by the host processor or other

downstream connected device on the subsequent SCLK rising edge.

4.11.3.1 GSPI Link Disable Operation

It is possible to disable the direct SDIN to SDOUT (Loop-Through) connection by writing

a value of 1 to the GSPI_LINK_DISABLE bit in REGISTER_0. When disabled, any data

appearing at the SDIN pin will not appear at the SDOUT pin and the SDOUT pin is HIGH.

Note: Disabling the Loop-Through operation is temporarily required when initializing

the Unit Address for up to 32 connected devices.

The time required to enable/disable the Loop-Through operation from assertion of the

register bit is less than the GSPI configuration command delay as defined by the

parameter t

(5 SCLK cycles).

cmd_GSPI_config

Table 4-6: GSPI_LINK_DISABLE Bit Operation

Bit State

Description

0

1

SDIN pin is looped through to the SDOUT pin

Data appearing at SDIN does not appear at SDOUT, and SDOUT pin is HIGH.

SDIN pin

Configuration and

Status Register

SDOUT pin

High-Z

GSPI_LINK

_DISABLE

BUS_THROUGH

CS pin

Figure 4-6: GSPI_LINK_DISABLE Operation

4.11.3.2 GSPI Bus-Through Operation

Using GSPI Bus-Through operation, the GS6150 can share a common PCB trace with

other GSPI devices for SDOUT output.

When configured for Bus-Through operation, by setting GSPI_BUS_THROUGH_ENABLE

bit to 1, the SDOUT pin will be high-impedance when the CS pin is HIGH.

When the CS pin is LOW, the SDOUT pin will be driven and will follow regular read and

write operation as described in Section 4.11.3.

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Multiple chains of GS6150 devices can share a single SDOUT bus connection to host by

configuring the devices for Bus-Through operation. In such configuration, each chain

requires a separate Chip Select (CS).

SDIN pin

Configuration and

Status Register

SDOUT pin

GSPI_LINK

_DISABLE

High-Z

BUS_THROUGH

CS pin

Figure 4-7: GSPI_BUS_THROUGH_ENABLE Operation

4.11.4 SCLK Pin

The SCLK pin is the GSPI serial data shift clock input to the device, and must be provided

by the host processor.

Serial data is clocked into the GS6150 SDIN pin on the rising edge of SCLK. Serial data is

clocked out of the device from the SDOUT pin on the falling edge of SCLK (read

operation). SCLK is ignored when CS is HIGH.

The maximum interface clock rate is 27MHz.

4.11.5 Command Word Description

All GSPI accesses are a minimum of 32 bits in length (a 16-bit Command Word followed

by a 16-bit Data Word) and the start of each access is indicated by the high-to-low

transition of the chip select (CS) pin of the GS6150.

The format of the Command Word and Data Words are shown in Figure 4-8.

Data received immediately following this high-to-low transition will be interpreted as a

new Command Word.

4.11.5.1 R/W bit - B15 Command Word

This bit indicates a read or write operation.

When R/W is set to 1, a read operation is indicated, and data is read from the register

specified by the ADDRESS field of the Command Word.

When R/W is set to 0, a write operation is indicated, and data is written to the register

specified by the ADDRESS field of the Command Word.

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4.11.5.2 B'CAST ALL - B14 Command Word

This bit is used in write operations to configure all devices connected in Loop-Through

and Bus-Through configuration with a single command.

When B’CAST ALL is set to 1, the following Data Word (AUTOINC = 0) or Data Words

(AUTOINC = 1) are written to the register specified by the ADDRESS field of the

Command Word (and subsequent addresses when AUTOINC = 1), regardless of the

setting of the UNIT ADDRESS(es).

When B’CAST ALL is set to 0, a normal write operation is indicated. Only those devices

that have a Unit Address matching the UNIT ADDRESS field of the Command Word write

the Data Word to the register specified by the ADDRESS field of the Command Word.

4.11.5.3 EMEM - B13 Command Word

When the EMEM bit is 1 the Address Word is extended to 23 bits to allow access to

registers located in the extended memory space.

When the EMEM bit is 0, the address word is limited to 7 bits.

4.11.5.4 AUTOINC - B12 Command Word

When AUTOINC is set to 1, Auto-Increment read or write access is enabled.

In Auto-Increment Mode, the device automatically increments the register address for

each contiguous read or write access, starting from the address defined in the ADDRESS

field of the Command Word.

The internal address is incremented for each 16-bit read or write access until a low-to-

high transition on the CS pin is detected.

When AUTOINC is set to 0, single read or write access is required.

Auto-Increment write must not be used to update values in HOST_CONFIG.

4.11.5.5 UNIT ADDRESS - B11:B7 Command Word

The 5 bits of the UNIT ADDRESS field of the Command Word are used to select one of 32

devices connected on a single chip select in Loop-Through or Bus-Through

configurations.

Read and write accesses are only accepted if the UNIT ADDRESS field matches the

programmed DEVICE_UNIT_ADDRESS in HOST_CONFIG.

By default at power-up or after a device reset, the DEVICE_UNIT_ADDRESS is set to 00h

4.11.5.6 ADDRESS - B6:B0 Command Word

If the extended memory is not being accessed (EMEM = 0), the 7 bits of the ADDRESS

field are used to select one of 128 register addresses in the device in single read or write

access mode, or to set the starting address for read or write accesses in Auto-Increment

Mode.

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Command Word

MSB

R / W

LSB

UNIT ADDRESS

ADDRESS

A3

B’CAST

ALL

EMEM

AUTOINC

A11

A10

A9 A8

A7

A6

A5

A4

A2

A1

A0

7-bit CSR address field providing up to

128 configuration registers.

5-bit UNIT ADDRESS field providing up to

32 devices to be connected on a single CS.

Auto increment read/write access when set.

Single read write access when reset.

Extended memory mode. When set, the extended memory mode is

enabled. When reset, normal GSPI addressing is enabled.

When set, the UNIT ADDRESS field is ignored and

all data accesses are actioned by the device.

When reset, the Unit Address is used to

manage data accesses in the device.

Read access when this bit is set.

Write access when this bit is reset.

Data Word

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

Figure 4-8: Command and Data Word Format

When EMEM is set to 1, the Address Word is extended to 23 bits. The Command and Data

Word format will be extended by another 16 bits, and is shown in Figure 4-9 below.

Command Word

MSB

LSB

UNIT ADDRESS

A9

ADDRESS[22:16]

A19

B’CAST

ALL

EMEM

A13

AUTOINC

A12

A11

A10

A8

A7

A22

A6

A21

A5

A20

A4

A18

A2

A17

A1

A16

R / W

A15

ADDRESS[15:0]

A14

A9

A8

A7

A3

D3

A0

Data Word

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D2

D1

D0

Figure 4-9: Command and Data Word Format with EMEM set to 1

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4.11.6 GSPI Transaction Timing

t_{cmd_GSPI_config}

t_cmd

t₉

SCLK

CS

X

SDIN

SDOUT

t₂

t₇

t₀

t₁

t₄

SCLK

CS

t₃

t₈

R/W

BCST

EMEM

Auto_Inc

UA4

UA3

UA2

UA1

UA0

A6

A5

A4

A3

A2

A1

A0

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

SDIN

SDOUT

R/W

BCST

EMEM

Auto_Inc

UA4

UA3

UA2

UA1

UA0

A6

A5

A4

A3

A2

A1

A0

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

SDI signal is looped out on SDO

Write Mode

t₅

t₉

SCLK

CS

t₆

R/W

RSV

EMEM

Auto_Inc

UA4

UA3

UA2

UA1

UA0

A6

A5

A4

A3

A2

A1

A0

SDIN

SDOUT

R/W

RSV

EMEM

Auto_Inc

UA4

UA3

UA2

UA1

UA0

A6

A5

A4

A3

A2

A1

A0

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

SDI signal is looped out on SDO

Read Data is output on SDO

Read Mode

Figure 4-10: GSPI External Interface Timing

Table 4-7: GSPI Timing Parameters

Equivalent

SCLK

Parameter

Symbol

Min

Typ

Max

Units

Cycles

(at 27MHz)

SCLK frequency

CS low before SCLK rising edge

SCLK period

—

2.0

37

—

50

—

27

—

60

—

MHz

ns

t₀

t₁

t₂

t₃

t₄

t₅

ns

SCLK duty cycle

40

%

Input data setup time

SCLK idle time -write

SCLK idle time - read

2.7

37

ns

1

5

ns

161.0

ns

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Table 4-7: GSPI Timing Parameters (Continued)

Equivalent

SCLK

Parameter

Symbol

Min

Typ

Max

Units

Cycles

(at 27MHz)

t_cmd

Inter-command delay time

4

5

120.0

162.0

—

ns

t_{cmd_GSPI_}

_conf1

Inter-command delay time

(after GSPI configuration write)

t₆

t₇

SDO after SCLK falling edge

—

7.5

—

ns

CS high after final SCLK falling

edge

0.0

t₈

t₉

Input data hold time

CS high time

1.0

—

ns

57.0

SDIN to SDOUT combinational

delay

—

5.0

1

ns

Max. chips daisy chained at

max SCLK frequency

GS6150

chips

When host clocks in SDOUT

data on rising edge of SCLK

Max. frequency for 32

daisy-chained devices

2.1

3

MHz

Max. chips daisy-chained at

max. SCLK frequency

GS6150

chips

When host clocks in SDOUT

data on falling edge of SCLK

Max. frequency for 32

daisy-chained devices

2.2

MHz

Note:

1. t_{cmd_GSPI_conf}inter-command delay must be used whenever modifying HOST_CONFIG register at address 0x00

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4.11.7 Single Read/Write Access

Single read/write access timing for the GSPI interface is shown in Figure 4-11 to

Figure 4-15.

When performing a single read or write access, one Data Word is read from/written to

the device per access. Each access is a minimum of 32-bits long, consisting of a

Command Word and a single Data Word. The read or write cycle begins with a high-to-

low transition of the CS pin. The read or write access is terminated by a low-to-high

transition of the CS pin.

The maximum interface clock rate is 27MHz and the inter-command delay time

indicated in the figures as t , is a minimum of 4 SCLK clock cycles. After modifying

cmd

values in HOST_CONFIG, the inter-command delay time, t

of 5 SCLK clock cycles.

, is a minimum

cmd_GSPI_config

For read access, the time from the last bit of the Command Word to the start of the data

output, as defined by t , corresponds to no less than 5 SCLK clock cycles at 27MHz.

5

t

cmd

SCLK

CS

COMMAND

DATA

X

COMMAND

SDIN

SDOUT

Figure 4-11: GSPI Write Timing – Single Write Access with Loop-Through Operation (default)

t

cmd

SCLK

CS

SDIN

COMMAND

DATA

X

COMMAND

SDOUT

Figure 4-12: GSPI Write Timing – Single Write Access with GSPI Link-Disable Operation

t

cmd

SCLK

CS

COMMAND

DATA

X

High-z

COMMAND

SDIN

High-Z

SDOUT

Figure 4-13: GSPI Write Timing – Single Write Access with Bus-Through Operation

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SCLK

CS

t

5

COMMAND

SDIN

DATA

SDOUT

Figure 4-14: GSPI Read Timing – Single Read Access with Loop-Through Operation (default)

t

5

SCLK

CS

COMMAND

SDIN

High-z

X

DATA

SDOUT

Figure 4-15: GSPI Read Timing – Single Read Access with Bus-Through Operation

4.11.8 Auto-increment Read/Write Access

Auto-increment read/write access timing for the GSPI interface is shown in Figure 4-16

to Figure 4-20.

Auto-increment mode is enabled by the setting of the AUTOINC bit of the Command

Word.

In this mode, multiple Data Words can be read from/written to the device using only one

starting address. Each access is initiated by a high-to-low transition of the CS pin, and

consists of a Command Word and one or more Data Words. The internal address is

automatically incremented after the first read or write Data Word, and continues to

increment until the read or write access is terminated by a low-to-high transition of the

CS pin.

Note: Writing to HOST_CONFIG using Auto-increment access is not allowed.

The maximum interface clock rate is 27MHz and the inter-command delay time

indicated in the diagram as t , is a minimum of 4 SCLK clock cycles.

cmd

For read access, the time from the last bit of the first Command Word to the start of the

data output of the first Data Word as defined by t , will be no less than 5 SCLK cycles at

5

27MHz. All subsequent read data accesses will not be subject to this delay during an

Auto-Increment read.

SCLK

CS

SDIN

COMMAND

DATA 1

DATA 2

SDOUT

Figure 4-16: GSPI Write Timing – Auto-Increment with Loop-Through Operation (default)

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SCLK

CS

COMMAND

DATA 1

DATA 2

SDIN

SDOUT

Figure 4-17: GSPI Write Timing – Auto-Increment with GSPI Link Disable Operation

SCLK

CS

SDIN

COMMAND

DATA 1

DATA 2

High-Z

SDOUT

Figure 4-18: GSPI Write Timing – Auto-Increment with Bus-Through Operation

SCLK

t

5

CS

SDIN

COMMAND

SDOUT

DATA 1

DATA 2

Figure 4-19: GSPI Read Timing – Auto-Increment Read with Loop-Through Operation (default)

SCLK

t

5

CS

SDIN

COMMAND

High-z

SDOUT

X

DATA 1

DATA 2

Figure 4-20: GSPI Read Timing – Auto-Increment Read with Bus-through Operation

4.11.9 Setting a Device Unit Address

Multiple (up to 32) GS6150 devices can be connected to a common Chip Select (CS) in

Loop-Through or Bus-Through operation.

To ensure that each device selected by a common CS can be separately addressed, a

unique Unit Address must be programmed by the host processor at start-up as part of

system initialization or following a device reset.

Note:By default at power up or after a device reset, the DEVICE_UNIT_ADDRESS of each

device is set to 0h and the SDIN->SDOUT non-clocked loop-through for each device is

enabled.

These are the steps required to set the DEVICE_UNIT_ADDRESS of devices in a chain to

values other than 0:

1. Write to Unit Address 0 selecting HOST_CONFIG (ADDRESS = 0), with the

GSPI_LINK_DISABLE bit set to 1 and the DEVICE_UNIT_ADDRESS field set to 0. This

disables the direct SDIN->SDOUT non-clocked path for all devices on chip select.

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2. Write to Unit Address 0 selecting HOST_CONFIG (ADDRESS = 0), with the

GSPI_LINK_DISABLE bit set to 0 and the DEVICE_UNIT_ADDRESS field set to a

unique Unit Address. This configures DEVICE_UNIT_ADDRESS for the first device in

the chain. Each subsequent such write to Unit Address 0 will configure the next

device in the chain. If there are 32 devices in a chain, the last (32nd) device in the

chain must use DEVICE_UNIT_ADDRESS value 0.

3. Repeat step 2 using new, unique values for the DEVICE_UNIT_ADDRESS field in

HOST_CONFIG until all devices in the chain have been configured with their own

unique Unit Address value.

Note: t

delay must be observed after every write that modifies

cmd_GSPI_conf

HOST_CONFIG.

All connected devices receive this command (by default the Unit Address of all devices

is 0), and the Loop-Through operation will be re-established for all connected devices.

Once configured, each device will only respond to Command Words with a

UNIT ADDRESS field matching the DEVICE_UNIT_ADDRESS in HOST_CONFIG

Note: Although the Loop-Through and Bus-Through configurations are compatible

with previous generation GSPI enabled devices (backward compatibility), only devices

supporting Unit Addressing can share a chip select. All devices on any single chip select

must be connected in a contiguous chain with only the last device's SDOUT connected

to the application host processor. Multiple chains configured in Bus-Through mode can

have their final SDOUT outputs connected to a single application host processor input.

4.11.10 Default GSPI Operation

By default at power up or after a device reset, the GS6150 is set for Loop-Through

Operation and the internal DEVICE_UNIT_ADDRESS field of the device is set to 0.

Figure 4-21 shows a functional block diagram of the Configuration and Status Register

(CSR) map in the GS6150 for non-extended memory accesses (EMEM = 0).

At power-up or after a device reset, DEVICE_UNIT_ADDRESS = 00h

[15]

[14]

[13]

[12]

[11:7]

[6:0]

bits

BCAST

ALL

Auto

Inc

Unit Address

32 devices

Local Address

128 registers

EMEM

R / W

CMD

[15:0]

Data to be written / Read Data

bits

Compare

DATA

[4:0]

[15]

[14]

[12:5]

bits

[13]

Read/Write

GSPI_BUS_

THROUGH

_ENABLE

GSPI_LINK

_DISABLE

Reg 0

RESERVED

DEVICE_UNIT_ADDRESS

RESERVED

Reg 1

Configuration and Status Registers

Reg 128

Figure 4-21: Internal Register Map Functional Block Diagram

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The steps required for the application host processor to write to the Configuration and

Status Registers via the GSPI, are as follows:

1. Set Command Word for write access (R/W = 0) to the local registers 0h-80h; set Auto

Increment; set the Unit Address field in the Command Word to match the

configured DEVICE_UNIT_ADDRESS which will be zero. Write the Command Word.

2. Write the Data Word to be written to the first register.

3. Write the Data Word to be written to the next register in Auto Increment mode, etc.

Read access is the same as the above with the exception of step 1, where the Command

Word is set for read access (R/W = 1).

Note: The UNIT ADDRESS field of the Command Word must always match

DEVICE_UNIT_ADDRESS for an access to be accepted by the device. Changing

DEVICE_UNIT_ADDRESS to a value other than 0 is only required if multiple devices are

connected to a single chip select (in Loop-Through or Bus-Through configuration.)

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5. Host Interface Register Map

Table 5-1: Register Descriptions - Standard Address Space

Bit

Slice

Reset

Value

Address Register Name

Parameter Name

R/W

Description

0_h

RSVD

15:15

14:14

RW

Reserved. Do not change.

GSPI loop-through disable.

GSPI_LINK_DISABLE

GSPI_BUS_THROUGH_

ENABLE

0_h

HOST_CONFIG

DEVICE_INFO

13:13

RW

GSPI bus-through enable.

0_h

1_h

RSVD

DEVICE_UNIT_ADDRESS

RSVD

12:5

4:0

RW

RO

RW

Reserved. Do not change.

Device address programmed by application.

Reserved.

15:8

7:0

1_h

DEVICE_VERSION_ID

RSVD

-

Device Version Identifier.

Reserved. Do not change.

GPIO1 Input/Output Select

0_h

15:14

0_h

GPIO1_IO_SELECT

RSVD

13:13

12:11

RW

0_b: Output

1_b: Input

Reserved. Do not change.

GPIO1 Signal Selection

If GPIO1_IO_SELECT is set to 0:

0000_b: LOS

0001_b: LOCKED (default)

0010_b: LBR_HBR

0011_b: Reserved

0100_b: Reserved

0101_b: RATE_DET0

0110_b: RATE_DET1

0111_b: RATE_DET2

1000_b: LOCKED_125M

1001_b: LOCKED_270M

1010_b: LOCKED_1G485

1011_b: LOCKED_2G97

1100_b: LOCKED_5G94

1101_b: RATE_CHANGE

GPIO_CONTROL_

REG_0

2_h

1_h

GPIO1_SELECT

10:7

RW

If GPIO1_IO_SELECT is set to 1:

0000_b: DDO0_DISABLE

0001_b: DDO1_DISABLE

GPIO0 Input/Output Select

0_b: Output

1_b: Input

0_h

GPIO0_IO_SELECT

RSVD

6:6

5:4

RW

Reserved. Do not change.

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Table 5-1: Register Descriptions - Standard Address Space (Continued)

Bit

Slice

Reset

Value

Address Register Name

Parameter Name

R/W

Description

GPIO0 Signal Selection

If GPIO0_IO_SELECT is set to 0:

0000_b: LOS (default)

0001_b: LOCKED

0010_b: LBR_HBR

0011_b: Reserved

0100_b: Reserved

0101_b: RATE_DET0

0110_b: RATE_DET1

0111_b: RATE_DET2

1000_b: LOCKED_125M

1001_b: LOCKED_270M

1010_b: LOCKED_1G485

1011_b: LOCKED_2G97

1100_b: LOCKED_5G94

1101_b: RATE_CHANGE

GPIO_CONTROL_

2_h

0_h

GPIO0_SELECT

3:0

RW

REG_0

If GPIO0_IO_SELECT is set to 1:

0000_b: DDO0_DISABLE

0001_b: DDO1_DISABLE

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Table 5-1: Register Descriptions - Standard Address Space (Continued)

Bit

Slice

Reset

Value

Address Register Name

Parameter Name

R/W

Description

0_h

1_h

0_h

RSVD

15:14

13:13

12:11

RW

Reserved. Do not change.

GPIO3 Input/Output Select

0_b: Output

1_b: Input

GPIO3_IO_SELECT

RSVD

RW

Reserved. Do not change.

GPIO3 Signal Selection

If GPIO3_IO_SELECT is set to 0:

0000_b: LOS

0001_b: LOCKED

0010_b: LBR_HBR

0011_b: Reserved

0100_b: Reserved

0101_b: RATE_DET0

0110_b: RATE_DET1

0111_b: RATE_DET2

1000_b: LOCKED_125M

1001_b: LOCKED_270M

1010_b: LOCKED_1G485

1011_b: LOCKED_2G97

1100_b: LOCKED_5G94

1101_b: RATE_CHANGE

GPIO_CONTROL_

3_h

REG_1

1_h

GPIO3_SELECT

10:7

RW

If GPIO3_IO_SELECT is set to 1:

0000_b: DDO0_DISABLE

0001_b: DDO1_DISABLE (default)

GPIO2 Input/Output Select

0_b: Output

0_h

GPIO2_IO_SELECT

6:6

RW

1_b: Input

GS6150

Final Data Sheet

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Table 5-1: Register Descriptions - Standard Address Space (Continued)

Bit

Slice

Reset

Value

Address Register Name

Parameter Name

R/W

Description

0_h

RSVD

5:4

RW

Reserved. Do not change.

GPIO2 Signal Selection

If GPIO2_IO_SELECT is set to 0:

0000_b: LOS

0001_b: LOCKED

0010_b: LBR_HBR (default)

0011_b: Reserved

0100_b: Reserved

0101_b: RATE_DET0

0110_b: RATE_DET1

0111_b: RATE_DET2

1000_b: LOCKED_125M

1001_b: LOCKED_270M

1010_b: LOCKED_1G485

1011_b: LOCKED_2G97

1100_b: LOCKED_5G94

1101_b: RATE_CHANGE

GPIO_CONTROL_

3_h

REG_1

2_h

GPIO2_SELECT

3:0

RW

If GPIO2_IO_SELECT is set to 1:

0000_b: DDO0_DISABLE

0001_b: DDO1_DISABLE

4_h

1C_h

RESERVED

RSVD

15:0

7:6

RW

Reserved. Do not change.

DDI3 Trace-EQ Configuration

00_b: OFF

01_b: 0dB/EQ BYPASS

10_b: LOW

0_h

DDI3_TRACE_EQ_CONTROL

11_b: HIGH

DDI2 Trace-EQ Configuration

00_b: OFF

0_h

DDI2_TRACE_EQ_ CONTROL

DDI1_TRACE_EQ_ CONTROL

DDI0_TRACE_EQ_ CONTROL

5:4

3:2

1:0

RW

01_b: 0dB/EQ BYPASS

10_b: LOW

11_b: HIGH

INPUT_CONTROL_

REG_0

5_h

DDI1 Trace-EQ Configuration

00_b: OFF

01_b: 0dB/EQ BYPASS

10_b: LOW

11_b: HIGH

DDI0 Trace-EQ Configuration

00_b: OFF

01_b: 0dB/EQ BYPASS

10_b: LOW

11_b: HIGH

GS6150

Final Data Sheet

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Table 5-1: Register Descriptions - Standard Address Space (Continued)

Bit

Slice

Reset

Value

Address Register Name

Parameter Name

R/W

Description

6_h

0_h

RESERVED

RSVD

15:0

RW

Reserved. Do not change.

Input Selection

15:12

00_b: DDI0

01_b: DDI1

10_b: DDI2

11_b: DDI3

0_h

DDI_SELECT

11:10

RW

Used when INPUT_SELECTION_CONTROL is

set to 01_bor 11_b

Determines the source for the input

selection block.

X0_b: Use DDI_SEL0_STROBE and DDI_SEL1

pins.

0_h

INPUT_SELECTION_CONTROL

9:8

RW

01_b: Use DDI_SELECT bits

11_b: Use DDI_SELECT bits; update occurs on

low-to-high transition of DDI_SEL0_STROBE

pin.

Enable DDI3 on-chip Trace-EQ DC

termination.

INPUT_CONTROL_

REG_2

7_h

DDI3_TRACE_EQ_DC_TERM_

ENABLE

1_h

7:7

6:6

5:5

4:4

RW

0_b: Disabled

1_b: Enabled

Enable DDI2 on-chip Trace-EQ DC

termination.

DDI2_TRACE_EQ_DC_TERM_

ENABLE

0_b: Disabled

1_b: Enabled

Enable DDI1 on-chip Trace-EQ DC

termination.

DDI1_TRACE_EQ_DC_TERM_

ENABLE

0_b: Disabled

1_b: Enabled

Enable DDI0 on-chip Trace-EQ DC

termination.

DDI0_TRACE_EQ_DC_TERM_

ENABLE

0_b: Disabled

1_b: Enabled

0_h

—

RSVD

3:0

RW

ROCW

RO

Reserved. Do not change.

Reserved.

8_h

9_h

A_h

B_h

C_h

RESERVED

15:0

RO

Reserved.

RO

Reserved.

RO

Reserved.

GS6150

Final Data Sheet

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Table 5-1: Register Descriptions - Standard Address Space (Continued)

Bit

Slice

Reset

Value

Address Register Name

Parameter Name

R/W

Description

D_h

E_h

—

0_h

RESERVED

RSVD

15:0

RO

RW

Reserved.

15:10

Reserved. Do not change.

Enables LOS threshold adjustment based on

the settings in the

DDI[3:0]_LOS_THRESHOLD_CONTROL bits

in the LOS_CONTROL_REG_1 and

LOS_CONTROL_REG_2 registers.

LOS_THRESHOLD_CONTROL_

ENABLE

0_h

9:9

RW

0_b: Default internal thresholds are used

1_b: Thresholds used in the

LOS_CONTROL_REG_1 and

LOS_CONTROL_REG_2 registers

LOS De-Assert Time Delay:

00_b: 2.30μs

2_h

LOS_DEASSERT_TIME

LOS_ASSERT_TIME

8:7

6:5

RW

01_b: 1.50μs

10_b: 1.20μs

11_b: 0.90μs

LOS Assert Time Delay:

00_b: 68μs

01_b: 64μs

2_h

10_b: 62μs

11_b: 61μs

LOS_CONTROL_

REG_0

F_h

LOS Threshold Hysteresis Adjustment:

0000_b: 0 dB

0001_b: 0.32 dB

0010_b: 0.64 dB

0011_b: 0.98 dB

0100_b: 1.34 dB

0101_b: 1.70 dB

0110_b: 2.09 dB

0111_b: 2.49 dB

1000_b: 2.84 dB

1001_b: 3.28 dB

1010_b: 3.74 dB

1011_b: 4.23 dB

1100_b: 4.75 dB

1101_b: 5.30 dB

1110_b: 5.89 dB

1111_b: 6.53 dB

0_h

LOS_HYSTERESIS

4:1

RW

Override the internal power-down control

for the LOS circuit.

0_h

LOS_PWRDN_OVERRIDE

0:0

RW

0_b: LOS active

1_b: LOS powered down

GS6150

Final Data Sheet

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Table 5-1: Register Descriptions - Standard Address Space (Continued)

Bit

Slice

Reset

Value

Address Register Name

Parameter Name

R/W

Description

LOS signal threshold for input DDI1 at

device pins is:

DDI1_LOS_THRESHOLD_

CONTROL

5A_h

15:8

7:0

RW

1.9mV

x DDI1_LOS_THRESHOLD_CONTROL x

ppd

(53/DEVICE_SPECIFIC_LOS_THRESHOLD)

(All above values are in decimal)

LOS_CONTROL_

10_h

REG_1

LOS signal threshold for input DDI0 at

device pins is:

DDI0_LOS_THRESHOLD_

CONTROL

RW

1.9mV

x DDI0_LOS_THRESHOLD_CONTROL x

ppd

(53/DEVICE_SPECIFIC_LOS_THRESHOLD)

(All above values are in decimal)

LOS signal threshold for input DDI3 at

device pins is:

DDI3_LOS_THRESHOLD_

CONTROL

15:8

7:0

1.9mV

x DDI3_LOS_THRESHOLD_CONTROL x (53/

ppd

DEVICE_SPECIFIC_LOS_THRESHOLD)

(All above values are in decimal)

LOS_CONTROL_

11_h

REG_2

LOS signal threshold for input DDI2 at

device pins is:

DDI2_LOS_THRESHOLD_

CONTROL

1.9mV

x DDI2_LOS_THRESHOLD_CONTROL x

ppd

(53/DEVICE_SPECIFIC_LOS_THRESHOLD)

(All above values are in decimal)

—

RSVD

15:8

7:0

RO

Reserved.

12_h

LOS_STATUS

Trimmed setting to achieve LOS threshold of

100mV_ppd

DEVICE_SPECIFIC_LOS_

THRESHOLD

13_h

14_h

280_h

—

RESERVED

RSVD

15:0

15:3

RW

RO

RW

Reserved. Do not change.

Reserved.

0_h

Reserved. Do not change.

Enables/Disables the reference buffer

output.

1_h

XTAL_BUF_OUT_ENABLE

2:2

RW

REF_CLK_

CONTROL

0_b: XTAL_BUF_OUT disabled

1_b: XTAL_BUF_OUT enabled

15_h

0_h

—

RSVD

1:1

0:0

RW

RO

Reserved. Do not change.

Reserved.

15:1

Indicates whether an external 27MHz

reference is being used by the device or its

internal oscillator.

16_h

REF_CLK_STATUS

XTAL_CLK_DET

0:0

RO

-

0_b: Internal oscillator being used

1_b: External crystal being used

GS6150

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Table 5-1: Register Descriptions - Standard Address Space (Continued)

Bit

Slice

Reset

Value

Address Register Name

Parameter Name

R/W

Description

Selects the low power mode, SLEEP or

STANDBY that is entered into when

AUTO_PWRDN_DISABLE is set to 0 and LOS

is asserted.

0_h

AUTO_PWRDN_MODE

3:3

2:2

RW

0_b: SLEEP mode is selected (default)

1_b: STANDBY mode is selected

Forces the device into STANDBY mode when

FORCE_PWRDN_SLEEP is set to 0.

0_h

FORCE_PWRDN_STANDBY

FORCE_PWRDN_SLEEP

RW

0_b: Device not in STANDBY mode

1_b: Device in STANDBY mode

Forces the device into SLEEP mode when

AUTO_PWRDN_DISABLE is set to 1.

PWRDN_

17_h

CONTROL

0_b: Device not in SLEEP mode

1_b: Device in SLEEP mode

0_h

1:1

When FORCE_PWRDN_SLEEP is set to 1, it

takes precedence over the

FORCE_PWRDN_STANDBY bit.

Disables Auto Powerdown mode which

automatically enters SLEEP or STANDBY

mode when LOS is asserted.

0_b: Device automatically enters SLEEP or

STANDBY when LOS is 1

1_b: Device only enters SLEEP or STANDBY

when FORCE_PWRDN_SLEEP or

1_h

—

AUTO_PWRDN_DISABLE

0:0

RW

RO

FORCE_PWRDN_STANDBY are set to 1

18_h

RESERVED

RSVD

15:0

Reserved.

GS6150

Final Data Sheet

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Table 5-1: Register Descriptions - Standard Address Space (Continued)

Bit

Slice

Reset

Value

Address Register Name

Parameter Name

R/W

Description

0_h

1_h

RSVD

15:8

7:7

RW

Reserved. Do not change.

Auto-Mute Enable on LOS.

0_h

AUTO_LOS_MUTE_ENABLE

6:6

RW

0_b: Output is unaffected by LOS

1_b: Output is muted when LOS is asserted

Mute control for the DDO1 output.

0_b: DDO1 output not muted

1_b: DDO1 output muted

0_h

DDO1_MUTE

5:5

RW

Output across DDO1 and DDO1 is static and

of magnitude DDO1_SWING_MUTE/2 when

DDO1_DISABLE is set to 0.

Mute control for the DDO0 output.

0_b: DDO0 output not muted

1_b: DDO0 output muted

0_h

DDO0_MUTE

4:4

3:3

RW

Output across DDO0 and DDO0 is static and

of magnitude DDO0_SWING_MUTE/2 when

DDO0_DISABLE is set to 0.

Disable control for the DDO1 output.

0_b: DDO1 output not disabled

1_b: DDO1 output disabled

DRIVER_CONTROL_

19_h

0_h

REG_0

DDO1_DISABLE

Output of both DDO1 and DDO1 is

VCC_DDO1.

This bit takes precedence over DDO1_MUTE.

Disable control for the DDO0 output.

0_b: DDO0 output not disabled

1_b: DDO0 output disabled

0_h

DDO0_DISABLE

2:2

RW

Output of both DDO0 and DDO0 is

VCC_DDO0.

This bit takes precedence over DDO0_MUTE.

Controls whether DDO1 is disabled using an

assigned GPIO pin or the DDO1_DISABLE

bit.

0_h

DDO1_DISABLE_SELECT

DDO0_DISABLE_SELECT

1:1

0:0

RW

0_b: DDO1 is disabled using assigned GPIO

1_b: DDO1 is disabled using the

DDO1_DISABLE bit

Controls whether DDO0 is disabled using an

assigned GPIO pin or the DDO0_DISABLE

bit.

1_h

0_b: DDO0 is disabled using assigned GPIO

1_b: DDO0 is disabled using the

DDO0_DISABLE bit

GS6150

Final Data Sheet

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Table 5-1: Register Descriptions - Standard Address Space (Continued)

Bit

Slice

Reset

Value

Address Register Name

Parameter Name

R/W

Description

0_h

RSVD

15:15

RW

Reserved. Do not change.

De-emphasis control for 5.94Gb/s (6Gb/s

UHD-SDI) signals output on DDO0

000 : 0dB

b

001 : 0.3dB

b

010 : 0.6dB (default)

2_h

DDO0_DEEMPHASIS_5G94

DDO0_DEEMPHASIS_2G97

DDO0_DEEMPHASIS_1G485

DDO0_DEEMPHASIS_270M

DDO0_DEEMPHASIS_125M

14:12

RW

b

011 : 2.3 B

b

100 : 4.0dB

b

101 : 6.6dB

b

110 : 10.0dB

b

De-emphasis control for 2.97Gb/s (3Gb/s SDI)

signals output on DDO0

000 : 0dB

b

001 : 0.4dB (default)

b

010 : 1.5dB

1_h

0_h

11:9

b

011 : 3.2dB

b

100 : 4.9dB

b

101 : 7.6dB

b

110 : 11.0dB

b

De-emphasis control for 1.485Gb/s (HD-SDI)

signals output on DDO0

000 : 0dB

b

DRIVER_CONTROL_

001 : 1.1dB (default)

b

1A_h

REG_1

010 : 2.4dB

8:6

b

011 : 4.0dB

b

100 : 5.7dB

b

101 : 8.2dB

b

110 : 11.5dB

b

De-emphasis control for 0.27Gb/s (SD-SDI)

signals output on DDO0

000 : 0dB (default)

b

001 : 1.2dB

b

010 : 2.5dB

5:3

b

011 : 4.1dB

b

100 : 6.0dB

b

101 : 8.5dB

b

110 : 12.0dB

b

De-emphasis control for 0.125Gb/s (MADI)

signals output on DDO0

000 : 0dB (default)

b

001 : 1.2dB

b

010 : 2.5dB

2:0

b

011 : 4.1dB

b

100 : 6.0dB

b

101 : 8.5dB

b

110 : 12.0dB

b

GS6150

Final Data Sheet

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Table 5-1: Register Descriptions - Standard Address Space (Continued)

Bit

Slice

Reset

Value

Address Register Name

Parameter Name

R/W

Description

0_h

RSVD

15:15

RW

Reserved. Do not change.

De-emphasis control for 5.94Gb/s (6Gb/s

UHD-SDI) signals output on DDO1

000 : 0dB

b

001 : 0.3dB

b

010 : 0.6dB (default)

2_h

DDO1_DEEMPHASIS_5G94

DDO1_DEEMPHASIS_2G97

DDO1_DEEMPHASIS_1G485

DDO1_DEEMPHASIS_270M

DDO1_DEEMPHASIS_125M

14:12

RW

b

011 : 2.3 B

b

100 : 4.0dB

b

101 : 6.6dB

b

110 : 10.0dB

b

De-emphasis control for 2.97Gb/s (3Gb/s SDI)

signals output on DDO1

000 : 0dB

b

001 : 0.4dB (default)

b

010 : 1.5dB

1_h

0_h

11:9

b

011 : 3.2dB

b

100 : 4.9dB

b

101 : 7.6dB

b

110 : 11.0dB

b

De-emphasis control for 1.485Gb/s (HD-SDI)

signals output on DDO1

000 : 0dB

b

DRIVER_CONTROL_

001 : 1.1dB (default)

b

1B_h

REG_2

010 : 2.4dB

8:6

b

011 : 4.0dB

b

100 : 5.7dB

b

101 : 8.2dB

b

110 : 11.5dB

b

De-emphasis control for 0.27Gb/s (SD-SDI)

signals output on DDO1

000 : 0dB (default)

b

001 : 1.2dB

b

010 : 2.5dB

5:3

b

011 : 4.1dB

b

100 : 6.0dB

b

101 : 8.5dB

b

110 : 12.0dB

b

De-emphasis control for 0.125Gb/s (MADI)

signals output on DDO1

000 : 0dB (default)

b

001 : 1.2dB

b

010 : 2.5dB

2:0

b

011 : 4.1dB

b

100 : 6.0dB

b

101 : 8.5dB

b

110 : 12.0dB

b

GS6150

Final Data Sheet

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Table 5-1: Register Descriptions - Standard Address Space (Continued)

Bit

Slice

Reset

Value

Address Register Name

Parameter Name

R/W

Description

0_h

RSVD

15:12

RW

Reserved. Do not change.

Differential swing (amplitude) control for

1.485Gb/s (HD-SDI) signals output on DDO0.

For details refer to Section 4.5.3.

3_h

DDO0_SWING_1G485

DDO0_SWING_270M

DDO0_SWING_125M

11:8

RW

DRIVER_CONTROL_

1C_h

Differential swing (amplitude) control for

0.27Gb/s (SD-SDI) signals output on DDO0.

For details refer to Section 4.5.3.

REG_3

3_h

7:4

3:0

Differential swing (amplitude) control for

0.125Gb/s (MADI) signals output on DDO0.

For details refer to Section 4.5.3.

Differential swing (amplitude) control for

unlocked signals output on DDO0 (when

reclocker is operating in BYPASS mode). For

details refer to Section 4.5.3.

3_h

DDO0_SWING_BYPASS

15:12

RW

Takes precedence over rate-specific swing

controls

Differential static amplitude control for

DDO0 when the output is muted. For details

refer to Section 4.5.3.

DRIVER_CONTROL_

3_h

DDO0_SWING_MUTE

DDO0_SWING_5G94

11:8

7:4

RW

1D_h

REG_4

Takes precedence over rate-specific swing

controls and bypass swing control

Differential swing (amplitude) control for

5.94Gb/s (6G UHD-SDI) signals output on

DDO0. For details refer to Section 4.5.3.

3_h

Differential swing (amplitude) control for

2.97Gb/s (3Gb/s SDI) signals output on

DDO0. For details refer to Section 4.5.3.

3_h

0_h

3_h

DDO0_SWING_2G97

RSVD

3:0

15:12

11:8

RW

Reserved. Do not change.

Differential swing (amplitude) control for

1.485Gb/s (HD-SDI) signals output on DDO1.

For details refer to Section 4.5.3.

DDO1_SWING_1G485

DRIVER_CONTROL_

1E_h

Differential swing (amplitude) control for

0.27Gb/s (SD-SDI) signals output on DDO1.

For details refer to Section 4.5.3.

REG_5

3_h

DDO1_SWING_270M

DDO1_SWING_125M

7:4

3:0

RW

Differential swing (amplitude) control for

0.125Gb/s (MADI) signals output on DDO1.

For details refer to Section 4.5.3.

GS6150

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Table 5-1: Register Descriptions - Standard Address Space (Continued)

Bit

Slice

Reset

Value

Address Register Name

Parameter Name

R/W

Description

Differential swing (amplitude) control for

unlocked signals output on DDO1 (when

reclocker is operating in BYPASS mode). For

details refer to Section 4.5.3.

3_h

DDO1_SWING_BYPASS

15:12

RW

Also applies when the device is not locked.

Takes precedence over rate-specific swing

controls

Differential static amplitude control for

DDO1 when the output is muted. For details

refer to Section 4.5.3.

DRIVER_CONTROL_

1F_h

3_h

DDO1_SWING_MUTE

DDO1_SWING_5G94

11:8

7:4

RW

REG_6

Takes precedence over rate-specific swing

controls and bypass swing control

Differential swing (amplitude) control for

5.94Gb/s (6G UHD-SDI) signals output on

DDO1. For details refer to Section 4.5.3.

3_h

Differential swing (amplitude) control for

2.97Gb/s (3Gb/s SDI) signals output on

DDO1. For details refer to Section 4.5.3.

3_h

0_h

DDO1_SWING_2G97

RSVD

3:0

RW

15:2

Reserved. Do not change.

Used to manually bypass the retiming block

in the reclocker.

0_b: Retimer not bypassed

1_b: Retimer bypassed

0_h

MANUAL_BYPASS

1:1

RW

The assertion of MANUAL_BYPASS takes

precedence irrespective of the setting of

AUTO_BYPASS

RECLOCKER_

20_h

BYPASS

Selects between automatic and manual

bypass of the retiming block when the

reclocker is not locked.

0_b: Auto-Bypass is disabled

1_b: Auto-Bypass is enabled

1_h

AUTO_BYPASS

0:0

RW

Even if AUTO_BYPASS is asserted, the

assertion of MANUAL_BYPASS will still cause

the retimer to be bypassed.

1_h

0_h

RSVD

15:7

6:6

RW

Reserved. Do not change.

Selects sampling method for LOCK

DETECTION

LOCK_SAMPLE

0_b: Strict sampling

21_h

PD_CONTROL

1_b: High-jitter sampling

2_h

0_h

RSVD

5:1

0:0

RW

Reserved. Do not change.

—

POLARITY_INVERT

GS6150

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Table 5-1: Register Descriptions - Standard Address Space (Continued)

Bit

Slice

Reset

Value

Address Register Name

Parameter Name

R/W

Description

22_h

23_h

24_h

25_h

26_h

27_h

28_h

29_h

2A_h

2B_h

2C_h

2D_h

2E_h

2F_h

30_h

31_h

32_h

33_h

34_h

35_h

36_h

37_h

38_h

39_h

3A_h

3B_h

3C_h

3D_h

4208_h

0_h

RESERVED

RSVD

15:0

RW

ROSW

RW

RO

Reserved. Do not change.

Reserved.

0_h

2_h

A8B_h

3_h

2_h

0_h

RO

Reserved.

0_h

RO

Reserved.

0_h

RO

Reserved.

0_h

RO

Reserved.

0_h

RO

Reserved.

0_h

RO

Reserved.

0_h

RO

Reserved.

0_h

RO

Reserved.

0_h

RO

Reserved.

0_h

RO

Reserved.

0_h

RO

Reserved.

0_h

RO

Reserved.

2_h

RW

ROSW

RW

Reserved. Do not change.

0_h

2_h

A8B_h

GS6150

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Table 5-1: Register Descriptions - Standard Address Space (Continued)

Bit

Slice

Reset

Value

Address Register Name

Parameter Name

R/W

Description

3E_h

3F_h

40_h

41_h

42_h

43_h

44_h

45_h

46_h

47_h

48_h

49_h

4A_h

4B_h

3_h

0_h

RESERVED

RSVD

15:0

RW

RO

Reserved. Do not change.

Reserved.

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Table 5-1: Register Descriptions - Standard Address Space (Continued)

Bit

Slice

Reset

Value

Address Register Name

Parameter Name

R/W

Description

0_h

RSVD

15:12

11:10

RW

Reserved. Do not change.

Determines the source of CARRIER_DETECT.

00_b: Edge detection

1_h

LOS_DETECTION_METHOD

RW

01_b: Strength detection

Force the PLL to retime a specific data rate.

000_b: Reserved

001_b: 0.270Gb/s

010_b: 1.485Gb/s

011_b: 2.97Gb/s

100_b: 5.94Gb/s

101_b: Reserved

110_b: Reserved

111_b: Reserved

1_h

FORCE_PLL_RATE

9:7

RW

Used when FORCE_PLL_RATE_ENABLE is set

to 1.

Enables the forced PLL rate override set

using the FORCE_PLL_RATE bits.

0_h

FORCE_PLL_RATE_ENABLE

RATE_ENABLE_125M

6:6

5:5

RW

Enables auto-detection of 0.125Gb/s (MADI)

signals

0_b: 0.125Gb/s signals will not be detected

1_b: 0.125Gb/s signals will be detected

4C_h

PLL_CONTROL

Enables auto-detection of 5.94Gb/s

(6G UHD-SDI) signals.

1_h

RATE_ENABLE_5G94

RATE_ENABLE_2G97

RATE_ENABLE_1G485

RATE_ENABLE_270M

4:4

3:3

2:2

1:1

RW

0_b: 5.94Gb/s signals will not be detected

1_b: 5.94Gb/s signals will be detected

Enables auto-detection of 2.97Gb/s

(3G SDI) signals.

0_b: 2.97Gb/s signals will not be detected

1_b: 2.97Gb/s signals will be detected

Enables auto-detection of 1.485Gb/s (HD-

SDI) signals.

0_b: 1.485Gb/s signals will not be detected

1_b: 1.485Gb/s signals will be detected

Enables auto-detection of 0.27Gb/s

(SD-SDI) signals.

0_b: 0.27Gb/s signals will not be detected

1_b: 0.27Gb/s signals will be detected

Synchronous soft-reset for the PLL rate

detection state machine.

0_b: Normal operation of the PLL rate

detection state machine

0_h

PLL_SOFT_RESET

0:0

RW

1_b: Resets the PLL rate detection state

machine

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Table 5-1: Register Descriptions - Standard Address Space (Continued)

Bit

Slice

Reset

Value

Address Register Name

Parameter Name

R/W

Description

4D_h

4E_h

110_h

RESERVED

RSVD

15:0

RW

Reserved. Do not change.

Indicates whether the retimer is active or

bypassed.

—

RETIMER_BYPASS

LBR_HBR

15:15

14:14

RO

0_b: Retimer is active

1_b: Retimer is bypassed

Indicates high-bit-rate versus low-bit-rate.

0_b: Input data rate is 5.94Gb/s,

2.97Gb/s, 1.485Gb/s, or BYPASS

1_b: Input data rate is 270Mb/s or 125Mb/s

Indicates the current rate found by the PLL

rate detection state machine.

000_b: 0.125Gb/s

001_b: 0.270Gb/s

010_b: 1.485Gb/s

011_b: 2.97Gb/s

100_b: 5.94Gb/s

101_b: Reserved

110_b: Reserved

111_b: Reserved

—

DETECTED_RATE

13:11

RO

4F_h

PLL_STATUS

—

RSVD

10:10

9:9

RO

Reserved.

Indicates if the CDR is locked or unlocked.

0_b: CDR is unlocked

LOCKED

1_b: CDR is locked

Indicates whether or not the CDR has lost

the signal.

—

LOS

8:8

7:0

RO

0_b: Signal is present

1_b: Loss of signal

RSVD

Reserved.

GS6150

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Table 5-1: Register Descriptions - Standard Address Space (Continued)

Bit

Slice

Reset

Value

Address Register Name

Parameter Name

R/W

Description

Sticky bit indicating that the device entered

STANDBY mode at least once.

0 : Device has not entered STANDBY mode

since this bit was last cleared

b

ROCW

STANDBY_STICKY

11:11

10:10

—

1 : Devices has entered STANDBY mode since

b

this bit was last cleared

Sticky bit indicating that the device entered

SLEEP mode at least once

0 : Device has not entered SLEEP mode since

b

ROCW

SLEEP_STICKY

this bit was last cleared

1 : Device has entered SLEEP mode since this

b

bit was last cleared

Sticky bit indicating that the retimer is/has

been bypassed.

0 : Retimer has not been bypassed since this

b

—

ROCW

RETIMER_BYPASS_STICKY

9:9

8:8

7:7

bit was last cleared

1 : Retimer has been bypassed since this bit

b

was last cleared

This bit is cleared by writing any value to it.

Sticky bit indicating that the rate is/has been

270Mb/s (low bit-rate).

0 : Rate has not been 270Mb/s since this bit

b

ROCW

LBR_HBR_STICKY

was last cleared

1 : Rate has been 270Mb/s since this bit was

b

50_h

STICKY_STATUS

last cleared

This bit is cleared by writing any value to it.

Sticky bit indicating that a rate change has

occurred.

0 : Rate has not changed since this bit was last

b

ROCW

RATE_CHANGE_STICKY

cleared

1 : Rate has changed since this bit was last

b

cleared

This bit is cleared by writing any value to it.

Sticky bit indicating that lock was lost.

0 : Lock has not been lost since this bit was last

b

cleared

—

ROCW

LOCK_LOST_STICKY

RSVD

6:6

5:5

4:4

3:0

1 : Lock has been lost since this bit was last

b

cleared

This bit is cleared by writing any value to it.

Reserved.

Sticky bit indicating a loss of signal.

0 : Signal has not been lost since this bit was

b

last cleared

LOS_STICKY

RSVD

1 : Signal has been lost since this bit was last

b

cleared

This bit is cleared by writing any value to it.

Reserved.

GS6150

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Table 5-2: Register Descriptions - Extended Address Space

Reset

Value

(Dec)

Register

Name

Parameter

Name

Bit

Slice

Address

R/W

Description

4_h

RSVD

15:5

RW

Reserved. Do not change.

Sets the rate specific PLL loop-bandwidth

when the device is locked.

00001_b: Nominal / 4

00010_b: Nominal / 2

00100_b: Nominal (default)

01000_b: Nominal x 2

11100_b: Nominal x 4

PLL_LBW_

CONTROL_

REG_0

E4_h

4_h

PLL_LOOP_BANDWIDTH

4:0

RW

See Table 2-3: AC Electrical Characteristics

for the PLL loop-bandwidth value set at

each rate by each of these settings.

RW = Read/Write

RO = Read Only

ROCW = Read Only/ Clear on Write

ROSW = Read Only/ Set on Write

GS6150

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6. Typical Application Circuit

27MHz

VCC

VCC_DDO0

VCC_DDO1

*C1

*C2

1MW

DDI0P

IN

DDI0N

GND

XTAL/CLK_IN

XTAL_OUT

DDI1P

IN

XTAL_BUFF_OUT

1

DDI1N

GND

DDO0P

DDO0N

OUT

DDI2P

IN

DDI2N

GND

DDI3P

DDO1P

DDO1N

IN

OUT

GS6150

DDI3N

RSV_40

RSV_41

RST

GPIO0

GPIO1

IO

IN

GPIO2

GPIO3

DDI_SEL0/STROBE

DDI_SEL1

IN

RSV_37

VCO_FILT

SDIN

SDOUT

SCLK

CS

IN

LF+

LF-

OUT

C_LF

1μF

IN

Notes:

VCC IS 1.8V

VCC_DDO0 AND VCC_DDO1 ARE IN THE RANGE +1.2V TO +2.5V

XTAL IS OPTIONAL

*VALUES FOR C1 AND C2 ARE CHOSEN BASED ON THE REQUIRED LOADING FOR THE SELECTED CRYSTAL

IF AC COUPLING IS REQUIRED ON THE HIGH-SPEED SERIAL INPUTS AND OUTPUTS BY THE APPLICATION, A CERAMIC CAPACITOR 4.7μF OR HIGHER WITH A STABLE DIELECTRIC IS RECOMMENDED

Figure 6-1: GS6150 Typical Application Circuit

GS6150

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7. Package and Ordering Information

7.1 Package Dimensions

M

0.10 C A B

A

4.65 0.15

DATUM A

6.00

B

M

0.10 C A B

DATUM B

DETAIL A

2x

0.10 C

2x

0.10 C

0.20 0.050

48x

C

0.10 C

M

0.07 C A B

48x

M

0.05

C

0.08 C

DATUM A OR B

SEATING PLANE

0.40 0.10

DETAIL A (SCALE 3:1)

NOTES:

1. DIMENSIONS AND TOLERANCE IS IN CONFORMANCE TO ASME Y14.5–1994

2. ALL DIMENSIONS ARE IN MILLIMETERS OR IN DEGREES

Figure 7-1: Package Dimensions

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7.2 Recommended PCB Footprint

0.4

0.2

0.6

5.8 4.3

CENTER PAD

Note: All dimensions

in millimeters

4.3

5.8

Figure 7-2: GS6150 PCB Footprint

7.3 Packaging Data

Table 7-1: Packaging Data

Parameter

Value

Package Type

6mm x 6mm 48-pin QFN

Moisture Sensitivity Level (Note 1)

Junction to Case Thermal Resistance, θ_j-c

3

26.2°C/W

Junction to Air Thermal Resistance, θ_j-a

Junction to Board Thermal Resistance, θ_j-b

21.6°C/W

4.4°C/W

0.2°C/W

Yes

Psi, Ψ

Pb-free and RoHS Compliant

Note:

1. Value per JEDEC J-STD-020C

GS6150

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7.4 Marking Diagram

Pin 1 ID

XXXX - Last 4 digits of Assembly lot

E3 - Pb-free & Green indicator

YYWW - Date Code

GS6150

XXXXE3

YYWW

Figure 7-3: GS6150 Marking Diagram

7.5 Solder Reflow Profile

Temperature

60-150 sec.

20-40 sec.

260°C

250°C

3°C/sec max

217°C

6°C/sec max

200°C

150°C

25°C

Time

60-180 sec. max

8 min. max

Figure 7-4: Maximum Pb-free Solder Reflow Profile

7.6 Ordering Information

Table 7-2: Ordering Information

Part Number

Package

Temperature Range

GS6150-INE3

Pb-free 48-pin QFN

-40°C to 85°C

Pb-free 48-pin QFN

GS6150-INTE3

GS6150-INTE3Z

-40°C to 85°C

(250pc. tape and reel)

Pb-free 48-pin QFN

(2.5k tape and reel)

GS6150

Final Data Sheet

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DOCUMENT IDENTIFICATION

FINAL DATA SHEET

CAUTION

ELECTROSTATIC SENSITIVE DEVICES

The product is in production. Semtech reserves the right to make changes to the

product at any time without notice to improve reliability, function or design, in

order to provide the best product possible.

DO NOT OPEN PACKAGES OR HANDLE EXCEPT AT A STATIC-

FREE WORKSTATION

information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable

and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication

thereof does not convey nor imply any license under patent or other industrial or intellectual property rights. Semtech assumes

no responsibility or liability whatsoever for any failure or unexpected operation resulting from misuse, neglect improper

installation, repair or improper handling or unusual physical or electrical stress including, but not limited to, exposure to

parameters beyond the specified maximum ratings or operation outside the specified range.

SEMTECH PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-

SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF SEMTECH PRODUCTS IN

SUCH APPLICATIONS IS UNDERSTOOD TO BE UNDERTAKEN SOLELY AT THE CUSTOMER’S OWN RISK. Should a customer

purchase or use Semtech products for any such unauthorized application, the customer shall indemnify and hold Semtech and

its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs damages and attorney fees

which could arise.

Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners.

Contact Information

Semtech Corporation

200 Flynn Road, Camarillo, CA 93012

Phone: (805) 498-2111, Fax: (805) 498-3804

www.semtech.com

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型号：	GS6150-INTE3Z
厂家：	SEMTECH CORPORATION
描述：	GS6150 Multi-Rate 6G UHD-SDI Reclocker
文件：	总64页 (文件大小：1917K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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