GS6151-INTE3_技术文档

GS6151

GS6151 Multi-Rate 6G UHD-SDI

Reclocker

Key Features

Applications

•

SMPTE ST 2081, ST 424, ST 292, and

ST 259-C compliant

•

SMPTE ST 2081, SMPTE ST 424,

SMPTE ST 292, SMPTE ST 259-C coaxial cable serial

digital interfaces

•

Supports retiming data at rates of 125Mb/s, 270Mb/s,

1.485 and 1.485/1.001Gb/s, 2.97 and 2.97/1.001Gb/s,

5.94 and 5.94/1.001Gb/s

•

EN50083-9 DVB-ASI interfaces

MADI standard

•

Supports retiming of DVB-ASI signals

Automatic or Manual Rate Selection

Description

Detected rate indication in Auto Mode

The GS6151 is a low-power, multi-rate serial digital CDR

designed to automatically recover the embedded clock

from a digital video signal and re-time the incoming video

data.

•

2:1 input selector

Option of two reclocked data outputs

Two configurable GPIO pins with ability to output

device status, including:

The GS6151 will recover the embedded clock signal and

re-time the data from 6G UHD-SDI signals compliant with

SMPTE ST 2081. In addition, it can also re-time SMPTE ST

259-C, SMPTE ST 292, SMPTE ST 424 or DVB-ASI compliant

digital video signals as well as MADI audio streams.

Lock Detect

Loss of Signal (LOS)

Low/High bit-rate indication for slew-rate control of

SDI cable drivers

•

On-chip 100Ω differential input and output

termination

The GS6151 features two high-speed differential signal

inputs feeding a 2:1 input selector. Input termination is

on-chip for seamless matching to 100Ω differential

transmission lines. The input selector is a component of a

video switching system with tightly constrained timing

requirements.

Bypass support for rates up to 5940Mb/s

Manual Bypass function

Configurable automatic Bypass when not locked

•

Option to use external reference or operate

referenceless

The GS6151 includes programmable trace equalization to

compensate for high-frequency losses associated with

board-level interconnect.

Cascading reference buffer supports multiple CDRs

using a single reference source

Two CML outputs interface seamlessly to devices with a

CML input reference between 1.2V and 2.5V.

Input signal equalization and output signal

de-emphasis to compensate for trace dielectric losses

•

Single power supply operation at 1.8V

Programmable output swing and de-emphasis provide

flexibility in managing signal integrity of the output signals.

130mW typical power consumption (150mW with

second output enabled)

The GS6151 can operate in either automatic rate detection

or manual rate selection mode. In auto mode the device

will automatically detect and lock onto incoming data

signals at any supported rate.

•

Pb-free and RoHS compliant

Operating temperature range: -40°C to 85°C

GS6151

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The device can operate without an external 27MHz

frequency reference. For applications which require rapid

signal lock, an external 27MHz reference may be used to set

the VCO frequency when not locked to the input signal. The

presence of an external reference crystal is automatically

detected by the device.

A four-wire Gennum Serial Peripheral Interface (GSPI)

facilitates configuration and status monitoring of the

device. Multiple GS6151 devices can be daisy-chained

together with a single 4-pin connection to the host system.

This device is Pb-free, and the encapsulation compound

does not contain halogenated flame retardant. This

component and all homogenous sub-components are

RoHS compliant.

In systems that require passing of non-supported data

rates, the GS6151 can be configured to either automatically

or manually enter a bypass mode in order to pass the signal

without reclocking.

XTAL_CLK_OUT

XTAL_CLK_IN

XTAL_BUF_OUT

LF+, LF–

XTAL

Oscillator

Buﬀer

DDO0

Reference Divide

Data Buﬀer

DDO0

Retimer

Phase Frequency

Detector

Charge Pump

VCO

Selectable Divide

DDI0

Equalizer/

Data Mux

Phase Detector

DDO1

DDI1

Data Buﬀer

LOS

Detect

SPI

Control

Oscillator

GPIO0

GPIO1

DDI_SEL/

STROBE

GS6151 Functional Block Diagram

GS6151

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Revision History

Version

ECO

PCN

Date

Changes and/or Modifications

4

027137

—

August 2015

Updated date and revision number

Updated Table 2-2, Table 2-3, and

Table 5-1. Updated to Final Data

Sheet.

3

2

027035

026418

—

July 2015

Updated Table 2-2, Table 2-3,

Section 4.12 and Table 5-1.

1

0

024872

022627

—

May 2015

Updated Table 5-1.

New Document

October 2014

Contents

1. Pin Out.................................................................................................................................................................5

1.1 Pin Assignment ...................................................................................................................................5

1.2 Pin Descriptions ..................................................................................................................................6

2. Electrical Characteristics................................................................................................................................8

2.1 Absolute Maximum Ratings ...........................................................................................................8

2.2 DC Electrical Characteristics ...........................................................................................................9

2.3 AC Electrical Characteristics ......................................................................................................... 11

3. Input/Output Circuits.................................................................................................................................. 14

4. Detailed Description.................................................................................................................................... 16

4.1 Serial Data Inputs ............................................................................................................................. 16

4.1.1 Input Trace Equalization................................................................................................... 16

4.1.2 Input Selection ..................................................................................................................... 17

4.2 Reference Clock ................................................................................................................................ 18

4.3 Signal Monitoring ............................................................................................................................ 18

4.3.1 Loss of Signal Detection.................................................................................................... 18

4.3.2 Lock Detection ..................................................................................................................... 20

4.3.3 Rate Detection...................................................................................................................... 21

4.3.4 Low/High Bit Rate Detection for Slew Rate Control ............................................... 21

4.4 Low Power Modes ........................................................................................................................... 22

4.5 Serial Data Output ........................................................................................................................... 22

4.5.1 Output Impedance ............................................................................................................. 23

4.5.2 Output Signal Interface Levels ....................................................................................... 23

4.5.3 Adjustable Output Swing................................................................................................. 23

4.5.4 Output De-emphasis.......................................................................................................... 24

4.5.5 Output Common Mode Voltage.................................................................................... 24

4.6 Output Mute and Disable ............................................................................................................. 25

4.7 Bypass Mode ..................................................................................................................................... 25

4.8 DVB-ASI ............................................................................................................................................... 26

GS6151

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4.9 Device Power Up ............................................................................................................................. 26

4.9.1 Power on Reset (POR) ........................................................................................................ 26

4.10 GPIO Pins Configuration ............................................................................................................. 26

4.11 GSPI Host Interface ....................................................................................................................... 28

4.11.1 CS Pin..................................................................................................................................... 28

4.11.2 SDIN Pin................................................................................................................................ 28

4.11.3 SDOUT Pin ........................................................................................................................... 28

4.11.4 SCLK Pin................................................................................................................................ 30

4.11.5 Command Word Description........................................................................................ 30

4.11.6 GSPI Transaction Timing ................................................................................................ 33

4.11.7 Single Read/Write Access............................................................................................... 35

4.11.8 Auto-increment Read/Write Access........................................................................... 36

4.11.9 Setting a Device Unit Address...................................................................................... 37

4.11.10 Default GSPI Operation ................................................................................................ 38

4.12 Diagnostic Features ..................................................................................................................... 40

4.12.1 Horizontal Eye Monitor Modes .................................................................................... 40

4.12.2 PRBS Checker...................................................................................................................... 43

4.12.3 PRBS Generator.................................................................................................................. 45

5. Host Interface Register Map...................................................................................................................... 47

6. Typical Application Circuit ........................................................................................................................ 73

7. Package and Ordering Information ....................................................................................................... 74

7.1 Package Dimensions ...................................................................................................................... 74

7.2 Recommended PCB Footprint .................................................................................................... 75

7.3 Packaging Data ................................................................................................................................ 75

7.4 Marking Diagram ............................................................................................................................. 76

7.5 Solder Reflow Profile ...................................................................................................................... 76

7.6 Ordering Information ..................................................................................................................... 76

GS6151

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1. Pin Out

1.1 Pin Assignment

32

31

30

29

28

27

26

25

1

2

3

4

5

6

7

8

24

23

22

21

20

19

18

17

DDI0

DDO0

GND

VCC_DDO0

VEE_DDO

VCC_DDO1

DDO1

DDI1

GS6151 32-pin QFN

(4mm x 4mm)

DDI1

GPIO0

GPIO1

DDO1

DDI_SEL/STROBE

VSS_DIG

9

10

11

12

13

14

15

16

Figure 1-1: GS6151 Pin Out

GS6151

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1.2 Pin Descriptions

Table 1-1: GS6151 Pin Descriptions

Pin Number

Name

Type

Description

1, 2

3

DDI0, DDI0

GND

Input

Power

Input

Serial Digital Differential Input 0.

Input channel isolation. Connect to ground or leave unconnected.

Serial Digital Differential Input 1.

4, 5

DDI1, DDI1

Multi-function Control/Status Input/Output 0.

Signal options are:

LOS (output; default)

LOCKED

LBR_HBR

RATE_DET0

RATE_DET1

RATE_DET2

Digital

Input/Output

6

GPIO0

LOCKED_270M

LOCKED_1G485

LOCKED_2G97

LOCKED_5G94

RATE_CHANGE

DDO0_DISABLE

DDO1_DISABLE

This pin is configured using the GPIO0_SELECT and

GPIO0_IO_SELECT bits in the GPIO_CONTROL_REG_0 register.

Multi-function Control/Status Input/Output 1.

Signal options are:

LOS

LOCKED (output; default)

LBR_HBR

RATE_DET0

RATE_DET1

RATE_DET2

Digital

Input/Output

7

GPIO1

LOCKED_270M

LOCKED_1G485

LOCKED_2G97

LOCKED_5G94

RATE_CHANGE

DDO0_DISABLE

DDO1_DISABLE

This pin is configured using the GPIO1_SELECT and

GPIO1_IO_SELECT bits in the GPIO_CONTROL_REG_0 register.

Input selection control.

8

9

DDI_SEL/STROBE

XTAL_CLK_IN

Digital Input

Input

Used to select the high-speed input for processing through the

device. Refer to Table 4-2 for details on input selection.

Reference Crystal Pin/27MHz clock input. Connect to an external

circuit as shown in Figure 6-1: GS6151 Typical Application Circuit or

to a digital clock source (XTAL_BUF_OUT of another GS6150, GS6151,

GS6152, or a 27MHz clock output from another device). Connect to

ground if operating referenceless.

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Table 1-1: GS6151 Pin Descriptions (Continued)

Pin Number

Name

Type

Description

Reference Crystal Pin. Connect to a external circuit as shown in Figure

6-1: GS6151 Typical Application Circuit, or leave unconnected if

XTAL_CLK_IN is driven by an external clock source or is connected to

ground (referenceless).

10

XTAL_CLK_OUT

Output

Buffered clock reference output. Leave unconnected if not used to

drive 27MHz clock input of another device.

11

12

XTAL_BUF_OUT

SDIN

Output

Serial digital data input for the Gennum Serial Peripheral Interface

(GSPI) host control/status port.

Digital Input

Refer to 4.11 GSPI Host Interface for more detail

Serial digital data output for the Gennum Serial Peripheral Interface

(GSPI) host control/status port.

Digital

Output

13

14

SDOUT

SCLK

Refer to 4.11 GSPI Host Interface for more detail

Burst-mode clock input for the Gennum Serial Peripheral Interface

(GSPI) host control/status port.

Digital Input

Refer to 4.11 GSPI Host Interface for more detail

Chip select input for the Gennum Serial Peripheral Interface (GSPI)

host control/status port.

15

16

CS

Digital Input

Power

Active-low input.

Refer to 4.11 GSPI Host Interface for more detail

Most positive power supply for the internal logic

Connect to 1.8V.

VDD_DIG

Most negative power supply for the internal logic

Connect to ground.

17

18, 19

20

VSS_DIG

DDO1, DDO1

VCC_DDO1

Power

Output

Power

Differential serial data output 1.

Most positive power supply connection for the DDO1/DDO1 output

driver. Connect to any voltage between 1.2V and 2.5V.

Most negative power supply connections for the output drivers.

Connect to ground.

21

VEE_DDO

Power

Most positive power supply connection for the DDO0/DDO0 output

driver. Connect to any voltage between 1.2V and 2.5V.

22

23, 24

25

VCC_DDO0

DDO0, DDO0

VCO_DFT_FILT

Power

Output

Differential serial data output 0.

Power

Decoupling

Connect through decoupling capacitor to ground.

26

27

VCC_DFT

VEE_DFT

Power

Connect to 1.8V.

Connect to ground.

Connect to LF– through C_LF

Refer to Figure 6-1: GS6151 Typical Application Circuit.

28

29

LF+

LF–

Passive

Connect to LF+ through C_LF

Refer to Figure 6-1: GS6151 Typical Application Circuit.

GS6151

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Table 1-1: GS6151 Pin Descriptions (Continued)

Pin Number

Name

Type

Description

External decoupling for the VCO.

Refer to Figure 6-1: GS6151 Typical Application Circuit.

30

VCO_FILT

Power

Most positive power supply connection for the analog core

Connect to 1.8V.

31

32

—

VCC_CORE

VEE_CORE

Center Pad

Power

Most negative power supply connection to the analog core

Connect to GND.

Ground pad on bottom of package.

Connect to ground.

2. Electrical Characteristics

2.1 Absolute Maximum Ratings

Table 2-1: Absolute Maximum Ratings

Parameter

Value

–0.5 to +2.1V_DC

–0.5 to +2.8V_DC

Supply Voltage – Core (VCC_CORE, VDD_DIG)

Supply Voltage – Output Driver (VCC_DDO0,

VCC_DDO1)

Input ESD Voltage

4kV

Storage Temperature Range (T_S)

–50ºC to +125ºC

–40ºC to +85ºC

–0.3 to (V_{CC_CORE}+ 0.3)V_DC

+260ºC

Operating Temperature Range (T_A)

Input Voltage Range (any input pin)

Solder Reflow Temperature

Note: Absolute Maximum Ratings are those values beyond which damage may occur.

Functional operation outside of the ranges shown in the AC/DC electrical characteristics tables

is not guaranteed.

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2.2 DC Electrical Characteristics

Table 2-2: DC Electrical Characteristics

VCC_CORE, VDD_DIG = +1.8V 5%, T_A= –40ºC to +85ºC unless otherwise specified

Parameter

Symbol Conditions

Min

Typ

Max

Units Notes

V_{CC_CORE}

V_{DD_DIG}

,

Supply Voltage – Core

(VCC_CORE, VDD_DIG)

—

1.710

1.8

1.890

V

Supply Voltage – Output

Driver (VCC_DDO0,

VCC_DDO1)

V_{CC_DDO0}

V_{CC_DDO1}

,

1.140

—

2.625

V

Data Rate 6G,

DDO1/DDO1 disabled

—

140

130

185

170

mW

1, 2

Data Rate <6G,

DDO1/DDO1 disabled

Data Rate 6G,

Default Settings,

DDO1/DDO1 enabled

—

210

190

280

575

280

255

360

630

mW

3, 4

5

Data Rate <6G,

Default Settings,

DDO1/DDO1 enabled

P_D

Power

Maximum Supply and Power

Settings with Diagnostic

Features Off

Maximum Supply and Power

Settings with Diagnostic

Features On

5

P_SLEEP

Power (Sleep operation)

—

20

80

35

mW

Power (Standby

operation)

P_STANDBY

110

Output Swing Register

Setting = 0000_b

—

4.8

7.5

15

7

mA

6, 7

I_{CC_DDO0}

I_{CC_DDO1}

,

Output Swing Register

Setting= 0100_b

Supply Current - Output

Driver

12

22

Output Swing Register

Setting = 1100_b

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Table 2-2: DC Electrical Characteristics (Continued)

VCC_CORE, VDD_DIG = +1.8V 5%, T_A= –40ºC to +85ºC unless otherwise specified

Parameter

Symbol Conditions

Output De-emphasis

Min

Typ

Max

Units Notes

Disabled

Data Rate 6G

—

82

—

mA

8

Output De-emphasis

Disabled

—

74

—

I_{CC_CORE}

Supply Current - Core

Data Rate 3G

Output De-emphasis Enabled

Data Rate 6G

—

90

81

—

mA

8

Output De-emphasis Enabled

Data Rate 3G

I_{CC_DIG}

Supply Current - Digital

Serial Input Termination

Serial Output Termination

External Crystal Referenced

Differential

—

75

7

12

mA

Ω

100

125

Differential

Ω

V_{CC_CORE}

- 50mV

Serial Input Common

Mode Voltage

V_CMIN

—

0.9

—

V

9, 10

0.65*

VDD_DIG

V_IH

VDD_DIG

Input Voltage - Digital

Pins

(CS, SDIN, CLK, GPIO[0:1])

0.35*

VDD_DIG

V_IL

0

VDD_DIG

– 0.45

V_OH

V_OL

I_OH= -2mA

I_OL= 2mA

Output Voltage - Digital

Pins

(SDOUT, GPIO[0:1])

—

V

—

0.45

Notes:

1. Normal operation in referenceless mode, minimum output swing with de-emphasis disabled

2. VCC_DDO0/1 = 1.2V

3. The swing is default and de-emphasis is on

4. VCC_DDO0/1 = 1.8V

5. DDO0/DDO0 and DDO1/DDO1 set to maximum swing setting, external crystal reference used

6. Consumption per enabled DDO output

7. Refer to Table 4-4 for the exact register settings for each ΔV_DDOoutput swing listed

8. For two enabled outputs

9. Maximum input voltage level = 1.8V 5%

10. Up to a maximum swing of 800mV

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2.3 AC Electrical Characteristics

Table 2-3: AC Electrical Characteristics

VCC_CORE, VDD_DIG = +1.8V 5%, T_A= –40ºC to +85ºC unless otherwise specified

Parameter

Symbol

DR_BYPASS

ΔV_SDI

Conditions

Min

Typ

Max

Units

Notes

Input Data Rate (Bypass)

Input Sensitivity

Bypass mode enabled

Differential

3

—

5940

800

Mb/s

1

mV_ppd

200

Output Swing Register

Setting = 0100_b

mV_ppd

310

600

410

800

510

2

ΔV_DDO

Output Voltage Swing

Output Swing Register

Setting = 1100_b

1000

Serial Input Jitter

Tolerance

Square wave

modulation

IJT

0.8

—

50

30

UI

Referenceless

ms

3

With External Reference

(MADI enabled)

PLL Lock Time —

Asynchronous

t_ALOCK

With External Reference

(MADI disabled)

—

20

ms

3

Referenceless

—

10

μs

3

PLL Lock Time —

Synchronous

t_SLOCK

With External Reference

20% ~ 80% rising edge

into 50Ω load

t_riseDDO

—

80

ps

4

Serial Data (DDO0 and

DDO1) Output Rise And

Fall Time

20% ~ 80% falling edge

into 50Ω load

t_fallDDO

Rise And Fall Time

Mismatch (DDO0 and

DDO1)

—

15

5

ps

%

4

Duty Cycle Distortion

(DDO0 and DDO1)

t_OJ(125Mb/s)

t_OJ(270Mb/s)

t_OJ(1485Mb/s)

t_OJ(2970Mb/s)

t_OJ(5940Mb/s)

t_OJ(BYPASS)

UI_P-P

ps

—

0.02

0.03

0.04

0.07

—

0.03

0.06

0.09

0.13

37

5, 6

BW = Nominal

PRN 2²³– 1 test pattern

Serial Data Output Jitter

Intrinsic

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Table 2-3: AC Electrical Characteristics (Continued)

VCC_CORE, VDD_DIG = +1.8V 5%, T_A= –40ºC to +85ºC unless otherwise specified

Parameter

Symbol

Conditions

Min

Typ

Max

Units

Notes

PLL_LOOP_BANDWIDTH

= 00001

—

37

—

kHz

7

PLL_LOOP_BANDWIDTH

= 00010

—

74

148

296

590

80

—

kHz

MHz

kHz

MHz

kHz

MHz

7

PLL_LOOP_BANDWIDTH

= 00100 (default)

BW_{LOOP(125Mb/s)}

PLL_LOOP_BANDWIDTH

= 01000

PLL_LOOP_BANDWIDTH

= 10000

PLL_LOOP_BANDWIDTH

= 00001

PLL_LOOP_BANDWIDTH

= 00010

160

320

640

1.28

438

875

1.75

3.5

PLL_LOOP_BANDWIDTH

= 00100 (default)

BW_{LOOP(270Mb/s)}

BW_{LOOP(1485Mb/s)}

BW_{LOOP(2970Mb/s)}

PLL_LOOP_BANDWIDTH

= 01000

PLL_LOOP_BANDWIDTH

= 10000

PLL Loop Bandwidth

PLL_LOOP_BANDWIDTH

= 00001

PLL_LOOP_BANDWIDTH

= 00010

PLL_LOOP_BANDWIDTH

= 00100 (default)

PLL_LOOP_BANDWIDTH

= 01000

PLL_LOOP_BANDWIDTH

= 10000

7

PLL_LOOP_BANDWIDTH

= 00001

875

1.75

3.5

PLL_LOOP_BANDWIDTH

= 00010

PLL_LOOP_BANDWIDTH

= 00100 (default)

PLL_LOOP_BANDWIDTH

= 01000

7.0

PLL_LOOP_BANDWIDTH

= 10000

14.0

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Table 2-3: AC Electrical Characteristics (Continued)

VCC_CORE, VDD_DIG = +1.8V 5%, T_A= –40ºC to +85ºC unless otherwise specified

Parameter

Symbol

Conditions

Min

Typ

Max

Units

Notes

PLL_LOOP_BANDWIDTH

= 00001

—

1.75

—

MHz

7

PLL_LOOP_BANDWIDTH

= 00010

—

3.5

7.0

—

MHz

7

PLL_LOOP_BANDWIDTH

= 00100 (default)

BW_{LOOP(5940Mb/s)}

PLL Loop Bandwidth

PLL_LOOP_BANDWIDTH

= 01000

14.0

28.0

PLL_LOOP_BANDWIDTH

= 10000

Note:

1. Edge detection method for LOS detection should be used for data rates below 20Mb/s

2. Refer to Table 4-4 for the exact register settings for each ΔV_DDOoutput swing listed

3. PRBS23 pattern used for supported video rates

4. At HD, 3G, and 6G rates

5. Jitter measured using an oscilloscope according to SMPTE RP-184

6. Accumulated jitter measured peak to peak differential over 2000 hits

7. Test pattern used is clock pattern with 100% toggle rate

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3. Input/Output Circuits

VCC_DDO0/1

VCC_CORE

3.7kΩ

50Ω

RLC

DDI

DDO

18.5kΩ

Figure 3-1: DDI0, DDI0, DDI1, DDI1 Serial Digital

Differential Inputs

Figure 3-2: DDO0, DDO0, DDO1, DDO1 Serial Digital

Differential Output

VDD_DIG VDD_DIG

VDD_DIG

SDIN,

SCLK

SDOUT

100kΩ

Figure 3-3: SDIN and SCLK

Figure 3-4: SDOUT

VDD_DIG

100kΩ

CS

Figure 3-5: CS

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VDD_DIG

DDI_SEL/

STROBE

XTAL_BUF_OUT

100kΩ

Figure 3-7: XTAL_BUF_OUT

Figure 3-6: DDI_SEL/STROBE

VDD_DIG

1kΩ

GPIO

100kΩ

VDD_DIG

Figure 3-8: General Purpose Inputs/Outputs (GPIO)

VDD_DIG

EN

VDD_DIG

246Ω

XTAL_CLK_OUT

246Ω

XTAL_CLK_IN

EN

Figure 3-9: XTAL_CLK_IN and XTAL_CLK_OUT

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4. Detailed Description

The GS6151 is a multi-standard CDR for signals operating at the following data rates:

125Mb/s, 270Mb/s, 1.485Gb/s, 1.485/1.001Gb/s, 2.97Gb/s, 2.97/1.001Gb/s, 5.94Gb/s,

and 5.94/1.001Gb/s.

4.1 Serial Data Inputs

The GS6151 features two 100Ω terminated differential input buffers.

A serial data input signal may be connected to either of the two input pin pairs of the

device: DDI0/DDI0 and DDI1/DDI1

By default, the self-biasing circuit at the input is enabled to allow AC coupling to

upstream devices. To enable DC coupling of the inputs, the user must disable the

self-biasing network by setting bits 4:4 through 5:5 to 0 in the register 7 :

h

DDI[0:1]_TRACE_EQ_DC_TERM_ENABLE.

In order to select DC coupling, please ensure that the output common mode of the

upstream device is in range of the input common mode voltage range shown in

Table 2-2.

The serial digital input buffer is capable of operating with any binary coded signal that

meets the input signal level requirements defined below, with any data rate between

3Mb/s and 5.94Gb/s.

4.1.1 Input Trace Equalization

The GS6151 features adjustable trace equalization to compensate for PCB trace

dielectric losses up to half the maximum supported data rate, or 3GHz.

Table 4-1: Equalization Settings

Data Rate

Trace Loss

Settings

2.97Gb/s and below

5.94Gb/s

0-7dB of trace loss at 1.5GHz

0-10dB of trace loss at 3GHz

7-12dB of trace loss at 1.5GHz

negligible trace loss

LOW (default)

2.97Gb/s and below

—

HIGH

0dB or EQ_BYPASS

These settings are selected using the DDI0_TRACE_EQ_CONTROL and

DDI1_TRACE_EQ_CONTROL bits in the INPUT_CONTROL_REG_0 register at address 5 .

h

The default state of the device is input trace equalization on all inputs set to LOW.

If system jitter profile allows, it is recommended that the loop bandwidth is reduced to

the minimum setting to maximize performance.

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4.1.2 Input Selection

The GS6151 incorporates a 2:1 input selector which allows the connection of two

independent streams of video/data.

The selector is controllable in three separate ways:

1. The DDI_SEL/STROBE pin can be used to select the input.

2. A GSPI accessible register can be used to select the input, with the state change

occurring as soon as the register value changes.

3. A GSPI accessible register can be used to select the input, with a rising edge on the

STROBE pin triggering a change to the next state.

Since these states are mutually exclusive, the DDI_SEL pin is shared with the STROBE

function.

In the case of using the DDI_SEL/STROBE pin (#1 above) or the STROBE pre-select

method (#3 above), the input selector will switch within 1μs of the change of state on

the corresponding pin(s). This strict timing requirement is not maintained when using

GSPI register selection (#2 above).

Each of the device’s two inputs is selected as shown in Table 4-2.

Table 4-2: Pin and Register Settings for Input Selection

Register Settings

Differential

DDI_SEL/STROBE High-speed Input

INPUT_SELECTION_

DDI_SELECT

Selected

CONTROL 7 [9:8]

7 [10]

h

X0 (default)

01

X

0

1

LOW

HIGH

X

DDI0, DDI0

DDI1, DDI1

DDI0, DDI0

DDI1, DDI1

01

X

on LOW-to-HIGH

transition

11

0

1

DDI0, DDI0

DDI1, DDI1

on LOW-to-HIGH

transition

11

Note: ‘X’ indicates ‘Do Not Care’

The DDI_SEL/STROBE pin includes an internal pull-down, which pulls the input voltage

LOW if the pin is left unconnected.

When using the STROBE pre-select method (#3 above), the pre-selected input buffer

and trace EQ is powered up in advance of the STROBE pulse.

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4.2 Reference Clock

The GS6151 can operate with or without an external frequency reference. For

applications requiring rapid asynchronous locking, a 27MHz reference or crystal is

required.

The PLL lock times for both referenceless and external crystal reference operation are

given in Table 2-3: AC Electrical Characteristics.

If a reference is connected to the XTAL_CLK_IN pin or a crystal is connected to the

XTAL_CLK_IN and XTAL_CLK_OUT pins of the device, it will automatically be used as the

reference frequency for rapid asynchronous lock. If XTAL_CLK_IN is not connected to a

crystal, XTAL_CLK_OUT must be left unconnected.

The XTAL_CLK_IN pin operates correctly when connected directly to the

XTAL_BUF_OUT from another GS6151, or a 27MHz output of a different device.

4.3 Signal Monitoring

The GS6151 measures and reports the following signal status and quality monitoring

parameters:

•

Loss of Signal

Lock Detection

Rate Detection

Low/High Bit Rate Detection

4.3.1 Loss of Signal Detection

LOS (Loss of Signal) detection is an active HIGH output available to the application on

either of the GPIO0 or GPIO1 multi-function status and control pins. It is selected for

output using the GPIO[0:1]_IO_SELECT and GPIO[0:1]_SELECT bits accessible in the

GPIO_CONTROL_REG_0 register at address 2 . It is the default output of the GPIO0 pin.

h

LOS indicates when the serial digital signal selected by the input selector is invalid. This

function is always active.

The corresponding GPIO pin will be HIGH (signal lost) when the input signal amplitude

within a predefined window falls below the threshold set by the bits

DDI[0:1]_LOS_THRESHOLD_CONTROL in the LOS_CONTROL_REG_1 register at address

10 . The LOS threshold hysteresis can be set by the LOS_HYSTERESIS bits in the

h

LOS_CONTROL_REG_0 register at address F .

h

The corresponding GPIO pin will be LOW (signal present) when the input signal

amplitude within a predefined window is above the defined threshold.

The LOS status is also available through the LOS bit in the PLL_STATUS register at

address 4F , and as a sticky status through the LOS_STICKY bit in the STICKY_STATUS

h

register at address 50 .

h

The corresponding GPIO pin will be LOW (signal present) when the input signal

amplitude within a predefined window is above the defined threshold.

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The method of strength detection is measurement of the average rectified differential

voltage on the input pins. The strength detection method is therefore inherently

dependent on the input signal's eye shape, particularly the rise/fall times of the input

signal relative to the data rate. Additionally, the circuit has a lower bandwidth limit of

operation (20Mb/s) below which it is recommended that the edge detection method is

used. The absolute value of the threshold can be determined for any input swings

according to Equation 4-1 below:

1.9mV × (DDI[0..3]_LOS_THRESHOLD_CONTROL ) × 53

----------------------------------------------------------------------------------------------------------------------------------------

Threshold =

Equation 4-1

(DEVICE_SPECIFIC_LOS_THRESHOLD)

where DEVICE_SPECIFIC_LOS_THRESHOLD specifies the LOS threshold value for a

100mV input swing at SD-rate specific to each device. The other rates scale according to

the fractional relationship given in Figure 4-1 and Figure 4-2 below.

60

55

50

45

40

35

30

0

20

40

60

80

100

120

Frequency (Mb/s)

Figure 4-1: LOS Threshold at 100mV Input Swing vs. Low Frequency Rates for a Nominal

DEVICE_SPECIFIC_LOS_THRESHOLD of 53

Note: Edge detection method is recommended for signals in shaded areas.

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60

55

50

45

40

35

30

SD-SDI

HD-SDI

3G-SDI

6G-SDI

0

1.485

2.97

Frequency (Gb/s)

4.455

5.94

Figure 4-2: LOS Threshold at 100mV Input Swing vs. SDI Data Rates for a Nominal

DEVICE_SPECIFIC_LOS_THRESHOLD of 53

Strength detection is unaffected by the Trace EQ settings in INPUT_CONTROL_REG_0.

When edge detection is used as the method of LOS detection the corresponding GPIO

pin will be HIGH (signal lost) when no transitions are detected on the selected input. The

corresponding GPIO pin will be LOW (signal present) when transitions are detected on

the input. The LOS status is also available through the LOS bit in the PLL_STATUS

register, and as a sticky status through the LOS_STICKY bit in the STICKY_STATUS

register at address 50 .

h

4.3.2 Lock Detection

The GS6151 lock detection circuitry outputs a LOCKED status signal which indicates that

the CDR has achieved phase lock to the incoming data stream. The LOCKED signal is an

active HIGH output available to the application on either of the GPIO[0:1] multi-function

status and control pins. It is selected for output using the GPIO[0:1]_IO_SELECT and

GPIO[0:1]_SELECT bits accessible in the GPIO_CONTROL_REG_0 register. By default,

LOCKED is output on GPIO1.

The LOCKED status is also available from the LOCKED bit in the PLL_STATUS register,

and the LOCK_LOST_STICKY bit in the STICKY_STATUS register indicates whether lock

has been lost since the bit was last cleared.

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4.3.2.1 Synchronous and Asynchronous Lock Time

Asynchronous lock time is defined as the time it takes the device to lock when a signal

is first applied to the serial digital inputs, or when the signal rate changes.

The synchronous lock time is defined as the time it takes the device to lock to a signal

which has been momentarily interrupted.

The asynchronous and synchronous lock times are defined in Table 2-3: AC Electrical

Characteristics.

To qualify for synchronous lock time, the maximum interruption time of the signal is

10μs for a 270Mb/s signal. 1.485Gb/s, 2.97Gb/s, and 5.94Gb/s signals, as well as their

ƒ/1.001 components, have a maximum interruption time of 6μs. The new signal, after

interruption, must have the same frequency as the original signal but can have arbitrary

phase.

4.3.3 Rate Detection

The GS6151 can be manually forced to lock to a specific supported data rate, or

automatically search for and lock to supported rates. The selection between manual and

automatic rate selection is through the FORCE_PLL_RATE and

FORCE_PLL_RATE_ENABLE bits of the PLL_CONTROL register at address 4C . By default

h

the device is set to automatically search for supported SDI rates.

When set to automatically detect supported data rates, the device repeatedly cycles

through each supported rate that is enabled through the RATE_ENABLE_5G94,

RATE_ENABLE_2G97, RATE_ENABLE_1G485, RATE_ENABLE_270M and

RATE_ENABLE_125M bits of the PLL_CONTROL register, until the device phase locks to

one of the enabled rates. If lock is lost the rate search resumes, continuously testing for

each rate in sequence until lock is regained.

The device reports the current data rate setting of the automatic rate search state

machine through the DETECTED_RATE bits in the PLL_STATUS register at address 4F .

h

Table 4-3 below shows the supported rate that can be detected.

Table 4-3: Automatic Rate Detection - Supported Data Rates

DETECTED_RATE

Data Rate

000

001

010

011

100

125Mb/s – MADI

270Mb/s – SD

1.485Gb/s – HD

2.97Gb/s – 3G

5.94Gb/s – 6G

4.3.4 Low/High Bit Rate Detection for Slew Rate Control

A status output named LBR_HBR is provided to control the slew rate selection input of

a downstream SDI cable driver. It can be connected to the SD_EN input of drivers such

as the GS6080 or GS6081 using the Semtech recommended application circuit.

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When this signal is HIGH, the data rate is 270Mb/s (SD) or 125Mb/s (MADI). This signal is

LOW for all other supported data rates, and when the GS6151 is operating in Bypass

Mode or any time the device is not locked.

The LBR_HBR output signal is available on either of the GPIO[0:1] multifunction status

and control pins. It is selected for output using the GPIO[0:1]_IO_SELECT and

GPIO[0:1]_SELECT bits accessible in the GPIO_CONTROL_REG_0 register at address 2 .

h

4.4 Low Power Modes

The device can be programmed via the GSPI to operate in two different low power

modes. SLEEP mode has minimum power consumption at the expense of recovery time

upon de-assertion of the FORCE_PWRDN_SLEEP bit. STANDBY mode has higher power

consumption relative to SLEEP mode but minimizes time to return to operation on

de-assertion of the FORCE_PWRDN_STANDBY bit. The features affected by each mode

are outlined below.

SLEEP mode:

•

LOS detection remains functional

The GSPI remains functional

The reference oscillator remains functional

STANDBY mode:

•

LOS detection remains functional

The GSPI remains functional

The reference oscillator remains functional

The VCO and PLL remains functional so as to minimize the lock time when a signal is detected

The rate detector remains set to the last valid data rate. On detection of a signal, the

last valid rate is tested first by the rate detect state machine

The device can be programmed to automatically enter into SLEEP or STANDBY mode

when LOS is asserted by programming the AUTO_PWRDN_DISABLE bit in the

PWRDN_CONTROL register at address 17 . The AUTO_PWRDN_MODE bit in the same

h

register selects which mode, SLEEP or STANDBY, is entered into upon assertion of LOS.

The device also features a power-save feature that reduces power when the CDR is

locked to HD, 3G or 6G rates. The HS_LOCKED_POWER_SAVE parameter of register

PWR_CONTROL at address D2 can be set to 1 to enable this feature.

h

4.5 Serial Data Output

The GS6151 has two current-mode differential output drivers, each capable of driving

up to 930mV differential into an external 100Ω differential load.

pp

The output drivers operate with any binary coded signal with supported data rates up

to 5.94Gb/s. This is applicable to both the serial data (DDO, DDO, DDO1, DDO1) outputs

of the device.

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4.5.1 Output Impedance

Each of the GS6151’s output buffers include two on-chip, 50Ω termination resistors.

4.5.2 Output Signal Interface Levels

The serial digital outputs operate within specification with an output CML power supply

of 1.2V to 2.5V.

4.5.3 Adjustable Output Swing

Through the GSPI, the output swing can be set in the range from approximately

230mV

to 930mV

in 45mV

increments, when the outputs are terminated with

ppd

50Ω loads. For the exact values, please see Table 4-4 below.

The output swing for each data rate is controlled using the bits in the

DRIVER_CONTROL_REG_3, DRIVER_CONTROL_REG_4, DRIVER_CONTROL_REG_5, and

DRIVER_CONTROL_REG_6 registers at addresses 1C through 1F .

h

The device automatically adjusts the swing setting depending on the state of the device

(i.e. detected rate, bypass mode, or mute). There are separate register controls for mute,

bypass and each data rate.

Table 4-4: Serial Digital Output Swing Settings

Register Setting

(See Note 1)

Min

Typ

Max

Units

0000_b

175

205

245

280

310

345

380

420

455

490

530

565

600

230

275

325

370

410

460

510

560

605

655

705

755

800

290

345

405

460

510

575

640

700

760

820

880

945

1000

mV

0001_b

0010_b

0011_b(default)

0100_b

0101_b

0110_b

0111_b

1000_b

1001_b

1010_b

1011_b

1100_b

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Table 4-4: Serial Digital Output Swing Settings (Continued)

Register Setting

(See Note 1)

Min

Typ

Max

Units

1101_b

630

670

700

840

890

930

1050

1110

1160

mV

1110_b

1111_b

Note:

1. Applicable registers that can be programmed with the values shown above are DDO0_SWING_1G485,

DDO0_SWING_270M, DDO0_SWING_125M, DDO0_SWING_BYPASS, DDO0_SWING_MUTE,

DDO0_SWING_5G94, DDO0_SWING_2G97, DDO1_SWING_1G485, DDO1_SWING_270M,

DDO1_SWING_125M, DDO1_SWING_BYPASS, DDO1_SWING_MUTE, DDO1_SWING_5G94, and

DDO1_SWING_2G97

4.5.4 Output De-emphasis

The GS6151 features adjustable output de-emphasis to compensate for PCB dielectric

trace loss. Each output can be independently set to a different de-emphasis setting for

each detected rate through controls found in the DRIVER_CONTROL_REG_1 and

DRIVER_CONTROL_REG_2 registers.

The effect of de-emphasis, illustrated in Figure 4-3, is to attenuate the swing of bits that

do not follow a bit transition (V ). The swing of bits that do follow a bit transition (V

)

DE

nom

is set by the output swing registers found in Section 4.5.3 and do not depend on the

de-emphasis settings.

Nominal

Swing (V_nom

De-emphasized

Swing (V_DE)

)

Data Pattern

0

1

0

De-emphasis = 20 x log₁₀(V_nom/ V_DE)

Figure 4-3: De-emphasis Waveform

The default de-emphasis settings for each rate are given in the register descriptions for

DRIVER_CONTROL_REG_1 and DRIVER_CONTROL_REG_2 in Table 5-1. De-emphasis is

disabled on both outputs in Bypass mode, when the output is muted, or when the

device is not locked.

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4.5.5 Output Common Mode Voltage

The output common mode voltage level (V

) is a function of the output voltage

) and how the transmission line is

CMOUT

swing, the output driver supply voltage (V

CC_DDO

terminated. If the outputs are terminated through 50Ω resistors to a voltage V

TERM

equal to V

, as shown in Figure 4-5 below, the output common mode voltage is

CC_DDO

given by the following expression:

ΔV_DDO

------------------

4

V_CMOUT= V_{CC_DDO}

–

Equation 4-2

Equation 4-3

If the differential outputs are terminated across a 100Ω resistor, as shown in Figure 4-4

below, the output common mode voltage is given by the following expression:

ΔV_DDO

V_CMOUT= V_{CC_DDO}

–

------------------

2

GS6151

VCC_DDO

V_TERMV_TERM

50Ω

50Ω 50Ω

50Ω

DDO

100Ω

Figure 4-4: 100Ω Parallel Output Termination

Figure 4-5: 50Ω Termination to V

TERM

4.6 Output Mute and Disable

The GS6151 outputs can each be individually muted using the DDO0_MUTE and

DDO1_MUTE bits in the DRIVER_CONTROL_REG_0 register at address 19 .

h

Each output can also be independently disabled through either register or GPIO control.

When disabled each pin of the output is pulled to V

. Register

CC_DDO

DRIVER_CONTROL_REG_0 contains both register based disable bits (DDO0_DISABLE,

DDO1_DISABLE) and bits for selection between register and GPIO control

(DDO0_DISABLE_SELECT, DDO1_DISABLE_SELECT). For GPIO control refer to

Section 4.10. By default DDO0, DDO0 is enabled/disabled through register control and

set to enabled. DDO1, DDO1 is enabled by default.

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4.7 Bypass Mode

In Bypass mode, the GS6151 passes the input data to the outputs, bypassing the

retiming functionality.

There are two bits in the control registers that control the bypass function:

MANUAL_BYPASS and AUTO_BYPASS in the CDR_BYPASS register at address 20 . The

h

MANUAL_BYPASS bit is inactive (set to 0) by default. The AUTO_BYPASS bit is active (set

to 1) by default, and places the GS6151 CDR into bypass mode when the PLL is not

locked to a data rate. The bypass function does not affect the trace equalization function

of the device.

Note: If MANUAL_BYPASS is active, it overrides the AUTO_BYPASS bit setting.

4.8 DVB-ASI

The GS6151 has the ability to reclock DVB-ASI signals at 270Mb/s. All relevant settings

and control registers that apply to SD-SDI signals at 270Mb/s are also compatible with

DVB-ASI signals at 270Mb/s.

4.9 Device Power Up

4.9.1 Power on Reset (POR)

The GS6151 features an on-chip power-on-reset that places all registers and internal

state machines into their known, default states when the chip is powered up.

4.10 GPIO Pins Configuration

The GS6151 has two GPIO pins that can each be configured as outputs for various

internal status signals, or as inputs to disable either output-driver via pin control. The

bits GPIO[0:1]_IO_SELECT are used to configure the GPIO pins as outputs (0) or inputs

(1). The signals that are output or input on the GPIO pins are selected by the

GPIO[0:1]_SELECT bits, in conjunction with the GPIO[0:1]_IO_SELECT bits of

GPIO_CONTROL_REG_0 at address 2 . The signals that can be output on the GPIO pins

h

are listed in Table 4-5 below and the signals that can be input are listed in Table 4-6.

Table 4-5: GPIO Status Outputs

GPIO[0:1]_SELECT

Parameter

Description

Loss of signal indication - High when there is no detected

signal on the selected DDI input

0000

LOS

Phase lock indication - High when the CDR has

phase-locked to a valid input signal

0001

0010

LOCKED

Low bit-rate/High bit-rate - High when the part is locked to

the SD data rate; low for all other data rates and in bypass.

LBR_HBR

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Table 4-5: GPIO Status Outputs (Continued)

GPIO[0:1]_SELECT

Parameter

Description

0101

0110

0111

RATE_DET0

RATE_DET1

RATE_DET2

Rate Detect - Three bits used in conjunction that represent

the data rate detected by the rate search state machine.

Refer to Table 4-3 for rate encoding details.

High when the rate search state machine is locked to a

MADI data rate (125Mb/s)

1000

1001

1010

1011

1100

LOCKED_125M

LOCKED_270M

LOCKED_1G485

LOCKED_2G97

LOCKED_5G94

High when the rate search state machine is locked to an SD

data rate (270Mb/s)

High when the rate search state machine is locked to an HD

data rate (1.485Gb/s)

High when the rate search state machine is locked to a 3G

data rate (2.97Gb/s)

High when the rate search state machine is locked to a 6G

data rate (5.94Gb/s)

When a change in the data rate is detected by the rate

search state machine, the RATE_CHANGE signal is pulsed

high for a duration of 37ns

1101

RATE_CHANGE

The signals that can be input on the GPIOs are listed in Table 4-6 below.

Table 4-6: GPIO Signal Inputs

GPIO[0:1]_SELECT

Parameter

Description

0000

0001

DDO0_DISABLE

DDO1_DISABLE

Disables serial data output 0 (DDO0, DDO0)

Disables serial data output 1 (DDO1, DDO1)

By default, the GPIO pins are configured to the following parameters:

GPIO0: LOS (output)

GPIO1: LOCKED (output)

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4.11 GSPI Host Interface

The GS6151 is controlled via the Gennum Serial Peripheral Interface (GSPI).

The GSPI host interface is comprised of a serial data input signal (SDIN pin), serial data

output signal (SDOUT pin), an active-low chip select (CS pin) and a burst clock (SCLK

pin).

The GS6151 is a slave device, therefore the SCLK, SDIN and CS signals must be sourced

by the application host processor.

All read and write access to the device is initiated and terminated by the application

host processor.

It is strongly recommended to connect the GSPI pins of the GS6151 to a host/system

processor/controller or FPGA to facilitate optimization of the device to meet specific

application requirements. Modification of many device settings is only facilitated

through the GSPI of the GS6151, and is not available on external pins.

4.11.1 CS Pin

The Chip Select pin (CS) is an active-low signal provided by the host processor to the

GS6151.

The high-to-low transition of this pin marks the start of serial communication to the

GS6151.

The low-to-high transition of this pin marks the end of serial communication to the

GS6151.

There is an option for each device to use a separate unique Chip Select signal from the

host processor or for up to 32 devices to be connected to a single Chip Select when

making use of the Unit Address feature.

Only those devices whose Unit Address matches the UNIT ADDRESS in the GSPI

Command Word will respond to communication from the host processor (unless the

B’CAST ALL bit in the GSPI Command Word is set to 1).

4.11.2 SDIN Pin

The SDIN pin is the GSPI serial data input pin of the GS6151.

The 16-bit Command and Data Words from the host processor or from the SDOUT pin

of other devices are shifted into the device on the rising edge of SCLK when the CS pin

is low.

4.11.3 SDOUT Pin

The SDOUT pin is the GSPI serial data output of the GS6151.

All data transfers out of the GS6151 to the host processor or to the SDIN pin of other

connected devices occur from this pin.

By default at power up or after system reset, the SDOUT pin provides a non-clocked path

directly from the SDIN pin, regardless of the CS pin state, except during the GSPI Data

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Word portion for read operations to the device. This allows multiple devices to be

connected in Loop-Through configuration.

For read operations, the SDOUT pin is used to output data read from an internal

Configuration and Status Register (CSR) when CS is LOW. Data is shifted out of the

device on the falling edge of SCLK, so that it can be read by the host processor or other

downstream connected device on the subsequent SCLK rising edge.

4.11.3.1 GSPI Link Disable Operation

It is possible to disable the direct SDIN to SDOUT (Loop-Through) connection by writing

a value of 1 to the GSPI_LINK_DISABLE bit in REGISTER_0. When disabled, any data

appearing at the SDIN pin will not appear at the SDOUT pin and the SDOUT pin is HIGH.

Note: Disabling the Loop-Through operation is temporarily required when initializing

the Unit Address for up to 32 connected devices.

The time required to enable/disable the Loop-Through operation from assertion of the

register bit is less than the GSPI configuration command delay as defined by the

parameter t

(5 SCLK cycles).

cmd_GSPI_config

Table 4-7: GSPI_LINK_DISABLE Bit Operation

Bit State

Description

0

1

SDIN pin is looped through to the SDOUT pin

Data appearing at SDIN does not appear at SDOUT, and SDOUT pin is HIGH.

SDIN pin

Configuration and

Status Register

SDOUT pin

High-Z

GSPI_LINK

_DISABLE

GSPI_BUS_

THROUGH_ENABLE

CS pin

Figure 4-6: GSPI_LINK_DISABLE Operation

4.11.3.2 GSPI Bus-Through Operation

Using GSPI Bus-Through operation, the GS6151 can share a common PCB trace with

other GSPI devices for SDOUT output.

When configured for Bus-Through operation, by setting GSPI_BUS_THROUGH_ENABLE

bit to 1, the SDOUT pin will be high-impedance when the CS pin is HIGH.

When the CS pin is LOW, the SDOUT pin will be driven and will follow regular read and

write operation as described in Section 4.11.3.

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Multiple chains of GS6151 devices can share a single SDOUT bus connection to host by

configuring the devices for Bus-Through operation. In such configuration, each chain

requires a separate Chip Select (CS).

SDIN pin

Configuration and

Status Register

SDOUT pin

GSPI_LINK

_DISABLE

High-Z

GSPI_BUS_

THROUGH_ENABLE

CS pin

Figure 4-7: GSPI_BUS_THROUGH_ENABLE Operation

4.11.4 SCLK Pin

The SCLK pin is the GSPI serial data shift clock input to the device, and must be provided

by the host processor.

Serial data is clocked into the GS6151 SDIN pin on the rising edge of SCLK. Serial data is

clocked out of the device from the SDOUT pin on the falling edge of SCLK (read

operation). SCLK is ignored when CS is HIGH.

The maximum interface clock rate is 27MHz.

4.11.5 Command Word Description

All GSPI accesses are a minimum of 32 bits in length (a 16-bit Command Word followed

by a 16-bit Data Word) and the start of each access is indicated by the high-to-low

transition of the chip select (CS) pin of the GS6151.

The format of the Command Word and Data Words are shown in Figure 4-8.

Data received immediately following this high-to-low transition will be interpreted as a

new Command Word.

4.11.5.1 R/W bit - B15 Command Word

This bit indicates a read or write operation.

When R/W is set to 1, a read operation is indicated, and data is read from the register

specified by the ADDRESS field of the Command Word.

When R/W is set to 0, a write operation is indicated, and data is written to the register

specified by the ADDRESS field of the Command Word.

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4.11.5.2 B'CAST ALL - B14 Command Word

This bit is used in write operations to configure all devices connected in Loop-Through

and Bus-Through configuration with a single command.

When B’CAST ALL is set to 1, the following Data Word (AUTOINC = 0) or Data Words

(AUTOINC = 1) are written to the register specified by the ADDRESS field of the

Command Word (and subsequent addresses when AUTOINC = 1), regardless of the

setting of the UNIT ADDRESS(es).

When B’CAST ALL is set to 0, a normal write operation is indicated. Only those devices

that have a Unit Address matching the UNIT ADDRESS field of the Command Word write

the Data Word to the register specified by the ADDRESS field of the Command Word.

4.11.5.3 EMEM - B13 Command Word

When the EMEM bit is 1 the Address Word is extended to 23 bits to allow access to

registers located in the extended memory space.

When the EMEM bit is 0, the address word is limited to 7 bits.

4.11.5.4 AUTOINC - B12 Command Word

When AUTOINC is set to 1, Auto-Increment read or write access is enabled.

In Auto-Increment Mode, the device automatically increments the register address for

each contiguous read or write access, starting from the address defined in the ADDRESS

field of the Command Word.

The internal address is incremented for each 16-bit read or write access until a

low-to-high transition on the CS pin is detected.

When AUTOINC is set to 0, single read or write access is required.

Auto-Increment write must not be used to update values in HOST_CONFIG.

4.11.5.5 UNIT ADDRESS - B11:B7 Command Word

The 5 bits of the UNIT ADDRESS field of the Command Word are used to select one of 32

devices connected on a single chip select in Loop-Through or Bus-Through

configurations.

Read and write accesses are only accepted if the UNIT ADDRESS field matches the

programmed DEVICE_UNIT_ADDRESS in HOST_CONFIG.

By default at power-up or after a device reset, the DEVICE_UNIT_ADDRESS is set to 00h

4.11.5.6 ADDRESS - B6:B0 Command Word

If the extended memory is not being accessed (EMEM = 0), the 7 bits of the ADDRESS

field are used to select one of 128 register addresses in the device in single read or write

access mode, or to set the starting address for read or write accesses in Auto-Increment

Mode.

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Command Word

MSB

R / W

LSB

UNIT ADDRESS

ADDRESS

A3

B’CAST

ALL

EMEM

AUTOINC

A11

A10

A9 A8

A7

A6

A5

A4

A2

A1

A0

7-bit CSR address field providing up to

128 configuration registers.

5-bit UNIT ADDRESS field providing up to

32 devices to be connected on a single CS.

Auto increment read/write access when set.

Single read write access when reset.

Extended memory mode. When set, the extended memory mode is

enabled. When reset, normal GSPI addressing is enabled.

When set, the UNIT ADDRESS field is ignored and

all data accesses are actioned by the device.

When reset, the Unit Address is used to

manage data accesses in the device.

Read access when this bit is set.

Write access when this bit is reset.

Data Word

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

Figure 4-8: Command and Data Word Format

When EMEM is set to 1, the Address Word is extended to 23 bits. The Command and Data

Word format will be extended by another 16 bits, and is shown in Figure 4-9 below.

Command Word

MSB

LSB

UNIT ADDRESS

A9

ADDRESS[22:16]

A19

B’CAST

ALL

EMEM

A13

AUTOINC

A12

A11

A10

A8

A7

A22

A6

A21

A5

A20

A4

A18

A2

A17

A1

A16

R / W

A15

ADDRESS[15:0]

A14

A9

A8

A7

A3

D3

A0

Data Word

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D2

D1

D0

Figure 4-9: Command and Data Word Format with EMEM set to 1

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4.11.6 GSPI Transaction Timing

t_{cmd_GSPI_config}

t_cmd

t₉

SCLK

CS

X

SDIN

SDOUT

t₂

t₇

t₀

t₁

t₄

SCLK

CS

t₃

t₈

R/W

BCST

EMEM

Auto_Inc

UA4

UA3

UA2

UA1

UA0

A6

A5

A4

A3

A2

A1

A0

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

SDIN

SDOUT

R/W

BCST

EMEM

Auto_Inc

UA4

UA3

UA2

UA1

UA0

A6

A5

A4

A3

A2

A1

A0

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

SDI signal is looped out on SDO

Write Mode

t₅

t₉

SCLK

CS

t₆

R/W

RSV

EMEM

Auto_Inc

UA4

UA3

UA2

UA1

UA0

A6

A5

A4

A3

A2

A1

A0

SDIN

SDOUT

R/W

RSV

EMEM

Auto_Inc

UA4

UA3

UA2

UA1

UA0

A6

A5

A4

A3

A2

A1

A0

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

SDI signal is looped out on SDO

Read Data is output on SDO

Read Mode

Figure 4-10: GSPI External Interface Timing

Table 4-8: GSPI Timing Parameters

Equivalent

SCLK

Parameter

Symbol

Min

Typ

Max

Units

Cycles

(at 27MHz)

SCLK frequency

CS low before SCLK rising edge

SCLK period

—

2.0

37

—

50

—

27

—

60

—

MHz

ns

t₀

t₁

t₂

t₃

t₄

t₅

ns

SCLK duty cycle

40

%

Input data setup time

SCLK idle time -write

SCLK idle time - read

2.7

37

ns

1

5

ns

161.0

ns

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Table 4-8: GSPI Timing Parameters (Continued)

Equivalent

SCLK

Parameter

Symbol

Min

Typ

Max

Units

Cycles

(at 27MHz)

t_cmd

Inter-command delay time

4

5

120.0

162.0

—

ns

t_{cmd_GSPI_}

_conf1

Inter-command delay time

(after GSPI configuration write)

t₆

t₇

SDO after SCLK falling edge

—

7.5

—

ns

CS high after final SCLK falling

edge

0.0

t₈

t₉

Input data hold time

CS high time

1.0

—

ns

57.0

SDIN to SDOUT combinational

delay

—

5.0

1

ns

Max. chips daisy chained at

max SCLK frequency

GS6151

chips

When host clocks in SDOUT

data on rising edge of SCLK

Max. frequency for 32

daisy-chained devices

2.1

3

MHz

Max. chips daisy-chained at

max. SCLK frequency

GS6151

chips

When host clocks in SDOUT

data on falling edge of SCLK

Max. frequency for 32

daisy-chained devices

2.2

MHz

Note:

1. t_{cmd_GSPI_conf}inter-command delay must be used whenever modifying HOST_CONFIG register at address 0x00

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4.11.7 Single Read/Write Access

Single read/write access timing for the GSPI interface is shown in Figure 4-11 to

Figure 4-15.

When performing a single read or write access, one Data Word is read from/written to

the device per access. Each access is a minimum of 32-bits long, consisting of a

Command Word and a single Data Word. The read or write cycle begins with a

high-to-low transition of the CS pin. The read or write access is terminated by a

low-to-high transition of the CS pin.

The maximum interface clock rate is 27MHz and the inter-command delay time

indicated in the figures as t , is a minimum of 4 SCLK clock cycles. After modifying

cmd

values in HOST_CONFIG, the inter-command delay time, t

of 5 SCLK clock cycles.

, is a minimum

cmd_GSPI_config

For read access, the time from the last bit of the Command Word to the start of the data

output, as defined by t , corresponds to no less than 5 SCLK clock cycles at 27MHz.

5

t

cmd

SCLK

CS

COMMAND

DATA

X

COMMAND

SDIN

SDOUT

Figure 4-11: GSPI Write Timing – Single Write Access with Loop-Through Operation (default)

t

cmd

SCLK

CS

SDIN

COMMAND

DATA

X

COMMAND

SDOUT

Figure 4-12: GSPI Write Timing – Single Write Access with GSPI Link-Disable Operation

t

cmd

SCLK

CS

COMMAND

DATA

X

High-z

COMMAND

SDIN

High-Z

SDOUT

Figure 4-13: GSPI Write Timing – Single Write Access with Bus-Through Operation

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SCLK

CS

t

5

COMMAND

SDIN

DATA

SDOUT

Figure 4-14: GSPI Read Timing – Single Read Access with Loop-Through Operation (default)

t

5

SCLK

CS

COMMAND

SDIN

High-z

X

DATA

SDOUT

Figure 4-15: GSPI Read Timing – Single Read Access with Bus-Through Operation

4.11.8 Auto-increment Read/Write Access

Auto-increment read/write access timing for the GSPI interface is shown in Figure 4-16

to Figure 4-20.

Auto-increment mode is enabled by the setting of the AUTOINC bit of the Command

Word.

In this mode, multiple Data Words can be read from/written to the device using only one

starting address. Each access is initiated by a high-to-low transition of the CS pin, and

consists of a Command Word and one or more Data Words. The internal address is

automatically incremented after the first read or write Data Word, and continues to

increment until the read or write access is terminated by a low-to-high transition of the

CS pin.

Note: Writing to HOST_CONFIG using Auto-increment access is not allowed.

The maximum interface clock rate is 27MHz and the inter-command delay time

indicated in the diagram as t , is a minimum of 4 SCLK clock cycles.

cmd

For read access, the time from the last bit of the first Command Word to the start of the

data output of the first Data Word as defined by t , will be no less than 5 SCLK cycles at

5

27MHz. All subsequent read data accesses will not be subject to this delay during an

Auto-Increment read.

SCLK

CS

SDIN

COMMAND

DATA 1

DATA 2

SDOUT

Figure 4-16: GSPI Write Timing – Auto-Increment with Loop-Through Operation (default)

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SCLK

CS

COMMAND

DATA 1

DATA 2

SDIN

SDOUT

Figure 4-17: GSPI Write Timing – Auto-Increment with GSPI Link Disable Operation

SCLK

CS

SDIN

COMMAND

DATA 1

DATA 2

High-Z

SDOUT

Figure 4-18: GSPI Write Timing – Auto-Increment with Bus-Through Operation

SCLK

t

5

CS

SDIN

COMMAND

SDOUT

DATA 1

DATA 2

Figure 4-19: GSPI Read Timing – Auto-Increment Read with Loop-Through Operation (default)

SCLK

t

5

CS

SDIN

COMMAND

High-z

SDOUT

X

DATA 1

DATA 2

Figure 4-20: GSPI Read Timing – Auto-Increment Read with Bus-through Operation

4.11.9 Setting a Device Unit Address

Multiple (up to 32) GS6151 devices can be connected to a common Chip Select (CS) in

Loop-Through or Bus-Through operation.

To ensure that each device selected by a common CS can be separately addressed, a

unique Unit Address must be programmed by the host processor at start-up as part of

system initialization or following a device reset.

Note:By default at power up or after a device reset, the DEVICE_UNIT_ADDRESS of each

device is set to 0h and the SDIN->SDOUT non-clocked loop-through for each device is

enabled.

These are the steps required to set the DEVICE_UNIT_ADDRESS of devices in a chain to

values other than 0:

1. Write to Unit Address 0 selecting HOST_CONFIG (ADDRESS = 0), with the

GSPI_LINK_DISABLE bit set to 1 and the DEVICE_UNIT_ADDRESS field set to 0. This

disables the direct SDIN->SDOUT non-clocked path for all devices on chip select.

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2. Write to Unit Address 0 selecting HOST_CONFIG (ADDRESS = 0), with the

GSPI_LINK_DISABLE bit set to 0 and the DEVICE_UNIT_ADDRESS field set to a

unique Unit Address. This configures DEVICE_UNIT_ADDRESS for the first device in

the chain. Each subsequent such write to Unit Address 0 will configure the next

device in the chain. If there are 32 devices in a chain, the last (32nd) device in the

chain must use DEVICE_UNIT_ADDRESS value 0.

3. Repeat step 2 using new, unique values for the DEVICE_UNIT_ADDRESS field in

HOST_CONFIG until all devices in the chain have been configured with their own

unique Unit Address value.

Note: t

delay must be observed after every write that modifies

cmd_GSPI_conf

HOST_CONFIG.

All connected devices receive this command (by default the Unit Address of all devices

is 0), and the Loop-Through operation will be re-established for all connected devices.

Once configured, each device will only respond to Command Words with a

UNIT ADDRESS field matching the DEVICE_UNIT_ADDRESS in HOST_CONFIG

Note: Although the Loop-Through and Bus-Through configurations are compatible

with previous generation GSPI enabled devices (backward compatibility), only devices

supporting Unit Addressing can share a chip select. All devices on any single chip select

must be connected in a contiguous chain with only the last device's SDOUT connected

to the application host processor. Multiple chains configured in Bus-Through mode can

have their final SDOUT outputs connected to a single application host processor input.

4.11.10 Default GSPI Operation

By default at power up or after a device reset, the GS6151 is set for Loop-Through

Operation and the internal DEVICE_UNIT_ADDRESS field of the device is set to 0.

Figure 4-21 shows a functional block diagram of the Configuration and Status Register

(CSR) map in the GS6151 for non-extended memory accesses (EMEM = 0).

At power-up or after a device reset, DEVICE_UNIT_ADDRESS = 00h

[15]

[14]

[13]

[12]

[11:7]

[6:0]

bits

BCAST

ALL

Auto

Inc

Unit Address

32 devices

Local Address

128 registers

EMEM

R / W

CMD

[15:0]

Data to be written / Read Data

bits

Compare

DATA

[4:0]

[15]

[14]

[12:5]

bits

[13]

Read/Write

GSPI_BUS_

THROUGH

_ENABLE

GSPI_LINK

_DISABLE

Reg 0

RESERVED

DEVICE_UNIT_ADDRESS

RESERVED

Reg 1

Configuration and Status Registers

Reg 128

Figure 4-21: Internal Register Map Functional Block Diagram

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The steps required for the application host processor to write to the Configuration and

Status Registers via the GSPI, are as follows:

1. Set Command Word for write access (R/W = 0) to the local registers 0h-80h; set Auto

Increment; set the Unit Address field in the Command Word to match the

configured DEVICE_UNIT_ADDRESS which will be zero. Write the Command Word.

2. Write the Data Word to be written to the first register.

3. Write the Data Word to be written to the next register in Auto Increment mode, etc.

Read access is the same as the above with the exception of step 1, where the Command

Word is set for read access (R/W = 1).

Note: The UNIT ADDRESS field of the Command Word must always match

DEVICE_UNIT_ADDRESS for an access to be accepted by the device. Changing

DEVICE_UNIT_ADDRESS to a value other than 0 is only required if multiple devices are

connected to a single chip select (in Loop-Through or Bus-Through configuration.)

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4.12 Diagnostic Features

To aid in debug, the GS6151 has an on-chip eye monitoring, error counting and

PRBS-signal generation features that can be used to check system links for error-free

7

6

operation. The PRBS signal generator outputs a PRBS7 bit stream (x +x +1 polynomial)

or clock (at the reference or divided rates) which can be clocked from either an on-chip

or off-chip source. The eye monitor is a 128-bit horizontal eye monitor (HEM) that can

automatically detect the error-free eye width, the first error-free phase position and

provide a bitmap of the error status of each phase without affecting the retiming

capability of the CDR. Additionally, the HEM can be configured to manually count the

number of errors at a given phase for a given time interval or to continually count errors

until programmed to stop. In any of these three modes, described in the next section,

Section 4.12.1, the criteria for measuring a bit error can also be set to measure bit errors

of arbitrary data (in which the input to the CDR is assumed to be BER-free at some phase)

or by checking against a PRBS7 bit stream for measuring error-free performance of

upstream devices. PRBS checking is described in Section 4.12.2. The PRBS generator is

described in Section 4.12.3. The HEM and PRBSCHK features operate at 3Gb/s and HD

data rates, while the PRBS generator operates at 3G, HD, SD and MADI rates.

4.12.1 Horizontal Eye Monitor Modes

The three modes of bit error characterization of the HEM are described below. In this

section it is assumed that arbitrary data is being input and checked. For each of these

modes (and the PRBS7 input data checking mode in section 4.12.3) the Horizontal Eye

Monitor must be enabled by setting the HORIZONTAL_EYE_MON_ENABLE bit of the

EYE_MON_ENABLE register at address 23 .

h

4.12.1.1 Automatic Eye Scan

The automatic eye-scan mode measures the error-free eye width and first error-free

phase (EYE_WIDTH and STARTING_PHASE bits, respectively, of

EYE_MON_STATUS_REG_2) position as well as the resultant error bitmap of each of the

128 phases (EYE_BITMAP bits of EYE_MON_STATUS_REG_4 to

EYE_MON_STATUS_REG_11, least-significant bits correspond to leftmost bits). A bit

value of 1 in the bitmap indicates error-free operation at the phase that corresponds to

the bit. A bit value of 0 indicates more than the ERROR_THRESHOLD number of errors

have been counted and the bit is considered as an error bit. It should be noted that the

eye is not necessarily centered in the results, i.e. the crossing may be in the center of the

bitmap and the open eye can wrap around from phase 127 back to 0. The automatic eye

scan takes this into account and calculates the value for the error-free eye across the

wrapping while the error-free phase corresponds to the leftmost portion of the

error-free eye rather than the leftmost error-free phase in the bitmap. Refer to

Figure 4-22 below.

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Figure 4-22: Example Eye Monitor Bitmap

With the eye monitor enabled by setting the HORIZONTAL_EYE_MON_ENABLE bit an

eye scan is started by writing a 1 to the AUTO_SCAN_START bit of the

EYE_MON_SCAN_START register. The eye-scan state machine then scans the eye and

writes a 0 to the AUTO_SCAN_START bit when it completes. The values in the above

registers are then valid if lock was not lost at any point during the eye scan. It is therefore

recommended that the LOCK_LOST_STICKY bit of the STICKY_STATUS register is

cleared before running the eye scan and checking its value after the eye scan is

complete.

After a successful automatic eye scan, the EYE_WIDTH bits hold a value corresponding

to the number of phases that had errors that did not exceed a predefined threshold. This

error threshold is defined as the number of errors that must be observed before the

phase is deemed to be not error-free and is set in the ERROR_THRESHOLD bits of the

EYE_MON_CONTROL_REG_4 register. By default the error threshold is set to 3.

A typical relationship between the EYE_WIDTH result and the input jitter amplitude is

given in Figure 4-22.

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HEM Eye Width Measurement vs. Input Jitter

120

110

100

90

80

70

60

50

40

30

20

10

0

3G, HD Data

0.00

0.20

0.40

0.60

0.80

Jitter Amplitude (UI)

Figure 4-23: HEM Eye Width vs. Input Jitter

The eye scan state machine counts errors at each of the 128 phases to determine the

above eye parameters, returning a 1 in the appropriate bit of the bitmap for an error-free

measurement, and a 0 when an error has been detected. The length of each

measurement, SAMPLE_TIME, is determined by Equation 4-4 .

SAMPLE_TIME = MEASUREMENT_PREDIVIDER × (MEASUREMENT_TIME + 1) × 1 ⁄ (108MHz)

Equation 4-4

In Equation 4-4 , MEASUREMENT_PREDIVIDER and MEASUREMENT_TIME are bits of the

EYE_MON_CONTROL_REG_1 and EYE_MON_CONTROL_REG_2 registers, respectively.

By default MEASUREMENT_PREDIVIDER is set to 4x (bit value 0) and

MEASUREMENT_TIME is set to A8B yielding a default measurement time per phase of

h

100μs. The length of time to complete a full eye scan is then approximately 128 bits x

SAMPLE_TIME x 2 passes. Two passes are executed by the state machine when checking

arbitrary data to map the left and right portions of the eye separately.

The equivalent bit-error-rate is then defined as at least ERROR_THRESHOLD / (data rate

* SAMPLE_TIME) for phases with errors.

4.12.1.2 Single Timed Measurement

A manual timed measurement can be used to count the number of errors at a single

phase for a pre-defined length of time. The length of the measurement is defined by the

number of bit errors recorded is stored in the ERROR_COUNT bits of the

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EYE_MON_STATUS_REG_3 register. The phase to be measured is set by setting the

MANUAL_PHASE bit of EYE_MON_CONTROL_REG_5, and for arbitrary data the

EYE_MON_WINDOW setting of the EYE_MON_CONTROL_REG_6.

For arbitrary data patterns the EYE_MON_WINDOW setting sets which portion of the

eye is being measured. The result for any phase is the lesser result stored in

ERROR_COUNT of the measurements at each EYE_MON_WINDOW setting, 0 and 1.

For PRBS7 data only the MANUAL_PHASE bit needs to be set and the

EYE_MON_WINDOW bit can be arbitrarily set. The left and right portions of the eye are

overlapped (wrap around the bit map).

Resetting the error indicator to 0 is done by programming the EYE_MON_FORCE_CLEAR

and EYE_MON_CLEAR bits of the EYE_MON_CONTROL_REG_6 register to 1. Both bits

should be set to 0 before starting a new measurement.

4.12.1.3 Continuous Measurement

A manual continuous measurement can be used to continually count the number of

errors at a single phase until explicitly stopped by disabling the manual continuous

mode. A continuous measurement is started by first setting the MANUAL_PHASE bit of

EYE_MON_CONTROL_REG_5, and for arbitrary data the EYE_MON_WINDOW setting of

the EYE_MON_CONTROL_REG_6, then enabling the measurement by setting the

CONTINUOUS_SCAN_ENABLE bit of the EYE_MON_CONTROL_REG_0 register to 1

(enable measurement).

When it is desired to stop the measurement the CONTINUOUS_SCAN_ENABLE bit of the

EYE_MON_CONTROL_REG_0 register should be set to 0 (disable measurement). The

result, the number of errors counted, is stored in ERROR_COUNT bits of the

EYE_MON_STATUS_REG_3 register.

Resetting the error indicator to 0 is done by programming the EYE_MON_FORCE_CLEAR

and EYE_MON_CLEAR bits of the EYE_MON_CONTROL_REG_6 register to 1. Both bits

should be set to 0 before starting a new measurement.

4.12.2 PRBS Checker

PRBS7 data streams can be checked for bit-errors at both the input of the CDR (non

re-timed Trace EQ output) and output of the CDR (re-timed output). Although the

general sequence for checking the input and output of the CDR are similar, different

registers are used to program and check the results of each.

4.12.2.1 Input PRBS Checker

The Input PRBS checker checks the eye and/or counts bit errors at the Trace EQ

output/input to the CDR. This feature can be used to optimize the Trace EQ setting,

other upstream jitter optimizations or to simply check for error-free transmission to the

CDR. The operation of the Input PRBS checker is similar to the Horizontal Eye Monitor for

Arbitrary Data, in the previous section, providing the same functionality of automatic

eye monitoring, manual timed error checking at a single phase and continuous error

checking at a single phase. Because the same sequence and most of the same registers

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are used to operate the Input PRBS checker (and in fact Input PRBS checking is

automatically performed by the device when an Arbitrary Data eye scan or error check

is performed) the user is referred to the previous section for details on programming the

HEM. PRBS-specific registers which are additionally set or observed and their Arbitrary

Data equivalents are given in Table 4-9 below.

Table 4-9: Arbitrary Data Checker Registers and Equivalent Input PRBS7 Checker Registers

Arbitrary Data Checker

Register Parameter

Input PRBS7 Checker

Register

Parameter

Does Not Apply

EYE_MON_ENABLE

EYE_MON_PRBS_NODATA_SET

EYE_MON_PRBS_ERROR_

THRESHOLD

EYE_MON_CONTROL_REG_4

ERROR_THRESHOLD

EYE_MON_CONTROL_REG_3

EYE_MON_CONTROL_REG_6

EYE_MON_WINDOW

EYE_MON_FORCE_CLEAR

EYE_MON_CLEAR

Does Not Apply

EYE_MON_CONTROL_REG_6

EYE_MON_PRBS_FORCE_CLEAR

EYE_MON_PRBS_CLEAR

EYE_MON_PRBS_STARTING_

PHASE

EYE_MON_STATUS_REG_2

STARTING_PHASE

EYE_MON_STATUS_REG_0

EYE_MON_STATUS_REG_2

EYE_WIDTH

EYE_MON_STATUS_REG_0

EYE_MON_STATUS_REG_1

EYE_MON_STATUS_REG_12

EYE_MON_PRBS_EYE_WIDTH

EYE_MON_PRBS_ERROR_COUNT

EYE_MON_PRBS_NODATA

ERROR_COUNT

Does Not Apply

The eye bitmap registers in EYE_MON_STATUS_REG_4… EYE_MON_STATUS_REG_11

can be set to provide the bitmap when the PRBS checker is used as the criteria for bit

errors when the EYE_MON_SELECT bit is set to 0 (PRBS7 bit stream).

Due to the nature of the PRBS polynomial an input without data transitions may be

detected as error-free. To circumvent this possibility the EYE_MON_PRBS_NODATA bit

of the EYE_MON_STATUS_REG_12 register indicates if no data transitions have been

detected if the bit remains high after the EYE_MON_PRBS_NODATA_SET bit of the

EYE_MON_ENABLE register has been toggled high, then low.

4.12.2.2 Re-timed Data PRBS Checker

The re-timed bit stream is checked using a separate PRBS checker which is controlled

and checked with separate registers from either the arbitrary eye monitor or Input

PRBS7 checker and is enabled by setting the PRBS_MON_ENABLE bit of the

PRBS_CHK_CTRL register and controlled with registers PRBS_CTRL_0 …, PRBS_CTRL_8.

The results are stored in PRBS_STATUS_REG_0 and PRBS_STATUS_REG_1. The operation

of the Re-timed Data PRBS checker is very similar to the Arbitrary Data HEM and Input

PRBS checker and the user is referred to the previous sections for equivalent registers

are given in Table 4-10 below.

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Table 4-10: Arbitrary Data Checker/Input PRBS7 Checker Registers and Equivalent Re-timed

PRBS7 Checker Registers

Arbitrary Data Checker/Input PRBS7 Checker

Re-timed PRBS7 Checker

Register

Parameter

Register

Parameter

HORIZONTAL_EYE_MON_

ENABLE

EYE_MON_ENABLE

PRBS_CHK_CTRL

PRBS_MON_ENABLE

EYE_MON_PRBS_NODATA

_SET

EYE_MON_ENABLE

PRBS_MON_NODATA_SET

EYE_MON_SCAN_START

MANUAL_SCAN_START

AUTO_SCAN_START

PRBS_CTRL_0

PRBS_MON_MANUAL_START

PRBS_MON_AUTO_SCAN_START

CONTINUOUS_SCAN_

ENABLE

PRBS_MON_CONTINUOUS_

ENABLE

EYE_MON_CONTROL_REG_0

EYE_MON_CONTROL_REG_1

EYE_MON_CONTROL_REG_2

PRBS_CTRL_1

PRBS_CTRL_2

PRBS_CTRL_3

EYE_MON_SOFT_RESET

PRBS_MON_SOFT_RESET

MEASUREMENT_

PREDIVIDER

PRBS_MON_MEASUREMENT

_PREDIVIDER

SAMPLE_INTERVAL

PRBS_MON_SAMPLE_INTERVAL

PRBS_MON_MEASUREMENT_

TIME

MEASUREMENT_TIME

PRBS_MON_PRBS_ERROR_

THRESHOLD

EYE_MON_CONTROL_REG_4

ERROR_THRESHOLD

PRBS_CTRL_4

PRBS_CTRL_5

EYE_MON_CONTROL_REG_5

EYE_MON_CONTROL_REG_6

EYE_MON_STATUS_REG_2

EYE_MON_STATUS_REG_3

EYE_MON_STATUS_REG_12

MANUAL_PHASE

EYE_MON_WINDOW

EYE_MON_CLEAR

PRBS_MON_MANUAL_PHASE

Does Not Apply

PRBS_CTRL_6

PRBS_MON_CLEAR

PRBS_MON_FORCE_CLEAR

PRBS_MON_EYE_WIDTH

PRBS_MON_STARTING_PHASE

PRBS_MON_ERROR_COUNT

PRBS_MON_NODATA

EYE_MON_FORCE_CLEAR

EYE_WIDTH

PRBS_STATUS_REG_0

PRBS_STATUS_REG_1

PRBS_STATUS_REG_11

STARTING_PHASE

ERROR_COUNT

EYE_MON_PRBS_NODATA

Note: For all PRBS7 measurements two errors are counted for each error observed. The

EYE_MON_ERROR_THRESHOLD and/or PRBS_MON_ERROR_THRESHOLD values should

be adjusted appropriately to get the desired BER criteria.

4.12.3 PRBS Generator

A signal generator, capable of generating PRBS7 or clock pattern data, is integrated in

the device. The pattern generator can be clocked by external pins (DFT_CLK_IN,

DFT_CLK_IN, GS6151 only), re-timed clock from input arbitrary data or by an on-chip

open-loop VCO (default). When the on-chip VCO is selected the data rate must be

selected by programming the PRBSGEN_RATESEL bits of the PRBS_GEN_CTRL register.

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It is important to note that while the on-chip VCO is trimmed to within 0.5% of SMPTE

data rates, VT variation may extend the deviation from exact SMPTE data rates. If

frequency precision is required it is recommended to use the external pins or retimed

clock to provide a clock reference for the PRBS generator. The selection of reference

clock for the PRBS generator is done through programming the bits as in Table 4-11.

Table 4-11: Reference Clock for the PRBS Generator

PRBS_EXT_CLK

PRBSGEN_CLKSEL

Clock Reference

0

1

0

1

X

On-chip PRBSGEN VCO

CDR re-timed clock

Clock reference pins (GS6151 only)

To enable the PRBS generator the PRBSGEN_ENABLE bit of the PRBS_GEN_CTRL register

must be set high. The PRBS bit stream starts on the falling edge of the PRBSGEN_START

bit. To output the PRBS generator on the trace driver output the OUTPUT_PRBS_DATA0

and/or OUTPUT_PRBS_DATA1 bits of the DRIVER_CONTROL_REG_0 register need to be

set to 1.

The PRBS generator can also output a clock instead of a PRBS7 bit stream. The clock

output is selected by setting the PRBSGEN_DATASEL bit of the PRBS_GEN_CTRL register

to 0. Both the PRBS7 generator and clock output can have their frequency of operation

divided by 1, 2, 4 or 8 by setting the PRBSGEN_DIV bits of the PRBS_GEN_CTRL register,

down to an output data rate of 125Mb/s.

Additionally, when either the On-Chip PRBSGEN VCO or the re-timed clock is used as the

clock reference for the PRBS generator the phase of the output can be coarsely adjusted

º

to 0, 90, 180 or 270 by programming PRBSGEN_PHASE bit of the PRBS_GEN_CTRL

register.

Note: It is recommended that the AUTO_LOS_MUTE_ENABLE and

AUTO_PWRDN_DISABLE parameters are set to disabled when the PRBS generator uses

the on-chip PRBSGEN VCO or the external clock pins to avoid muting the (PRBS

generator) output upon loss of signal on the input pins.

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5. Host Interface Register Map

Table 5-1: Register Descriptions - Standard Address Space

Bit

Slice

Reset

Value

Address Register Name

Parameter Name

R/W

Description

0_h

RSVD

15:15

14:14

RW

Reserved. Do not change.

GSPI loop-through disable.

GSPI_LINK_DISABLE

GSPI_BUS_THROUGH_

ENABLE

0_h

HOST_CONFIG

DEVICE_INFO

13:13

RW

GSPI bus-through enable.

0_h

—

0_h

RSVD

DEVICE_UNIT_ADDRESS

RSVD

12:5

4:0

RW

RO

RW

Reserved. Do not change.

Device address programmed by application.

Reserved. Do not change.

15:8

7:0

1_h

DEVICE_VERSION_ID

RSVD

—

0_h

Device Version Identifier.

15:14

Reserved. Do not change.

GPIO1 Input/Output Select.

0_h

GPIO1_IO_SELECT

RSVD

13:13

12:11

RW

00_b: Output

01_b: Input

Reserved. Do not change.

GPIO1 Signal Selection

If GPIO1_IO_SELECT is set to 0:

0000_b: LOS

0001_b: LOCKED (default)

0010_b: LBR_HBR

0011_b: Reserved

0100_b: Reserved

0101_b: RATE_DET0

0110_b: RATE_DET1

0111_b: RATE_DET2

1000_b: LOCKED_125M

1001_b: LOCKED_270M

1010_b: LOCKED_1G485

1011_b: LOCKED_2G97

1100_b: LOCKED_5G94

1101_b: RATE_CHANGE

GPIO_CONTROL_

REG_0

2_h

1_h

GPIO1_SELECT

10:7

RW

If GPIO1_IO_SELECT is set to 1:

0000_b: DDO0_DISABLE

0001_b: DDO1_DISABLE

GPIO0 Input/Output Select.

00_b: Output

01_b: Input

0_h

GPIO0_IO_SELECT

RSVD

6:6

5:4

RW

Reserved. Do not change.

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Table 5-1: Register Descriptions - Standard Address Space (Continued)

Bit

Slice

Reset

Value

Address Register Name

Parameter Name

R/W

Description

GPIO0 Signal Selection

If GPIO0_IO_SELECT is set to 0:

0000_b: LOS (default)

0001_b: LOCKED

0010_b: LBR_HBR

0011_b: Reserved

0100_b: Reserved

0101_b: RATE_DET0

0110_b: RATE_DET1

0111_b: RATE_DET2

1000_b: LOCKED_125M

1001_b: LOCKED_270M

1010_b: LOCKED_1G485

1011_b: LOCKED_2G97

1100_b: LOCKED_5G94

1101_b: RATE_CHANGE

GPIO_CONTROL_

2_h

0_h

GPIO0_SELECT

3:0

RW

REG_0

If GPIO0_IO_SELECT is set to 1:

0000_b: DDO0_DISABLE

0001_b: DDO1_DISABLE

Reserved. Do not change.

3_h

4_h

2082_h

1C_h

RESERVED

RSVD

15:14

15:0

15:4

RW

A_h

DDI1 Trace-EQ Configuration

00_b: OFF

2_h

01_b: 0dB/EQ BYPASS

10_b: LOW

DDI1_TRACE_EQ_ CONTROL

3:2

RW

INPUT_CONTROL_

REG_0

5_h

11_b: HIGH

DDI0 Trace-EQ Configuration

00_b: OFF

2_h

0_h

01_b: 0dB/EQ BYPASS

10_b: LOW

11_b: HIGH

DDI0_TRACE_EQ_ CONTROL

RSVD

1:0

RW

6_h

RESERVED

15:0

Reserved. Do not change.

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Table 5-1: Register Descriptions - Standard Address Space (Continued)

Bit

Slice

Reset

Value

Address Register Name

Parameter Name

R/W

Description

0_h

RSVD

15:12

RW

Reserved. Do not change.

Input Selection

00_b: DDI0

0_h

01_b: DDI1

DDI_SELECT

11:10

RW

Used when INPUT_SELECTION_CONTROL is

set to 01_bor 11_b

Determines the source for the input

selection block.

X0_b: Use the DDI_SEL/STROBE pin

01_b: Use the DDI_SELECT bit

0_h

INPUT_SELECTION_CONTROL

9:8

11_b: Use the DDI_SELECT bit; update occurs

on low-to-high transition of

DDI_SEL/STROBE pin.

INPUT_CONTROL_

7_h

REG_2

3_h

1_h

RSVD

7:6

5:5

RW

Reserved. Do not change.

Enable DDI1 on-chip Trace-EQ DC

termination.

DDI1_TRACE_EQ_DC_TERM_

ENABLE

00_b: Disabled

01_b: Enabled

Enable DDI0 on-chip Trace-EQ DC

termination.

DDI0_TRACE_EQ_DC_TERM_

ENABLE

1_h

4:4

RW

00_b: Disabled

01_b: Enabled

0_h

—

RSVD

3:0

RW

ROCW

RO

Reserved. Do not change.

8_h

RESERVED

15:0

9_h

A_h

B_h

C_h

D_h

E_h

RESERVED

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Table 5-1: Register Descriptions - Standard Address Space (Continued)

Bit

Slice

Reset

Value

Address Register Name

Parameter Name

R/W

Description

0_h

RSVD

15:10

9:9

RW

Reserved. Do not change.

Enables LOS threshold adjustment based on

the settings in the

DDI[0:1]_LOS_THRESHOLD_CONTROL bits

in the LOS_CONTROL_REG_1 register.

LOS_THRESHOLD_CONTROL_

ENABLE

0_h

RW

00_b: Default internal thresholds are used

01_b: Thresholds used in the

LOS_CONTROL_REG_1 register

LOS De-Assert Time Delay:

00_b: 2.30μs

2_h

LOS_DEASSERT_TIME

LOS_ASSERT_TIME

8:7

6:5

RW

01_b: 1.50μs

10_b: 1.20μs

11_b: 0.90μs

LOS Assert Time Delay:

00_b: 68μs

01_b: 64μs

2_h

10_b: 62μs

11_b: 61μs

LOS_CONTROL_

F_h

LOS Threshold Hysteresis Adjustment:

REG_0

0000_b: 0 dB

0001_b: 0.32 dB

0010_b: 0.64 dB

0011_b: 0.98 dB

0100_b: 1.34 dB

0101_b: 1.70 dB

0110_b: 2.09 dB

0111_b: 2.49 dB

1000_b: 2.84 dB

1001_b: 3.28 dB

1010_b: 3.74 dB

1011_b: 4.23 dB

1100_b: 4.75 dB

1101_b: 5.30 dB

1110_b: 5.89 dB

1111_b: 6.53 dB

0_h

LOS_HYSTERESIS

4:1

RW

Override the internal power-down control

for the LOS circuit.

0_h

LOS_PWRDN_OVERRIDE

0:0

RW

00_b: LOS active

01_b: LOS powered down

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Table 5-1: Register Descriptions - Standard Address Space (Continued)

Bit

Slice

Reset

Value

Address Register Name

Parameter Name

R/W

Description

LOS signal threshold for input DDI1 at

device pins is:

DDI1_LOS_THRESHOLD_

CONTROL

5A_h

15:8

7:0

RW

1.9mV

x DDI1_LOS_THRESHOLD_CONTROL x

ppd

(53/DEVICE_SPECIFIC_LOS_THRESHOLD)

(All above values are in decimal)

LOS_CONTROL_

10_h

REG_1

LOS signal threshold for input DDI0 at

device pins is:

DDI0_LOS_THRESHOLD_

CONTROL

RW

1.9mV

x DDI0_LOS_THRESHOLD_CONTROL x

ppd

(53/DEVICE_SPECIFIC_LOS_THRESHOLD)

(All above values are in decimal)

11_h

12_h

5A5A_h

—

RESERVED

RSVD

15:0

15:8

RW

RO

Reserved. Do not change.

LOS_STATUS

Trimmed setting to achieve LOS threshold of

100mV_ppd

DEVICE_SPECIFIC_LOS_

THRESHOLD

7:0

RO

—

13_h

14_h

280_h

RESERVED

RSVD

15:0

15:3

RW

RO

RW

Reserved. Do not change.

—

0_h

Enables/Disables the reference buffer

output.

1_h

XTAL_BUF_OUT_ENABLE

2:2

RW

REF_CLK_

CONTROL

00_b: XTAL_BUF_OUT disabled

01_b: XTAL_BUF_OUT enabled

15_h

0_h

—

RSVD

1:1

0:0

RW

RO

Reserved. Do not change.

15:1

Indicates whether an external 27MHz

reference is being used by the device or its

internal oscillator.

16_h

REF_CLK_STATUS

XTAL_CLK_DET

0:0

RO

—

00_b: Internal oscillator being used

01_b: External crystal being used

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Table 5-1: Register Descriptions - Standard Address Space (Continued)

Bit

Slice

Reset

Value

Address Register Name

Parameter Name

R/W

Description

Selects the low power mode, SLEEP or

STANDBY that is entered into when

AUTO_PWRDN_DISABLE is set to 0 and LOS

is asserted.

0_h

AUTO_PWRDN_MODE

3:3

2:2

RW

00_b: SLEEP mode is selected (default)

01_b: STANDBY mode is selected

Forces the device into STANDBY mode when

FORCE_PWRDN_SLEEP is set to 0.

0_h

FORCE_PWRDN_STANDBY

FORCE_PWRDN_SLEEP

RW

00_b: Device not in STANDBY mode

01_b: Device in STANDBY mode

Forces the device into SLEEP mode when

AUTO_PWRDN_DISABLE is set to 1.

PWRDN_

17_h

CONTROL

00_b: Device not in SLEEP mode

01_b: Device in SLEEP mode

0_h

1:1

When FORCE_PWRDN_SLEEP is set to 1, it

takes precedence over the

FORCE_PWRDN_STANDBY bit.

Disables Auto Powerdown mode which

automatically enters SLEEP or STANDBY

mode when LOS is asserted.

00_b: Device automatically enters SLEEP or

STANDBY on a rising edge of the LOS signal

01_b: Device only enters SLEEP or STANDBY

when FORCE_PWRDN_SLEEP or

FORCE_PWRDN_STANDBY are set to 1

1_h

—

AUTO_PWRDN_DISABLE

0:0

RW

RO

18_h

RESERVED

RSVD

15:0

Reserved. Do not change.

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Table 5-1: Register Descriptions - Standard Address Space (Continued)

Bit

Slice

Reset

Value

Address Register Name

Parameter Name

R/W

Description

0_h

RSVD

15:8

9:9

RW

Reserved. Do not change.

Selects either CDR or PRBSgen data to output

on DDO1.

OUTPUT_PRBS_DATA1

OUTPUT_PRBS_DATA0

RW

0

00 : CDR data

b

01 : PRBSgen data

b

Selects either CDR or PRBSgen data to output

on DDO0.

8:8

0

00 : CDR data

b

01 : PRBSgen data

b

1_h

RSVD

7:7

6:6

RW

Reserved. Do not change.

Auto-Mute Enable on LOS.

00 : Output is unaffected by LOS

AUTO_LOS_MUTE_ENABLE

b

01 : Output is muted when LOS is asserted

b

Mute control for the DDO1 output.

00 : DDO1 output not muted

b

01 : DDO1 output muted

b

0_h

DDO1_MUTE

DDO0_MUTE

5:5

4:4

RW

Output across DDO1 and DDO1 is

DDO1_SWING_MUTE/2 when DDO1_DISABLE

is set to 0.

Mute control for the DDO0 output.

00 : DDO0 output not muted

b

DRIVER_CONTROL_

01 : DDO0 output muted

b

19_h

0_h

REG_0

Output across DDO0 and DDO0 is

DDO0_SWING_MUTE/2 when DDO1_DISABLE

is set to 0.

Disable control for the DDO1 output.

00 : DDO1 output not disabled

b

01 : DDO1 output disabled

0_h

DDO1_DISABLE

DDO0_DISABLE

3:3

2:2

RW

b

Output of both DDO1 and DDO1 is VCC_DDO1.

This bit takes precedence over DDO1_MUTE.

Disable control for the DDO0 output.

00 : DDO0 output not disabled

b

01 : DDO0 output disabled

0_h

b

Output of both DDO0 and DDO0 is VCC_DDO0.

This bit takes precedence over DDO0_MUTE.

Controls whether DDO1 is disabled using an

assigned GPIO pin or the DDO1_DISABLE bit.

0_h

00 : DDO1 is disabled using assigned GPIO

DDO1_DISABLE_SELECT

DDO0_DISABLE_SELECT

1:1

0:0

RW

b

01 : DDO1 is disabled using the

b

DDO1_DISABLE bit

Controls whether DDO0 is disabled using an

assigned GPIO pin or the DDO0_DISABLE bit.

1_h

00 : DDO0 is disabled using assigned GPIO

b

01 : DDO0 is disabled using the

b

DDO0_DISABLE bit

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Table 5-1: Register Descriptions - Standard Address Space (Continued)

Bit

Slice

Reset

Value

Address Register Name

Parameter Name

R/W

Description

0_h

RSVD

15:15

RW

Reserved. Do not change.

De-emphasis control for 5.94Gb/s (6Gb/s

UHD-SDI) signals output on DDO0.

000 : 0dB

b

001 : 0.3dB

b

010 : 0.6dB (default)

2_h

DDO0_DEEMPHASIS_5G94

DDO0_DEEMPHASIS_2G97

DDO0_DEEMPHASIS_1G485

DDO0_DEEMPHASIS_270M

DDO0_DEEMPHASIS_125M

14:12

RW

b

011 : 2.3 B

b

100 : 4.0dB

b

101 : 6.6dB

b

110 : 10.0dB

b

De-emphasis control for 2.97Gb/s (3Gb/s SDI)

signals output on DDO0.

000 : 0dB

b

001 : 0.4dB (default)

b

010 : 1.5dB

1_h

0_h

11:9

b

011 : 3.2dB

b

100 : 4.9dB

b

101 : 7.6dB

b

110 : 11.0dB

b

De-emphasis control for 1.485Gb/s (HD-SDI)

signals output on DDO0.

000 : 0dB

b

DRIVER_CONTROL_

001 : 1.1dB (default)

b

1A_h

REG_1

010 : 2.4dB

8:6

b

011 : 4.0dB

b

100 : 5.7dB

b

101 : 8.2dB

b

110 : 11.5dB

b

De-emphasis control for 0.27Gb/s (SD-SDI)

signals output on DDO0.

000 : 0dB (default)

b

001 : 1.2dB

b

010 : 2.5dB

5:3

b

011 : 4.1dB

b

100 : 6.0dB

b

101 : 8.5dB

b

110 : 12.0dB

b

De-emphasis control for 0.125Gb/s (MADI)

signals output on DDO0.

000 : 0dB (default)

b

001 : 1.2dB

b

010 : 2.5dB

2:0

b

011 : 4.1dB

b

100 : 6.0dB

b

101 : 8.5dB

b

110 : 12.0dB

b

GS6151

Final Data Sheet

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Table 5-1: Register Descriptions - Standard Address Space (Continued)

Bit

Slice

Reset

Value

Address Register Name

Parameter Name

R/W

Description

0_h

RSVD

15:15

RW

Reserved. Do not change.

De-emphasis control for 5.94Gb/s (6Gb/s

UHD-SDI) signals output on DDO1.

000 : 0dB

b

001 : 0.3dB

b

010 : 0.6dB (default)

2_h

DDO1_DEEMPHASIS_5G94

DDO1_DEEMPHASIS_2G97

DDO1_DEEMPHASIS_1G485

DDO1_DEEMPHASIS_270M

DDO1_DEEMPHASIS_125M

14:12

RW

b

011 : 2.3 B

b

100 : 4.0dB

b

101 : 6.6dB

b

110 : 10.0dB

b

De-emphasis control for 2.97Gb/s (3Gb/s SDI)

signals output on DDO1.

000 : 0dB

b

001 : 0.4dB (default)

b

010 : 1.5dB

1_h

0_h

11:9

b

011 : 3.2dB

b

100 : 4.9dB

b

101 : 7.6dB

b

110 : 11.0dB

b

De-emphasis control for 1.485Gb/s (HD-SDI)

signals output on DDO1.

000 : 0dB

b

DRIVER_CONTROL_

001 : 1.1dB (default)

b

1B_h

REG_2

010 : 2.4dB

8:6

b

011 : 4.0dB

b

100 : 5.7dB

b

101 : 8.2dB

b

110 : 11.5dB

b

De-emphasis control for 0.27Gb/s (SD-SDI)

signals output on DDO1.

000 : 0dB (default)

b

001 : 1.2dB

b

010 : 2.5dB

5:3

b

011 : 4.1dB

b

100 : 6.0dB

b

101 : 8.5dB

b

110 : 12.0dB

b

De-emphasis control for 0.125Gb/s (MADI)

signals output on DDO1.

000 : 0dB (default)

b

001 : 1.2dB

b

010 : 2.5dB

2:0

b

011 : 4.1dB

b

100 : 6.0dB

b

101 : 8.5dB

b

110 : 12.0dB

b

GS6151

Final Data Sheet

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Table 5-1: Register Descriptions - Standard Address Space (Continued)

Bit

Slice

Reset

Value

Address Register Name

Parameter Name

R/W

Description

0_h

RSVD

15:12

RW

Reserved. Do not change.

Differential swing (amplitude) control for

1.485Gb/s (HD-SDI) signals output on DDO0.

For details refer to Section 4.5.3.

3_h

DDO0_SWING_1G485

DDO0_SWING_270M

DDO0_SWING_125M

11:8

RW

DRIVER_CONTROL_

1C_h

Differential swing (amplitude) control for

0.27Gb/s (SD-SDI) signals output on DDO0.

For details refer to Section 4.5.3.

REG_3

3_h

7:4

3:0

Differential swing (amplitude) control for

0.125Gb/s (MADI) signals output on DDO0.

For details refer to Section 4.5.3.

Differential swing (amplitude) control for

unlocked signals output on DDO0 (when

CDR is operating in BYPASS mode). For

details refer to Section 4.5.3.

3_h

DDO0_SWING_BYPASS

15:12

RW

Takes precedence over rate-specific swing

controls

DRIVER_CONTROL_

1D_h

REG_4

Differential static amplitude control for

DDO0 when the output is muted. For details

refer to Section 4.5.3.

3_h

DDO0_SWING_MUTE

DDO0_SWING_5G94

11:8

7:4

RW

Takes precedence over rate-specific swing

controls and bypass swing control

Differential swing (amplitude) control for

5.94Gb/s (6G UHD-SDI) signals output on

DDO0. For details refer to Section 4.5.3.

3_h

DRIVER_CONTROL_

1D_h

REG_4

Differential swing (amplitude) control for

2.97Gb/s (3Gb/s SDI) signals output on

DDO0. For details refer to Section 4.5.3.

3_h

0_h

3_h

DDO0_SWING_2G97

RSVD

3:0

15:12

11:8

RW

Reserved. Do not change.

Differential swing (amplitude) control for

1.485Gb/s (HD-SDI) signals output on DDO1.

For details refer to Section 4.5.3.

DDO1_SWING_1G485

DRIVER_CONTROL_

1E_h

Differential swing (amplitude) control for

0.27Gb/s (SD-SDI) signals output on DDO1.

For details refer to Section 4.5.3.

REG_5

3_h

DDO1_SWING_270M

DDO1_SWING_125M

7:4

3:0

RW

Differential swing (amplitude) control for

0.125Gb/s (MADI) signals output on DDO1.

For details refer to Section 4.5.3.

GS6151

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Table 5-1: Register Descriptions - Standard Address Space (Continued)

Bit

Slice

Reset

Value

Address Register Name

Parameter Name

R/W

Description

Differential swing (amplitude) control for

unlocked signals output on DDO1 (when

CDR is operating in BYPASS mode). For

details refer to Section 4.5.3.

3_h

DDO1_SWING_BYPASS

15:12

RW

Also applies when the device is not locked.

Takes precedence over rate-specific swing

controls

Differential static amplitude control for

DDO1 when the output is muted. For details

refer to Section 4.5.3.

DRIVER_CONTROL_

1F_h

3_h

DDO1_SWING_MUTE

DDO1_SWING_5G94

11:8

7:4

RW

REG_6

Takes precedence over rate-specific swing

controls and bypass swing control

Differential swing (amplitude) control for

5.94Gb/s (6G UHD-SDI) signals output on

DDO1. For details refer to Section 4.5.3.

3_h

Differential swing (amplitude) control for

2.97Gb/s (3Gb/s SDI) signals output on

DDO1. For details refer to Section 4.5.3.

3_h

0_h

DDO1_SWING_2G97

RSVD

3:0

RW

15:2

Reserved. Do not change.

Used to manually bypass the retiming block

in the CDR.

00_b: Re-timer not bypassed

01_b: Re-timer bypassed

0_h

MANUAL_BYPASS

1:1

0:0

RW

The assertion of MANUAL_BYPASS takes

precedence irrespective of the setting of

AUTO_BYPASS

20_h

CDR_BYPASS

Selects between automatic and manual

bypass of the retiming block when the CDR

is not locked.

00_b: Auto-Bypass is disabled

01_b: Auto-Bypass is enabled

1_h

AUTO_BYPASS

RW

Even if AUTO_BYPASS is asserted, the

assertion of MANUAL_BYPASS will still cause

the re-timer to be bypassed.

0_h

RSVD

15:11

10:10

RW

Reserved. Do not change.

Signal polarity invert at output of

CDR/bypass.

00_b: Not inverted

OUTPUT_POLARITY_INVERT

01_b: Inverted

21_h

PD_CONTROL

2_h

0_h

RSVD

9:6

5:1

RW

Reserved. Do not change.

Signal polarity invert at input to CDR/bypass.

00_b: Not inverted

0_h

INPUT_POLARITY_INVERT

0:0

RW

01_b: Inverted

GS6151

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Table 5-1: Register Descriptions - Standard Address Space (Continued)

Bit

Slice

Reset

Value

Address Register Name

Parameter Name

R/W

Description

Determines the DFT data output.

00_b: Clock

01_b: PRBS7 data

1_h

PRBSGEN_DATASEL

14:14

13:12

RW

Divide ratio for the DFT clock.

00_b: divide by 1

01_b: divide by 2

10_b: divide by 4

11_b: divide by 8

0_h

PRBSGEN_DIV

RW

When toggled HIGH then LOW starts the

internal PRBS7 data source.

0_h

PRBSGEN_START

11:11

10:10

RW

Selects the source for the DFT clock:

PRBSGEN_EXT_CLK

00_b: Internally generated clock

01_b: External clock

Controls the phase of the internally

generated DFT clock.

00_b: 0 degree phase

01_b: 90 degree phase

10_b: 180 degree phase

11_b: 270 degree phase

2_h

PRBSGEN_PHASE

PRBSGEN_CLKSEL

9:8

7:7

RW

22_h

PRBS_GEN_CTRL

Determines the source clock used by the

PRBS generator when PRBSGEN_EXT = 0

(internally generated clock).

0_h

00_b: DFT VCO clock

01_b: CDR clock

One-hot encoded rate indicator for the

dividers in PRBS generator circuit.

00001_b: MADI

00010_b: SD

00100_b: HD

01000_b: 3G

10000_b: 6G

2_h

PRBSGEN_RATESEL

6:2

RW

When HIGH, causes the open-loop PRBSGEN

VCO to be shut off even if PRBSGEN_ENABLE

= 1.

PRBSGEN_VCO_

POWERDOWN

0_h

1:1

0:0

RW

Has no effect when PRBSGEN_ENABLE = 0.

When HIGH, the PRBS7 generator circuit is

enabled.

0_h

PRBSGEN_ENABLE

Must be enabled when using any feature in

the PRBS_GEN_CTRL register.

GS6151

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Table 5-1: Register Descriptions - Standard Address Space (Continued)

Bit

Slice

Reset

Value

Address Register Name

Parameter Name

R/W

Description

0_h

RSVD

15:2

RW

Reserved. Do not change.

When HIGH, sets a latch in the Input PRBS

checker (EYE_MON_PRBS_NODATA bit of

EYE_MON_STATUS_REG_12) HIGH. This bit

must be set LOW before checking the

EYE_MON_PRBS_NODATA bit. The

EYE_MON_PRBS_NODATA bit will then be

automatically set LOW if transitions are

detected.

EYE_MON_PRBS_NODATA_

SET

0_h

1:1

RW

EYE_MON_

23_h

ENABLE

Enables the horizontal eye monitor.

00_b: Horizontal Eye Monitor disabled

HORIZONTAL_EYE_MON_

ENABLE

0_h

0:0

RW

01_b: Horizontal Eye Monitor enabled

RSVD

15:2

ROSW

Reserved. Do not change.

Writing a 1 to this bit triggers the start of a

manually timed horizontal eye scan using

the parameters defined in

EYE_MON_CONTROL_REG_[0:6] registers.

0_h

MANUAL_SCAN_START

1:1

0:0

ROSW

The bit then becomes read-only, and will be

reset to a value of 0 by the device to indicate

when the scan is complete.

EYE_MON_SCAN

24_h

_START

Writing a 1 to this bit triggers the start of an

automatic horizontal eye scan using the

device’s default parameters.

0_h

AUTO_SCAN_START

The bit then becomes read-only, and will be

reset to a value of 0 by the device to indicate

when the scan is complete.

GS6151

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Table 5-1: Register Descriptions - Standard Address Space (Continued)

Bit

Slice

Reset

Value

Address Register Name

Parameter Name

R/W

Description

0_h

RSVD

15:2

RW

Reserved. Do not change.

Enables a continuous, manually timed

horizontal eye scan using the parameters

defined in EYE_MON_CONTROL_REG_[0:6]

registers.

Setting CONTINUOUS_SCAN_ENABLE to 1

clears the ERROR_COUNT bits and starts a

new measurement.

CONTINUOUS_SCAN_

ENABLE

Error counting continues until

CONTINUOUS_SCAN_ENABLE is set to 0, at

which point the ERROR_COUNT bits may be

read.

0_h

1:1

RW

EYE_MON_

CONTROL_

REG_0

25_h

The ERROR_COUNT bits hold their value

until any new scan is started using

AUTO_SCAN_START,

MANUAL_SCAN_START, or

CONTINUOUS_SCAN_ENABLE.

Synchronous soft-reset for the horizontal

eye monitor block and its associated

registers (EYE_MON_CONTROL_REG_[0:6]

and EYE_MON_STATUS_REG_[2:12]).

0_h

EYE_MON_SOFT_RESET

0:0

RW

00_b: Normal operation of the horizontal eye

monitor

01_b: Resets the horizontal eye monitor

0_h

RSVD

15:8

Reserved. Do not change.

Selects the pre-divider value for the

sampling interval.

0000_b: 4

0001_b: 8

0010_b: 16

0011_b: 32

0100_b: 64

MEASUREMENT_

PREDIVIDER

0101_b: 128

0110_b: 256

0111_b: 512

1000_b: 1024

1001_b: 2048

1010_b-1111_b: INVALID

0_h

7:4

RW

EYE_MON_

CONTROL_

REG_1

26_h

This parameter, combined with

MEASUREMENT_TIME, defines the length of

time per phase for an auto eye scan

Controls the sampling interval in device

clock cycles.

2_h

SAMPLE_INTERVAL

3:0

RW

Sampling interval = SAMPLE_INTERVAL + 1

device clock cycle.

GS6151

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Table 5-1: Register Descriptions - Standard Address Space (Continued)

Bit

Slice

Reset

Value

Address Register Name

Parameter Name

R/W

Description

Selects measurement interval in multiples of

SAMPLE_INTERVAL_PREDIVIDER cycles.

The measurement time for a single phase

and bypass setting is:

MEASUREMENT_PREDIVIDER x

(MEASUREMENT_TIME + 1) x (1/108MHz)

EYE_MON_

CONTROL_

REG_2

27_h

A8B_h

MEASUREMENT_TIME

15:0

RW

The default value sets 100μs per sample,

which is approximately 25.6ms for a full scan

of 128 phases * 2 bypass settings.

The maximum MEASUREMENT_TIME value

results in a full scan taking approximately

1.25 seconds.

Error count threshold for pass/fail. The

phase being tested is considered to pass if

EYE_MON_PRBS_ERROR_COUNT is less than

or equal to

EYE_MON_PRBS_ERROR_THRESHOLD. The

phase fails if the

EYE_MON_PRBS_ERROR_COUNT exceeds

EYE_MON_PRBS_ERROR_THRESHOLD. The

default value of

EYE_MON_

CONTROL_

REG_3

EYE_MON_PRBS_ERROR_

THRESHOLD

28_h

3_h

15:0

RW

EYE_MON_PRBS_ERROR_THRESHOLD

corresponds to a bit error rate of 3.37x10-6

at a data rate of 5.94Gb/s using the default

MEASUREMENT_TIME of 100μs.

Error count threshold for pass/fail. The

phase being tested is considered to pass if

ERROR_COUNT is less than or equal to

ERROR_THRESHOLD. The phase fails if the

ERROR_COUNT exceeds

EYE_MON_

CONTROL_

REG_4

29_h

3_h

ERROR_THRESHOLD

15:0

RW

ERROR_THRESHOLD.

The default value of ERROR_THRESHOLD

corresponds to a bit error rate of 6.73x10-6

at a data rate of 5.94Gb/s using the default

MEASUREMENT_TIME of 100μs.

Phase setting for manually timed

(MANUAL_SCAN_START) and continuous

(CONTINUOUS_SCAN_ENABLE) scan

measurements.

0_h

3_h

EYE_MON_

CONTROL_

REG_5

MANUAL_PHASE

RSVD

10:4

3:0

RW

2A_h

Reserved. Do not change.

GS6151

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Table 5-1: Register Descriptions - Standard Address Space (Continued)

Bit

Slice

Reset

Value

Address Register Name

Parameter Name

R/W

Description

0_h

RSVD

15:6

5:5

RW

Reserved. Do not change.

Override value for EYE_MON_PRBS_CLEAR.

0_h

EYE_MON_CLEAR

EYE_MON_FORCE_CLEAR

EYE_MON_PRBS_CLEAR

RW

Only used when

EYE_MON_FORCE_PRBS_CLEAR = 1.

01_b: Overrides the EYE_MON_CLEAR output

with the PRBS_MON__CLEAR value

0_h

4:4

3:3

Allows host interface to directly control the

PRBS/eye monitor bypassing the

PRBS_MON_CTRL state machines.

Override value for EYE_MON_PRBS_CLEAR.

0_h

Only used when

EYE_MON_FORCE_PRBS_CLEAR = 1.

EYE_MON_

CONTROL_

REG_6

01_b: Overrides the EYE_MON_PRBS_CLEAR

output with the EYE_MON_PRBS_CLEAR

value

2B_h

EYE_MON_PRBS_FORCE_

CLEAR

0_h

2:2

1:1

RW

Allows host interface to directly control the

PRBS/eye monitor bypassing the

EYE_MON_CTRL state machines.

Selects which criteria is used to populate the

eye bitmap.

1_h

EYE_MON_SELECT

00_b: PRBS7 check

01_b: Arbitrary data check

Sets which portion of the eye is to be

sampled for manually timed and continuous

scan measurements. Result for the phase is

the lesser count of errors at each

0_h

EYE_MON_WINDOW

RSVD

0:0

15:15

14:8

RW

RO

EYE_MON_WINDOW setting.

Reserved. Do not change.

Starting (leftmost) phase of

EYE_MON_PRBS_EYE_WIDTH in the most

recent scan. This parameter only applies to

automatic (AUTO_SCAN_START)

measurements.

EYE_MON_PRBS_STARTING_

PHASE

Widest open portion of the eye in the most

recent scan, based on the

EYE_MON_

STATUS_REG_0

2C_h

EYE_MON_PRBS_ERROR_COUNT indication.

The value of EYE_MON_PRBS_EYE_WIDTH is

the number of contiguous phases with

EYE_MON_PRBS_ERROR_COUNT less than

or equal to

0_h

EYE_MON_PRBS_EYE_WIDTH

7:0

RO

EYE_MON_PRBS_ERROR_THRESHOLD.

This parameter only applies to automatic

(AUTO_SCAN_START) measurements.

GS6151

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Table 5-1: Register Descriptions - Standard Address Space (Continued)

Bit

Slice

Reset

Value

Address Register Name

Parameter Name

R/W

Description

Twice the PRBS Error count from the most

recent manually timed

(MANUAL_SCAN_START) or continuous

(CONTINUOUS_SCAN_ENABLE) scan

measurements.

EYE_MON_

2D_h

EYE_MON_PRBS_ERROR_

COUNT

0_h

15:0

RO

STATUS_REG_1

This value is not defined for automatic

(AUTO_SCAN_START) scan measurements.

0_h

RSVD

15:15

14:8

RO

Reserved. Do not change.

Starting (leftmost) phase of EYE_WIDTH in

the most recent scan.

STARTING_PHASE

This parameter only applies to automatic

(AUTO_SCAN_START) measurements.

EYE_MON_

2E_h

Widest open portion of the eye in the most

recent scan, based on the ERROR_COUNT

indication.

STATUS_REG_2

The value of EYE_WIDTH is the number of

contiguous phases with ERROR_COUNT less

than or equal to ERROR_THRESHOLD.

0_h

EYE_WIDTH

7:0

RO

This parameter only applies to automatic

(AUTO_SCAN_START) measurements.

Error count from the most recent manually

timed (MANUAL_SCAN_START) or

continuous (CONTINUOUS_SCAN_ENABLE)

scan measurements.

EYE_MON_

2F_h

0_h

ERROR_COUNT

15:0

STATUS_REG_3

This value is not defined for automatic

(AUTO_SCAN_START) scan measurements.

Bitmap of the per-phase pass/fail result from

the most recent automatic

(AUTO_SCAN_START) scan measurement for

phases 127 to 112.

A value of 1 in each bit indicates a pass for

the corresponding phase, while a value of 0

indicates a fail for that phase.

EYE_MON_

30_h

0_h

EYE_BITMAP_127_112

15:0

RO

STATUS_REG_4

The order of the numbers shown in the

Parameter Name field corresponds to the bit

orientation for each phase being reported in

this register.

Bitmap of the per-phase pass/fail result from

the most recent automatic

(AUTO_SCAN_START) scan measurement for

phases 111 to 96.

A value of 1 in each bit indicates a pass for

the corresponding phase, while a value of 0

indicates a fail for that phase.

EYE_MON_

31_h

0_h

EYE_BITMAP_111_96

15:0

RO

STATUS_REG_5

The order of the numbers shown in the

Parameter Name field corresponds to the bit

orientation for each phase being reported in

this register.

GS6151

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Table 5-1: Register Descriptions - Standard Address Space (Continued)

Bit

Slice

Reset

Value

Address Register Name

Parameter Name

R/W

Description

Bitmap of the per-phase pass/fail result from

the most recent automatic

(AUTO_SCAN_START) scan measurement for

phases 95 to 80.

A value of 1 in each bit indicates a pass for

the corresponding phase, while a value of 0

indicates a fail for that phase.

EYE_MON_

32_h

0_h

EYE_BITMAP_95_80

15:0

RO

STATUS_REG_6

The order of the numbers shown in the

Parameter Name field corresponds to the bit

orientation for each phase being reported in

this register.

Bitmap of the per-phase pass/fail result from

the most recent automatic

(AUTO_SCAN_START) scan measurement for

phases 79 to 64.

A value of 1 in each bit indicates a pass for

the corresponding phase, while a value of 0

indicates a fail for that phase.

EYE_MON_

33_h

EYE_BITMAP_79_64

EYE_BITMAP_63_48

EYE_BITMAP_47_32

RO

STATUS_REG_7

The order of the numbers shown in the

Parameter Name field corresponds to the bit

orientation for each phase being reported in

this register.

Bitmap of the per-phase pass/fail result from

the most recent automatic

(AUTO_SCAN_START) scan measurement for

phases 63 to 48.

A value of 1 in each bit indicates a pass for

the corresponding phase, while a value of 0

indicates a fail for that phase.

EYE_MON_

34_h

STATUS_REG_8

The order of the numbers shown in the

Parameter Name field corresponds to the bit

orientation for each phase being reported in

this register.

Bitmap of the per-phase pass/fail result from

the most recent automatic

(AUTO_SCAN_START) scan measurement for

phases 47 to 32.

A value of 1 in each bit indicates a pass for

the corresponding phase, while a value of 0

indicates a fail for that phase.

EYE_MON_

35_h

STATUS_REG_9

The order of the numbers shown in the

Parameter Name field corresponds to the bit

orientation for each phase being reported in

this register.

GS6151

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Table 5-1: Register Descriptions - Standard Address Space (Continued)

Bit

Slice

Reset

Value

Address Register Name

Parameter Name

R/W

Description

Bitmap of the per-phase pass/fail result from

the most recent automatic

(AUTO_SCAN_START) scan measurement for

phases 31 to 16.

A value of 1 in each bit indicates a pass for

the corresponding phase, while a value of 0

indicates a fail for that phase.

EYE_MON_

36_h

0_h

EYE_BITMAP_31_16

15:0

RO

STATUS_REG_10

The order of the numbers shown in the

Parameter Name field corresponds to the bit

orientation for each phase being reported in

this register.

Bitmap of the per-phase pass/fail result from

the most recent automatic

(AUTO_SCAN_START) scan measurement for

phases 15 to 0.

A value of 1 in each bit indicates a pass for

the corresponding phase, while a value of 0

indicates a fail for that phase.

EYE_MON_

37_h

0_h

EYE_BITMAP_15_0

15:0

RO

STATUS_REG_11

The order of the numbers shown in the

Parameter Name field corresponds to the bit

orientation for each phase being reported in

this register.

0_h

RSVD

15:11

10:10

RO

Reserved. Do not change.

When HIGH, indicates that no data

transitions have been detected in the PRBS

checker since the

EYE_MON_PRBS_NODATA_SET was last set

to 1.

EYE_MON_

38_h

EYE_MON_PRBS_NODATA

STATUS_REG_12

0_h

RSVD

9:0

RO

Reserved. Do not change.

15:4

RW

When HIGH, sets a latch in the Retime PRBS

checker (PRBS_MON_NODATA bit of

PRBS_STATUS_REG_11) HIGH. This bit must

be set LOW before checking the

PRBS_MON_NODATA bit. The

PRBS_MON_NODATA bit will then be

automatically set LOW if transitions are

detected.

0_h

PRBS_MON_NODATA_SET

3:3

RW

39_h

PRBS_CHK_CTRL

1_h

0_h

RSVD

2:1

0:0

RW

Reserved. Do not change.

When asserted the Re-time PRBS7 checker

circuit is enabled.

PRBS_MON_ENABLE

GS6151

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Table 5-1: Register Descriptions - Standard Address Space (Continued)

Bit

Slice

Reset

Value

Address Register Name

Parameter Name

R/W

Description

Enable for manual timed measurement

using the Re-time PRBS checker.

PRBS_MON_MANUAL_

START

0_h

01_b: Triggers a scan

1:1

0:0

ROSW

Automatically cleared to 0 when the scan

completes.

3A_h

PRBS_CTRL_0

Enable for automatic eye scan using the

Re-time PRBS checker.

PRBS_MON_AUTO_SCAN_

START

0_h

01_b: Triggers a scan

ROSW

Automatically cleared to 0 when the scan

completes.

Enable for manual continuous

measurement using the Re-time PRBS

checker. Rising edge clears the error counter

and starts a measurement. Error counting

continues until

PRBS_MON_CONTINUOUS_ENABLE is set to

0, at which point the error counter

PRBS_MON_ERROR_COUNT can be read.

PRBS_MON_CONTINUOUS_

ENABLE

0_h

1:1

0:0

RW

3B_h

PRBS_CTRL_1

The error counter holds its value until any

new scan is started (manual or auto).

When HIGH, the logic in PRBS monitor state

machine is synchronously reset.

0_h

PRBS_MON_SOFT_RESET

Along with

PRBS_MON_MEASUREMENT_TIME,

determines the length of time of a

measurement for a given phase in

automatic or manual timed modes

(PRBS_MON_AUTO_SCAN_START = 1 or

PRBS_MON_MANUAL_START = 1).

Pre-divider value vs. sampling interval:

0000_b: 4

0001_b: 8

0010_b: 16

PRBS_MON_MEASUREMENT_

PREDIVIDER

0_h

7:4

RW

0011_b: 32

3C_h

PRBS_CTRL_2

0100_b: 64

0101_b: 128

0110_b: 256

0111_b: 512

1000_b: 1024

1001_b: 2048

1010_b-1111_b: INVALID

Controls sampling interval for an error

signal. The sampling interval is

PRBS_MON_SAMPLE_INTERVAL + 1 clock

cycles. The minimum allowable value is 1

(sampling interval of 2).

PRBS_MON_SAMPLE_

INTERVAL

2_h

3:0

RW

GS6151

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Table 5-1: Register Descriptions - Standard Address Space (Continued)

Bit

Slice

Reset

Value

Address Register Name

Parameter Name

R/W

Description

Selects measurement interval in multiples of

pre-divider cycles. The measurement time

for a single phase is:

PRBS_MON_MEASURE_PREDIVIDER *

(PRBS_MON_MEASUREMENT_TIME + 1) *

(1/108MHz).

PRBS_MON_MEASUREMENT_

TIME

3D_h

A8B_h

PRBS_CTRL_3

15:0

RW

The default value results in a 100μs

measurement time or roughly 12.8ms for a

full scan of 128 phases. The maximum

measurement time is ~1.25 seconds.

PRBS error count threshold for good/bad

BER for automatic eye scan. A measurement

is considered to pass if

PRBS_MON_PRBS_ERROR_

THRESHOLD

PRBS_ERROR_COUNT is less than or equal to

this threshold. It fails if the count is greater.

The default threshold corresponds to a bit

error rate of 6.67E-6 at 6G using the default

measurement interval of 100μs.

3E_h

3_h

PRBS_CTRL_4

15:0

RW

0_h

3_h

RSVD

15:11

10:4

3:0

RW

Reserved. Do not change.

Phase setting for manual timed or

continuous scans

3F_h

PRBS_CTRL_5 PRBS_MON_MANUAL_PHASE

RSVD

Reserved. Do not change.

00_b: No effect

01_b: Manually clear error indication

0_h

PRBS_MON_CLEAR

1:1

0:0

RW

Only used when

PRBS_MON_FORCE_CLEAR = 1

40_h

PRBS_CTRL_6

00_b: Manual error clearing is disabled

01_b: Enables error clearing through

PRBS_MON_CLEAR

0_h

PRBS_MON_FORCE_CLEAR

Allows host interface to directly control the

PRBS error counting algorithm, bypassing

the PRBS_MON_CTRL state machine.

GS6151

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Table 5-1: Register Descriptions - Standard Address Space (Continued)

Bit

Slice

Reset

Value

Address Register Name

Parameter Name

R/W

Description

0_h

RSVD

15:15

RO

Reserved. Do not change.

Starting (leftmost) phase of

PRBS_MON_EYE_WIDTH in the most recent

scan.

PRBS_MON_

STARTING_

PHASE

0_h

14:8

RO

This parameter only applies to automatic

(AUTO_SCAN_START) measurements.

PRBS_STATUS_

41_h

Widest open portion of the eye in the most

recent scan, based on the

PRBS_MON_ERROR_COUNT indication.

REG_0

The value of PRBS_MON_EYE_WIDTH is the

number of contiguous phases with

0_h

PRBS_MON_EYE_WIDTH

7:0

PRBS_MON_ERROR_COUNT less than or

equal to PRBS_MON_ERROR_THRESHOLD.

This parameter only applies to automatic

(AUTO_SCAN_START) measurements.

Twice the PRBS error count from the most

recent manually timed

(MANUAL_SCAN_START) or continuous

(CONTINUOUS_SCAN_ENABLE) scan

measurements.

PRBS_STATUS_

42_h

0_h

PRBS_MON_ERROR_COUNT

15:0

RO

REG_1

This value is not defined for automatic

(AUTO_SCAN_START) scan measurements

when a PRBS7 bit stream is input.

43_h

44_h

45_h

46_h

47_h

48_h

49_h

4A_h

0_h

RESERVED

RSVD

15:0

15:9

RO

Reserved. Do not change.

When HIGH, indicates that no data

transitions have been detected in the PRBS

checker since the PRBS_MON_NODATA_SET

was last set to 1.

PRBS_STATUS_

REG_11

4B_h

0_h

PRBS_MON_NODATA

RSVD

8:8

7:0

RO

Reserved. Do not change.

GS6151

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Table 5-1: Register Descriptions - Standard Address Space (Continued)

Bit

Slice

Reset

Value

Address Register Name

Parameter Name

R/W

Description

0_h

RSVD

15:12

11:10

RW

Reserved. Do not change.

Determines the source of CARRIER_DETECT.

00 : Edge detection

1_h

LOS_DETECTION_METHOD

RW

b

01 : Strength detection

b

Force the PLL to retime a specific data rate.

000 : Reserved

b

001 : 0.270Gb/s

b

010 : 1.485Gb/s

b

011 : 2.97Gb/s

b

1_h

FORCE_PLL_RATE

9:7

100 : 5.94Gb/s

b

101 : Reserved

b

110 : Reserved

b

111 : Reserved

b

Used when FORCE_PLL_RATE_ENABLE is set to

1.

Enables the forced PLL rate override set using

the FORCE_PLL_RATE bits.

0_h

FORCE_PLL_RATE_ENABLE

RATE_ENABLE_125M

6:6

5:5

RW

Enables auto-detection of 0.125Gb/s (MADI)

signals

00 : 0.125Gb/s signals will not be detected

b

01 : 0.125Gb/s signals will be detected

b

4C_h

PLL_CONTROL

Enables auto-detection of 5.94Gb/s

(6G UHD-SDI) signals.

1_h

RATE_ENABLE_5G94

RATE_ENABLE_2G97

RATE_ENABLE_1G485

RATE_ENABLE_270M

4:4

3:3

2:2

1:1

RW

00 : 5.94Gb/s signals will not be detected

b

01 : 5.94Gb/s signals will be detected

b

Enables auto-detection of 2.97Gb/s

(3G SDI) signals.

00 : 2.97Gb/s signals will not be detected

b

01 : 2.97Gb/s signals will be detected

b

Enables auto-detection of 1.485Gb/s (HD-SDI)

signals.

00 : 1.485Gb/s signals will not be detected

b

01 : 1.485Gb/s signals will be detected

b

Enables auto-detection of 0.27Gb/s

(SD-SDI) signals.

00 : 0.27Gb/s signals will not be detected

b

01 : 0.27Gb/s signals will be detected

b

Synchronous soft-reset for the PLL rate

detection state machine.

00 : Normal operation of the PLL rate

detection state machine

b

0_h

PLL_SOFT_RESET

RSVD

0:0

RW

01 : Resets the PLL rate detection state

b

machine

4D_h

110_h

RESERVED

15:0

Reserved. Do not change.

GS6151

Final Data Sheet

PDS-060389

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Table 5-1: Register Descriptions - Standard Address Space (Continued)

Bit

Slice

Reset

Value

Address Register Name

Parameter Name

R/W

Description

4E_h

110_h

RESERVED

RSVD

15:0

RW

Reserved. Do not change.

Indicates whether the re-timer is active or

bypassed.

RETIMER_BYPASS

LBR_HBR

15:15

RO

—

00_b: Re-timer is active

01_b: Re-timer is bypassed

Indicates high-bit-rate versus low-bit-rate.

00_b: Input data rate is 5.94Gb/s,

2.97Gb/s, 1.485Gb/s, or BYPASS

14:14

13:11

—

01_b: Input data rate is 270Mb/s or 125Mb/s

Indicates the current rate found by the PLL

rate detection state machine.

000_b: 0.125Gb/s

001_b: 0.270Gb/s

010_b: 1.485Gb/s

011_b: 2.97Gb/s

100_b: 5.94Gb/s

101_b: Reserved

110_b: Reserved

111_b: Reserved

DETECTED_RATE

RO

4F_h

PLL_STATUS

RSVD

10:10

9:9

RO

—

Reserved. Do not change.

Indicates if the CDR is locked or unlocked.

00_b: CDR is unlocked

LOCKED

01_b: CDR is locked

Indicates whether or not the CDR has lost

the signal.

LOS

8:8

7:0

RO

—

00_b: Signal is present

01_b: Loss of signal

RSVD

Reserved. Do not change.

GS6151

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Table 5-1: Register Descriptions - Standard Address Space (Continued)

Bit

Slice

Reset

Value

Address Register Name

Parameter Name

R/W

Description

Sticky bit indicating that the device entered

STANDBY mode at least once.

00 : Device has not entered STANDBY mode

since this bit was last cleared

b

ROCW

STANDBY_STICKY

11:11

10:10

—

01 : Devices has entered STANDBY mode since

b

this bit was last cleared

Sticky bit indicating that the device entered

SLEEP mode at least once

00 : Device has not entered SLEEP mode since

b

ROCW

SLEEP_STICKY

this bit was last cleared

01 : Device has entered SLEEP mode since this

b

bit was last cleared

Sticky bit indicating that the re-timer is/has

been bypassed.

00 : Re-timer has not been bypassed since this

b

ROCW

RETIMER_BYPASS_STICKY

9:9

8:8

7:7

—

bit was last cleared

01 : Re-timer has been bypassed since this bit

b

was last cleared

This bit is cleared by writing any value to it.

Sticky bit indicating that the rate is/has been

270Mb/s (low bit-rate).

00 : Rate has not been 270Mb/s since this bit

b

ROCW

LBR_HBR_STICKY

was last cleared

01 : Rate has been 270Mb/s since this bit was

b

50_h

STICKY_STATUS

last cleared

This bit is cleared by writing any value to it.

Sticky bit indicating that a rate change has

occurred.

00 : Rate has not changed since this bit was

b

ROCW

RATE_CHANGE_STICKY

last cleared

01 : Rate has changed since this bit was last

b

cleared

This bit is cleared by writing any value to it.

Sticky bit indicating that lock was lost.

00 : Lock has not been lost since this bit was

b

last cleared

ROCW

LOCK_LOST_STICKY

RSVD

6:6

5:5

4:4

3:0

—

01 : Lock has been lost since this bit was last

b

cleared

This bit is cleared by writing any value to it.

Reserved. Do not change.

Sticky bit indicating a loss of signal.

00 : Signal has not been lost since this bit was

b

last cleared

LOS_STICKY

RSVD

01 : Signal has been lost since this bit was last

b

cleared

This bit is cleared by writing any value to it.

Reserved. Do not change.

GS6151

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Table 5-2: Register Descriptions - Extended Address Space

Reset

Value

(Dec)

Register

Name

Parameter

Name

Bit

Slice

Address

R/W

Description

0_h

RSVD

15:2

1:1

RW

Reserved. Do not change.

PWR_

CONTROL

When enabled, reduces power when

locked to a rate of HD, 3G or 6G.

D2_h

HS_LOCKED_POWER_SAVE

1_h

4_h

RSVD

0:0

RW

Reserved. Do not change.

15:5

Sets the rate specific PLL loop-bandwidth

when the device is locked.

00001_b: Nominal / 4

00010_b: Nominal / 2

00100_b: Nominal (default)

01000_b: Nominal x 2

11100_b: Nominal x 4

PLL_LBW_

CONTROL_

REG_0

E4_h

4_h

PLL_LOOP_BANDWIDTH

4:0

RW

See Table 2-3: AC Electrical Characteristics

for the PLL loop-bandwidth value set at

each rate by each of these settings.

RW = Read/Write

RO = Read Only

ROCW = Read Only/ Clear on Write

ROSW = Read Only/ Set on Write

GS6151

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6. Typical Application Circuit

VCC

27MHz

10nF 10nF 10nF 10nF

VCC

10nF 10μF

10nF

C1*

C2*

1M

Ω

9

XTAL_CLK_IN

10

11

XTAL_CLK_OUT

XTAL_BUFF_OUT

OUT

1

24

23

DDI0

DDO0

IN

OUT

2

19

18

4

5

DDO1

OUT

IN

DDI1

GS6151

6

GPIO_0

GPIO_1

IO

8

IN

DDI_SEL/STROBE

7

12

13

14

15

25

SDI

DFT_VCO_FILT

LF+

SDO

SCLK

CS

28

29

10nF 10μF

IN

220nF

OUT

IN

LF-

IN

Notes:

VCC IS 1.8V

VCC_DDO0 AND VCC_DDO1 ARE IN THE RANGE +1.2V TO +2.5V

If XTAL_CLK_IN is not connected to a crystal, XTAL_CLK_OUT must be left unconnected.

*VALUES FOR C1 AND C2 ARE CHOSEN BASED ON THE REQUIRED LOADING FOR THE SELECTED CRYSTAL

IF AC COUPLING IS REQUIRED ON THE HIGH-SPEED SERIAL INPUTS AND OUTPUTS BY THE APPLICATION, A CERAMIC CAPACITOR 4.7μF OR HIGHER WITH A STABLE DIELECTRIC IS RECOMMENDED

Figure 6-1: GS6151 Typical Application Circuit

GS6151

Final Data Sheet

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7. Package and Ordering Information

7.1 Package Dimensions

M

0.10 C A B

2.75 0.10

4.00

A

B

DATUM A

M

0.10 C A B

PIN 1 AREA

DATUM B

2X

0.10 C

DETAIL B

DETAIL A

2X

0.10 C

C

32X

0.08 C

SEATING PLANE

0.20 0.05

24X

M

0.07 C A B

DATUM A OR B

M

C

0.20 0.05

0.05

8X

M

0.07 C A B

M

C

0.05

0.35 0.10

0.30 0.10

DETAIL B (SCALE 3:1)

DETAIL A (SCALE 3:1)

NOTES:

1. DIMENSIONING AND TOLERANCE IS IN CONFORMANCE TO ASME Y14.5–1994.

ALL DIMENSIONS ARE IN MILLIMETERS, ° IN DEGREES.

2. DIMENSION OF LEAD WIDTH APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.15mm AND 0.30mm

FROM THE TERMINAL TIP (BOTH ROWS). IF THE TERMINAL HAS OPTIONAL RADIUS ON THE END OF THE TERMINAL,

THE LEAD WIDTH DIMENSION SHOULD NOT BE MEASURED IN THAT RADIUS AREA.

Figure 7-1: GS6151 Package Dimensions

GS6151

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7.2 Recommended PCB Footprint

0.40

0.20

0.55

3.90 2.75

CENTER PAD

Note: All dimensions

in millimeters

2.75

3.90

Figure 7-2: GS6151 PCB Footprint

7.3 Packaging Data

Table 7-1: Packaging Data

Parameter

Value

32-pin QFN / 4mm x 4mm /

0.4mm pad pitch

Package Type

Moisture Sensitivity Level (Note 1)

3

Junction to Case Thermal Resistance, θ_j-c

29.8°C/W

35.4°C/W

Junction to Air Thermal Resistance, θ_j-a

Junction to Board Thermal Resistance, θ_j-b

12.0°C/W

0.3°C/W

Yes

Psi, Ψ

Pb-free and RoHS Compliant

Note:

1. Value per JEDEC J-STD-020C

GS6151

Final Data Sheet

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7.4 Marking Diagram

Pin 1 ID

XXXX - Last 4 digits of Assembly lot

E3 - Pb-free & Green indicator

YYWW - Date Code

GS6151

XXXXE3

YYWW

Figure 7-3: GS6151 Marking Diagram

7.5 Solder Reflow Profile

Temperature

60-150 sec.

20-40 sec.

260°C

250°C

3°C/sec max

217°C

6°C/sec max

200°C

150°C

25°C

Time

60-180 sec. max

8 min. max

Figure 7-4: Maximum Pb-free Solder Reflow Profile

7.6 Ordering Information

Table 7-2: Ordering Information

Part Number

Package

Temperature Range

Pb-free 32-pin QFN

(490 piece tray)

GS6151-INE3

-40°C to 85°C

Pb-free 32-pin QFN

(250 piece reel)

GS6151-INTE3

GS6151-INTE3Z

-40°C to 85°C

Pb-free 32-pin QFN

(2500 piece reel)

GS6151

Final Data Sheet

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IMPORTANT NOTICE

Information relating to this product and the application or design described herein is believed to be reliable, however such information is

provided as a guide only and Semtech assumes no liability for any errors in this document, or for the application or design described herein.

Semtech reserves the right to make changes to the product or this document at any time without notice. Buyers should obtain the latest relevant

information before placing orders and should verify that such information is current and complete. Semtech warrants performance of its

products to the specifications applicable at the time of sale, and all sales are made in accordance with Semtech’s standard terms and conditions

of sale.

SEMTECH PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS,

DEVICES OR SYSTEMS, OR IN NUCLEAR APPLICATIONS IN WHICH THE FAILURE COULD BE REASONABLY EXPECTED TO RESULT IN PERSONAL

INJURY, LOSS OF LIFE OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE. INCLUSION OF SEMTECH PRODUCTS IN SUCH APPLICATIONS IS

UNDERSTOOD TO BE UNDERTAKEN SOLELY AT THE CUSTOMER’S OWN RISK. Should a customer purchase or use Semtech products for any such

unauthorized application, the customer shall indemnify and hold Semtech and its officers, employees, subsidiaries, affiliates, and distributors

harmless against all claims, costs damages and attorney fees which could arise.

The Semtech name and logo are registered trademarks of the Semtech Corporation. All other trademarks and trade names mentioned may be

marks and names of Semtech or their respective companies. Semtech reserves the right to make changes to, or discontinue any products

described in this document without further notice. Semtech makes no warranty, representation or guarantee, express or implied, regarding the

Contact Information

Semtech Corporation

200 Flynn Road, Camarillo, CA 93012

Phone: (805) 498-2111, Fax: (805) 498-3804

www.semtech.com

GS6151

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型号：	GS6151-INTE3
厂家：	SEMTECH CORPORATION
描述：	Multi-Rate 6G UHD-SDI
文件：	总77页 (文件大小：2092K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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