SC1155_01 [SEMTECH]
Programmable Synchronous DC/DC Hysteretic Controller with VRM 9.0VID Range; 可编程同步DC / DC控制器的滞后与VRM 9.0VID范围
| 型号： | SC1155_01 |
| 厂家： | 
SEMTECH CORPORATION |
| 描述： | Programmable Synchronous DC/DC Hysteretic Controller with VRM 9.0VID Range |
| 文件： | 总20页 (文件大小：264K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SC1155
Programmable Synchronous DC/DC
Hysteretic Controller with VRM 9.0 VID Range
PRELIMINARY
POWER MANAGEMENT
ꢀeatures
Description
The SC1155 is a synchronous-buck switch-mode con-
troller designed for use in single ended power supply ap-
plications where efficiency is the primary concern. The
controller is a hysteretic type, with a user selectable hys-
teresis. The SC1155 is ideal for implementing DC/DC
converters needed to power advanced microprocessors
such as Pentium® llI and Athlon®, in both single and mul-
tiple processor configurations. Inhibit, under-voltage lock-
out and soft-start functions are included for controlled
power-up.
u Programmable hysteresis
u 5 bit DAC programmable output (1.1V-1.85V)
u On-chip power good and OVP functions
u Designed to meet latest Intel specifications
u Up to 95% efficiency
u +1% tolerance over temperature
Applications
SC1155 features include an integrated 5 bit D/A con-
verter, temperature compensated voltage reference,
current limit comparator, over-current protection, and an
adaptive deadtime circuit to prevent shoot-through of
the power MOSꢀET during switching transitions. Power
good signaling, logic compatible shutdown, and over-volt-
age protection are also provided. The integrated D/A
converter provides programmability of output voltage
from 1.1V to 1.85V in 25mV increments.
u Server Systems and Workstations
u Pentium® III Core Supplies
u AMD Athlon® Core Supplies
u Multiple Microprocessor Supplies
u Voltage Regulator Modules
The SC1155 high side driver can be configured as either
a ground-referenced or as a floating bootstrap driver.
The high and low side MOSꢀET drivers have a peak cur-
rent rating of 2 amps.
Typical Application Circuit
+5V
R1
*
R10
1k
R9
10k
U1
SC1155
R3
*
PWRGD
1
2
28
27
26
25
24
23
22
21
20
19
18
17
16
15
IOUT
PWRGD
VID0
"POWER GOOD"
R2
1k
C6
0.1
DROOP
OCP
R4
1k
INHIB
3
VID1
"INHIBIT"
C7
0.1
R11
1k
4
VHYST
VREFB
VSENSE
AGND
SOFTST
N/C
VID2
R5
*
5
VID3
L1
0.5uH
C1
0.1
R6
20k
6
+
VID4
C2
0.001
Cin
Hꢀ
Cin
Bulk
7
Vin +5V/12V
INHIBIT
IOUTLO
LOSENSE
HISENSE
BOOTLO
HIGHDR
BOOT
8
_
C8
0.033
C3
0.1
9
+5V
10
11
12
13
14
LODRV
LOHIB
DRVGND
LOWDR
DRV
C4
0.01
Q1
ꢀDB6035AL
R12
1.0
L2
1.0uH
C9
1.0
+12V
+
Q2
VIN12V
ꢀDB7030BL
R14
1.6
Cout
Bulk
Cout
Hꢀ
1.10 to 1.825V
C5
C10
_
R7
*
R8
10k
*) for the values see specific application circuit somewhere else in the datasheet
Revision 2, June 2001
1
www.semtech.com
SC1155
PRELIMINARY
Units
POWER MANAGEMENT
Absolute Maximum Ratings
Parameter
Symbol
Maximum
VIN12V
VINMAX
-0.3 to 14
-0.3 to 25
-0.3 to 15
-0.5 to 18
-0.5 to 7.3
±0.5
V
V
V
V
V
V
V
V
V
BOOT to DRVGND
BOOT to BOOTLO
BOOTLO tp DRVGND
VIDS, INHIB, LODRV, PWRGD, OCP, DROOP
AGND to DRVGND
LOHIB to AGND
-0.3 to 14
-0.3 to 14
-0.3 to 14
LOSENSE to AGND
IOTLO to AGND
HISENSE to AGND
-0.3 to 14
-0.3 to 5
1.2
V
V
VSENSE to AGND
Continuous Power Dissipation, TA = 25 0C
Continuous Power Dissipation, TC = 25 0C
Operating Junction Temperature Range
Lead Temperature (Soldering) 10 Sec.
Storage Temperature
PD
PD
TJ
W
W
°C
°C
°C
6.25
0 to +125
300
TL
TSTG
-65 to 150
DC Electrical Characteristics
Unless specified: 0 < TJ < 125°C, VIN = 12V
Parameter
Symbol
Conditions
Min
11.4
Typ
12
Max
Units
V
Supply Voltage Range
Supply Current (Quiescent)
VIN12V
13
I q
INH = 5V, VID not 11111, Vin above UVLO
threshold during start-up,
15
mA
IN
fsw = 200 kHz, BOOTLO = 0V,
C
DH = CDL = 50pF
High Side Driver Supply
Current (Quiescent)
IBOOTq
INH = OV or VID = 11111 or Vin below
UVLO threshold during start-up,
BOOT = 13V, BOOTLO = OV
10
µA
INH = 5V, VID not 11111, VIN above UVLO
threshold during start-up,
5
mA
fsw = 200kHz, BOOT = 13V, BOOTLO = 0V,
CDH = 50pF
www.semtech.com
2001 Semtech Corp.
2
SC1155
PRELIMINARY
POWER MANAGEMENT
DC Electrical Characteristics (Cont.)
Unless specified: 0 < TJ < 125°C, VIN = 12V
Parameter
Symbols Conditions
Min
Typ
Max
Units
Reference/Voltage Identification
Reference Voltage Accuracy
VREF
11.4V < VIN12V< 12.6V, over full
VID range (see Output Voltage
Table)
-1
1
%
VIDO - VID4 High Threshold
Voltage
VTH(H)
2.25
90
V
V
VIDO - VID4 Low Threshold Voltage
VTH(L)
1
Power Good
Undervoltage Threshold
VTH(PWRGD)
95
%VREF
Output Saturation Voltage
Hysteresis
VSAT
IO = 5mA
0.5
10
V
VHYS(PWRGD)
mV
Over Voltage Protection
OVP Trip Point
VOVP
2.08
10.4
2.15
13
2.22
15.6
V
Soft Start
Charge Current
ICHG
VSS = 0.5V, resistance from VREFB
pin to AGND = 20kΩ, VREFB = 1.3V
Note: ICHG = (IVREFB / 5)
µA
Discharge Current
Idischg V(SS) = 1V
1
mA
V
Inhibit Comparator
Start Threshold
Vstart(NH)
1
2.0
2.4
VIN 12V UVLO
Start Threshold
VstartUVLO
VhysUVLO
9.25 10.25 11.25
V
V
Hysteresis
1.8
2
2.2
Hysteretic Comparator
Input Offset Voltage
Input Bias Current
VosHYSCMP VDROOP pin grounded
5
1
mV
uA
IbiasHYSCM-
P
Hysteresis Accuracy
Hysteresis Setting
VHYS ACC
VHYS SET
7
mV
mV
60
www.semtech.com
2001 Semtech Corp.
3
SC1155
PRELIMINARY
POWER MANAGEMENT
DC Electrical Characteristics (Cont.)
Parameter
Symbols
Conditions
Min
Typ
Max
Units
Droop Compensation
Initial Accuracy
VDROOP ACC VDROOP = 50 mV
5
mV
Overcurrent Protection
OCP Trip Point
VOCP
0.09
0.1
2
0.11
100
V
Input Bias Current
High-Side VDS Sensing
Gain
IbiasOCP
nA
V/V
mV
Initial Accuracy
IOUT Source
VIOUT
VHISENSE = 12V, VIOUTLO = 11.9V
6
ACC
VIOUT = 0.5V, VHISENSE = 12V,
VIOUTLO = 11.5V
IsourceIOUT
500
µA
IsinkIOUT VIOUT =0.05V, VHISENSE = 12V,
IOUTLO = 12V
IOUT Sink Current
40
0
50
µA
V
V
VIOUT(11)
VIOUT(4.5)
VIOUT(3)
VHISENSE = 11V, RIOUT = 10K0hm
3.75
2.0
VIOUT Voltage Swing
VHISENSE = 4.5V,
RIOUT = 10k0hm
0
V
VHISENSE = 3V, RIOUT = 10k0hm
0
1.0
V
V
V
Ω
LOSENSE High Level Input Voltage VihLOSENSE VHISENSE = 4.5V (Note 1)
2.85
LOSENSE Low Level Input Voltage
Sample/Hold Resistance
Buffered Reference
VilLOSENSE VHISENSE = 4.5V (Note 1)
RS/H (Note 1)
1.8
80
50
65
2
VREFB Load Regulation
Deadtime Circuit
VldregREFB 10µA < IREFB < 500µA
VihLOHIB (Note 1)
mV
LOHIB High Level Voltage
LOHIB Low Level Input Voltage
LOWDR High Level Input Voltage
LOWDR Low Level Input Voltage
Drive Regulator
2
2
V
V
V
V
VilLOHIB
(Note 1)
1.0
1.0
9
VihLOWDR (Note 1)
VilLOWDR (Note 1)
DRV Voltage
VDRV
11.4 < VIN12V < 12.6V, IDRV = 50mA
7
V
Load Regulation
VldregDRV 1mA < IDRV < 50mA
IshortDRV
100
mV
mA
Short Circuit Current
100
www.semtech.com
2001 Semtech Corp.
4
SC1155
PRELIMINARY
POWER MANAGEMENT
DC Electrical Characteristics (Cont.)
Parameter
Symbol
Conditions
Min
Typ
Max
Units
High-Side Output Driver(1)
Peak Output Current
IsrcHIGHDR duty cycle < 2%, tpw < 100µs,
2
A
IsinkHIGHDR TJ = 125°C
VBOOT - VBOOTLO = 6.5V, VHIGHDR = 1.5V (src)
or VHIGHDR = 5V (sink)
Equivalent Output Resistance
RsrcHIGHDR TJ = 125°C
BOOT - VBOOTLO = 6.5V, VHIGHDR = 6V
45
5
Ω
V
RsinkHIGHDR TJ = 125°C
VBOOT - VBOOTLO = 6.5V, VHIGHDR = 0.5V
Low-Side Output Driver(1)
Peak Output Current
IsrcLOWDR
IsinkLOWDR TJ = 125°C
VDRV - VBOOTLO = 6.5V, VLOWDR = 1.5V (src)
or VLOWDR = 5V (sink)
duty cycle < 2%, tpw < 100us,
2
Equivalent Output Resistance
RsrcLOWDR TJ = 125°C
VDRV = 6.5V, VLOWDR = 6V
45
5
Ω
RsinkLOWDR TJ = 125°C
VDRV = 6.5V, VLOWDR = 0.5V
(Note 1)
AC Electrical Characteristics
Hysteretic Comparators
Propagation Delay Time from
VSENSE to HIGHDR or
LOWDR (excluding
deadtime)
tHCPROP
10mV overdrive,
1.3V ≤ Vref ≤ 1.8V
150
250
ns
Output Drivers
HIGHDR rise/fall time
trHIGHDR
trHIGHDR
CI = 9nF, VBOOT = 6.5V,
VBOOTLO = grounded,
TJ =125°C
60
60
ns
ns
LOWDR rise/falltime
trLOWDR
tfLOWDR
CI = 9nF, VDRV = 6.5V,
TJ =125°C
Overcurrent Protection
Comparator Propagation
Delay Time
tOVPROP
1
µs
µs
Deglitch Time (Includes
comparator propagation
delay time)
tOVDGL
2
5
www.semtech.com
2001 Semtech Corp.
5
SC1155
PRELIMINARY
POWER MANAGEMENT
(Note 1)
AC Electrical Characteristics (Cont.)
Parameter
Symbol
Conditions
Min
Typ
Max
Units
Overvoltage Protection
Comparator Propagation Delay Time
tOVPROP
tOVPDGL
1
µs
µs
Deglitch Time (Includes comparator
protection delay time)
1
3
High-Side Vds Sensing
Response Time
tVDSRESP
VHISENSE = 12V, VIOUTLO pulsed
from 12V to 11.9V, 100ns rise
and fall times
2
3
3
µs
µs
µs
V
HISENSE = 4.5V, VIOUTLO pulsed
from 4.5V to 4.4V, 100ns rise
and fall times
V
HISENSE = 3V, VIOUTLO pulsed
from 3.0v to 2.9V, 100ns rise
and fall times
Short Circuit Protection Rising Edge
Delay
tVDSRED
LOSENSE grounded
3V < VHISENSE < 11V
300
30
500
100
ns
ns
Sample/Hold Switch turn-on/turn-off
Delay
tSWXDLY
V
LOSENSE = VHISENSE
Power Good
Comparator Propagation Delay
Softstart
tPWRGD
1
µs
ns
Comparator Propagation Delay
Deadtime
tSLST
overdrive = 10mV
560
900
100
400
CLOWDR = 9nF, 10% threshold on
LOWDR
Driver Nonoverlap Time
tNOL
30
ns
ns
LODRV
Propagation Delay
TLODRVDLY
Notes:
(1) Guaranteed, but not tested.
(2) This device is ESD sensitive. Use of standard ESD handling precautions is required.
www.semtech.com
2001 Semtech Corp.
6
SC1155
PRELIMINARY
POWER MANAGEMENT
Test Circuit
Timing Diagram
Simplified Block Diagram
www.semtech.com
2001 Semtech Corp.
7
SC1155
PRELIMINARY
POWER MANAGEMENT
Ordering Information
Pin Configuration
Device (1)
SC1155CSW.TR
SC1155EVB
Package
Temp Range (TJ)
Top View
SO-28
0° to 125°C
Evaluation Board
Note:
(1) Only available in tape and reel packaging. A reel
contains 1000 devices.
(28-Pin SOIC)
Pin Descriptions
Pin #
Pin Name
Pin Function
1
IOUT
Current Out. The output voltage on this pin is proportional to the load current as measured
across the high side MOSFET, and is approximately equal to 2 x RDS(ON) x ILOAD.
DROOP
OCP
Droop Voltage. This pin is used to set the amount of output voltage set-point droop as a
function of load current. The voltage is set by a resistor divider between IOUT and AGND.
2
3
Over Current Protection. This pin is used to set the trip point for over current protection by a
resistor divider between IOUT and AGND.
4
VHYST
Hysteresis Set Pin. This pin is used to set the amount of hysteresis required by a resistor
divider between VREFB and AGND.
5
6
VREFB
VSENSE
AGND
Buffered Reference Voltage (from VID circuitry).
Output Voltage Sense.
7
Small Signal Analog and Digital Ground.
Soft Start. Connecting a capacitor from this pin to AGND sets the time delay.
Not connected.
8
SOFTST
NC
9
10
LODRV
Low Drive Control. Connecting this pin to +5V enables normal operation. When LOHIB is
grounded, this pin can be used to control LOWDR.
11
12
13
LOHIB
DRVGND
LOWDR
Low Side Inhibit. This pin is used to eliminate shoot-thru current.
Power Ground. Insure output capacitor ground is connected to this pin.
Low Side Driver Output. Connect to gate of low side MOSFET.
www.semtech.com
2001 Semtech Corp.
8
SC1155
PRELIMINARY
POWER MANAGEMENT
Pin Descriptions (Cont.)
Pin #
14
Pin Name
DRV
Pin Function
Drive Regulator for the MOSFET Drivers.
12V Supply. Connect to 12V power rail.
15
VIN12V
BOOT
16
Bootstrap. This pin is used to generate a floating drive for the high side FET driver.
High Side Driver Output. Connect to gate of high side MOSFET.
17
HIGHDR
BOOTLO
HISENSE
18
Bootstrap Low. In desktop applications, this pin connect to DRVGND.
19
High Current Sense. Connected to the drain of the high side FET,or the input side of a
current sense resistor between the input and the high side FET.
20
21
22
LOSENSE
IOUTLO
INHIBIT
Low Current Sense. Connected to the source of the high side FET, or the FET side of a
current sense resistor between the input and the high side FET.
This is the sampling capacitors bottom leg. Voltage on this pin is voltage on the
LOSENSE pin when the high side FET is on.
Inhibit. If this pin is grounded, the MOSFET drivers are disabled. Usually connected to
+5V through a pull-up resistor.
23
24
25
26
27
28
VID4
VID3
Programming Input (MSB)
Programming Input
VID2
Programming Input
VID1
Programming Input
VID0
Programming Input (LSB)
PWRGD
Power Good. This open collector logic output is high if the output voltage is within
5-10% of the set point.
www.semtech.com
2001 Semtech Corp.
9
SC1155
PRELIMINARY
POWER MANAGEMENT
Block Diagram
www.semtech.com
2001 Semtech Corp.
10
SC1155
PRELIMINARY
POWER MANAGEMENT
Output Voltage Table
0 = VSS; 1 = OPEN
VID4
VID3
VID2
VID1
VIDO
VDC
(V)
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
1
0
1
0
1
0
1
0
Output Off
1.1
1.125
1.15
1.175
1.2
1.225
1.250
1.275
1.3
1.325
1.35
1.375
1.4
1.425
1.45
1.475
1.5
1.525
1.55
1.575
1.6
1.625
1.65
1.675
1.7
1.725
1.75
1.775
1.8
1.825
1.85
NOTE:
(1) If the VID bits are set to 11111, then the high-side and the low-side driver outputs will be set low, and the
controller will be set to a low-Iq state.
www.semtech.com
2001 Semtech Corp.
11
SC1155
PRELIMINARY
POWER MANAGEMENT
Applications Information - ꢀunctional Description
diode, connected between the DRV and BOOT pins, is a
Schottky for improved drive efficiency. The maximum
voltage that can be applied between the BOOT pin and
ground is 25V. The driver can be referenced to ground
by connecting BOOTLO to PGND, and connecting +12V
to the BOOT pin.
Reference/Voltage Identification
The reference/voltage identification (VID) section con-
sists of a temperature compensated bandgap reference
and a 5-bit voltage selection network. The 5 VID pins
are TTL compatable inputs to the VID selection network.
They are internally pulled up to +5V generated from the
+12V supply by a resistor divider, and provide program-
mability of output voltage from 1.1V to 1.8V in 25mV
increments.
Deadtime Control
Deadtime control prevents shoot-through current from
flowing through the main power ꢀETs during switching
transitions by actively controlling the turn-on times of the
ꢀET drivers. The high side driver is not allowed to turn on
until the gate drive voltage to the low-side ꢀET is below 2
volts, and the low side driver is not allowed to turn on
until the voltage at the junction of the 2 ꢀETs (VPHASE) is
below 2 volts. An internal low-pass filter with an 11MHz
pole is located between the output of the low-side driver
(DL) and the input of the deadtime circuit that controls
the high-side driver, to filter out noise that could appear
on DL when the high-side driver turns on.
Refer to the Output Voltage Table for the VID code set-
tings. The output voltage of the VID network, VREꢀ is
within 1% of the nominal setting over the full input and
output voltage range and junction temperature range.
The output of the reference/VID network is indirectly
brought out through a buffer to the REꢀB pin. The volt-
age on this pin will be within 3mV of VREꢀ. It is not rec-
ommended to drive loads with REꢀB other than setting
the hysteresis of the hysteretic comparator, because the
current drawn from REꢀB sets the charging current for
the soft start capacitor. Refer to the soft start section
for additional information.
Current Sensing
Hysteretic Comparator
Current sensing is achieved by sampling and holding the
voltage across the high side ꢀET while it is turned on.
The sampling network consists of an internal 50Ω switch
and an external 0.1µꢀ hold capacitor. Internal logic con-
trols the turn-on and turn-off of the sample/hold switch
such that the switch does not turn on until VPHASE tran-
sitions high and turns off when the input to the high side
driver goes low. Thus sampling will occur only when the
high side ꢀET is conducting current. The voltage at the
IO pin equals 2 times the sensed voltage. In applica-
tions where a higher accuracy in current sensing is re-
quired, a sense resistor can be placed in series with the
high side ꢀET and the voltage across the sense resistor
can be sampled by the current sensing circuit.
The hysteretic comparator regulates the output voltage
of the synchronous-buck converter. The hysteresis is
set by connecting the center point of a resistor divider
from REꢀB to AGND to the HYST pin. The hysteresis of
the comparator will be equal to twice the voltage differ-
ence between REꢀB and HYST, and has a maximum value
of 60mV. The maximum propagation delay from the com-
parator inputs to the driver outputs is 250ns.
Low Side Driver
The low side driver is designed to drive a low RDS(ON) N-
channel MOSꢀET, and is rated for 2 amps source and
sink. The bias for the low side driver is provided inter-
nally from VDRV.
Droop Compensation
The droop compensation network reduces the load tran-
sient overshoot/undershoot at VOUT, relative to VREꢀ.
VOUT is programmed to a voltage greater than VREꢀ equal
to VREꢀ (1+R7/R8) (see Typ. App. Circuit, Pg 1) by an
external resistor divider from VOUT to the VSENSE pin to
reduce the undershoot on VOUT during a low to high load
current transient. The overshoot during a high to low
load current transient is reduced by subtracting the volt-
High Side Driver
The high side driver is designed to drive a low RDS(ON) N-
channel MOSꢀET, and is rated for 2 amps source and
sink. It can be configured either as a ground referenced
driver or as a floating bootstrap driver. When configured
as a floating driver, the bias voltage to the driver is de-
veloped from the DRV regulator. The internal bootstrap
www.semtech.com
2001 Semtech Corp.
12
SC1155
PRELIMINARY
POWER MANAGEMENT
Applications Information - ꢀunctional Description (Cont.)
age that is on the DROOP pin from VREꢀ. The voltage on value for all VID settings. The soft start charging current
the IO pin is divided down with an external resistor di- is determined by the following equation: ISS = IREꢀB/5.
vider, and connected to the DROOP pin. Thus, under Where IREꢀB is the current flowing out of the REꢀB pin. It
loaded conditions, VOUT is regulated to:
is recommended that no additional loads be connected
to REꢀB, other than the resistor divider for setting the
hysteresis voltage. Thus these resistor values will deter-
mine the soft start charging current. The maximum cur-
rent that can be sourced by REꢀB is 500µA.
VOUT = VREꢀ (1+R7/R8) - IOUT R2/(R1+R2).
Inhibit
The inhibit pin is a TTL compatible digital pin that is used
to enable the controller. When INH is low, the output Power Good
drivers are low, the soft start capacitor is discharged,
the soft start current source is disabled, and the control- The power good circuit monitors for an undervoltage con-
ler is in a low IQ state. When INH goes high, the short dition on VOUT. If VSENSE is 7% (nominal) below VREꢀ,
across the soft start capacitor is removed, the soft start then the power good pin is pulled low. The PWRGD pin is
current source is enabled, and normal converter opera- an open drain output.
tion begins. When the system logic supply is connected
to INH, it controls power sequencing by locking out con- Overvoltage Protection
troller operation until the system logic supply exceeds
the input threshold voltage of the INH circuit; thus the The overvoltage protection circuit monitors VOUT for an
+12V supply and the system logic supply (either +5V or overvoltage condition. If VSENSE is greater then 2.15V
3.3V) must be above UVLO thresholds before the con- (nominal), a fault latch is set and both output drivers are
troller is allowed to start up.
turned off. The latch will remain set until VIN goes below
the undervoltage lockout value. A 1ms deglitch timer is
included for noise immunity.
VIN
The VIN undervoltage lockout circuit disables the con- Overcurrent Protection
troller while the +12V supply is below the 10V start
threshold during power-up. While the controller is dis- The overcurrent protection circuit monitors the current
abled, the output drivers will be low, the soft start ca- through the high side ꢀET. The overcurrent threshold is
pacitor will be shorted and the soft start current is dis- adjustable with an external resistor divider between IO
abled and the controller will be in a low IQ state. When and AGND, with the divider voltage connected to the OCP
VIN exceeds the start threshold, the short across the pin. If the voltage on the OCP pin exceeds 100mV, then
soft start capacitor is removed, the soft start current a fault latch is set and the output drivers are turned off.
source is enabled and normal converter operation be- The latch will remain set until VIN goes below the
gins. There is a 2V hysteresis in the undervoltage lock- undervoltage lockout value. A 1ms deglitch timer is in-
out circuit for noise immunity.
cluded for noise immunity. The OCP circuit is also de-
signed to protect the high side ꢀET against a short-to-
ground fault on the terminal common to both power ꢀETs
(VPHASE).
Soft Start
The soft start circuit controls the rate at which VOUT pow-
ers up. A capacitor is connected between SS and AGND Drive Regulator
and is charged by an internal current source. The value
of the current source is proportional to the reference The drive regulator provides drive voltage to the low side
voltage so the charging rate of CSS is also proportional to driver, and to the high side driver when the high side
the reference voltage. By making the charging current driver is configured as a floating driver. The minimum
proportional to VREꢀ, the power-up time for VOUT will be drive voltage is 7V. The minimum short circuit current is
independent of VREꢀ. Thus, CSS can remain the same 100mA.
www.semtech.com
2001 Semtech Corp.
13
SC1155
PRELIMINARY
POWER MANAGEMENT
Application Circuit
www.semtech.com
2001 Semtech Corp.
14
SC1155
PRELIMINARY
POWER MANAGEMENT
Typical Characteristics
V
= 5V; I
= 0A to 40A
OUT
IN
Droop & Offset Disabled
V
V
V
= 1.8 V
OUT
100%
90%
80%
70%
60%
50%
40%
30%
20%
10%
0%
3%
2%
1%
0%
-1%
-2%
-3%
0
5
10
15
20
25
30
35
40
0
5
10
15
20
25
30
35
40
Current, A
Current, A
= 1.5V
OUT
3%
2%
100%
90%
80%
70%
60%
50%
40%
30%
20%
10%
0%
1%
0%
-1%
-2%
-3%
0
5
10
15
20
25
30
35
40
0
5
10
15
20
25
30
35
40
Current, A
Current, A
= 1.1V
OUT
3%
2%
100%
90%
80%
70%
60%
50%
40%
30%
20%
10%
0%
1%
0%
-1%
-2%
-3%
0
5
10
15
20
25
30
35
40
0
5
10
15
20
25
30
35
40
Current, A
Current, A
www.semtech.com
2001 Semtech Corp.
15
SC1155
PRELIMINARY
POWER MANAGEMENT
Typical Characteristics
V
= 12V; I
= 0A to 40A
OUT
IN
Droop & Offset Disabled
V
= 1.8 V
OUT
100%
90%
80%
70%
60%
50%
40%
30%
20%
10%
0%
3%
2%
1%
0%
-1%
-2%
-3%
0
5
10
15
20
25
30
35
40
0
5
10
15
20
25
30
35
40
Current, A
Current, A
V
= 1.5V
OUT
100%
90%
80%
70%
60%
50%
40%
30%
20%
10%
0%
3%
2%
1%
0%
-1%
-2%
-3%
0
5
10
15
20
25
30
35
40
0
5
10
15
20
25
30
35
40
Current, A
Current, A
V
= 1.1V
OUT
100%
90%
80%
70%
60%
50%
40%
30%
20%
10%
0%
3%
2%
1%
0%
-1%
-2%
-3%
0
5
10
15
20
25
30
35
40
0
5
10
15
20
25
30
35
40
Current, A
Current, A
www.semtech.com
2001 Semtech Corp.
16
SC1155
PRELIMINARY
POWER MANAGEMENT
Evaluation Board Artwork
Top Layer
Bottom Layer
Mid Layer
www.semtech.com
2001 Semtech Corp.
17
SC1155
PRELIMINARY
POWER MANAGEMENT
Evaluation Board Artwork (Cont.)
Top Overlay
Bottom Overlay
www.semtech.com
2001 Semtech Corp.
18
SC1155
PRELIMINARY
POWER MANAGEMENT
Materials List
Quantity Reference
Part/Description
0.001µF
0.1µF
Vendor
3
6
C1,C2,C5
TDK, Murata, Taiyo-Yuden
C3,C4,C6,C7,C9,C10
any
any
any
any
any
1
C11
0.033µF
22µF
1
C12
11
2
C13, C15-C23, C59
1µF
C8,C14
C24 - C32
C37 - C46
C47 - C58
C33 - C36
D1
2.2µF
9
820µF, 16V
SANYO P/N: 16MV820AX
10
12
4
1500µF, 6.3V, thru hole SANYO P/N: 6R3MV1500AX
10µF
any
.0022µF
any
1
MBRA130L. Schottky
ON Semi
1
D2 (optional)
L1
MBRB2515L
ON Semi
1
0.5uH, Toroid
Micrometals P/N: T51-26C, 18 AWG
1
L2
1.0uH, Toroid
Magnetics, #77310, 3ts, 4 X 20 AWG
2
Q1,Q2
Q3,Q4
R1
D2Pak, MOSFET
Fairchild P/N: FDB6035AL
2
D2Pak, MOSFET
Fairchild P/N: FDB7030BL
1
2k
any
4
R2,R4,R11,R12
R3
1k
any
1
4.3k
any
1
R5
68.1
any
1
R6
20k
any
1
R7
100
any
2
R8,R10
R9
10k
any
1
150
any
2
R20,R21
R22,R23
R24,R25,R26,R27
U1
1
any
2
1.6
3.3
any
4
any
1
SC1155CSW.TR
Semtech Corp. 805-498-2111
www.semtech.com
2001 Semtech Corp.
19
SC1155
PRELIMINARY
POWER MANAGEMENT
Layout Guidelines (See pg. 1)
10. If Schottky diode used in parallel with a synchronous
(bottom) FET, to achieve a greater efficiency at lower Vout
settings, it needs to be placed next to the aforementioned
FET in very close proximity.
11. Since the feedback path relies on the accurate sampling
of the output ripple voltage, the best results can be achieved
by connecting the AGND to the ground side of the bulk
output capacitors.
12. DRVGND pin should be tight to the main ground plane
utilizing very low impedance connection, e.g., multiple vias.
13. In order to prevent substrate glitching, a small (0.5A)
Schottky diode should be placed in close proximity to the
chip with the cathode connected to BOOTLO and anode
connected to DRVGND.
1. Locate R8 and C2 close to pins 6 and 7.
2. Locate C1 close to pins 5 and 7.
3. Components connected to IOUT, DROOP, OCP, VHYST,
VREFB, VSENSE, and SOFTST should be referenced to
AGND.
4. The bypass capacitors C5 and C10 should be placed
close to the IC and referenced to DRVGND.
5. Locate bootstrap capacitor C8 close to the IC.
6. Place bypass capacitor close to Drain of the top FET and
Source of the bottom FET to be effective.
7. Route HISENSE and LOSENSE close to each other to
minimize induced differential mode noise.
8. Bypass a high frequency disturbance with ceramic
capacitor at the point where HISENSE is connected to Vin.
9. Input bulk capacitors should placed as close as possible
to the power FETs because of the very high ripple current
flow in this pass.
Outline Drawing - SO-28
Contact Information
Semtech Corporation
Power Management Products Division
652 Mitchell Rd., Newbury Park, CA 91320
Phone: (805)498-2111 ꢀAX (805)498-3804
www.semtech.com
2001 Semtech Corp.
20
相关型号：
SC1157CST
Switching Controller, Voltage-mode, 155kHz Switching Freq-Max, PDSO16, MS-012AC, SOIC-16
SEMTECH
SC1157CSTR
Switching Controller, Voltage-mode, 155kHz Switching Freq-Max, BIPolar, PDSO16, MS-012AC, SOIC-16
SEMTECH
SC1157CSTRT
Switching Controller, Voltage-mode, 155kHz Switching Freq-Max, PDSO16, MS-012AC, SOIC-16
SEMTECH
©2020 ICPDF网 联系我们和版权申明