SC1186CSW.TR [SEMTECH]
Switching Controller, Voltage-mode, 1A, 160kHz Switching Freq-Max, PDSO24, MS-013AD, SOIC-24;
| 型号： | SC1186CSW.TR |
| 厂家： | 
SEMTECH CORPORATION |
| 描述： | Switching Controller, Voltage-mode, 1A, 160kHz Switching Freq-Max, PDSO24, MS-013AD, SOIC-24 开关 光电二极管 |
| 文件： | 总15页 (文件大小：269K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SC1186
Programmable Synchronous DC/DC
Converter, Dual LDO Controller
POWER MANAGEMENT
Features
Description
The SC1186 combines a synchronous voltage mode
controller with two low-dropout linear regulators
providing most of the circuitry necessary to implement three
DC/DC converters for powering advanced microprocessors
such as Pentium® II & III.
Synchronous design, enables no heatsink solution
95% efficiency (switching section)
5 bit DAC for output programmability
Designed for Intel Pentium® ll & III requirements
1.5V, 2.5V short circuit protected linear controllers
1.265V ± 1.5% Reference available
The SC1186 switching section features an integrated 5
bit D/A converter, latched drive output for enhanced noise
immunity, pulse by pulse current limiting and logic
compatible shutdown. The SC1186 switching section
operates at a fixed frequency of 140kHz, providing an op-
timum compromise between size, efficiency and cost in
the intended application areas. The integrated D/A con-
verter provides programmability of output voltage from 2.0V
to 3.5V in 100mV increments and 1.30V to 2.05V in
50mV increments with no external components.
Applications
Pentium® ll & III microprocessor supplies
Flexible motherboards
1.3V to 3.5V microprocessor supplies
Programmable triple power supplies
The SC1186 linear sections are low dropout regulators
with short circuit protection, supplying 1.5V for GTL bus
and 2.5V for non-GTL I/O. The Reference voltage is made
available for external linear regulators.
Typical Application Circuit
12V
+
0.1uF
47uF
5V
+
1500uF
x4
10
5
7
9
VCC
CS+
CS-
0.1uF
8
LDOEN
VID0
0.1uF
0.1uF
VID0
VID1
VID2
VID3
VID4
EN
22
21
20
19
18
16
1
17
15
11
14
13
10
12
6
IRLR3103N
2R2
1.00k
2.32k
VOSENSE
BSTH
DH
VID1
5mOhm
VCC_CORE
VID2
1.9uH
IRLR3103N
2R2
VID3
BSTL
VID4
DL
+
0.1uF
EN
PGNDH
PGNDL
REF
1500uF
x6
AGND
LDOV
GATE2
LDOS2
23
24
4
1k
1
2
12V
3.3V
GATE1
LDOS1
3
8
+
SC1186CS
3
2
3.3V
+
IRLR024N
VLIN3
-
LM358
4
1.5V
2.5V
330uF
IRLR024N
+
IRLR024N
330uF
+
+
330uF
330uF
1
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Revision: December 2, 2004
SC1186
POWER MANAGEMENT
Absolute Maximum Ratings
Exceeding the specifications below may result in permanent damage to the device, or device malfunction. Operation outside of the parameters specified
in the Electrical Characteristics section is not implied. Exposure to Absolute Maximum rated conditions for extended periods of time may affect device
reliability.
Parameter
Symbol
Maximum
Units
VCC to AGND
VIN
-0.3 to +7
±1
V
V
PGNDH, PGNDL to AGND
BSTH to PGNDH, BSTL to PGNDL
DH to PGNDH, DL to PGNDL (Note2)
Operating Temperature Range
Junction Temperature Range
-0.3 to +15
-1 to +15
0 to +70
0 to +125
-65 to +150
300
V
V
TA
TJ
°C
°C
Storage Temperature Range
TSTG
TLEAD
θJA
°C
Lead Temperature (Soldering) 10 Sec.
Thermal Resistance Junction to Ambient
Thermal Impedance Junction to Case
°C
80
°C/W
°C/W
25
θJC
Electrical Characteristics
Unless specified: VCC = 4.75V to 5.25V; GND = PGND = 0V; VOSENSE = VO; 0mV < (CS+-CS-) < 60mV; LDOV = BST = 11.4V to 12.6V; TA = 0 to 70°C
Parameter
Conditions
Min
Typ
Max
Units
Switching Section
Output Voltage
IO = 2A in Application Circuit
VCC
See Output Voltage Table
7
Supply Voltage
4.5
V
Supply Current
VCC = 5.0V
8
1
15
mA
%
Load Regulation
IO = 0.8A to 15A
Line Regulation
±0.5
70
%
Current Limit Voltage
Oscillator Frequency
Oscillator Max Duty Cycle
Peak DH Sink/Source Current
60
120
90
85
mV
kHz
%
140
95
160
BSTH - DH = 4.5V, DH- PGNDH = 3.3V
DH- PGNDH = 1.5V
1
A
100
mA
Peak DL Sink/Source Current
BSTL - DL = 4.5V, DL - PGNDL= 3.3V
DL- PGNDH = 1.5V
1
A
100
mA
Gain (AOL)
VOSENSE to VO
VIDx < 2.4V
VIDx = 5V
35
10
dB
uA
uA
%
VID Source Current
VID Leakage
1
10
Power good threshold voltage
Dead Time
88
40
112
100
ns
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2004 Semtech Corp.
2
SC1186
POWER MANAGEMENT
Electrical Characteristics (Cont.)
Unless specified: VCC = 4.75V to 5.25V; GND = PGND = 0V; VOSENSE = VO; 0mV < (CS+-CS-) < 60mV; LDOV = BST = 11.4V to 12.6V; TA = 0 to 70°C
Parameter
Conditions
Min
Typ
Max
Units
Linear Sections
Quiescent Current
Output Voltage LDO1
LDOV = 12V
5
mA
V
2.493
1.496
1.246
2.525
2.556
1.534
1.284
Output Voltage LDO2
Reference Voltage
Gain (AOL)
1.515
1.265
90
V
V
Iref < 100uA
LDOS (1,2) to GATE (1,2)
IO = 0 to 8A
dB
%
%
kΩ
V
Load Regulation
0.3
0.3
1.5
10
Line Regulation
Output Impedance
LDOV Undervoltage Lockout
LDOEN Threshold
LDOEN Sink Current
VGATE = 6.5V
1
6.5
1.3
8.0
1.9
V
LDOEN = 3.3V
LDOEN = 0V
0.01
-200
1.0
µA
µA
-300
Overcurrent Trip Voltage
% of Vo set point
20
1
40
5
60
60
%
Power-up Output Short Circuit Immunity
Output Short Circuit Glitch Immunity
Gate Pulldown Impedance
ms
ms
kΩ
0.5
80
4
20
GATE (1,2) -AGND;
VCC+BST=0V
300
750
VOSENSE Impedance
10
kΩ
Note:
(1) This device is ESD sensitive. Use of standard ESD handling precautions is required.
(2) See Gate Resistor Selection recomendations.
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2004 Semtech Corp.
3
SC1186
POWER MANAGEMENT
Ordering Information
Pin Configuration
Device (1)
Package(1)
Linear
Temp
TOP VIEW
Voltage
Range (TJ)
AGND
GATE1
LDOS1
LDOS2
VCC
REF
LDOEN
CS-
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
16
15
14
13
GATE2
LDOV
VID0
VID1
VID2
SC1186CSW.TR
SC1186CSWTRT(2)
SO-24
1.5V/2.5V 0° to 125°C
VID3
VID4
Notes:
(1) Only available in tape and reel packaging. A reel
contains 1000 devices.
VOSENSE
EN
BSTH
BSTL
DL
CS+
PGNDH
DH
9
(2) Lead free product. This product is fully WEEE and
RoHS compliant.
10
11
12
PGNDL
(24 Pin SOIC)
Pin Descriptions
Pin #
1
2
3
4
Pin Name
Pin Function
AGND
GATE1
LDOS1
LDOS2
VCC
Small Signal Analog and Digital Ground
Gate Drive Output LDO1
Sense Input for LDO1
Sense Input for LDO2
Input Voltage
5
6
7
8
9
REF
LDOEN
CS-
CS+
PGNDH
DH
PGNDL
DL
BSTL
Buffered Reference Voltage output
LDO Supply Monitor.
Current Sense Input (negative)
Current Sense Input (positive)
Power Ground for High Side Switch
High Side Driver Output
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Power Ground for Low Side Switch
Low Side Driver Output
Supply for Low Side Driver
Supply for High Side Driver
Logic low shuts down the converter, High or open for normal operation
Top end of internal feedback chain.
Programming Input (MSB)
Programming Input
Programming Input
Programming Input
Programming Input (LSB)
+12V for LDO section
Gate Drive Output LDO2
BSTH
EN(1)
VOSENSE
(1)
VID4
VID3 (1)
VID2 (1)
VID1 (1)
VID0 (1)
LDOV
GATE2
Note:
(1) All logic level inputs and outputs are open collector TTL compatible.
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2004 Semtech Corp.
4
SC1186
POWER MANAGEMENT
Block Diagram
VCC
CS- CS+
70mV
EN
CURRENT
LIMIT
BSTH
DH
REF
D/A
+
-
VID4
VID3
VID2
VID1
VID0
LEVEL SHIFT AND
HIGH SIDE DRIVE
+
-
-
+
ERROR
AMP
PGNDH
VOSENSE
AGND
R
S
SHOOT-THRU
CONTROL
Q
OSCILLATOR
BSTL
DL
LDOEN
LDOS1
GATE1
2.5V FET
1.5V FET
SYNCHRONOUS
MOSFET DRIVE
CONTROLLER
CONTROLLER
1.275V
REF
PGNDL
LDOV
REF
GATE2 LDOS2
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2004 Semtech Corp.
5
SC1186
POWER MANAGEMENT
Applications Information - Output Voltage Table
Unless specified: 4.75V < VCC < 5.25V; GND = PGND = 0V; VOSENSE = VO; 0mV < (CS+-CS-) < 60mV; = 0°C < Tj < 85°C
Parameter
Conditions
Vid
Min
Typ
Max
Units
43210
Output Voltage (1) IO = 2A in Application circuit (Figure 1)
01111
01110
01101
01100
01011
01010
01001
01000
00111
00110
00101
00100
00011
00010
00001
00000
11111
11110
11101
11100
11011
11010
11001
11000
10111
10110
10101
10100
10011
10010
10001
10000
1.277
1.326
1.375
1.424
1.478
1.527
1.576
1.625
1.675
1.724
1.782
1.832
1.881
1.931
1.980
2.030
1.970
2.069
2.167
2.266
2.364
2.463
2.561
2.660
2.758
2.842
2.940
3.038
3.136
3.234
3.332
3.430
1.300
1.350
1.400
1.450
1.500
1.550
1.600
1.650
1.700
1.750
1.800
1.850
1.900
1.950
2.000
2.050
2.000
2.100
2.200
2.300
2.400
2.500
2.600
2.700
2.800
2.900
3.000
3.100
3.200
3.300
3.400
3.500
1.323
1.374
1.425
1.476
1.523
1.573
1.624
1.675
1.726
1.776
1.818
1.869
1.919
1.970
2.020
2.071
2.030
2.132
2.233
2.335
2.436
2.538
2.639
2.741
2.842
2.958
3.060
3.162
3.264
3.366
3.468
3.570
V
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2004 Semtech Corp.
6
SC1186
POWER MANAGEMENT
Layout Guidelines
Careful attention to layout requirements are necessary for transition switching. Connections should be as wide and
successful implementation of the SC1186 PWM control- as short as possible to minimize loop inductance. Mini-
ler. High currents switching at 140kHz are present in the mizing this loop area will a) reduce EMI, b) lower ground
application and their effect on ground plane voltage differ- injection currents, resulting in electrically “cleaner” grounds
entials must be understood and minimized.
for the rest of the system and c) minimize source ringing,
1). The high power parts of the circuit should be laid out resulting in more reliable gate switching signals.
first. A ground plane should be used, the number and 3). The connection between the junction of Q1, Q2 and
position of ground plane interruptions should be such as the output inductor should be a wide trace or copper re-
to not unnecessarily compromise ground plane integrity. gion. It should be as short as practical. Since this connec-
Isolated or semi-isolated areas of the ground plane may tion has fast voltage transitions, keeping this connection
be deliberately introduced to constrain ground currents to short will minimize EMI. The connection between the out-
particular areas, for example the input capacitor and bot- put inductor and the sense resistor should be a wide trace
tom FET ground.
or copper area, there are no fast voltage or current transi-
2). The loop formed by the Input Capacitor(s) (Cin), the Top tions in this connection and length is not so important,
FET (Q1) and the Bottom FET (Q2) must be kept as small however adding unnecessary impedance will reduce effi-
as possible. This loop contains all the high current, fast ciency.
12V IN
5V
10
1
2
24
AGND
GATE1
LDOS1
LDOS2
VCC
GATE2
LDOV
VID0
23
22
21
20
19
18
17
16
15
14
13
2.32k
3
Cin
+
4
Q1
Q2
1.00k
VID1
0.1uF
0.1uF
5
5mOhm
VID2
Vout
6
REF
VID3
L
+
7
LDOEN
CS-
VID4
Cout
8
VOSENSE
EN
9
CS+
10
11
12
PGNDH
DH
BSTH
BSTL
DL
PGNDL
SC1186
Heavy lines indicate
high current paths.
3.3V
Vo Lin1
Q3
+
+
Cout Lin1
Cin Lin
Layout Diagram
SC1186
Vo Lin2
Q4
+
Cout Lin2
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7
SC1186
POWER MANAGEMENT
Layout Guidelines (Cont.)
4) The Output Capacitor(s) (Cout) should be located as 6) Vcc for the SC1186 should be supplied from the 5V
close to the load as possible, fast transient load currents supply through a 10Ω resistor, the Vcc pin should be
are supplied by Cout only, and connections between Cout decoupled directly to AGND by a 0.1µF ceramic capacitor,
and the load must be short, wide copper areas to mini- trace lengths should be as short as possible.
mize inductance and resistance.
7) The Current Sense resistor and the divider across it
5) The SC1186 is best placed over a quiet ground plane should form as small a loop as possible, the traces run-
area, avoid pulse currents in the Cin, Q1, Q2 loop flowing ning back to CS+ and CS- on the SC1186 should run par-
in this area. PGNDH and PGNDL should be returned to allel and close to each other. The 0.1µF capacitor should
the ground plane close to the package. The AGND pin be mounted as close to the CS+ and CS- pins as possible.
should be connected to the ground side of (one of) the 8) Ideally, the grounds for the two LDO sections should be
output capacitor(s). If this is not possible, the AGND pin returned to the ground side of (one of) the output
may be connected to the ground path between the Output capacitor(s).
Capacitor(s) and the Cin, Q1, Q2 loop. Under no circum-
stances should AGND be returned to a ground inside the
Cin, Q1, Q2 loop.
5V
Currents in Power Section
+
Vout
+
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8
SC1186
POWER MANAGEMENT
Component Selection
SWITCHING SECTION
The calculated maximum inductor value assumes 100%
OUTPUT CAPACITORS - Selection begins with the most and 0% duty cycle capability, so some allowance must be
critical component. Because of fast transient load current made. Choosing an inductor value of 50 to 75% of the
requirements in modern microprocessor core supplies, the calculated maximum will guarantee that the inductor cur-
output capacitors must supply all transient load current rent will ramp fast enough to reduce the voltage dropped
requirements until the current in the output inductor ramps across the ESR at a faster rate than the capacitor sags,
up to the new level. Output capacitor ESR is therefore one hence ensuring a good recovery from transient with no
of the most important criteria. The maximum ESR can be additional excursions.
simply calculated from:
We must also be concerned with ripple current in the out-
put inductor and a general rule of thumb has been to
allow 10% of maximum output current as ripple current.
Note that most of the output voltage ripple is produced by
the inductor ripple current flowing in the output capacitor
ESR. Ripple current can be calculated from:
Vt
It
RESR
≤
Where
Vt = Maximum transient voltage excursion
It = Transient current step
V
IN
IL
=
RIPPLE
4 L fOSC
For example, to meet a 100mV transient limit with a 10A
load step, the output capacitor ESR must be less than
10mΩ. To meet this kind of ESR level, there are three
available capacitor technologies.
Ripple current allowance will define the minimum permit-
ted inductor value.
POWER FETS - The FETs are chosen based on several
criteria, with probably the most important being power
dissipation and power handling capability.
TOP FET - The power dissipation in the top FET is a com-
bination of conduction losses, switching losses and bot-
tom FET body diode recovery losses.
Each Cap.
ESR
Total
ESR
Qty.
Technology
C
C
Rqd.
(µF) (mΩ)
(µF) (mΩ)
Low ESR Tantalum
OS-CON
330
330
60
25
44
6
3
5
2000
990
10
8.3
8.3
a) Conduction losses are simply calculated as:
PCOND = IO2 RDS(on)
δ
Low ESR Aluminum
1500
7500
where
VO
The choice of which to use is simply a cost/performance
issue, with Low ESR Aluminum being the cheapest, but
taking up the most space.
δ = duty cycle ≈
V
IN
b) Switching losses can be estimated by assuming a switch-
ing time, if we assume 100ns then:
INDUCTOR - Having decided on a suitable type and value
of output capacitor, the maximum allowable value of in-
ductor can be calculated. Too large an inductor will pro-
duce a slow current ramp rate and will cause the output
capacitor to supply more of the transient load current for
longer - leading to an output voltage sag below the ESR
excursion calculated above.
−2
PSW = IO
V
10
IN
or more generally,
IO
=
V
(tr + tf ) fOSC
4
IN
PSW
c) Body diode recovery losses are more difficult to esti-
mate, but to a first approximation, it is reasonable to as-
sume that the stored charge on the bottom FET body di-
ode will be moved through the top FET as it starts to turn
on. The resulting power dissipation in the top FET will be:
The maximum inductor value may be calculated from:
RESR
It
C
L ≤
VA
where VA is thelesser of VO or V − VO
( )
IN
PRR = QRR
V
fOSC
IN
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9
SC1186
POWER MANAGEMENT
Component Selection (Cont.)
To a first order approximation, it is convenient to only
consider conduction losses to determine FET suitability.
For a 5V in; 2.8V out at 14.2A requirement, typical FET
losses would be:
INPUT CAPACITORS - since the RMS ripple current in the
input capacitors may be as high as 50% of the output
current, suitable capacitors must be chosen accordingly.
Also, during fast load transients, there may be restric-
tions on input di/dt. These restrictions require useable
energy storage within the converter circuitry, either as
extra output capacitance or, more usually, additional in-
put capacitors. Choosing low ESR input capacitors will
help maximize ripple rating for a given size.
Using 1.5X Room temp RDS(ON) to allow for temperature rise.
FET type
IRL34025
IRL2203
Si4410
RDS(on) (mΩ) PD (W)
Package
D2Pak
D2Pak
S0-8
15
1.69
1.19
2.26
10.5
20
GATE RESISTOR SELECTION - The gate resistors for the
top and bottom switching FETs limit the peak gate current
and hence control the transition time. It is important to
control the off time transition of the top FET, it should be
fast to limit switching losses, but not so fast as to cause
excessive phase node oscillation below ground as this can
lead to current injection in the IC substrate and erratic
behaviour or latchup. The actual value should be deter-
mined in the application, with the final layout and FETs.
BOTTOM FET - Bottom FET losses are almost entirely
due to conduction. The body diode is forced into conduc-
tion at the beginning and end of the bottom switch con-
duction period, so when the FET turns on and off, there
is very little voltage across it, resulting in low switching
losses. Conduction losses for the FET can be determined
by:
PCOND = IO2 RDS(on) (1− δ)
SHORT CIRCUIT PROTECTION - LINEARS
The Short circuit feature on the linear controllers is imple-
mented by using the Rds(on) of the FETs. As output cur-
rent increases, the regulation loop maintains the output
voltage by turning the FET on more and more. Eventually,
as the Rds(on) limit is reached, the FET will be unably to
turn on more fully, and output voltage will start to fall.
When the output voltage falls to approximately 40% of
nominal, the LDO controller is latched off, setting output
voltage to 0. Power must be cycled to reset the latch.
To prevent false latching due to capacitor inrush currents
or low supply rails, the current limit latch is initially dis-
abled. It is enabled at a preset time (nominally 2ms) after
both the LDOV and LDOEN pins rise above their lockout
points.
To be most effective, the linear FET Rds(on) should not be
selected artificially low, the FET should be chosen so that,
at maximum required current, it is almost fully turned on.
If, for example, a linear supply of 1.5V at 4A is required
from a 3.3V ± 5% rail, max allowable Rds(on) would be.
Rds(on)max = (0.95*3.3-1.5)/4 » 400mΩ
For the example above:
FET type
IRL34025
IRL2203
Si4410
RDS(on) (mΩ) PD (W)
Package
D2Pak
D2Pak
S0-8
15
1.33
0.93
1.77
10.5
20
Each of the package types has a characteristic thermal
impedance. For the surface mount packages on double
sided FR4, 2 oz printed circuit board material, thermal
impedances of 40oC/W for the D2PAK and 80oC/W for the
SO-8 are readily achievable. The corresponding tempera-
ture rise is detailed below:
Temperature Rise (OC)
FET type
IRL34025
IRL2203
Si4410
Top FET
67.6
Bottom FET
53.2
To allow for temperature effects 200mΩ would be a suit-
able room temperature maximum, allowing a peak short
circuit current of approximately 15A for a short time be-
fore shutdown.
47.6
37.2
180.8
141.6
It is apparent that single SO-8 Si4410 are not adequate
for this application, but by using parallel pairs in each
position, power dissipation will be approximately halved
and temperature rise reduced by a factor of 4.
2004 Semtech Corp.
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10
SC1186
POWER MANAGEMENT
Theory of Operation (Linear OCP)
The Linear controllers in the SC1186 have built in
Overcurrent Protection (OCP). An overcurrent is assumed
to have occured when the external FET is turned fully on
and the output currrent is RDS(ON) limited, this is detected
by the gate voltage going very high while the output volt-
age is below approximately 40% of it’s setpoint. To allow
for capacitor charging and very short overcurrent dura-
tions, the gate voltage is ramped very slowly upwards when-
ever the output voltage is below the OCP threshold. To
guarantee that the LDO output voltage is capable of reach-
ing it’s setpoint, the gate drive is disabled until both LDOV
Undervoltage Lockout (UVLO) and LDOEN Threshold val-
ues are exceeded, ensuring that there is sufficient gate
drive capability and sufficient LDO input voltage capabil-
ity. A block diagram of one LDO controller is shown below.
Gate
Vout
1.4V/us
1V/ms
Vout/2
Time
Startup with no short circuit
If at some later time, a short circuit is applied to the out-
put, the GATEx voltage will ramp up quickly as Vout falls to
try and maintain regulation. Once Vout has fallen to the
OCP threshold, switch S1 will open and the gate will con-
tinue ramping at the 1V/ms rate. If the short is not re-
moved before the GATEx output reaches approximately
LDOV - 0.7V, the GATEx pin will be latched low, disabling
the LDO
12V
LDOV
3.3V
LDOEN
+
-
10pF
C
Short
RAMP
LDOV
LDOV-0.7V
applied
-
1V/ms
-
+
gm
GATEx
LDOSx
+
Gate
VREF
1.3V
R2
Vout
1.26V
SWITCH CLOSED
ON LOW
R
R
Vout
Vout/2
-
+
S1
+
10nA
R1
Time
14uA
AGND
Short circuit after startup
RESET BY
LDOV LOW
S
R
+
-
Q
If the LDO tries to start into a short, the gate ramps at the
1V/ms rate to LDOV - 0.7V, where the GATEx pin will be
latched low.
LDOV-0.7V
LDOV-0.7V
Gate
During a normal start-up, once LDOV and LDOEN have
reached their thresholds, the GATEx pin is released and
CRAMP is charged by 10nA causing the GATEx voltage to
ramp at 10nA/10pF = 1V/ms. Once the GATEx output has
ramped to the external FET threshold, Vout starts to ramp
up, following GATEx. When Vout reaches the OCP thresh-
old, approximately 40% of setpoint, switch S1 is closed
and GATEx ramps up at a much faster rate, followed by
Vout, until Vout reaches setpoint and the loop settles into
steady state regulation.
1V/ms
Time
Startup into short circuit
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2004 Semtech Corp.
11
SC1186
POWER MANAGEMENT
Typical Characteristics
Typical Ripple, Vo=2.0V, Io=10A
Typical Efficiency (Switching section)
96%
PIN9D2% e
88%
84%
Vo=2.8V
Vo=2.0V
Vo=2.5V
80%
76%
0.0
2.0
4.0
6.0
8.0
10.0
12.0
14.0
16.0
Io (Amps)
Transient Response Vo=2.4V, Io=300mA to 15A
2.5V Linear Short circuit output response
www.semtech.com
2004 Semtech Corp.
12
SC1186
POWER MANAGEMENT
Evaluation Board Schematic
www.semtech.com
2004 Semtech Corp.
13
SC1186
POWER MANAGEMENT
Evaluation Board Bill of Materials
Item
1
Qty.
6
Reference
Value
0.1uF
Notes
C1, C4, C5, C10, C13, C28
C2, C3, C6, C7, C8, C9, C18, C19, C20, C21,
C22, C23
Low ESR Sanyo MV-GX or
equivalent
2
12
1500uF
3
8
1
1
3
3
1
1
1
1
4
1
2
1
1
2
1
1
C11, C12, C14, C15, C16, C17, C24, C25
330uF
47uF
4
C27
5
L1
1.9uH
6
Q1, Q2, Q3, Q4
IRLR3103N
IRLR024N
10
7
Q5, Q6, Q7
8
R1
9
R3
EMPTY
1.00k
10
11
12
13
14
15
16
17
18
19
R4
1%
1%
R5
2.32k
R6, R7, R9, R10
2R2
R8
5mOhm
See Table 2
1k
IRC OAR1
R15, R11
R12
R16
0
R17, R18
U1
See Table
SC1186CS
LM358
SEMTECH
U2
www.semtech.com
2004 Semtech Corp.
14
SC1186
POWER MANAGEMENT
Outline Drawing - SO-24
DIMENSIONS
INCHES MILLIMETERS
A
D
E
e
DIM
A
N
MIN NOM MAX MIN NOM MAX
-
-
-
-
-
-
-
-
-
-
.093
.104 2.35
.012 0.10
.100 2.05
.020 0.31
.013 0.20
2.65
0.30
2.55
0.51
0.33
A1 .004
A2 .081
2X E/2
R
b
c
D
.012
.008
.602 .606 .610 15.30 15.40 15.50
E1 .291 .295 .299 7.40 7.50 7.60
E1
E
e
.406 BSC
10.30 BSC
1.27 BSC
.050 BSC
-
-
h
J
.010
.020
.016
.030 0.25
.030 0.50
.041 0.40
0.75
0.75
1.04
-
-
-
-
L
(.041)
(1.04)
L1
N
24
24
1
2
3
ccc
C
-
-
R
.024
0°
.035 0.60
0.90
8°
-
-
2X N/2 TIPS
01
8°
0°
e/2
aaa
.004
.010
.013
0.10
0.25
0.33
B
bbb
ccc
D
h
aaa
SEATING
C
A2
A
h
H
PLANE
bxN
bbb
A1
C
C
A-B D
c
GAGE
J
PLANE
0.25
L
(L1)
01
SEE DETAIL A
DETAIL A
SIDE VIEW
NOTES:
1. CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES).
2. DATUMS -A- AND -B- TO BE DETERMINED AT DATUM PLANE-H-
3. DIMENSIONS "E1" AND "D" DO NOT INCLUDE MOLD FLASH, PROTRUSIONS
OR GATE BURRS.
4. REFERENCE JEDEC STD MS-013, VARIATION AD.
Outline Drawing - SO-24
X
DIMENSIONS
DIM
INCHES
MILLIMETERS
(.362)
.276
.050
.024
.087
.449
(9.20)
7.00
C
G
P
X
Y
Z
(C)
G
Y
Z
1.27
0.60
2.20
11.40
P
NOTES:
1. THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY.
CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR
COMPANY'S MANUFACTURING GUIDELINES ARE MET.
2. REFERENCE IPC-SM-782A, RLP NO. 307A.
Contact Information for Semtech International AG
Taiwan Branch
Korea Branch
Shanghai Office
Tel: 886-2-2748-3380
Fax: 886-2-2748-3390
Semtech Switzerland GmbH
Japan Branch
Tel: 81-3-6408-0950
Fax: 81-3-6408-0951
Tel: 82-2-527-4377
Fax: 82-2-527-4376
Semtech Limited (U.K.)
Semtech France SARL
Semtech Germany GmbH
Tel: 44-1794-527-600
Fax: 44-1794-527-601
Tel: 86-21-6391-0830
Fax: 86-21-6391-0831
Tel: 33-(0)169-28-22-00
Fax: 33-(0)169-28-12-98
Semtech International AG is a wholly-owned subsidiary of
Semtech Corporation, which has its headquarters in the U.S.A.
Tel: 49-(0)8161-140-123
Fax: 49-(0)8161-140-124
www.semtech.com
2004 Semtech Corp.
15
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