SC120SKTRT [SEMTECH]
Low Voltage Synchronous Boost Regulator; 低电压同步升压稳压器
| 型号： | SC120SKTRT |
| 厂家： | 
SEMTECH CORPORATION |
| 描述： | Low Voltage Synchronous Boost Regulator |
| 文件： | 总32页 (文件大小：552K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SC120
Low Voltage Synchronous
Boost Regulator
POWER MANAGEMENT
Features
Description
Input voltage — 0.7V to 4.5V
The SC120 is a high efficiency, low noise, synchronous
step-up DC-DC converter that provides boosted voltage
levels in low-voltage handheld applications. The wide
input voltage range allows use in systems with single
NiMH or alkaline battery cells as well as in systems with
higher voltage battery supplies. It features an internal
1.2A switch and synchronous rectifier to achieve up to
94% efficiency and to eliminate the need for an external
Schottky diode. The output voltage can be set to 3.3V
with internal feedback, or to any voltage within the speci-
fied range using a standard resistor divider.
Minimum input startup voltage — 0.865V
Output voltage — fixed at 3.3V; adjustable from 1.8V
to 5.0V
Peak input current limit — 1.2A
Output current at 3.3 VOUT — 80mA with VIN = 1.0V,
190mA with VIN = 1.5V
Efficiency up to 94%
Internal synchronous rectifier
Switching frequency — 1.2MHz
Automatic power save
Anti-ringing circuit
Operating supply current (measured at OUT) — 50μA
Shutdown current — 0.1μA (typ)
No forward conduction path during shutdown
Available in ultra-thin 1.5 × 2.0 × 0.6 (mm)
MLPD-UT-6 and SOT23-6 packages
Lead-free and halogen-free
The SC120 operates in Pulse Width Modulation (PWM)
mode for moderate to high loads and Power Save Mode
(PSAVE) for improved efficiency under light load condi-
tions. It features anti-ringing circuitry for reduced EMI in
noise sensitive applications. Output disconnect capability
is included to reduce leakage current, improve efficiency,
and eliminate external components sometimes needed to
disconnect the load from the supply during shutdown.
WEEE and RoHS compliant
Applications
Low quiescent current is obtained despite a high 1.2MHz
operating frequency. Small external components and the
space saving MLPD-UT-6, 1.5×2.0×0.6 (mm) package, or
low cost SOT23-6 package, make this device an excellent
choice for small handheld applications that require the
longest possible battery life.
MP3 players
Smart Phones and cellular phones
Palmtop computers and handheld Instruments
PCMCIA cards
Memory cards
Digital cordless phones
Personal medical products
Wireless VoIP phones
Small motors
Typical Application Circuit
L1
IN
LX
Single
Cell
OUT
3.3V
EN
(1.2V)
FB
GND
CIN
COUT
SC120
April 30, 2010
1
© 2010 Semtech Corporation
SC120
Pin Configuration — SOT23
Ordering Information
Device
Package
OUT
4
EN
6
FB
5
SC120ULTRT(1)(2)
SC120SKTRT (1)(2)
MLPD-UT-6 1.5×2
SOT23-6
SC120EVB
Evaluation Board, MLPD-UT-6 version
Evaluation Board, SOT23-6 version
SC120SKEVB
Top View
Notes:
(1) Available in tape and reel only. A reel contains 3,000 devices.
(2) Lead-free packaging, only. Device is WEEE and RoHS compliant,
and halogen-free.
1
2
3
Pin Configuration — MLPD-UT
IN
GND
LX
SOT23; 6 LEAD
θJA = 130°C/W
1
2
3
LX
GND
IN
6
5
4
OUT
FB
TOP VIEW
Marking Information — SOT23
Top View
T
EN
MLPD-UT; 1.5×2, 6 LEAD
θJA = 84°C/W
CP00
Bottom View
Marking Information — MLPD-UT
120
yw
yyww
MLPD-UT; 1.5×2, 6 LEAD
yw = date code
SOT23, 6 LEAD
yyww = date code
2
SC120
Absolute Maximum Ratings
Recommended Operating Conditions
IN, OUT, LX, FB (V) . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +6.0
EN (V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to (VIN + 0.3)
ESD Protection Level(1) (kV) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Ambient Temperature Range (°C). . . . . . . . . . . . -40 to +85
VIN (V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.7 to 4.5
VOUT (V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.8 to 5.0
Thermal Information
Thermal Res. MLPD, Junction-Ambient(2) (°C/W) . . . . . . . 84
Thermal Res., SOT23, Junction -Ambient(2) (°C/W) . . . 130
Maximum Junction Temperature (°C) . . . . . . . . . . . . . . . 150
Storage Temperature Range (°C) . . . . . . . . . . . -65 to +150
Peak IR Reflow Temperature (10s to 30s) (°C) . . . . . . +260
Exceeding the above specifications may result in permanent damage to the device or device malfunction. Operation outside of the parameters
specified in the Electrical Characteristics section is not recommended.
NOTES:
(1) Tested according to JEDEC standard JESD22-A114.
(2) Calculated from package in still air, mounted to 3 x 4.5 (in), 4 layer FR4 PCB with thermal vias under the exposed pad per JESD51 standards.
Electrical Characteristics
Unless otherwise noted VIN = 2.5V, CIN = COUT = 22μF, L1 = 4.7μH, TA = -40 to +85°C. Typical values are at TA = 25°C.
Parameter
Symbol
VIN
Conditions
Min
Typ
Max
Units
V
Input Voltage Range
0.7
4.5
Minimum Startup Voltage
Shutdown Current
VIN-SU
ISHDN
IOUT < 1mA, TA = 0°C to 85°C
TA = 25°C, VEN = 0V
0.865
0.1
50
V
1
μA
μA
MHz
%
Operating Supply Current(1)
Internal Oscillator Frequency
Maximum Duty Cycle
Minimum Duty Cycle
Output Voltage
IQ
In PSAVE mode, non-switching, measured at OUT
fOSC
1.2
90
DMAX
DMIN
15
%
VOUT
VFB = 0V
3.3
V
Adjustable Output Voltage Range
VOUT_RNG
For VIN such that DMIN < D < DMAX
1.8
5.0
1.5
0.1
V
Regulation Feedback Reference Volt-
age Accuracy (Internal or External
Programming)
VReg-Ref
-1.5
%
FB Pin Input Current
Startup Time
IFB
VFB = 1.2V
ꢀA
ms
tSU
1
3
SC120
Electrical Characteristics (continued)
Parameter
Symbol
RDSP
RDSN
ILIM(N)
ILIM(P)-SU
ILXP
Conditions
VOUT = 3.3V
Min
Typ
0.6
Max
Units
Ω
P-Channel ON Resistance
N-Channel ON Resistance
N-Channel Current Limit
P-Channel Startup Current Limit
LX Leakage Current PMOS
LX Leakage Current NMOS
Logic Input High
VOUT = 3.3V
0.5
Ω
VIN = 3.0V
0.9
1.2
A
VIN > VOUT, VEN > VIH
TA = 25°C, VLX = 0V
TA = 25°C, VLX = 3.3V
VIN = 3.0V
150
mA
μA
μA
V
1
1
ILXN
VIH
0.85
-0.2
Logic Input Low
VIL
VIN = 3.0V
0.2
1
V
Logic Input Current High
Logic Input Current Low
IIH
VEN = VIN = 3.0V
VEN = 0V
μA
μA
IIL
NOTES:
(1) Quiescent operating current is drawn from OUT while in regulation. The quiescent operating current projected to IN is approximately
IQ × (VOUT/VIN).
4
SC120
Typical Characteristics — VOUT = 1.8V
Efficiency vs. IOUT (VOUT = 1.8V)
Efficiency vs. IOUT (VOUT = 1.8V)
R1 = 499k , R2 = 1M , L = 4.7 H, TA = 25οC
Ω
Ω
μ
Ω
Ω
μ
R1 = 499k , R2 = 1M , L = 4.7 H, VIN = 1.2V
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
VIN = 1.6V
TA = –40°C
TA = 85°C
VIN = 0.8V
VIN = 1.2V
TA = 25°C
0.1
0.2
0.5
1
2
5
10
20
50
100 200
0.1
0.2
0.5
1
2
5
10
20
50
100 200
IOUT (mA)
IOUT (mA)
Load Regulation (VOUT = 1.8V)
Load Regulation (VOUT = 1.8V)
R1 = 499k , R2 = 1M , L = 4.7 H, TA = 25οC
R1 = 499k , R2 = 1M , L = 4.7 H, VIN = 1.2V
Ω
Ω
μ
Ω
Ω
μ
1.84
1.82
1.8
1.84
1.82
1.8
TA = 85°C
VIN = 1.6V
VIN = 1.2V
1.78
1.78
1.76
TA = –40°C
TA = –40°C
TA = 25°C
TA = 85°C
VIN = 0.8V
1.76
0
50
100
150
200
250
0
50
100
150
200
250
IOUT (mA)
IOUT (mA)
Line Regulation — PSAVE Mode (VOUT = 1.8V)
Line Regulation — PWM Mode (VOUT = 1.8V)
Ω
Ω
μ
Ω
Ω
μ
R1 = 499k , R2 = 1M , L = 4.7 H, IOUT = 35mA
R1 = 499k , R2 = 1M , L = 4.7 H, IOUT = 5mA
1.84
1.82
1.8
1.84
1.82
1.8
TA = 85°C
TA = –40°C
TA = 25°C
TA = –40°C
1.78
1.78
TA = 85°C
TA = 25°C
0.9
1.76
1.76
0.7
0.8
1
1.1
1.2
1.3
1.4
1.5
1.6
0.7
0.8
0.9
1
1.1
1.2
1.3
1.4
1.5
1.6
VIN (V)
VIN (V)
5
SC120
Typical Characteristics — VOUT = 1.8V (continued)
Temperature Regulation — PSAVE Mode (VOUT = 1.8V)
Temperature Regulation — PWM Mode (VOUT = 1.8V)
Ω
Ω
μ
R1 = 499k , R2 = 1M , L = 4.7 H, IOUT = 5mA
Ω
Ω
μ
R1 = 499k , R2 = 1M , L = 4.7 H, IOUT = 35mA
1.84
1.82
1.8
1.84
1.82
1.8
VIN = 1.6V
VIN = 1.2V
VIN = 0.8V
VIN = 1.2V
VIN = 1.6V
1.78
1.76
1.78
1.76
VIN = 0.8V
-50
-25
0
25
50
75
100
-50
-25
0
25
50
75
100
Junction Temperature (oC)
Junction Temperature (oC)
Startup Maximum Load Current vs. VIN (VOUT = 1.8V)
Startup Minimum Load Resistance vs. VIN (VOUT = 1.8V)
Ω
Ω
μ
Ω
Ω
μ
R1 = 499k , R2 = 1M , L = 4.7 H
R1 = 499k , R2 = 1M , L = 4.7 H
50
40
30
20
10
0
160
140
120
100
80
TA = 25°C
TA = –40°C
TA = 85°C
60
TA = –40°C
TA = 85°C
40
20
TA = 25°C
0
0.7
0.8
0.9
1
1.1
1.2
1.3
1.4
1.5
1.6
0.7
0.8
0.9
1
1.1
1.2
1.3
1.4
1.5
1.6
VIN (V)
VIN (V)
Maximum IOUT vs. VIN (VOUT = 1.8V)
Ω
Ω
μ
R1 = 499k , R2 = 1M , L = 4.7 H
350
300
250
200
150
100
50
TA = –40°C
TA = 25°C
TA = 85°C
0
0.7
0.8
0.9
1
1.1
1.2
1.3
1.4
1.5
1.6
VIN (V)
6
SC120
Typical Characteristics — VOUT = 3.3V
Efficiency vs. IOUT (VOUT = 3.3V)
Efficiency vs. IOUT (VOUT = 3.3V)
FB grounded, L = 4.7 H, TA = 25οC
μ
μ
FB grounded, L = 4.7 H, VIN = 2V
100
90
80
70
60
50
40
30
20
10
0
100
TA = –40°C
VIN = 3.0V
90
80
TA = 85°C
70
VIN = 1.0V
60
VIN = 2.0V
50
TA = 25°C
40
30
20
10
0
0.1 0.2
0.5
1
2
5
10
20
50
100 200
0.1 0.2
0.5
1
2
5
10
20
50
100 200
IOUT (mA)
IOUT (mA)
Load Regulation (VOUT = 3.3V)
Load Regulation (VOUT = 3.3V)
FB grounded, L = 4.7 H, TA = 25οC
FB grounded, L = 4.7 H, VIN = 2V
μ
μ
3.4
3.36
3.32
3.28
3.24
3.2
3.4
3.36
3.32
3.28
3.24
3.2
TA = 85°C
VIN = 3.0V
TA = –40°C
TA = –40°C
VIN = 2.0V
TA = 85°C
VIN = 1.0V
TA = 25°C
350 400
0
50
100
150
200
250
300
350
400
0
50
100
150
200
250
300
IOUT (mA)
IOUT (mA)
Line Regulation — PSAVE Mode (VOUT = 3.3V)
FB grounded, L = 4.7 H, IOUT = 5mA
Line Regulation — PWM Mode (VOUT = 3.3V)
μ
FB grounded, L = 4.7 H, IOUT = 75mA
μ
3.4
3.36
3.32
3.28
3.24
3.2
3.4
3.36
3.32
3.28
3.24
3.2
TA = 85°C
TA = –40°C
TA = –40°C
TA = 25°C
TA = 85°C
TA = 25°C
0.6
1
1.4
1.8
2.2
2.6
3
3.4
0.6
1
1.4
1.8
2.2
2.6
3
3.4
VIN (V)
VIN (V)
7
SC120
Typical Characteristics — VOUT = 3.3V (continued)
Temperature Regulation — PSAVE Mode (VOUT = 3.3V)
Temperature Regulation — PWM Mode (VOUT = 3.3V)
μ
μ
FB grounded, L = 4.7 H, IOUT = 5mA
FB grounded, L = 4.7 H, IOUT = 75mA
3.4
3.36
3.32
3.28
3.24
3.2
3.4
3.36
3.32
3.28
3.24
3.2
VIN = 2.0V
VIN = 3.0V
VIN = 3.0V
VIN = 1.0V
VIN = 2.0V
VIN = 1.0V
-50
-25
0
25
50
75
100
-50
-25
0
25
50
75
100
Junction Temperature (oC)
Junction Temperature (oC)
Startup Minimum Load Resistance vs. VIN (VOUT = 3.3V)
Startup Maximum Load Current vs. VIN (VOUT = 3.3V)
μ
μ
FB grounded, L = 4.7 H
FB grounded, L = 4.7 H
90
80
70
60
50
40
30
20
10
0
160
140
120
100
80
TA = 25°C
TA = 85°C
TA = –40°C
TA = –40°C
60
40
TA = 85°C
20
TA = 25°C
0
0.6
1
1.4
1.8
2.2
2.6
3
3.4
0.6
1
1.4
1.8
2.2
2.6
3
3.4
VIN (V)
VIN (V)
Maximum IOUT vs. VIN (VOUT = 3.3V)
μ
FB grounded, L = 4.7 H
500
450
400
350
300
250
200
150
100
50
TA = –40°C
TA = 25°C
TA = 85°C
0
0.6
1
1.4
1.8
2.2
2.6
3
3.4
VIN (V)
8
SC120
Typical Characteristics — VOUT = 4.0V
Efficiency vs. IOUT (VOUT = 4.0V)
Efficiency vs. IOUT (VOUT = 4.0V)
R1 = 931k , R2 = 402k , L = 4.7 H, CFB = 2.2pF, TA = 25οC
Ω
Ω
μ
Ω
Ω
μ
R1 = 931k , R2 = 402k , L = 4.7 H, CFB = 2.2pF, VIN = 2.4V
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
TA = –40°C
VIN = 3.2V
TA = 85°C
VIN = 1.2V
TA = 25°C
VIN = 2.4V
0.1 0.2
0.5
1
2
5
10
20
50
100 200
0.1 0.2
0.5
1
2
5
10
20
50
100 200
IOUT (mA)
IOUT (mA)
Load Regulation (VOUT = 4.0V)
Load Regulation (VOUT = 4.0V)
R1 = 931k , R2 = 402k , L = 4.7 H, CFB = 2.2pF, TA = 25οC
R1 = 931k , R2 = 402k , L = 4.7 H, CFB = 2.2pF, VIN = 2.4V
Ω
Ω
μ
Ω
Ω
μ
4.1
4.05
4
4.1
4.05
4
TA = 85°C
TA = 25°C
VIN = 3.2V
TA = –40°C
TA = 85°C
3.95
3.9
3.95
3.9
VIN = 2.4V
VIN = 1.2V
TA = 25°C
TA = –40°C
3.85
3.85
0
50
100
150
200
250
300
350
400
0
50
100
150
200
250
300
350
400
IOUT (mA)
IOUT (mA)
Line Regulation — PSAVE Mode (VOUT = 4.0V)
R1 = 931k , R2 = 402k , L = 4.7 H, CFB = 2.2pF, IOUT = 5mA
Line Regulation — PWM Mode (VOUT = 4.0V)
R1 = 931k , R2 = 402k , L = 4.7 H, CFB = 2.2pF, IOUT = 75mA
Ω
Ω
μ
Ω
Ω
μ
4.1
4.05
4
4.1
4.05
4
TA = 85°C
TA = –40°C
TA = 25°C
TA = 25°C
TA = 85°C
3.95
3.9
3.95
3.9
TA = –40°C
3.85
3.85
0.6
1
1.4
1.8
2.2
2.6
3
3.4
3.8
0.6
1
1.4
1.8
2.2
2.6
3
3.4
3.8
VIN (V)
VIN (V)
9
SC120
Typical Characteristics — VOUT = 4.0V (continued)
Temperature Regulation — PWM Mode (VOUT = 4.0V)
Temperature Regulation — PSAVE Mode (VOUT = 4.0V)
Ω
Ω
μ
Ω
Ω
μ
R1 = 931k , R2 = 402k , L = 4.7 H, CFB = 2.2pF, IOUT = 75mA
R1 = 931k , R2 = 402k , L = 4.7 H, CFB = 2.2pF, IOUT = 5mA
4.1
4.05
4
4.1
4.05
4
VIN = 3.2V
VIN = 1.2V
VIN = 2.4V
VIN = 3.2V
VIN = 2.4V
3.95
3.9
3.95
3.9
VIN = 1.2V
3.85
3.85
-50
-25
0
25
50
75
100
-50
-25
0
25
50
75
100
Junction Temperature (oC)
Junction Temperature (oC)
Startup Minimum Load Resistance vs. VIN (VOUT = 4.0V)
Startup Maximum Load Current vs. VIN (VOUT = 4.0V)
Ω
Ω
μ
Ω
Ω
μ
R1 = 931k , R2 = 402k , L = 4.7 H, CFB = 2.2pF
R1 = 931k , R2 = 402k , L = 4.7 H, CFB = 2.2pF
100
90
80
70
60
50
40
30
20
10
0
160
140
120
100
80
TA = 25°C
TA = 85°C
TA = –40°C
TA = 25°C
TA = –40°C
60
40
TA = 85°C
20
0
0.6
1
1.4
1.8
2.2
2.6
3
3.4
3.8
0.6
1
1.4
1.8
2.2
2.6
3
3.4
3.8
VIN (V)
VIN (V)
Maximum IOUT vs. VIN (VOUT = 4.0V)
Ω
Ω
μ
R1 = 931k , R2 = 402k , L = 4.7 H, CFB = 2.2pF
500
450
400
350
300
250
200
150
100
50
TA = 25°C
TA = –40°C
TA = 85°C
0
0.6
1
1.4
1.8
2.2
2.6
3
3.4
3.8
VIN (V)
10
SC120
Typical Characteristics — VOUT = 5.0V, Low VIN Range
Efficiency vs. IOUT (VOUT = 5.0V)
Efficiency vs. IOUT (VOUT = 5.0V)
R1 = 931k , R2 = 294k , L = 3.3 H, CFB = 10pF, TA = 25οC
Ω
Ω
μ
Ω
Ω
μ
R1 = 931k , R2 = 294k , L = 3.3 H, CFB = 10pF, VIN = 1.2V
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
VIN = 1.6V
TA = 25°C
TA = –40°C
VIN = 1.2V
VIN = 0.8V
TA = 85°C
TA = –40°C
0.1
0.2
0.5
1
2
5
10
20
50
100
0.1
0.2
0.5
1
2
5
10
20
50
100
IOUT (mA)
IOUT (mA)
Load Regulation (VOUT = 5.0V)
Load Regulation (VOUT = 5.0V)
R1 = 931k , R2 = 294k , L = 3.3 H, CFB = 10pF, TA = 25οC
R1 = 931k , R2 = 294k , L = 3.3 H, CFB = 10pF, VIN = 1.2V
Ω
Ω
μ
Ω
Ω
μ
5.1
5.05
5
5.1
5.05
5
TA = 85°C
VIN = 1.6V
TA = –40°C
VIN = 0.8V
4.95
4.95
TA = –40°C
TA = 85°C
VIN = 1.2V
TA = 25°C
100
4.9
4.9
0
20
40
60
80
100
120
0
20
40
60
IOUT (mA)
80
120
IOUT (mA)
Line Regulation — PWM Mode (VOUT = 5.0V)
Line Regulation — PSAVE Mode (VOUT = 5.0V)
Ω
Ω
μ
R1 = 931k , R2 = 294k , L = 3.3 H, CFB = 10pF, IOUT = 1mA
Ω
Ω
μ
R1 = 931k , R2 = 294k , L = 3.3 H, CFB = 10pF, IOUT = 35mA
5.1
5.05
5
5.1
5.05
5
TA = –40°C
TA = 85°C
TA = 25°C
TA = 85°C
TA = –40°C
4.95
4.95
TA = 25°C
4.9
4.9
0.6
0.8
1
1.2
1.4
1.6
1.8
0.6
0.8
1
1.2
1.4
1.6
1.8
VIN (V)
VIN (V)
11
SC120
Typical Characteristics — VOUT = 5.0V, Low VIN Range (continued)
Temperature Regulation — PWM Mode (VOUT = 5.0V)
Temperature Regulation — PSAVE Mode (VOUT = 5.0V)
Ω
Ω
μ
R1 = 931k , R2 = 294k , L = 3.3 H, CFB = 10pF, IOUT = 1mA
Ω
Ω
μ
R1 = 931k , R2 = 294k , L = 3.3 H, CFB = 10pF, IOUT = 35mA
5.1
5.05
5
5.1
5.05
5
VIN = 1.6V
VIN = 0.8V
VIN = 1.2V
VIN = 1.6V
VIN = 1.2V
VIN = 0.8V
4.95
4.95
4.9
4.9
-50
-25
0
25
50
75
100
-50
-25
0
25
50
75
100
Junction Temperature (oC)
Junction Temperature (oC)
See page 16 for all VOUT = 5.0V operation and startup load data.
12
SC120
Typical Characteristics — VOUT = 5.0V, Mid VIN Range
Efficiency vs. IOUT (VOUT = 5.0V)
Efficiency vs. IOUT (VOUT = 5.0V)
R1 = 931k , R2 = 294k , L = 4.7 H, CFB = 2.2pF, TA = 25οC
Ω
Ω
μ
Ω
Ω
μ
R1 = 931k , R2 = 294k , L = 4.7 H, CFB = 2.2pF, VIN = 2.4V
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
VIN = 3.2V
TA = –40°C
TA = 85°C
TA = 25°C
VIN = 1.6V
VIN = 2.4V
0.1
0.2
0.5
1
2
5
10
20
50
100 200
0.1
0.2
0.5
1
2
5
10
20
50
100 200
IOUT (mA)
IOUT (mA)
Load Regulation (VOUT = 5.0V)
Load Regulation (VOUT = 5.0V)
R1 = 931k , R2 = 294k , L = 4.7 H, CFB = 2.2pF, TA = 25οC
R1 = 931k , R2 = 294k , L = 4.7 H, CFB = 2.2pF, VIN = 2.4V
Ω
Ω
μ
Ω
Ω
μ
5.1
5.05
5
5.1
5.05
5
TA = 85°C
TA = –40°C
TA = –40°C
4.95
4.95
TA = 85°C
TA = 25°C
VIN = 1.6V
VIN = 2.4V
VIN = 3.2V
4.9
4.9
0
50
100
150
200
250
300
350
0
50
100
150
200
250
300
350
IOUT (mA)
IOUT (mA)
Line Regulation — PWM Mode (VOUT = 5.0V)
Line Regulation — PSAVE Mode (VOUT = 5.0V)
R1 = 931k , R2 = 294k , L = 4.7 H, CFB = 2.2pF, IOUT = 5mA
Ω
Ω
μ
Ω
Ω
μ
R1 = 931k , R2 = 294k , L = 4.7 H, CFB = 2.2pF, IOUT = 75mA
5.1
5.05
5
5.1
5.05
5
TA = 85°C
TA = –40°C
TA = 25°C
TA = –40°C
TA = 85°C
4.95
4.95
TA = 25°C
4.9
4.9
1.2
1.6
2
2.4
2.8
3.2
1.2
1.6
2
2.4
2.8
3.2
VIN (V)
VIN (V)
13
SC120
Typical Characteristics — VOUT = 5.0V, Mid VIN Range (continued)
Temperature Regulation — PSAVE Mode (VOUT = 5.0V)
Temperature Regulation — PWM Mode (VOUT = 5.0V)
Ω
Ω
μ
Ω
Ω
μ
R1 = 931k , R2 = 294k , L = 4.7 H, CFB = 2.2pF, IOUT = 5mA
R1 = 931k , R2 = 294k , L = 4.7 H, CFB = 2.2pF, IOUT = 75mA
5.1
5.05
5
5.1
5.05
5
VIN = 1.6V
VIN = 3.2V
VIN = 3.2V
VIN = 2.4V
VIN = 2.4V
VIN = 1.6V
4.95
4.9
4.95
4.9
-50
-25
0
25
50
75
100
-50
-25
0
25
50
75
100
Junction Temperature (oC)
Junction Temperature (oC)
See page 16 for all VOUT = 5.0V operation and startup load data.
14
SC120
Typical Characteristics — VOUT = 5.0V, High VIN Range
Efficiency vs. IOUT (VOUT = 5.0V)
Efficiency vs. IOUT (VOUT = 5.0V)
R1 = 931k , R2 = 294k , L = 6.8 H, CFB = 2.2pF, TA = 25οC
Ω
Ω
μ
Ω
Ω
μ
R1 = 931k , R2 = 294k , L = 6.8 H, CFB = 2.2pF, VIN = 3.6V
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
VIN = 4.2V
TA = –40°C
TA = 85°C
VIN = 3.0V
TA = 25°C
VIN = 3.6V
0.1 0.2
0.5
1
2
5
10
20
50 100 200
500
0.1 0.2
0.5
1
2
5
10
20
50 100 200
500
IOUT (mA)
IOUT (mA)
Load Regulation (VOUT = 5.0V)
Load Regulation (VOUT = 5.0V)
R1 = 931k , R2 = 294k , L = 6.8 H, CFB = 2.2pF, TA = 25οC
R1 = 931k , R2 = 294k , L = 6.8 H, CFB = 2.2pF, VIN = 3.6V
Ω
Ω
μ
Ω
Ω
μ
5.1
5.05
5
5.1
5.05
5
TA = 85°C
VIN = 4.2V
TA = –40°C
4.95
4.9
4.95
4.9
TA = –40°C
VIN = 3.0V
VIN = 3.6V
TA = 25°C
TA = 85°C
4.85
4.85
0
50
100
150
200
250
IOUT (mA)
300
350
400
450
500
0
50
100
150
200
250
IOUT (mA)
300
350
400
450
500
Line Regulation — PSAVE Mode (VOUT = 5.0V)
R1 = 931k , R2 = 294k , L = 6.8 H, CFB = 2.2pF, IOUT = 5mA
Line Regulation — PWM Mode (VOUT = 5.0V)
Ω
Ω
μ
Ω
Ω
μ
R1 = 931k , R2 = 294k , L = 6.8 H, CFB = 2.2pF, IOUT = 75mA
5.1
5.05
5
5.1
5.05
5
TA = 85°C
TA = –40°C
TA = –40°C
TA = 25°C
TA = 85°C
4.95
4.9
4.95
4.9
TA = 25°C
4.85
4.85
0.5
1
1.5
2
2.5
3
3.5
4
4.5
0.5
1
1.5
2
2.5
3
3.5
4
4.5
VIN (V)
VIN (V)
15
SC120
Typical Characteristics — VOUT = 5.0V, High VIN Range (continued)
Temperature Regulation — PSAVE Mode (VOUT = 5.0V)
Temperature Regulation — PWM Mode (VOUT = 5.0V)
Ω
Ω
μ
Ω
Ω
μ
R1 = 931k , R2 = 294k , L = 6.8 H, CFB = 2.2pF, IOUT = 75mA
R1 = 931k , R2 = 294k , L = 6.8 H, CFB = 2.2pF, IOUT = 5mA
5.1
5.05
5
5.1
5.05
5
VIN = 4.2V
VIN = 3.0V
VIN = 4.2V
VIN = 3.6V
VIN = 3.0V
VIN = 3.6V
4.95
4.9
4.95
4.9
4.85
4.85
-50
-25
0
25
50
75
100
-50
-25
0
25
50
75
100
Junction Temperature (oC)
Junction Temperature (oC)
Startup Min. Load Res. vs. VIN (VOUT=5.0V, all VIN Ranges)
Startup Max. Load Current vs. VIN (VOUT=5.0V, all VIN’s)
Ω
Ω
μ
Ω
Ω
μ
R1 = 931k , R2 = 294k , L = 6.8 H, CFB = 2.2pF
R1 = 931k , R2 = 294k , L = 6.8 H, CFB = 2.2pF
140
120
100
80
160
140
120
100
80
TA = –40°C
TA = –40°C
TA = 25°C
TA = 85°C
TA = 25°C
60
60
TA = 85°C
40
40
TA = 25°C
TA = 85°C
20
20
TA = –40°C
0
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
0.5
1
1.5
2
2.5
3
3.5
4
4.5
VIN (V)
VIN (V)
Maximum IOUT vs. VIN (VOUT = 5.0V, all VIN Ranges)
Ω
Ω
μ
R1 = 931k , R2 = 294k , L = 4.7 H, CFB = 2.2pF
500
450
400
350
300
250
200
150
100
50
TA = –40°C
TA = 25°C
TA = 85°C
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
VIN (V)
16
SC120
Typical Characteristics (continued)
Load Transient (PSAVE to PWM)
VOUT = 3.3V, VIN = 1.2V, TA = 25°C
Load Transient (PWM to PWM)
VOUT = 3.3V, VIN = 1.5V, TA =25°C
IOUT = 40mA to
140mA
IOUT = 5mA to
100mA
(50mA/div)
(50mA/div)
VOUT
(100mV/div)
AC Coupled
VOUT
(100mV/div)
AC Coupled
Time = (100μs/div)
Time = (100μs/div)
PWM Operation
PSAVE Operation
VOUT = 3.3V, VIN = 1.5V, IOUT = 50mA
V
OUT = 3.3V, VIN = 1.5V, IOUT = 20mA
VOUT ripple
(50mV/div)
VOUT ripple
(10mV/div)
IL
IL
(100mA/div)
(100mA/div)
VLX
VLX
(5V/div)
(5V/div)
Time = (10μs/div)
Time = (400ns/div)
Minimum Startup VIN vs. Temperature (Any VOUT
)
0.95
0.925
0.9
0.875
0.85
0.825
0.8
-50
-25
0
25
50
75
100
Junction Temperature (oC)
17
SC120
Pin Descriptions
MLPD Pin # SOT23 Pin #
Pin Name
LX
Pin Function
1
2
3
2
Switching node — connect an inductor from the input supply to this pin.
Signal and power ground.
GND
Battery or supply input — requires an external 10μF bypass capacitor (capacitance evalu-
ated while under VIN bias) for normal operation.
3
1
IN
4
5
6
5
EN
FB
Enable digital control input — active high.
Feedback input — connect to GND for preset 3.3V output. A voltage divider is connected
from OUT to GND to adjust output from 1.8V to 5.0V.
Output voltage pin — requires an external 10μF bypass capacitor (capacitance evaluated
while under VOUT bias) for normal operation.
6
T
4
OUT
Thermal
Pad
Thermal Pad (MLPD package only) is for heat sinking purposes — connect to ground
plane using multiple vias — not connected internally.
NA
18
SC120
Block Diagram
VOUT
Comp.
IN
+
-
OUT
+
1.7 V
-
+
-
Start-up
Oscillator
EN
P
LIM
Amp.
Gate Drive
and
Logic
Bulk
Bias
Oscillator and
Slope
Generator
Slope
Comp.
Control
LX
PWM
Comp.
+
PWM
Control
-
+
-
NLIM
Amplifier
Error
+
-
Amp.
Output Voltage
Selection Logic
-
FB
Current
Amplifier
+
GND
VREF
+
-
1.2 V
19
SC120
Applications Information
to ground and is increasing. When the n-channel FET is
turned off and the p-channel FET is turned on (known as
the off-state), the inductor is then connected between IN
and OUT. The (now decreasing) inductor current flows
from the input to the output, boosting the output voltage
above the input voltage.
Detailed Description
The SC120 is a synchronous step-up Pulse Width
Modulated (PWM) DC-DC converter utilizing a 1.2MHz
fixed frequency current mode architecture. It is designed
to provide output voltages in the range 1.8V to 5.0V from
an input voltage as low as 0.7V, with a (output unloaded)
start up input voltage of 0.85V.
Output Voltage Selection
The device operates in two modes: PWM and automatic
PSAVE mode. In PWM operation, the devices uses pulse
width modulation control to regulate the output under
moderate to heavy load conditions. It switches to PSAVE
mode when lightly loaded. Quiescent current consump-
tion is as little as 50μA, into the OUT pin, when in PSAVE
mode.
The SC120 output voltage can be programmed to an
internally preset value or it can be programmed with
external resistors. The output is internally programmed
to 3.3V when the FB pin is connected to GND. Any output
voltage in the range 1.8V to 5.0V can be programmed
with a resistor voltage divider between OUT and the FB
pin as shown in Figure 1.
The regulator control circuitry is shown in the Block
Diagram. It is comprised of a programmable feedback
controller, an internal 1.2MHz oscillator, an n-
channel Field Effect Transistor (FET) between the LX and
GND pins, and a p-channel FET between the LX and OUT
pins. The current flowing through both FETs is monitored
and limited as required for startup, PWM operation, and
PSAVE operation. An external inductor must be connected
between the IN pin and the LX pin. When the n-channel
FET is turned on, the LX pin is internally grounded, con-
necting the inductor between IN and GND. This is called
the on-state. During the on-state, inductor current flows
The values of the resistors in the voltage divider network
are chosen to satisfy the equation
§
·
R1
R2
¨
¸
¸
VOUT 1.2u 1ꢂ
ꢀVꢁ
¨
©
¹
.
A large value of R2, ideally 590kΩ or larger, is preferred for
stability for VIN within approximately 400mV of VOUT. For
lower VIN, lower resistor values can be used. The values of
R1 and R2 can be as large as desired to achieve low quies-
cent current.
L1
IN
LX
OUT
EN
VOUT
CFB
R1
FB
GND
CIN
COUT
SC120
R2
Figure 1 — Output Voltage Feedback Circuit
20
SC120
Applications Information (continued)
output of the PLIM amplifier falls to 0V during the off-state
due to low load current.
PWM Operation
The PWM cycle runs at a fixed frequency (fosc = 1.2MHz),
with a variable duty cycle (D). PWM operation continually
draws current from the input supply (except for discon-
tinuous mode, described subsequently). During the on-
state of the PWM cycle, the n-channel FET is turned on,
grounding the inductor at the LX pin. This causes the
current flowing from the input supply through the induc-
tor to ground to ramp up. During the off-state, the n-
channel FET is turned off and the p-channel FET
(synchronous rectifier) is turned on. This causes the
inductor current to flow from the input supply through
the inductor into the output capacitor and load, boosting
the output voltage above the input voltage. The cycle
then repeats to re-energize the inductor.
PSAVE mode requires fewer circuit resources than PWM
mode. All unused circuitry is disabled to reduce quies-
cent power dissipation. In PSAVE mode, the OUT pin
voltage monitoring circuit remains active and the output
voltage error amplifier operates as a comparator. PSAVE
regulation is shown in Figure 2. When VOUT < 1.008xVREG
,
where VREG is the programmed output voltage, a burst of
fixed-period switching occurs to boost the output voltage.
The n-channel FET turns on (on-state) until the inductor
current rises to approximately 240mA. The n-channel FET
then turns off and the p-channel FET turns on to transfer
the inductor energy to the output capacitor and load for
the duration of the off-state. This cycle repeats until
V
OUT > 1.018×VREG, at which point both FETs are turned off.
The output capacitor then discharges into the load until
OUT < 1.008×VREG, and the burst cycle repeats.
Ideally, the steady state (constant load) duty cycle is
determined by D = 1 – (VIN/VOUT), but must be greater in
practice to overcome dissipative losses. The SC120 PWM
controller constrains the value of D such that 0.15 < D < 0.90
(approximately).
V
When the output current increases above a predeter-
mined level, either of two PSAVE exit conditions will force
the resumption of PWM operation. The first PSAVE exit
criterion is shown in Figure 2. If the PSAVE burst cycle
cannot provide sufficient current to the output, the
output voltage will decrease during the burst. If
The average inductor current during the off-state multi-
plied by (1-D) is equal to the average load current. The
inductor current is alternately ramping up (on-state) and
down (off-state) at a rate and amplitude determined by
the inductance value, the input voltage, and the on-time
(TON = D×T, T = 1/fOSC). Therefore, the instantaneous induc-
tor current will be alternately larger and smaller than the
average. If the average output current is sufficiently small,
the minimum inductor current can reach zero during the
off-state. If the energy stored in the inductor is depleted
(the inductor current decreases to zero) during the off-
state, both FETs turn off for the remainder of the off-state.
If this discontinuous mode (DM) operation persists, the
SC120 transitions to PSAVE operation.
VOUT < 0.98 × VREG, PWM operation will resume. The second
PSAVE exit criterion, illustrated in Figure 3, depends on
the rate of discharge of the output capacitor between
PSAVE bursts. If the time between bursts is less than 5μs,
then PWM operation resumes. The output capacitance
value will affect the second criterion, but not the first.
Reducing the output capacitor will reduce the output
load at which PSAVE mode exits to PWM mode.
Within each on/off cycle of a PSAVE burst, the rate of
decrease of the inductor current during the off-state is
proportional to (VOUT − VIN). If VIN is sufficiently close to
PSAVE Operation
VOUT, the decrease in current during the off-state may not
At light loads, the SC120 will operate in PSAVE mode. At
low output load, PSAVE mode will operate more efficiently
than PWM mode. PSAVE mode also ensures regulation
while the output load is too small to keep the PWM mode
duty cycle above its minimum value, especially when VIN
is close to VOUT. PSAVE operation is triggered by 256 con-
secutive cycles of DM operation in PWM mode, when the
overcome the increase in current during the minimum
on-time of the on-state, approximately 100ns. This can
result in the peak inductor current rising above the PSAVE
mode n-channel FET current limit. (Normally, when the
n-channel FET current limit is reached, the on-state ends
immediately and the off-state begins. This sets the duty
cycle on a cycle-by-cycle basis.) This inductor current rise
21
SC120
Applications Information (continued)
PWM Mode at
High Load
PSAVE Mode at
Moderate Load
Higher Load
Applied
PSAVE exit due
to output decay
BURST
OFF
BURST
OFF
BURST
PWM Mode
+1.8%
+0.8%
Prog’d
VOUT
Voltage
-2%
Inductor
Current
240mA
0A
Time
Figure 2 — PSAVE Operation With Exit to PWM Due To Output Voltage Decay
PWM Mode at
High Load
PSAVE Mode at
Moderate Load
Higher Load
Applied
PSAVE exit due to
off-time reduction
OFF
(> 5μs)
OFF
(< 5μs)
BURST
BURST
PWM Mode
+1.8%
+0.8%
Prog’d
VOUT
Voltage
-2%
Inductor
Current
240mA
0A
Time
Figure 3 — PSAVE Operation With Exit to PWM Due To Off-time < 5μs
22
SC120
Applications Information (continued)
accumulates with each successive cycle in the burst. The
result is that the output load current that can be sup-
ported in PSAVE under this high VIN condition will be
greater than occurs if the 240mA current limit can be
enforced. Therefore the PSAVE exit load due to the first
exit criterion (Figure 2) can increase significantly. This
phenomenon is advantageous. Reverting to PWM opera-
tion with high VIN can result in VOUT rising above VREG, due
to the PWM minimum duty cycle. PSAVE operation avoids
this voltage rise because of its hysteretic voltage-thresh-
old on/off control. If the load remains low enough to
remain in PSAVE, VIN can approach and even slightly
exceed VOUT. To initally enter PSAVE mode, the initial
startup load must be small enough to cause discontinu-
ous mode PWM operation. This PSAVE mode startup load
upper limit can be increased if needed by reducing the
inductance. (Refer to the Inductor Selection section.)
Sufficiently large output capacitance will prevent PSAVE
exit due to the second exit criterion (Figure 3).
Regulator Startup, Short Circuit Protection, and
Current Limits
The SC120 permits power up at input voltages from 0.85V
to 4.5V. Startup current limiting of the internal switching
n-channel and p-channel FET power devices protects
them from damage in the event of a short between OUT
and GND. As the output voltage rises, progressively less-
restrictive current limits are applied. This protection
unavoidably prevents startup into an excessive load.
To begin, the p-channel FET between the LX and OUT pins
turns on with its current limited to approximately 150mA,
the short-circuit output current. When VOUT approaches VIN
(but is still below 1.7V), the n-channel current limit is set
to 350mA (the p-channel limit is disabled), the internal
oscillator turns on (approximately 200kHz), and a fixed
75% duty cycle PWM operation begins. (See the section
PWM Operation.) When the output voltage exceeds 1.7V,
fixed frequency PWM operation begins, with the duty
cycle determined by an n-channel FET peak current limit
of 350mA. When this n-channel FET startup current limit
is exceeded, the on-state ends immediately and the off-
state begins. This determines the duty cycle on a cycle-
by-cycle basis. When VOUT is within 2% of the programmed
regulation voltage, the n-channel FET current limit is
raised to 1.2A, and normal voltage regulation PWM control
begins.
PSAVE VOUT ripple may increase due to parasitic capaci-
tance on the external FB pin network. If using external
feedback programming, it is prudent to add a small capaci-
tor between OUT and FB to the circuit board layout. When
operating the SC120 in the final configuration in PSAVE,
observe the amplitude of PSAVE ripple. If the ripple
exceeds 50mV for the expected range of input voltage, a
small-value capacitor should be tried. Capacitance on the
order of a few picofarads is often sufficient to bring the
ripple amplitude to approximately 50mV.
Once normal voltage regulation PWM control is initiated,
the output becomes independent of VIN and output regu-
lation can be maintained for VIN as low as 0.7V, subject to
the maximum duty cycle and peak current limits. The duty
cycle must remain between 15% and 90% for the device
to operate within specification.
In the case of low VIN and high VOUT, larger values of CFB
may be needed, perhaps 4.7pF or higher. If using the
SOT23-6 package (SC120SKTRT) with low VIN and high VOUT
,
at least 10pF to 12pF is recommended.
Note that startup with a regulated active load is not the
same as startup with a resistive load. The resistive load
output current increases proportionately as the output
voltage rises until it reaches programmed VOUT/RLOAD, while
a regulated active load presents a constant load as the
output voltage rises from 0V to programmed VOUT. Note
also that if the load applied to the output exceeds an
applicable VOUT dependent startup current limit or duty
cycle limit, the criterion to advance to the next startup
stage may not be achieved. In this situation startup may
The Enable Pin
The EN pin is a high impedance logical input that can be
used to enable or disable the SC120 under processor
control. VEN < 0.2V will disable regulation, set the LX pin in
a high-impedance state (turn off both FET switches), and
turn on an active discharge device to discharge the output
capacitor via the OUT pin. VEN > 0.85V will enable the
output. The startup sequence from the EN pin is identical
to the startup sequence from the application of input
power.
23
SC120
Applications Information (continued)
pause at a reduced output voltage until the load is reduced
further.
viding a moderate resistance path across the inductor to
dampen the oscillations at the LX pin. This effectively
reduces EMI that can develop from the resonant circuit
formed by the inductor and the drain capacitance at LX.
Output Overload and Recovery
When in PSAVE operation, an increasing load will eventu-
ally satisfy one of the PSAVE exit criteria and regulation
will revert to PWM operation. As previously noted, the
PWM steady state duty cycle is determined by
D = 1 – (VIN/VOUT), but must be somewhat greater in prac-
tice to overcome dissipative losses. As the output load
increases, the dissipative losses also increase. The PWM
controller must increase the duty cycle to compensate.
Eventually, one of two overload conditions will occur,
determined by VIN, VOUT, and the overall dissipative losses
due to the output load current. Either the maximum duty
cycle of 90% will be reached or the n-channel FET 1.2A
(nominal) peak current limit will be reached, which effec-
tively limits the duty cycle to a lower value. Above that
load, the output voltage will decrease rapidly and in
reverse order the startup current limits will be invoked as
the output voltage falls through its various voltage thresh-
olds. How far the output voltage drops depends on the
load voltage vs. current characteristic.
The anti-ringing circuitry is disabled between PSAVE
bursts.
Component Selection
The SC120 provides optimum performance when a 4.7μH
inductor is used with a 10μF output capacitor. Different
component values can be used to modify PSAVE exit or
entry loads, modify output voltage ripple in PWM mode,
improve transient response, or to reduce component size
or cost.
Inductor Selection
The inductance value primarily affects the amplitude of
inductor current ripple (ΔIL). Reducing inductance
increases ΔIL. This raises the inductor peak current,
I
L-max = IL-avg + ΔIL/2, where IL-avg is the inductor current aver-
aged over a full on/off cycle. IL-max is subject to the
n-channel FET current limit ILIM(N), therefore reducing the
inductance may lower the output overload current thresh-
old. Increasing ΔIL also lowers the inductor minimum
current, IL-min = IL-avg – ΔIL/2, thus raising the PSAVE entry
load current threshold. This is the output load below
which IL-min = 0, the boundary between continuous mode
and discontinuous mode PWM regulation, which signals
the SC120 controller to switch to PSAVE operation. In the
extreme case of VIN approaching VOUT, smaller inductance
can also reduce the PSAVE inductor burst-envelope current
ripple and voltage ripple.
A reduction in input voltage, such as a discharging battery,
will lower the load current at which overload occurs.
Lower input voltage increases the duty cycle required to
produce a given output voltage. And lower input voltage
also increases the input current to maintain the input
power, which increases dissipative losses and further
increases the required duty cycle. Therefore an increase in
load current or a decrease in input voltage can result in
output overload. Once an overload has occurred, the load
must be decreased to permit recovery. The conditions
required for overload recovery are identical to those
required for successful initial startup.
Equate input power to output power, note that input
current equals inductor current, and average over a full
PWM switching cycle to obtain
Anti-ringing Circuitry
1 VOUT uIOUT
In PWM operation, the n-channel and p-channel FETs are
simultaneously turned off when the inductor current
reaches zero. They remain off for the zero-inductor-
current portion of the off-state. Note that discontinuous
mode is a marginal-load condition, which if persistent will
trigger a transition to PSAVE operation.
ILꢃavg
u
K
V
IN
where η is efficiency.
ΔIL is the inductor (and thus the input) peak-to-peak
current. Neglecting the n-channel FET RDS-ON and the
inductor DCR, for duty cycle D, and with T = 1/fosc,
When both FET switches are simultaneously turned off, an
internal switch between the IN and LX pins is closed, pro-
24
SC120
Applications Information (continued)
DT
1
L
V uDuT
smallest and largest expected values of VIN. If the input
IN
'ILꢃon
V dt
IN
2
³
0
range includes VIN = /3 VOUT, also determine IPSAVE-entry-max
.
L
Note that at high VIN (VIN close to VOUT) PSAVE exit may
require an unusually high output load current. In this
case, PSAVE re-entry may be of little concern. So if the
largest VIN exceeds approximately 90% of VOUT, instead
This is the change in IL during the on-state. During the
off-state, again neglecting the p-channel FET RDS-ON and
the inductor DCR,
evaluate PSAVE entry at VIN = 0.9VOUT
.
'ILꢃoff
T ꢀV ꢃ VOUT
ꢁ
dt
ꢀ
1ꢃD
ꢁ
To ensure that IPSAVE-entry-max will be less than the PSAVE exit
current, evaluate the PSAVE-PWM mode transistions while
applying increasing and decreasing loads with VIN at and
1
L
ꢀ
V ꢃ VOUT
ꢁ
uT
IN
IN
³
DT
L
Note that this is a negative quantity, since VOUT > VIN and
0 < D < 1. For a constant load in steady-state, the inductor
current must satisfy ΔIL-on + ΔIL-off = 0. Substituting the two
expressions and solving for D, obtain D = 1 – VIN/VOUT
Using this expression, and the positive valued expression
2
above /3 VOUT. This should be done at the application’s
lowest specified ambient temperature as well as at room
temperature. If the PSAVE exit current is not sufficiently
greater than the PSAVE entry current, the separation can
be enhanced by increasing the output capacitance to raise
.
ΔIL = ΔIL-on for current ripple amplitude, obtain expanded
I
PSAVE-exit due to the 5μs off-time criterion (see Figure 3), or
expression for IL-max and IL-min
.
by increasing the inductor value to reduce IPSAVE-entry
.
VOUT uIOUT
T
V
IN
The inductor selection should also consider the n-channel
FET current limit for the expected range of input voltage
and output load current. The largest IL-avg will occur at the
expected smallest VIN and largest IOUT. Determine the
ILꢃmax,min
r
u
u
ꢀ
VOUT ꢃ VIN ꢁ
V uK
2uL VOUT
IN
If the value of IOUT decreases until IL-min = 0, which is the
boundary of continuous and discontinuous PWM opera-
tion, the SC120 will transition from PWM operation to
PSAVE operation. Define this value of IOUT as IPSAVE-entry
Setting the expression for IL-min to 0 and solving,
largest allowable ΔIL, based on the largest expected IL-avg
,
the minimum n-channel FET current limit, and the
inductor tolerance. Ensure that in the worst case,
.
I
L-avg + ΔIL/2 < ILIM(N).
2
§
·
These calculations include the parameter η, efficiency.
Efficiency varies with VIN, IOUT, and temperature. Estimate η
using the plots provided in this datasheet, or from experi-
mental data, at the operating condition of interest when
computing the effect of a new inductor value on PSAVE
entry and I-limit margin.
KuT
V
IN
¨
¨
¸
¸
IPSAVEꢃentry
ꢀ
VOUT ꢃ VIN ꢁ
2uL VOUT
©
¹
The programmed value of VOUT is constant. IPSAVE-entry is a
polynomial function of VIN. Equating dIPSAVE-entry/dVIN = 0
and solving for VIN reveals that there is one non-zero extre-
mum of this function, a maximum, at VIN = /3 VOUT.*
Applying this value of VIN,
2
Any chosen inductor should have low DCR, compared to
the RDS-ON of the FET switches, to maintain efficiency,
though for DCR << RDS-ON, further reduction in DCR will
provide diminishing benefit. The inductor ISAT value should
exceed the expected IL-max. The inductor self-resonant fre-
quency should exceed 5×fosc. Any inductor with these
properties should provide satisfactory performance.
KuT
L
2
27
IPSAVEꢃentryꢃmax
u
uVOUT
The value of the inductor determines the PSAVE entry
output load current for a given VIN. Evaluate IPSAVE-entry at the
* For simplicity, efficiency (η) is represented as a constant. But efficien-
cy, itself a function of VIN, decreases with decreasing VIN (and decreases
with increasing temperature). Therefore at a given temperature, the
input voltage that produces the maximum PSAVE entry load current
L = 4.7μH should perform well for most applications. For
high VOUT, (4.0V to 5.0V), and relatively high VIN (3.3V and
above), L = 6.8μH, along with a larger output capacitance
or larger-package output capacitor (for better V-bias per-
will be slightly greater than 2/3 of VOUT
.
25
SC120
Applications Information (continued)
formance), will ensure correct mode–switching behavior.
at the switching frequency of the SC120. Ceramic capaci-
tors of type Y5V are not recommended as their tempera-
ture coefficients and large capacitance tolerance make
them unsuitable for this application. The following table
lists recommended capacitors. For smaller values and
smaller packages, it may be necessary to use multiple
For very low VIN (0.7V to 0.8V) such as is obtained with a
nearly-depleted single-cell alkaline battery), a smaller
value of inductance will help to ensure that PWM mode
will switch to PSAVE mode as the load decreases. This
consideration may be of little importance in most applica-
tions, as there is little energy remaining in such a deeply
discharged battery.
devices in parallel, especially for COUT
.
Case
Height
(mm)
Manufacturer/
Part Number
Value
(ꢀF)
Rated Volt-
age (VDC)
Case
Size
Type
Murata
GRM21BR60J226ME39B
The following table lists the manufacturers of recom-
mended inductor options. The specification values shown
are simplified approximations or averages of many device
parameters under various test conditions. See manufac-
turers’documentation for full performance data.
22
22
4.7
22
22
6.3
10
4
X5R
X7R
X5R
X5R
X5R
0805
1206
0603
0805
0805
1.25
1.6
Murata
GRM31CR71A226KE15L
Murata
GRM185R60G475ME15
0.5
TDK
10
20
0.85
1.25
C2012X5R1A226M
Rated
Current
(mA)
Dimensions
LxWxH
Manufacturer/
Part #
Value DCR
Tolerance
(%)
Taiyo Yuden
JMK212BJ226MG-T
(ꢀH)
(Ω)
(mm)
Murata
LQM31PN4R7M00
4.7
4.7
0.3
0.7
700
500
20
20
3.2 x 1.6 x 0.95
2 x 2 x 0.6
PCB Layout Considerations
Coilcraft
XFL2006-472
Poor layout can degrade the performance of the DC-DC
converter and can contribute to EMI problems, ground
bounce, and resistive voltage losses. Poor regulation and
instability can result.
Capacitor Selection
Input and output capacitors must be chosen carefully to
ensure that they are of the correct value and rating. The
output capacitor requires a minimum capacitance value
of 10μF at the programmed output voltage to ensure sta-
bility over the full operating range, and to ensure positive
mode-switching hysteresis. The DC bias must be included
in capacitor derating to ensure the required effective
capacitance is provided, especially when considering
small package-size capacitors. For example, a 10μF 0805
capacitor may provide sufficient capacitance at low output
voltages but may be too low at higher output voltages.
Therefore, a higher capacitance value may be required to
provide the minimum of 10μF at these higher output volt-
ages. Additional output capacitance may be required for
VIN close to VOUT to reduce ripple in PSAVE mode, to increase
the PSAVE exit threshold for high VIN, and to ensure stabil-
ity in PWM mode, especially at higher output load
currents.
The following simple design rules can be implemented to
ensure good layout:
• Place the inductor and filter capacitors as close
to the device as possible and use short wide
traces between the power components.
• Route the output voltage feedback path away
from the inductor and LX node to minimize
noise and magnetic interference.
• Maximize ground metal on the component side
to improve the return connection and thermal
dissipation. Separation between the LX node
and GND should be maintained to avoid cou-
pling capacitance between the LX node and the
ground plane.
• Use a ground plane with several vias connecting
to the component side ground to further reduce
noise interference on sensitive circuit nodes.
Low ESR capacitors such as X5R or X7R type ceramic
capacitors are recommended for input bypassing and
output filtering. Low-ESR tantalum capacitors are not rec-
ommended due to possible reduction in capacitance seen
A layout drawing for the MLP package is shown in Figure 4
and a layout drawing for the SOT23 package is shown in
Figure 5.
26
SC120
Applications Information (continued)
7.0mm
VOUT
COUT
LX
OUT
FB
CFB
R1
GND
IN
SC120
5.2mm
LX
(2nd layer)
EN
R2
VIN
CIN
GND
Figure 4 — Layout Drawing for MLP package
8mm
VIN
GND
CIN
(2nd layer)
IN
GND
LX
EN
FB
R2
R1
LX
SC120
CFB
5.5mm
OUT
VOUT
COUT
Figure 5 — Layout Drawing for SOT23-6 package
27
SC120
Outline Drawing — MLPD-UT-6 1.5x2
DIMENSIONS
INCHES
B
E
A
D
MILLIMETERS
DIM
MIN
.020
.000
NOM
-
MAX
.024
.002
MIN
0.50
0.00
NOM MAX
-
A
A1
A2
b
0.60
-
-
0.05
(.006)
.010
(.152)
0.25
PIN 1
INDICATOR
.007
.055
.035
.075
.026
.012
.063
.055
.083
.035
0.18
1.40
0.90
1.90
0.65
0.30
1.60
1.40
2.10
0.90
D
.059
-
1.50
-
(LASER MARK)
D1
E
.079
.031
2.00
0.80
E1
e
.020 BSC
.014
0.50 BSC
0.35
A2
C
L
N
aaa
.012
.016
0.30
0.40
A
6
6
SEATING
PLANE
.003
0.08
aaa
C
bbb
.004
0.10
A1
D1
2
1
LxN
E1
N
bxN
bbb
C A B
e
NOTES:
1. CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES).
2. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS TERMINALS.
28
SC120
Land Pattern — MLPD-UT-6 1.5x2
H
R
DIMENSIONS
INCHES
DIM
MILLIMETERS
(.077)
.047
.051
.031
.020
.006
.012
.030
.106
(1.95)
1.20
1.30
0.80
0.50
0.15
0.30
0.75
2.70
C
G
H
K
P
R
X
Y
Z
Z
G
Y
(C)
K
P
X
NOTES:
1.
2.
CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES).
THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY.
CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR
COMPANY'S MANUFACTURING GUIDELINES ARE MET.
THERMAL VIAS IN THE LAND PATTERN OF THE EXPOSED PAD
3.
SHALL BE CONNECTED TO A SYSTEM GROUND PLANE.
FAILURE TO DO SO MAY COMPROMISE THE THERMAL AND/OR
FUNCTIONAL PERFORMANCE OF THE DEVICE.
29
SC120
Outline Drawing — SOT23-6
DIMENSIONS
MILLIMETERS
DIM
A
NOM MAX
MIN
-
-
A
0.90
1.45
0.15
e1
D
E
A1 0.00
A2 0.90 1.15 1.30
-
N
b
c
D
0.25
0.08
0.50
0.22
2X E/2
-
E1
2.80 2.90 3.10
E1 1.50 1.60 1.75
1
2
E
e
2.80 BSC
0.95 BSC
ccc C
e1
L
L1
N
01
aaa
bbb
ccc
1.90 BSC
0.30 0.45 0.60
(0.60)
2X N/2 TIPS
e
6
-
0.10
0.20
0.20
B
0°
10°
D
aaa C
A2
A
SEATING
PLANE
H
C
A1
c
GAUGE
PLANE
bxN
bbb
C A-B D
0.25
01
L
(L1)
SEE DETAIL A
SIDE VIEW
DETAIL A
NOTES:
1. CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES).
2. DATUMS -A- AND -B- TO BE DETERMINED AT DATUM PLANE -H-
3. DIMENSIONS "E1" AND "D" DO NOT INCLUDE MOLD FLASH, PROTRUSIONS
OR GATE BURRS.
30
SC120
Land Pattern — SOT23-6
X
DIMENSIONS
DIM
MILLIMETERS
(2.50)
1.40
0.95
0.60
1.10
3.60
C
G
P
X
Y
Z
Z
(C)
G
Y
P
NOTES:
1. CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES).
2.
THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY.
CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR
COMPANY'S MANUFACTURING GUIDELINES ARE MET.
31
SC120
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