SC202FMLTRT_技术文档

SC202F

3.5MHz, 500mA Step-down

Regulator with Integrated Inductor

POWER MANAGEMENT

Features

Description



Input Voltage — 2.9V to 5.5V

Output Voltage — 0.8V to 3.3V

Output current capability — 500mA

Internal inductor

15 programmable output voltages

Fast transient response

Temperature range — -40 to +85°C

Oscillator frequency — 3.5MHz

100% duty cycle capability

Quiescent current — 11mA typ

Shutdown current — 0.1μA typ

Internal soft-start

The SC202F is a high eﬃciency 500mA step-down regula-

tor that includes an integrated inductor inside the

package. The input voltage range makes it ideal for

battery operated applications with space limitations. The

SC202F operates at a ﬁxed 3.5MHz switching frequency in

normal PWM (Pulse-Width Modulation) mode. The

SC202F also includes fifteen programmable output

voltage settings that can be selected using the four

control pins, eliminating the need for external feedback

resistors. The output voltage can be fixed to a single

setting or dynamically switched between diﬀerent levels.

Pulling all four control pins low disables the output.

Over-voltage protection

The SC202F provides several protection features to safe-

guard the device under stressed conditions. These

include short circuit protection, over-temperature protec-

tion, under-voltage lockout, and soft-start to control

in-rush current. These features, coupled with the small

2.5 x 3.0 x 1.0 (mm) package, make the SC202F a versatile

device ideal for step-down regulation in products needing

high eﬃciency and a small PCB footprint.

Current limit and short circuit protection

Over-temperature protection

Under-voltage lockout

Floating control pin protection

MLPQ-13 — 2.5 x 3.0 x 1.0 (mm) package

Lead-free and halogen-free

WEEE and RoHS compliant

Applications



Optical modules, GN1157B, GN1599 etc

Set top boxes

Telecommunication equipment

Power rails demand small voltage ripple and compact

size

Typical Application Circuit

SC202F

V_IN

IN

SNS

2.9V to 5.5V

V_{O UT}

0.8V to 3.3V

C_IN

O UT

4.7μF

CTL3

CTL2

CTL1

CTL0

C_{O UT}

10μF

Control Logic

Lines

G ND

LX

NC

Rev 2.0

1

SC202F

Pin Conﬁguration

Ordering Information

Device

Package

SC202FMLTRT⁽¹⁾⁽²⁾

MLPQ-13 — 2.5 x 3.0

Evaluation Board

LX

1

13 O UT

SC202FEVB

Notes:

2

3

12 O UT

11 O UT

(1) Available in tape and reel only. A reel contains 3,000 devices.

(2) Lead-free packaging only. Device is WEEE and RoHS compliant

and halogen-free.

TOP VIEW

SNS

CTL3

CTL0

4

5

6

10 G ND

9

IN

7

8

CTL1 CTL2

MLPQ-13; 2.5 x 3.0, 13 LEAD

θ_JA= 58°C/W

Table 1 – Output Voltage Settings

CTL3

CTL2

CTL1

CTL0

Vout

Oﬀ

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Marking Information

0.80

1.00

1.20

1.40

1.50

1.60

1.80

2.3

202F

yyww

xxxx

2.35

2.00

2.4

2.45

2.8

yyww = Date Code

xxxx = Semtech Lot Number

3.00

3.30

2

SC202F

Absolute Maximum Ratings

Recommended Operating Conditions

IN (V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +6.0

LX Voltage (V). . . . . . . . . . . . . . . . . . . . . . . . . . . .-1.0 to V_IN+ 0.5

Other Pins (V). . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3 to V_IN+ 0.3

Output Short Circuit to GND. . . . . . . . . . . . . . . . Continuous

ESD Protection Level⁽¹⁾(kV) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Input Voltage Range (V) . . . . . . . . . . . . . . . . . . . . . +2.9 to+5.5

Operating Temperature Range (°C) . . . . . . . . . . -40 to +85

Thermal Information

Thermal Resistance, Junction to Ambient⁽²⁾(°C/W). . . . . 58

Junction Temperature Range (°C) . . . . . . . . . . . -40 to +150

Storage Temperature Range (°C). . . . . . . . . . . . -65 to +150

Exceeding the above speciﬁcations may result in permanent damage to the device or device malfunction. Operation outside of the parameters

speciﬁed in the Electrical Characteristics section is not recommended.

NOTES:

(1) Tested according to JEDEC standard JESD22-A114-B.

(2) Calculated from package in still air, mounted to 3 x 4.5 (in), 4 layer FR4 PCB per JESD51 standards.

Electrical Characteristics

Unless otherwise speciﬁed: V_IN= 3.6V, C_IN=4.7μF, C_OUT=10μF, V_OUT=2.0V, T_J(MAX)=125°C, T_A= -40 to +85 °C. Typical values are T_A=+25 °C

Parameter

Symbol

V_OUT

Condition

Min

0.8

Typ

Max

3.3 ⁽¹⁾

2.0

Units

V

Output Voltage Range

Output Voltage Tolerance

Line Regulation

V_{OUT_TOL}

ΔV_LINEREG

ΔV_LOADREG

I_OUT

I_OUT= 200mA

-2.0

%

2.9 ≤ V_IN≤ 5.5V, I_OUT= 200mA

200mA ≤ I_OUT≤ 500mA

0.3

-1

%/V

%/A

mA

V

Load Regulation

Output Current Capability

Current Limit Threshold

Foldback Current Limit

500

800

I_LIMIT

1300

2.9

I_{FB_LIM}

I_LOAD> I_LIMIT

Rising V_IN

150

Under-Voltage Lockout

V_UVLO

Hysteresis

200

11

mV

mA

μA

Quiescent Current

I_Q

I_SD

No switching, I_OUT= 0mA

V_{CTL 0-3}= 0V

Shutdown Current

0.1

250

350

3.5

1.0

Output Leakage Current

High Side Switch Resistance⁽²⁾

Low Side Switch Resistance⁽³⁾

Switching Frequency

I_OUT

Into OUT pin

I_OUT= 100mA

μA

R_{DSON_P}

R_{DSON_N}

f_SW

mΩ

I_OUT= 100mA

2.8

4.2

MHz

3

SC202F

Electrical Characteristics (continued)

Parameter

Symbol

t_SS

Condition

Min

Typ

100

160

20

Max

Units

μs

Soft-Start

V_OUT= 90% of ﬁnal value

Rising temperature

500

Thermal Shutdown

Thermal Shutdown Hysteresis

T_OT

°C

T_HYST

°C

Logic Inputs - CTL0, CTL1, CTL2, and CTL3

Input High Voltage

V_IH

V_IL

I_IH

1.6

V

Input Low Voltage

0.4

5.0

2.0

Input High Current

V_{CTL 0-3}= V_IN

-2.0

μA

Input Low Current

Notes

I_IL

V_{CTL 0-3}= GND

(1) Maximum output voltage is limited to VIN if the input is less than 3.3V.

(2) Measured from IN to LX.

(3) Measured from LX to GND.

4

SC202F

Typical Characteristics

C_IN= 4.7μF, C_OUT= 10μF, T_A= 25°C unless otherwise noted.

Load Regulation, Vin=3.6V

Eﬃciency vs Load, Vin=3.6V

Eﬃciency vs Load, Vin=4.2V

Load Regultation, Vin=4.2V

Eﬃciency vs Load, Vin=5.5V

Load Regulation, Vin=5.5V

5

SC202F

Typical Characteristics (continued)

Output Voltage vs Temperature

Switching Frequency vs Temperature

Soft Start, Light Load

Soft Start, Heavy Load

3 Steps Current Limit, Vout Ramp to Regulation

4 Steps Current Limit, Vout Ramp to Regulation

50mV/div

1V/div

5V/div

1A/div

Time (400us/div)

5Vin, 2Vout, 3.5MHz, Vout Ripple

VID Transition (CTL2 Low_High_Low)

5V/div

2V/div

10mV/div

5V/div

500mA/div

Time (200ns/div)

Time (200us/div)

6

SC202F

Typical Characteristics (continued)

VID Transition: Voltage Rise, CTL2 Low to High

VID Transition - Voltage Fall, CTL2 High to Low

5V/div

2V/div

5V/div

2V/div

5V/div

500mA/div

Time (10us/div)

Approaching 100 % Duty Cycle Operation

Vin=3.7V, Vout=3.3V Heavy Load

0A to 200mA Load Step Response

50mV/div

5V/div

50mV/div

5V/div

500mA/div

Time (1μs/div)

Time (100μs/div)

Short Circuit Protection:Current Limit for

32 Cycles then to Foldback I-Limit

Recovery From Short Circuit: Operating with

Foldback I-Limit Ramp up Vout to Regulation

2V/div

5V/div

1A/div

Time (4μs/div)

Time (10μs/div)

7

SC202F

Pin Descriptions

Pin Name

Pin Function

1, 2, 3

LX

Switching node sense pin — for test purposes only.

4

SNS

CTL3

CTL0

CTL1

CTL2

IN

Output sense pin — connect to output capacitor for proper sensing of output voltage.

Control bit 3 — see Table 1, page 2, for decoding. This pin has a weak pull-down resistor (> 1MΩ) in place at

reset that is removed when CTL3 is pulled above the logic high threshold.

5

Control bit 0 — see Table 1, page 2, for decoding. This pin has a weak pull-down resistor (> 1MΩ) in place at

reset that is removed when CTL0 is pulled above the logic high threshold.

6

Control bit 1 — see Table 1, page 2, for decoding. This pin has a weak pull-down resistor (> 1MΩ) in place at

reset that is removed when CTL1 is pulled above the logic high threshold.

7

Control bit 2 — see Table 1, page 2, for decoding. This pin has a weak pull-down resistor (> 1MΩ) in place at

reset that is removed when CTL2 is pulled above the logic high threshold.

8

9

10

Input power supply pin — connect a bypass capacitor from this pin to GND.

Ground reference and power ground for the SC202F.

GND

OUT

11, 12, 13

Regulator output pin — connect a 10μF ceramic capacitor to this pin for proper ﬁltering.

8

SC202F

Block Diagram

Plim it Am p

9

IN

Current Am p

OSC & Slope

Generator

A

B

LX

1μH

Control

Logic

OUT

PW M

Com p

500m V

Ref

Error Am p

Nlim it Am p

10

GND

5

8

7

6

CTL3

CTL2

Voltage

Select

CTL1

CTL0

4

SNS

A = pins 1, 2, 3

B = pins 11, 12, 13

9

SC202F

Applications Information

CTL pins when changing the output voltage will tempo-

rarily disable the device, so it is important to avoid this

combination when dynamically changing levels.

General Description

The SC202F is a synchronous step-down PWM (Pulse

Width Modulated) DC-DC regulator utilizing a 3.5MHz

ﬁxed-frequency voltage-mode architecture and an inter-

nal 1μH inductor. The device is designed to operate in

ﬁxed-frequency PWM mode. Two capacitors are the only

external components required — one for input decou-

pling and one for output ﬁltering. The output voltage is

programmable, eliminating the need for external pro-

gramming resistors. Loop compensation is also internal,

eliminating the need for external components to control

stability.

Adjustable Output Voltage Selection

If an output voltage other than one of the 15 program-

mable settings is needed, an external resistor divider

network can be added to the SC202F to adjust the output

voltage setting. This network scales the output based on

the resistor ratio and the programmed output setting.

The resistor values can be determined using the

equation

ª

º

Programmable Output Voltage

R_FB1ꢀ R_FB2

V_OUT V_SET

u

ꢀI_SNSuR_FB1

«

¬

»

¼

R_FB2

The SC202F has 15 ﬁxed output voltage levels which can

be individually selected by programming the CTL control

pins (CTL3-0 — see Table 1 on page 2 for settings). The

device is disabled whenever all four CTL pins are pulled

low and enabled whenever at least one of the CTL pins is

pulled high. This conﬁguration eliminates the need for a

dedicated enable pin. Each CTL pin is internally pulled

down via 1MΩ if V_INis below 1.5V or if the voltage on the

control pin is below the input high voltage. This ensures

that the output is disabled when power is applied if there

are no inputs to the CTL pins. Each weak pull-down is dis-

abled whenever its pin is pulled high and remains disabled

until all CTL pins are pulled low.

where V_OUTis the desired output voltage, V_SETis the voltage

setting selected by the CTL pins, R_FB1is the resistor

between the output capacitor and the SNS pin, R_FB2is the

resistor between the SNS pin and ground, and I_SNSis the

leakage current into the SNS pin during normal opera-

tion. The current into the SNS pin is typically 1μA, so the

last term of the equation can be neglected if the current

through R_FB2is much larger than 1μA. Selecting a resistor

value of 10kΩ or lower will simplify the design. If I_SNSis

neglected and R_FB2is ﬁxed, R_FB1can be determined using

the equation

V_OUTꢁ V_SET

R_FB1 R_FB2

u

The output voltage can be set using diﬀerent approaches.

If a static output voltage is required, the CTL pins can be

tied to either IN or GND to set the desired voltage when-

ever power is applied at IN. If enable control is required,

each CTL pin can be tied to either GND or to a micropro-

cessor I/O line to create the desired control code whenever

the control signal is forced high. This approach is equiva-

lent to using the CTL pins collectively as a single enable

pin. A third option is to connect each of the four CTL pins

to individual microprocessor I/O lines. Any of the 15

output voltages can be programmed using this approach.

If only two output voltages are needed, the CTL pins can

be combined in a way that will reduce the number of I/O

lines to 1, 2, or 3, depending on the control code for each

desired voltage. Other CTL pins could be hard-wired to

GND or IN. This option allows dynamic voltage adjust-

ment for systems that reduce the supply voltage when

entering sleep states. Note that applying all zeros to the

V_SET

Inserting resistance in the feedback loop will adversely

aﬀect the system’s transient performance if feed-forward

capacitance is not included in the circuit. The circuit in

Figure 1 illustrates how the resistor divider and feed-

forward capacitor can be added to the SC202F schematic.

The value of feed-forward capacitance needed can be

determined using the equation

2

V_SET

ꢂ

V_OUTꢁ 0.5

ꢃ

C_FF 4u10^ꢁ6

u

R_FB1

V_OUTꢁ V_SETꢃꢂV_SETꢁ 0.5

ꢂ ꢃ

10

SC202F

Applications Information (continued)

operation. An internal synchronous NMOS rectiﬁer turns

on complementary to the top PMOSFET.

SC202F

V_IN

IN

V_{O UT}

O UT

C_IN

C_OUT

C_FF

100% Duty Cycle Operation

The duty cycle (percentage of time PMOS is active)

increases as VIN decreases to maintain output voltage

regulation. As the input voltage approaches the pro-

grammed output voltage, the duty cycle approaches

100% (PMOS always on) and the device enters a pass

through mode until the input voltage increases or the

load decreases enough to allow PWM switching to

resume.

CTL3

CTL2

CTL1

CTL0

SNS

G ND

R_FB1

R_FB2

Enable

Figure 1 – Application Circuit with External Resistors

To simplify the design, it is recommended to program the

output setting to 1.0V, use resistor values smaller than

10kΩ, and include a feed-forward capacitance calculated

with the previous equation. If the output voltage is set to

1.0V, the previous equation reduces to

Protection Features

The SC202F provides the following protection features:

• ^{Soft-Start Operation}

• ^{Over-Voltage Protection}

• ^{Current Limit}

2

ꢂ

V_OUTꢁ 0.5

ꢃ

C_FF 8u10^ꢁ6

u

R_FB1

ꢂ

V_OUTꢁ1

ꢃ

• ^{Thermal Shutdown}

• ^{Under-Voltage Lockout}

Example:

Soft Start with Current Limit

An output voltage of 1.3V is desired, but this is not a pro-

grammable option. What external component values for

Figure 1 are needed?

The soft-start sequence is activated after a CTL code tran-

sition from an all zeros code to a non-zero code enables

the start up process. From the beginning of a start-up

process, the internal reference start-up takes typically

50ꢀs, then PMOS current limit is stepped through four

levels: 25%, 40%, 60%, and 100%. Each step is maintained

for typically 75ꢀs. A complete 4 steps start-up period

could take 350ꢀs. Before VOUT reaches 90%, the inductor

current is not allowed to go negative. The inductor

current is conﬁned between diﬀerent current limit levels,

25%, 40%, 60%, or 100% to zero.

Solution: To keep the circuit simple, set R_FB2to 10kΩ so

current into the SNS pin can be neglected and set the

CTL3-0 pins to 0010 (1.0V setting). The necessary compo-

nent values for this situation are

V_OUTꢁ V_SET

R_FB1 R_FB2

u

3k:

V_SET

2

ꢂ

V_OUTꢁ 0.5

ꢃ

As VOUT reaches 90% of the target value, the device will

transition into a ﬁxed 3.5MHz operation allowing induc-

tor current in both directions.

C_FF 8 u10^ꢁ6

u

5.69nF

R_FB1

ꢂ

V_OUTꢁ1

ꢃ

Due to current limit operation, if the load is heavy or the

output capacitor is large, the soft start process may expe-

rience all 4 current limit steps before reaching 90% target

voltage. This will make the soft start time long. If the load

is light and output capacitor is small, the device may only

need the ﬁrst current limit step, reaching 90% of target,

and transition into PWM operation. This makes the soft

PWM Operation

In order to start up from pre-charged output voltage,

SC202F does not allow inductor current to go negative

in soft start stage, refer to the soft start waveforms in the

Typical Characteristics page. When the output voltage

exceeds 90% of the set point, determined by the CTLx

combinations, the device will enter ﬁxed 3.5MHz PWM

11

SC202F

Applications Information (continued)

capacitor above this minimum value will reduce the cross-

over frequency and provide greater phase margin.

start time shorter.

Over-Voltage Protection

Capacitors with X7R or X5R ceramic dielectric are recom-

mended for their low ESR and superior temperature and

voltage characteristics. Y5V capacitors should not be used

as their temperature coeﬃcients make them unsuitable

for this application.

Over-voltage protection ensures the output voltage does

not rise to a level that could damage its load. When V_OUT

exceeds the regulation voltage by 15%, the PWM drive is

disabled. Switching does not resume until V_OUThas fallen

below the regulation voltage by 2%.

In addition to ensuring stability, the output capacitor

serves other important functions. This capacitor deter-

mines the output voltage ripple — as capacitance

increases, ripple voltage decreases. It also supplies current

during a large load step for a few switching cycles until

the control loop responds (typically 3 switching cycles).

Once the loop responds, regulation is restored and the

desired output is reached. During the period prior to PWM

operation resuming, the relationship between output

voltage and output capacitance can be approximated

using the equation

Current Limit

The SC202F switching stage is protected by a current limit

function. If the output load exceeds the PMOS current

limit for 32 consecutive switching cycles, the device enters

fold-back current limit mode and the output current is

limited to approximately 150mA. Under these conditions,

the output voltage will be the product of I_FB-LIMand the load

resistance. The load must fall below I_FB-LIMfor the device to

exit fold-back current limit mode. This function makes the

device capable of sustaining an indeﬁnite short circuit on

its output under fault conditions.

3u 'I_LOAD

V_DROOPu f

Thermal Shutdown

C_OUT

The SC202F has a thermal shutdown feature to protect the

device if the junction temperature exceeds 160°C. During

thermal shutdown, the PMOS and NMOS switches are

both disabled, tri-stating the LX output. When the junc-

tion temperature drops by the hysteresis value (20°C), the

device goes through the soft-start process and resumes

normal operation.

This equation can be used to approximate the minimum

output capacitance needed to ensure voltage does not

droop below an acceptable level. For example, a load step

from 50mA to 400mA requiring droop less than 50mV

would require the minimum output capacitance to be

Under-Voltage Lockout

3u0.4

C_OUT

6.0PF

0.05u3.5u10⁶

UVLO (Under-Voltage Lockout) activates when the supply

voltage drops below the falling UVLO threshold. This pre-

vents the device from entering an ambiguous state in

which regulation cannot be maintained. Hysteresis of

approximately 200mV is included to prevent chattering

near the threshold.

In this example, using a standard 10μF capacitor would be

adequate to keep voltage droop less than the desired

limit. Note that if the voltage droop limit were decreased

from 50mV to 25mV, the output capacitance would need

to be increased to at least 12μF (twice as much capaci-

tance for half the droop). Capacitance will decrease from

the nominal value when a ceramic capacitor is biased with

a DC current, so it is important to select a capacitor whose

value exceeds the necessary capacitance value at the pro-

grammed output voltage. Check the manufacturer’s

capacitance vs. DC voltage graphs when selecting an

C_OUTSelection

The internal voltage loop compensation in the SC202F

limits the minimum output capacitor value to 10ꢀF. This

is due to its inﬂuence on the loop crossover frequency,

phase margin, and gain margin. Increasing the output

12

SC202F

Applications Information (continued)

output capacitor to ensure the capacitance will be

adequate.

tor should be placed as closely as possible to the IN and

GND pins. Table 3 lists recommended input capacitor

options from diﬀerent manufacturers.

Table 2 lists the manufacturers of recommended output

capacitor options.

Table 3 — Recommended Input Capacitors

Rated

Dimensions

Manufacturer

Part Number

Value

(μF)

Table 2 — Recommended Output Capacitors

Type Voltage LxWxH (mm)

(VDC)

Case Size

Rated

Dimensions

Manufacturer

Part Number

Value

(μF)

Murata

GRM188R60J475K

1.6x0.8x0.8

0603

Type Voltage LxWxH (mm)

4.7 10%

10 10%

4.7 10%

X5R

6.3

(VDC)

Case Size

Murata

GRM188R60J106K

1.6x0.8x0.8

0603

Murata

GRM188R60J106ME47D

1.6x0.8x0.8

0603

6.3

10 20%

10 10%

10 20%

X5R

6.3

Taiyo Yuden

JMK107BJ475KA

1.6x0.8x0.8

0603

Murata

GRM21BR60J106K

2.0x1.25x1.25

0805

6.3

TDK

1.6x0.8x0.8

0603

Taiyo Yuden

JMK107BJ106MA-T

1.6x0.8x0.8

0603

6.3

C1608X5R0J475KT

TDK

1.6x0.8x0.8

0603

6.3

C1608X5R0J106MT

PCB Layout Considerations

The layout diagram in Figure 3 shows a recommended

PCB top-layer for the SC202F and supporting compo-

nents. Speciﬁed layout rules must be followed since the

layout is critical for achieving the performance speciﬁed in

the Electrical Characteristics table. Poor layout can

degrade the performance of the DC-DC converter and can

contribute to EMI problems, ground bounce, and resistive

voltage losses. Poor regulation and instability can also

result.

C_INSelection

The SC202F input source current will appear as a DC

supply current with a triangular ripple imposed on it. To

prevent large input voltage ripple, a low ESR ceramic

capacitor is required. A minimum value of 4.7ꢀF should

be used. It is important to consider the DC voltage coeﬃ-

cient characteristics when determining the actual required

value. For example, a 10ꢀF, 6.3V, X5R ceramic capacitor

with 5V DC applied may exhibit a capacitance as low as

4.5ꢀF. The value of required input capacitance is estimated

by determining the acceptable input ripple voltage and

calculating the minimum value required for C_INusing the

equation

The following guidelines are recommended for designing

a PCB layout:

1. C_INshould be placed as close to the IN and GND pins

as possible. This capacitor provides a low impedance

loop for the pulsed currents present at the buck

converter’s input. Use short wide traces to minimize

trace impedance. This will also minimize EMI and

input voltage ripple by localizing the high frequency

current pulses.

§

·

V_OUT

¨

¸

1ꢁ

V

IN

©

IN

¹

C_IN

§

·

'V

I_OUT

¨

¸

ꢁESR f

¸

©

¹

2.

C

_OUTshould be connected as closely as possible to the

The input voltage ripple is at maximum level when the

input voltage is twice the output voltage (50% duty cycle

scenario).

OUT pin.

3. Use a ground plane referenced to the GND pin. Use

several vias to connect to the component side ground

to further reduce noise and interference on sensitive

circuit nodes.

The input capacitor provides a low impedance loop for

the edges of pulsed current drawn by the PMOS switch.

Low ESR/ESL X5R ceramic capacitors are recommended

for this function. To minimize stray inductance, the capaci-

4. Route the output voltage feedback/sense trace

13

SC202F

Applications Information (continued)

be electrically

CTL1

connected to the PCB.

IN

(connected to the SNS pin) away from the LX node

as shown in Figure 2 to minimize noise and magnetic

interference.

CTL0

CTL3

C_IN

5. Minimize the resistance from the OUT and GND pins

to the load. This will reduce errors in DC regulation

due to voltage drops in the traces.

GND

SNS

3.5m m

SC202F

6. The two smaller exposed pads on this package should

not be connected to any traces. The area beneath

these two pads must be kept clear so that they do

not make electrical contact with any traces, including

ground.

LX

(no

connection

needed)

C_OUT

OUT

3.8m m

Figure 2 — Recommended PCB Layout

14

SC202F

Outline Drawing — MLPQ-13

15

SC202F

Land Pattern — MLPQ-13

16

SC202F

owner. The information presented in this document does not form part of any quotation or contract, is believed to be

accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any conse-

quence of its use. Publication thereof does not convey nor imply any license under patent or other industrial or

intellectual property rights. Semtech assumes no responsibility or liability whatsoever for any failure or unexpected

operation resulting from misuse, neglect improper installation, repair or improper handling or unusual physical or elec-

trical stress including, but not limited to, exposure to parameters beyond the speciﬁed maximum ratings or operation

outside the speciﬁed range.

SEMTECH PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-

SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF SEMTECH PRODUCTS

IN SUCH APPLICATIONS IS UNDERSTOOD TO BE UNDERTAKEN SOLELY AT THE CUSTOMER’S OWN RISK. Should a customer

purchase or use Semtech products for any such unauthorized application, the customer shall indemnify and hold

Semtech and its oﬃcers, employees, subsidiaries, aﬃliates, and distributors harmless against all claims, costs damages

and attorney fees which could arise.

Notice: All referenced brands, product names, service names and trademarks are the property of their respective

owners.

Contact Information

Semtech Corporation

Power Management Products Division

200 Flynn Road, Camarillo, CA 93012

Phone: (805) 498-2111 Fax: (805) 498-3804

www.semtech.com

17


型号：	SC202FMLTRT
厂家：	SEMTECH CORPORATION
描述：	3.5MHz, 500mA Step-down Regulator with Integrated Inductor
文件：	总17页 (文件大小：931K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

SC202FMLTRT [SEMTECH]

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