SC2446ITETRT [SEMTECH]
Dual-Phase Single or Two Output Synchronous Step-Down Controllers; 双相单或双输出同步降压型控制器型号: | SC2446ITETRT |
厂家: | SEMTECH CORPORATION |
描述: | Dual-Phase Single or Two Output Synchronous Step-Down Controllers |
文件: | 总38页 (文件大小:799K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
SC2446
Dual-Phase Single or Two Output
Synchronous Step-Down Controllers
POWER MANAGEMENT
Features
Description
2-Phase synchronous continuous conduction mode
for high efficiency step-down converters
Out of phase operation for low input current ripples
Output source and sink currents
Fixed frequency peak current-mode control
75mV/-110mV maximum current sense voltage
Synthesized MOSFET RDS(ON) current-sensing for
low-cost applications
The SC2446 is a high-frequency dual synchronous step-
down switching power supply controller. It provides out-
of-phase high-current output gate drives to all N-chan-
nel MOSFET power stages. The SC2446 operates in syn-
chronous continuous-conduction mode. Both phases are
capable of maintaining regulation with sourcing or sink-
ing load currents, making the SC2446 suitable for gen-
erating both VDDQ and the tracking VTT for DDR applica-
tions.
The SC2446 employs fixed frequency peak current-mode
control for the ease of frequency compensation and fast
transient response.
The dual-phase step-down controllers of the SC2446 can
be configured to provide two individually controlled and
regulated outputs or a single output with shared current
in each phase. The Step-down controllers operate from an
input of at least 4.7V and are capable of regulating out-
puts as low as 0.5V
The step-down controllers in the SC2446 have the pro-
vision to sense a synthesized MOSFET RDS(ON) for cur-
rent-mode control. This sensing scheme (U.S. patent
6,441,597) eliminates the need of the current-sense re-
sistor and is more noise-immune than direct sensing of
the high-side or the low-side MOSFET voltage. Precise cur-
rent-sensing with sense resistor is optional.
Individual soft-start and overload shutdown timer is in-
cluded in each step-down controller. The SC2446 imple-
ments hiccup overload protection. In two-phase single-
output configuration, the master timer controls the soft-
start and overload shutdown functions of both control-
lers.
Optional resistor current-sensing for precise current-
limit
Dual outputs or 2-phase single output operation
Excellent current sharing between individual phases
Wide input voltage range: 4.7V to 16V
Individual soft-start, overload shutdown and enable
Duty cycle up to 88%
0.5V feedback voltage for low-voltage outputs
External reference input for DDR applications
Buffered VDDQ/2 output
Programmable frequency up to 1 MHz per phase
External synchronization
Industrial temperature range
28-lead TSSOP - EDP package
Applications
Telecommunication power supplies
DDR memory power supplies
Graphic power supplies
Servers and base stations
Typical Application Circuit
VIN
C92
D11
D12
PVCC
Q21
Q22
BST2
BST1
R73
R74
GDH2
GDH1
VO2
VO1
L11
C93
C94
L12
C99
C95
Q23
Q24
C98
C100
CFILTER
RFILTER
R77
R78
CFILTER
RFILTER
+
+
GDL2
GDL1
PGND
VPN1
CS1+
C96
R75
R76
C97
R79
R81
R80
R82
VPN2
RCS+
RCS+
CS2+
RCS-
RCS-
CS2-
CS1-
IN2-
IN1-
C101
C103
C102
C105
COMP2
REFIN
VIN2
COMP1
REF
R83
REF
VIN
C104
R84
AGND
Rosc
SYNC
R85
SYNC
SS1/EN1
SS2/EN2
VIN
AVCC
REFOUT
C106
C107
C108
C109
U1
SC2446
Figure 1
Dual Independant Outputs
1
U.S. Patent No. 6,441,597, www.semtech.com
Revision: September 9, 2004
SC2446
POWER MANAGEMENT
Absolute Maximum Rating
Exceeding the specifications below may result in permanent damage to the device, or device malfunction. Operation outside of the parameters specified
in the Electrical Characteristics section is not implied.
Parameter
Symbol
AVCC, PVCC
VIN2
Maximum Ratings
-0.3 to 20
-0.3 to 20
-0.3 to 32 (steady state)
Units
V
V
Supply Voltage For Step-Down Controllers
Input Voltage For the Second Converter
High-Side Driver Supply Voltages
VBST1,VBST2
V
-0.3 to 40
(for <10ns @ freq. < 500kHz)
VPN
-0.3 to 20 (steady state)
VVPN
V
-0.3 to 26
(for <10ns @ freq. < 500kHz)
IN1-, IN2- Voltages
REF, REFOUT Voltages
REFIN Voltage
COMP1, COMP2 Voltages
CS1+, CS1-, CS2+ and CS2- Voltages
SYNC Voltage
VIN1-,VIN2-
VREF ,VREFOUT
VREFIN
-0.3 to AVCC+0.3
V
V
V
V
V
V
V
-0.3 to 6
-0.3 to AVCC+0.3
-0.3 to AVCC+0.3
-0.3 to AVCC+0.3
-0.3 to AVCC+0.3
-0.3 to 6
VCOMP1,VCOMP2
VCS1+,VCS1-,VCS2+,VCS2-
VSYNC
SS1/EN1 AND SS2/EN2 Voltages
VSS1,VSS2
Peak Gate Drive Currents
Peak VPN1 and VPN2 Output Currents
Ambient Temperature Range
Thermal Resistance Junction to Case (TSSOP-28)
Thermal Resistance Junction to Ambient (TSSOP-28)
Storage Temperature Range
Lead Temperature (Soldering) 10 sec
Maximum Junction Temperature
I
GDH1, IGDH2, IGDL1, IGDL2
IVPN1, IVPN2
TA
3
100
-40 to 85
13
A
mA
°C
°C/W
°C/W
°C
θJC
84
θJA
TSTG
TLEAD
TJ
-60 to 150
260
°C
°C
150
Electrical Characteristics
Unless specified: AVCC = PVCC = VIN2 =12V, VBST1 = VBST2 = 12V, SYNC= 0, ROSC = 51.1kΩ, -40°C < TA = TJ < 85°C
Parameter
Symbol
Conditions
Min
Typ
Max
Units
Undervoltage Lockout
AVCC Start Threshold
AVCC Start Hysteresis
AVCC Operating Current
AVCCTH
AVCCHYST
ICC
4.5
0.17
12
4.7
V
AVCCIncreasing
V
AVCC= 12V
16
mA
mA
AVCC Quiescent Current in UVLO
Channel 1 Error Amplifier
Non-inverting Input Voltage
Non-inverting Input Line Regulation
Input Offset Voltage
AVCC = AVCCTH - 0.2V
1.7
VIN1+
0.490
0.500
0.510
0.02
±3
V
AVCCTH < AVCC< 15V
%/V
mV
nA
1
-100
Inverting Input Bias Current
IIN1-
-250
µΩ−1
Amplifier Transconductance
Amplifier Open-Loop Gain
Amplifier Unity Gain Bandwidth
GM1
aOL1
260
65
5
dΒ
ΜΗz
V
CS1+ = VCS1- = 0
Minimum COMP1 Switching Threshold
2.2
V
VSS1 Increasing
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2
SC2446
POWER MANAGEMENT
Electrical Characteristics (Cont.)
Unless specified: AVCC = PVCC = VIN2 =12V, VBST1 = VBST2 = 12V, SYNC= 0, ROSC = 51.1kΩ, -40°C < TA = TJ < 85°C
Parameter
Symbol
Conditions
Min
Typ
Max
Units
Amplifier Output Sink Current
Amplifier Output Source Current
Channel 2 Error Amplifier
Input Common-mode Voltage Range
Inverting Input Voltage Range
Input Offset Voltage
VIN1- = 1V, VCOMP1 = 2.5V
VIN1- = 0, VCOMP1 = 2.5V
16
12
µA
µA
(Note 1)
(Note 1)
0
0
3
V
V
mV
nA
nA
AVCC
±3
-380
-250
1.5
-150
-100
Non-inverting Input Bias Current
Inverting Input Bias Current
IIN2+
IIN2-
Inverting Input Voltage for 2-Phase Single
2.5
V
Output Operation
µΩ−1
Amplifier Transconductance
Amplifier Open-Loop Gain
Amplifier Unity Gain Bandwidth
GM2
aOL2
260
65
5
dΒ
MHz
V
= VCS2- = 0
VCSSS22+Increasing
VCOMP2 = 2.5V
Minimum COMP2 Switching Threshold
2.2
V
Amplifier Output Sink Current
Amplifier Output Source Current
Oscillator
16
12
µA
µA
VCOMP2 = 2.5V
Channel Frequency
f
CH1, fCH2
450
2.1fCH
1.5
500
550
0.5
KHz
KHz
V
Synchronizing Frequency
SYNC Input High Voltage
SYNC Input Low Voltage
(Note 1)
V
V
= 0.2V
1
VSSYYNNCC = 2V
100
SYNC Input Current
ISYNC
DMAX1, DMAX2
µA
Channel Maximum Duty Cycle
Channel Minimum Duty Cycle
Current-limit Comparators
Input Common-Mode Range
88
%
%
DMIN1, DMIN2
0
V
0
AVCC - 1
90
VILIM1+,
VILIM2+
VCS1- = V = 0.5V,
SourcingCMS2o- de
Cycle-by-cycle Peak Current Limit
60
75
mV
Valley Current Overload Shutdown
Threshold
VCS1- = VCS2- = 0.5V,
VILIM1-, VILIM2-
-85
-110
-0.7
-0.7
-130
-2
mV
µA
µA
Sinking Mode
V
= VCS1- = 0
VCCSS21+- = VCS2- = 0
Positive Current-Sense Input Bias Current
ICS1+, ICS2+
CS1-, ICS2-
Negative Current-Sense Input Bias
Current
V
= VCS1- = 0
VCCSS21++ = VCS2- = 0
I
-2
Gate Drivers
High-side Gate Drive Peak Source
VBST1 ,VBST2 = 12V
1.5
1
A
A
Current
High-side Gate Drive Peak Sink Current
VBST1 ,VBST2 = 12V
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SC2446
POWER MANAGEMENT
Electrical Characteristics (Cont.)
Unless specified: AVCC = PVCC = VIN2 =12V, VBST1 = VBST2 = 12V, SYNC= 0, ROSC = 51.1kΩ, -40°C < TA = TJ < 85°C
Parameter
Symbol
Conditions
Min
Typ
Max
Units
Low-side Gate Drive Peak Source
AVCC = PVCC =12V
1.5
A
Current
Low-side Gate Drive Peak Sink Current
AVCC = PVCC =12V
CL = 2200pF
1
A
Gate Drive Rise Time
Gate Drive Fall Time
20
20
ns
ns
CL = 2200pF
Low-side Gate Drive to High-side Gate
Drive Non-overlapping Delay
CL = 0
90
ns
High-side Gate Drive to Low-side Gate
CL = 0
90
ns
ns
Drive Non-overlapping Delay
Minimum On-Time
TA = 25°C
150
Soft-Start, Overload Latchoff and Enable
Soft-Start Charging Current
I
SS1, ISS2
VSS1 = VSS2 = 1.5V
2
µA
V
Overload Latchoff Enabling Soft-Start
Voltage
VSS1 and VSS2 Increasing
VSS1 = 3.8V, VIN1-Decreasing
VSS2 = 3.8V, VIN2-Decreasing
3.2
Overload Latchoff IN1- Threshold
0.75VREF
V
0.72 X
VREFIN
Overload Latchoff IN2- Threshold
V
VIN1-= 0.5VREF
VSINS21- = VSS2 = 3.8V
,
ISS1(DIS),
ISS2(DIS)
Soft-Start Discharge Current
V
= 0.5VREFIN
,
1.4
µA
Overload Latchoff Recovery Soft-Start
Voltage
Gate Drive Disable SS/EN Voltage
VSSRCV1,
VSSRCV2
VSS1 and VSS2 Decreasing
0.3
0.7
0.5
0.7
1.5
V
0.9
1.2
V
V
Gate Drive Enable SS/EN Voltage
Channel 1 Virtual Phase Node Voltage
Output High Voltage
VVPN1H
VVPN1L
IVPN1= -100µA, VBST1= 24V
IVPN1= 100µA, VBST1= 24V
VPVCC-0.05
V
Output Low Voltage
20
mV
V
BST1= 24V,
Output Sourcing Current
7
7
mA
mA
VVPN1= VPVCC - 0.2V
Output Sinking Current
VBST1= 24V, VVPN1= 0.2V
Channel 2 Virtual Phase Node Voltage
Output High Voltage
VVPN2H
VVPN2L
IVPN2= -100µA, VBST2= 24V
IVPN2= 100µA, VBST2= 24V
VIN2 - 0.05
V
Output Low Voltage
20
mV
V
BST2= 24V,
Output Sourcing Current
Output Sinking Current
7
7
mA
mA
VVPN2= VIN2 - 0.2V
VBST2= 24V, VVPN2= 0.2V
External Reference Buffer
External Reference Input Voltage Range
Buffered Output Voltage
VREFIN
0
4
V
V
VREFIN -0.01
VREFIN +0.01
VREFOUT
VREFIN=1.25V, IREFOUT= -1mA
VREFIN
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SC2446
POWER MANAGEMENT
Electrical Characteristics (Cont.)
Unless specified: AVCC = PVCC = VIN2 =12V, VBST1 = VBST2 = 12V, SYNC= 0, ROSC = 51.1kΩ, -40°C < TA = TJ < 85°C
Parameter
Symbol
Conditions
Min
Typ
Max
Units
Load Regulation
0 < IREFOUT < -5mA
0.02
%/mA
Internal 0.5V Reference Buffer
Output Voltage
VREF
IREF= -1mA
490
500
510
mV
Load Regulation
0 < IREF < -5mA
0.05
%/mA
Notes:
(1) Guaranteed by design not tested in production.
(2) This device is ESD sensitive. Use of standard ESD handling precautions is required.
Pin Configurations
Ordering Information
(TOP VIEW)
Device
SC2446ITETRT(2) TSSOP-28-EDP
Package(1)
Temp. Range( TA)
CS1+
CS1-
SS1/EN1
VPN1
-40 to 85°C
BST1
ROSC
IN1-
SC2446EVB
Evaluation Board
GDH1
GDL1
PVCC
COMP1
Notes:
SYNC
AGND
REF
(1) Only available in tape and reel packaging. A reel
contains 2500 devices for TSSOP package.
(2) Lead free product.
PGND
GDL2
GDH2
REFOUT
REFIN
BST2
COMP2
IN2-
VPN2
VIN2
CS2-
AVCC
CS2+
SS2/EN2
(28-Pin TSSOP)
Figure 2
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SC2446
POWER MANAGEMENT
Pin Descriptions
TSSOP Package
Pin
Pin Name
Pin Function
1
CS1+
The Non-inverting Input of the Current-sense Amplifier/Comparator for the Controller 1.
The Inverting Input of the Current-sense Amplifier/Comparator for the Controller 1. Normally
tied to the output of the converter.
2
3
4
CS1-
ROSC
IN1-
An external resistor connected from this pin to GND sets the oscillator frequency.
Inverting Input of the Error Amplifier for the Step-down Controller 1. Tie an external resistive
divider between OUTPUT1 and the ground for output voltage sensing.
The Error Amplifier Output for Step-down Controller 1. This pin is used for loop
compensation.
5
6
COMP1
SYNC
Edge-triggered Synchronization Input. When not synchronized, tie this pin to a voltage above
1.5V or the ground. An external clock (frequency > frequency set with ROSC) at this pin
synchronizes the controllers.
7
8
AGND
REF
Analog Signal Ground.
Buffered Output of the Internal 0.5V Reference. The non-inverting input of the error amplifier
for the step-down converter 1 is internally connected to this pin .
9
REFOUT
REFIN
Buffered output of the external voltage applied to Pin 10.
An external Reference voltage is applied to this pin.The non-inverting input of the error
amplifier for the step-down converter 2 is internally connected to this pin.
10
The Error Amplifier Output for Step-down Controller 2. This pin is used for loop
compensation.
11
12
COMP2
IN2-
Inverting Input of the Error Amplifier for the Step-down Controller 2. Tie an external resistive
divider between output2 and the ground for output voltage sensing. Tie to AVCC for two-phase
single output applications
The Inverting Input of the Current-sense Amplifier/Comparator for the Controller 2. Normally
tied to the output of the converter.
13
14
CS2-
CS2+
The Non-inverting Input of the Current-sense Amplifier/Comparator for the Controller 2
An external capacitor tied to this pin sets (i) the soft-start time (ii) output overload latch off
time for step-down converter 2. Pulling this pin below 0.7V shuts off the gate drivers for the
second controller. Leave open for two-phase single output applications.
15
SS2/EN2
16
17
AVCC
VIN2
Power Supply Voltage for the Analog Portion of the Controllers.
This pin is tied to the voltage supplying the drain of the high side power MOSFET of converter
2. This pin is used only in "Combi" current sense.
The Second Step-down Converter Virtual Phase Node (Unloaded). Used for "Combi" current
sense only. This pin is left open when sensing current with a sense resistor at the converter
output.
18
VPN2
Bootstrapped Supply for the High-side Gate Drive 2. Connect to a bootstrap capacitor and an
external diode as described in application information.
19
20
BST2
Gate Drive Output for the High-side N-channel MOSFET of Output 2. Gate drive voltage
swings from ground to VBST2.
GDH2
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SC2446
POWER MANAGEMENT
Pin Descriptions
Pin
Pin Name
Pin Function
Gate Drive Output for the Low-side N-channel MOSFET of Output 2. Gate drive voltage
swings from ground to PVCC.
21
GDL2
22
23
PGND
PVCC
Ground Supply for All the Gate drivers.
Power Supply Voltage for Low-side MOSFET Drivers.
Gate Drive Output for the Low-side N-channel MOSFET of Output 1. Gate drive voltage
swings from ground to PVCC.
24
25
26
GDL1
GDH1
BST1
Gate Drive Output for the High-side N-channel MOSFET of Output 1. Gate drive voltage
swings from ground to VBST1.
Bootstrapped Supply for the High-side Gate Drive 1. Connect to a bootstrap capacitor and an
external diode as described in application information.
The First Step-down Converter Virtual Phase Node (Unloaded). Used for "Combi" current
sense only. This pin is left open when sensing current with a sense resistor at the converter
output.
27
28
VPN1
An external capacitor tied to this pin sets (i) the soft-start time (ii) output overload latch off
time for buck converter 1. Pulling this pin below 0.7V shuts off the gate drivers for the first
controller.
SS1/EN1
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SC2446
POWER MANAGEMENT
Block Diagram
SYNC
6
AVCC
16
CLK2
CLK1
REFERENCE
OSCILLATOR
ROSC
3
COMP1
5
UVLO
4.3/4.5V
BST1
26
GDH1
25
IN1-
4
-
R
S
EA1
REF/IN1+
8
-
Q
PWM
Non-Overlapping
Conduction
Control
+
PVCC
23
GDL1
24
+
0.5V
+
UVLO
-
0.75 VREF
VPN1
27
SLOPE
COMP
CS1+
1
OL
Soft-Start And
Overload
Hiccup
+
PGND
22
+
-
+
DSBL
CS1-
2
ISEN
Σ
SS1/EN1
Control
28
+
ILIM+
-
-
GDH2
20
75mV
OCN
VIN2
17
VPN2
18
ILIM-
+
110mV
COMP2
11
IN2-
12
-
+
EA2
GDL2
21
REF /IN2+
IN
10
+
-
REFOUT
9
0.72 VREFOUT
AGND
7
Figure 3. SC2446 Block Diagram (Channel 1 PWM Control Only)
OCN
IN-
-
S
0.75(VREF
/ 0.72(VREFOUT
)
+
2µΑ
OL
Q
)
R
SS/EN
UVLO
0.5V/3.2V
0.9V/1.2V
DSBL
3.4µΑ
Figure 4. Soft-Start and Overload Hiccup Control Circuit
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SC2446
POWER MANAGEMENT
Operation
Overview
The SC2446 is a constant frequency 2–phase current-
mode step-down PWM switching controller driving all N-
channel MOSFET’s. The two channels of the controller
operate at 180 degrees out of phase from each other.
Since input currents are interleaved in a two-phase
converter, input ripple current is lower and smaller input
capacitor can be used for filtering. Also, with lower
inductor current and smaller inductor ripple current per
phase, overall I2R losses are reduced.
inductor current reaches the threshold determined by
the error amplifier output and ramp compensation, the
high-side MOSFET is turned off. After a non-overlapping
conduction time of 90ns, the low-side MOSFET is turned
on.
The supply voltages for the high-side gate drivers are
obtained from two diode-capacitor bootstrap circuits. If the
bootstrap capacitor is charged from VCC, the high-side gate
drive voltage swing will be from approximately 2VCC to the
ground. The power dissipated in the high-side gate driver
is not higher with higher voltage swing because the gate-
source voltage of the high-side MOSFET still swing from
zero to VCC.The outputs of the low-side gate drivers swing
from VC to the ground.
The SC2446 operates in synchronous continuous-
conduction mode. It can be configured either as two
independent step-down controllers producing two
separate outputs or as a dual-phase single-output
controller by tying the IN2- pin to VCC. In single output
operation, the channel one error amplifier controls both
channels and the channel two error amplifier is disabled.
Soft-start and overload hiccup of both channels is
synchronized to channel one.
The SC2446 has internal ramp-compensation to prevent
sub-harmonic oscillation when operating above 50% duty
cycle. There is enough ramp internally for a sensed
voltage ripple between ¼ to 1/3 of the full-scale sensed
voltage limit of 75mV. The maximum sensed voltage limit
is unaffected by the compensation ramp.
Frequency Setting and Synchronization
The internal oscillator of the SC2446 runs at twice the
phase frequency. The free-running frequency of the
oscillator can be programmed with an external resistor
from the ROSC pin to the ground. The step-down controllers
are capable of operating up to 1 MHz. It is necessary to
consider the operating duty-ratio before deciding the
switching frequency. See Applications Information section
for more details.
Current-Sensing
There are two ways to sense the inductor current for
current-mode control with the SC2446. Since the peak
inductor current corresponds to 75mV of sensed voltage
(CS+ - CS-), resistor current sensing can be used at the
output without resulting in excessive power dissipation.
Although accurate and far easier to lay out than high-
side resistor sensing, a pair of precision sense resistors
adds cost to the converter. The SC2446 has provision to
reconstruct a differential voltage proportional to the
inductor current at the output of the converter (U.S. patent
6,441,597). The voltage to current ratio or the equivalent
sense resistance Req is a combination of high-side and low-
side MOSFET RDS(ON) ’s and the inductor series resistance
(hence the name “Combi-Sense”). The SC2446 provides
the virtual phase voltages VPN1 and VPN2 (these are
When synchronized externally, the applied clock frequency
should be twice the desired phase frequency. The
synchronizing clock frequency should also be between 1-
1.33 times the set free-running frequency.
Control Loop
The SC2446 uses peak current-mode control for fast
transient response, ease of compensation and current
sharing in single output operation. The low-side MOSFET
of each channel is turned off at the falling-edge of the
phase timing clock. After a brief non-overlapping time
interval of 90ns, the high-side MOSFET is turned on. The
phase inductor current ramps up. When the sensed
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SC2446
POWER MANAGEMENT
Operation (Cont.)
unloaded versions of their respective power phase
voltages) for current sensing. This method does not
require any precision sense resistor. It is cheaper to
implement but is less accurate than resistor current
sensing. Since the sensed voltage is developed at the
output of the step-down converter, it is less prone to
Soft-Start and Overload Protection
The undervoltage lockout circuit discharges the SS/EN
capacitors. After VCC rises above 4.5V, the SS/EN capacitors
are slowly charged by internal 2µA current source. With
internal PNP transistors, the SS/EN voltages clamp the
switching transient spikes. This method will be described error amplifier outputs. When the error amplifier output
in more details in the Applications Information section.
rises to 2.2V, the high-side MOSFET starts to switch. As
the SS/EN capacitor continues to be charged, the COMP
voltage follows. The converter gradually delivers increasing
power to the output. The inductor current follows the COMP
Error Amplifiers
In closed loop operation, the error amplifier output ranges voltage envelope until the output goes into regulation. The
from 1.1V to 3.5V. The upper output operating range of SS/EN clamp on COMP is then released.
either error amplifier is reserved for positive current-
sense voltage (CS+ - CS-) and corresponds to positive After the SS/EN capacitor is charged above 3.2V (high
(sourcing) output current. If the amplifier swings to its enough for the error amplifier to provide full load current),
lower operating range, the amplifier will still modulate the overload detection circuit is activated. If the output
the high-side gate drive duty-ratio. However the peak voltage falls below 70% of its set value or the valley
current-sense voltage (hence the peak inductor current) current-sense voltage exceeds –110mV, an overload latch
will be limited to a negative value. The error amplifier will be set and both the top and the bottom MOSFETs will
output is about 2.2V when the peak sense-voltage is zero. be turned off. The SS/EN capacitor is slowly discharged
The built-in offset in the current sense amplifier together
with an internal 1.4µA current sink. The overload latch is
with synchronous continuous-conduction mode of
operation allows the SC2446 to regulate the output
irrespective of the direction of the load current.
reset when the SS/EN capacitor is discharged below 0.5V.
The SS/EN capacitor is then recharged with the 2µA current
source and the converter undergoes soft-start. If overload
persists, the SC2446 will undergo repetitive shutdown and
restart (Figure 3).
The non-inverting input of the first feedback amplifier is
tied to the internal 0.5V voltage reference. Both the non-
inverting and the inverting inputs of the second error
amplifier are brought out as device pins so that the output
of the second converter can be made to track the output
of the first channel. For example in DDR applications,
Channel 1 can be used to generate VDDQ (2.5V) from the
input (5V or 12V) and channel 2 is used to produce a
tracking VTT (1.25V) with VDDQ being its input.
If the output is short-circuited, the inductor current will
not increase indefinitely between the time the inductor
current reaching its current limit and the instant the
converter shuts down. This is due to cycle skipping
reduces the actual operating frequency.
The SS/EN pin can also be used as the enable input for
that channel. Both the high-side and the low-side
MOSFETs will be turned off if the SS/EN pin is pulled
below 0.7V.
Current-Limit
The maximum current sense voltage of +75mV is the
cycle-by-cycle peak current limit when the load is drawing
current from the converter. There is no cycle-by-cycle
current limiting when the inductor current flows in the
negative direction. However once the valley of the current
sense voltage exceeds –110mV, the corresponding
channel will undergo shutdown and restart (hiccup).
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10
SC2446
POWER MANAGEMENT
Application Information
SC2446 consists of two current-mode synchronous buck
controllers with many integrated functions. By proper
application circuitry configuration, SC2446 can be used
to generate
1) two independent outputs from a common input or two
different inputs or
1) Passive component size
2) Circuitry efficiency
3) EMI condition
4) Minimum switch on time and
5) Maximum duty ratio
2) dual phase output with current sharing,
3) current sourcing/sinking from common or separate
inputs as in DDR (I and II) memory application.
The application information related to the converter design
using SC2446 is described in the following.
For a given output power, the sizes of the passive
components are inversely proportional to the switching
frequency, whereas MOSFET’s/Diodes switching losses are
proportional to the operating frequency. Other issues such
as heat dissipation, packaging and the cost issues are
also to be considered. The frequency bands for signal
transmission should be avoided because of EM
interference.
Step-down Converter
Starting from the following step-down converter
specifications,
Minimum Switch On Time Consideration
Input voltage range: V [Vin,min,V
Input voltage ripple (peak-to-peak): ∆Vin
Output voltage: Vo
]
in
in,max
In the SC2446 the falling edge of the clock turns on the
top MOSFET. The inductor current and the sensed voltage
ramp up. After the sensed voltage crosses a threshold
determined by the error amplifier output, the top MOSFET
is turned off. The propagation delay time from the turn-
on of the controlling FET to its turn-off is the minimum
switch on time. The SC2446 has a minimum on time of
about 150ns at room temperature. This is the shortest
on interval of the controlling FET. The controller either does
not turn on the top MOSFET at all or turns it on for at least
150ns.
For a synchronous step-down converter, the operating duty
cycle is VO/VIN. So the required on time for the top MOSFET
is VO/(VINfs). If the frequency is set such that the required
pulse width is less than 150ns, then the converter will
start skipping cycles. Due to minimum on time limitation,
simultaneously operating at very high switching frequency
and very short duty cycle is not practical. If the voltage
conversion ratio VO/VIN and hence the required duty cycle
is higher, the switching frequency can be increased to reduce
the sizes of passive components.
Output voltage accuracy: ε
Output voltage ripple (peak-to-peak): ∆Vo
Nominal output (load) current: Io
Maximum output current limit: Io,max
Output (load) current transient slew rate: dIo (A/s)
Circuit efficiency: η
Selection criteria and design procedures for the following
are described.
1) output inductor (L) type and value,
2) output capacitor (Co) type and value,
3) input capacitor (Cin) type and value,
4) power MOSFET’s,
5) current sensing and limiting circuit,
6) voltage sensing circuit,
7) loop compensation network.
Operating Frequency (fs)
The switching frequency in the SC2446 is user-
programmable. The advantages of using constant
frequency operation are simple passive component
selection and ease of feedback compensation. Before
setting the operating frequency, the following trade-offs
should be considered.
There will not be enough modulation headroom if the on
time is simply made equal to the minimum on time of the
SC2446. For ease of control, we recommend the required
pulse width to be at least 1.5 times the minimum on time.
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11
SC2446
POWER MANAGEMENT
Application Information (Cont.)
Setting the Switching Frequency
The followings are to be considered when choosing
inductors.
a) Inductor core material: For high efficiency applications
above 350KHz, ferrite, Kool-Mu and polypermalloy
materials should be used. Low-cost powdered iron cores
can be used for cost sensitive-applications below 350KHz
but with attendant higher core losses.
The switching frequency is set with an external resistor
connected from Pin 3 to the ground. The set frequency
is inversely proportional to the resistor value (Figure 5).
b) Select inductance value: Sometimes the calculated
inductance value is not available off-the-shelf. The
designer can choose the adjacent (larger) standard
inductance value. The inductance varies with
temperature and DC current. It is a good engineering
practice to re-evaluate the resultant current ripple at
the rated DC output current.
c) Current rating: The saturation current of the inductor
should be at least 1.5 times of the peak inductor current
under all conditions.
800
700
600
500
400
300
200
100
0
0
50
100
150
200
250
Output Capacitor (Co) and Vout Ripple
Rosc (k Ohm)
The output capacitor provides output current filtering in
steady state and serves as a reservoir during load transient.
The output capacitor can be modeled as an ideal capacitor
in series with its parasitic ESR (Resr) and ESL (Lesl) (Figure
6).
Figure 5. Free running frequency vs. ROSC
.
Inductor (L) and Ripple Current
Both step-down controllers in the SC2446 operate in
synchronous continuous-conduction mode (CCM) regardless
of the output load. The output inductor selection/design
is based on the output DC and transient requirements.
Both output current and voltage ripples are reduced with
larger inductors but it takes longer to change the inductor
current during load transients. Conversely smaller inductors
results in lower DC copper losses but the AC core losses
(flux swing) and the winding AC resistance losses are
higher. A compromise is to choose the inductance such
that peak-to-peak inductor ripple-current is 20% to 30% of
the rated output load current.
Co
Lesl
Resr
Figure 6. An equivalent circuit of Co.
If the current through the branch is ib(t), the voltage across
the terminals will then be
Assuming that the inductor current ripple (peak-to-peak)
value is δ*Io, the inductance value will then be
t
1
Co
dib(t)
dt
Vo (1− D)
δIofs
vo (t) = Vo +
ib(t)dt + Lesl
+ Resrib(t).
∫
L =
.
0
This basic equation illustrates the effect of ESR, ESL and
Co on the output voltage.
The peak current in the inductor becomes (1+δ/2)*Io
and the RMS current is
δ2
The first term is the DC voltage across Co at time t=0. The
second term is the voltage variation caused by the charge
balance between the load and the converter output. The
IL,rms = Io 1+
.
12
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12
SC2446
POWER MANAGEMENT
Application Information (Cont.)
should be an order of magnitude smaller than the voltage
ripple caused by the ESR. To guarantee this, the
capacitance should satisfy
third term is voltage ripple due to ESL and the fourth
term is the voltage ripple due to ESR. The total output
voltage ripple is then a vector sum of the last three
terms.
10
Co >
.
2πfsResr
Since the inductor current is a triangular waveform with
peak-to-peak value δ*Io, the ripple-voltage caused by
inductor current ripples is
In many applications, several low ESR ceramic capacitors
are added in parallel with the aluminum capacitors in
order to further reduce ESR and improve high frequency
decoupling. Because the values of capacitance and ESR
are usually different in ceramic and aluminum capacitors,
the following remarks are made to clarify some practical
issues.
δIo
8Cofs
∆vC ≈
,
the ripple-voltage due to ESL is
δIo
D
∆vESL = Leslfs
,
Remark 1: High frequency ceramic capacitors may not carry
most of the ripple current. It also depends on the capacitor
value. Only when the capacitor value is set properly, the
effect of ceramic capacitor low ESR starts to be significant.
For example, if a 10µF, 4mΩ ceramic capacitor is
connected in parallel with 2x1500µF, 90mΩ electrolytic
capacitors, the ripple current in the ceramic capacitor is
only about 42% of the current in the electrolytic capacitors
at the ripple frequency. If a 100µF, 2mΩ ceramic capacitor
is used, the ripple current in the ceramic capacitor will be
about 4.2 times of that in the electrolytic capacitors. When
two 100µF, 2mΩ ceramic capacitors are used, the current
ratio increases to 8.3. In this case most of the ripple
current flows in the ceramic decoupling capacitor. The ESR
of the ceramic capacitors will then determine the output
ripple-voltage.
and the ESR ripple-voltage is
∆vESR = Resr δIo.
Aluminum capacitors (e.g. electrolytic, solid OS-CON,
POSCAP, tantalum) have high capacitances and low ESL’s.
The ESR has the dominant effect on the output ripple
voltage. It is therefore very important to minimize the ESR.
When determining the ESR value, both the steady state
ripple-voltage and the dynamic load transient need to be
considered. To keep the steady state output ripple-voltage
< ∆Vo, the ESR should satisfy
∆Vo
δIo
Resr1
<
.
To limit the dynamic output voltage overshoot/undershoot
within α (say 3%) of the steady state output voltage) from
no load to full load, the ESR value should satisfy
Remark 2: The total equivalent capacitance of the filter
bank is not simply the sum of all the paralleled capacitors.
The total equivalent ESR is not simply the parallel
combination of all the individual ESR’s either. Instead they
should be calculated using the following formulae.
αVo
Resr2
<
.
Io
Then, the required ESR value of the output capacitors
should be
2
2
(R1a + R1b )2 ω2C1a C1b + (C1a + C1b )2
Ceq(ω) :=
Req(ω) :=
Resr = min{Resr1,Resr2 }.
2
2
(R1a C1a + R1b C1b )ω2C1aC1b + (C1a + C1b )
The voltage rating of aluminum capacitors should be at
least 1.5Vo. The RMS current ripple rating should also be
greater than
2
2
2
2
R1aR1b(R1a + R1b )ω2C1a C1b + (R1bC1b + R1aC1a
)
2
2
(R1a + R1b )2 ω2C1a C1b + (C1a + C1b )2
δIo
2 3
.
where R1a and C1a are the ESR and capacitance of
electrolytic capacitors, and R1b and C1b are the ESR and
capacitance of the ceramic capacitors respectively. (Figure
7)
Usually it is necessary to have several capacitors of the
same type in parallel to satisfy the ESR requirement. The
voltage ripple cause by the capacitor charge/discharge
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13
SC2446
POWER MANAGEMENT
Application Information (Cont.)
C1a
C1b
Ceq
R1a
R1b
Req
Figure 7. Equivalent RC branch.
Req and Ceq are both functions of frequency. For rigorous
design, the equivalent ESR should be evaluated at the
ripple frequency for voltage ripple calculation when both
ceramic and electrolytic capacitors are used. If R1a = R1b =
R1 and C1a = C1b = C1, then Req and Ceq will be frequency-
independent and
Figure 9. Typical waveforms at converter input.
It can be seen that the current in the input capacitor pulses
with high di/dt. Capacitors with low ESL should be used. It
is also important to place the input capacitor close to the
MOSFET’s on the PC board to reduce trace inductances
around the pulse current loop.
Req = 1/2 R1 and Ceq = 2C1.
Input Capacitor (Cin)
The input supply to the converter usually comes from a
pre-regulator. Since the input supply is not ideal, input
capacitors are needed to filter the current pulses at the
switching frequency. A simple buck converter is shown in
Figure 8.
The RMS value of the capacitor current is approximately
δ2
ICin = Io D[(1+ )(1− )2 +
D
η
D
(1−D)].
η2
12
The power dissipated in the input capacitors is then
2
PCin = ICin Resr.
For reliable operation, the maximum power dissipation in
the capacitors should not result in more than 10oC of
temperature rise. Many manufacturers specify the
maximum allowable ripple current (ARMS) rating of the
capacitor at a given ripple frequency and ambient
temperature. The input capacitance should be high enough
to handle the ripple current. For higher power applications,
multiple capacitors are placed in parallel to increase the
ripple current handling capability.
Figure 8. A simple model for the converter input
In Figure 8 the DC input voltage source has an internal
impedance Rin and the input capacitor Cin has an ESR of
Resr. MOSFET and input capacitor current waveforms, ESR
voltage ripple and input voltage ripple are shown in Figure
9.
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14
SC2446
POWER MANAGEMENT
Application Information (Cont.)
2
2
ICin ≈ 0.5Io1 + D2(Io1 +Io2 )2 + (D1 − D2 − 0.5)Io2
.
Sometimes meeting tight input voltage ripple
specifications may require the use of larger input
capacitance. At full load, the peak-to-peak input voltage
ripple due to the ESR is
If D1>0.5 and D2 > 0.5, then
δ
∆vESR = Resr (1+ )Io.
2
2
2
ICin ≈ (D1 + D2 −1)(Io1 + Io2 )2 + (1−D2 )Io1 + (1−D1)Io2
.
The peak-to-peak input voltage ripple due to the capacitor
is
Choosing Power MOSFET’s
DIo
Cinfs
Main considerations in selecting the MOSFET’s are power
dissipation, cost and packaging. Switching losses and
conduction losses of the MOSFET’s are directly related to
the total gate charge (Cg) and channel on-resistance
(Rds(on)). In order to judge the performance of MOSFET’s,
the product of the total gate charge and on-resistance is
used as a figure of merit (FOM). Transistors with the same
FOM follow the same curve in Figure 10.
∆vC
≈
,
From these two expressions, CIN can be found to meet the
input voltage ripple specification. In a multi-phase
converter, channel interleaving can be used to reduce ripple.
The two step-down channels of the SC2446 operate at
180 degrees from each other. If both step-down channels
in the SC2446 are connected in parallel, both the input
and the output RMS currents will be reduced.
50
40
Ripple cancellation effect of interleaving allows the use of
smaller input capacitors. When converter outputs are
connected in parallel and interleaved, smaller inductors
and capacitors can be used for each channel. The total
output ripple-voltage remains unchanged. Smaller
inductors speeds up output load transient.
Cg(100, Rds)
Cg(200, Rds)
20
Cg(500, Rds)
1
0
0
1
5
10
Rds
15
20
20
When two channels with a common input are interleaved,
the total DC input current is simply the sum of the individual
DC input currents. The combined input current waveform
depends on duty ratio and the output current waveform.
Assuming that the output current ripple is small, the
following formula can be used to estimate the RMS value
of the ripple current in the input capacitor.
On-resistance (mOhm)
FOM:100*10^{-12}
FOM:200*10^{-12}
FOM:500*10^{-12}
Figure 10. Figure of Merit curves.
The closer the curve is to the origin, the lower is the FOM.
This means lower switching loss or lower conduction loss
or both. It may be difficult to find MOSFET’s with both low
Cg and low Rds(on. Usually a trade-off between Rds(on and Cg
has to be made.
Let the duty ratio and output current of Channel 1 and
Channel 2 be D1, D2 and Io1, Io2, respectively.
If D1<0.5 and D2<0.5, then
MOSFET selection also depends on applications. In many
applications, either switching loss or conduction loss
dominates for a particular MOSFET. For synchronous buck
converters with high input to output voltage ratios, the top
MOSFET is hard switched but conducts with very low duty
cycle. The bottom switch conducts at high duty cycle but
switches at near zero voltage. For such applications,
MOSFET’s with low Cg are used for the top switch and
2
2
ICin ≈ D1Io1 + D2Io2
.
If D1>0.5 and (D1-0.5) < D2<0.5, then
2
2
ICin ≈ 0.5Io1 + (D1 − 0.5)(Io1 + Io2 )2 + (D2 −D1 + 0.5)Io2
.
If D1>0.5 and D2 < (D1-0.5) < 0.5, then
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15
SC2446
POWER MANAGEMENT
Application Information (Cont.)
MOSFET’s with low Rds(on) are used for the bottom switch.
Qgs2 is the additional gate charge required for the switch
current to reach its full-scale value Ids and
.
Qgd is the charge needed to charge gate-to-drain (Miller)
MOSFET power dissipation consists of
capacitance when Vds is falling.
Switching losses occur during the time interval [t1, t3].
Defining tr = t3-t1 and tr can be approximated as
a) conduction loss due to the channel resistance Rds(on)
,
b) switching loss due to the switch rise time tr and fall time
tf, and
c) the gate loss due to the gate resistance RG.
(Qgs2 + Qgd )Rgt
tr =
.
Vcc − Vgsp
Top Switch:
where Rgt is the total resistance from the driver supply rail
to the gate of the MOSFET. It includes the gate driver internal
impedance Rgi, external resistance Rge and the gate
resistance Rg within the MOSFET i.e.
The RMS value of the top switch current is calculated as
2
δ
IQ1,rms = Io D(1+ 12 ).
The conduction losses are then
2
Rgt = Rgi+Rge+Rg.
Ptc = IQ1,rms Rds(on)
.
V
gsp is the Miller plateau voltage shown in Figure 11.
Rds(on) varies with temperature and gate-source voltage.
Curves showing Rds(on) variations can be found in
manufacturers’ data sheet. From the Si4860 datasheet,
Rds(on) is less than 8mΩ when Vgs is greater than 10V.
However Rds(on) increases by 50% as the junction
temperature increases from 25oC to 110oC.
Similarly an approximate expression for tf is
(Qgs2 + Qgd )Rgt
tf =
.
Vgsp
The switching losses can be estimated using the simple
formula
Only a portion of the total losses Pg = QgVccfs is dissipated in
the MOSFET package. Here Qg is the total gate charge
specified in the datasheet. The power dissipated within
the MOSFET package is
1
δ
2
Pts = (tr + tf )(1+ )Io Vinfs.
2
where tr is the rise time and tf is the fall time of the switching
process. Different manufactures have different definitions
and test conditions for t and t . To clarify these, we sketch
Rg
Rgt
P =
QgVccfs.
tg
r
f
the typical MOSFET switching characteristics under clamped
inductive mode in Figure 11.
The total power loss of the top switch is then
Pt = Ptc+Pts+Ptg.
If the input supply of the power converter varies over a
wide range, then it will be necessary to weigh the relative
importance of conduction and switching losses. This is
because conduction losses are inversely proportional
to the input voltage. Switching loss however increases
with the input voltage. The total power loss of MOSFET
should be calculated and compared for high-line and
low-line cases. The worst case is then used for thermal
design.
Gate charge
Bottom Switch:
The RMS current in bottom switch can be shown to be
Figure 11. MOSFET switching characteristics
2
δ
In Figure 11,
IQ2,rms = Io (1− D)(1+ 12 ).
Qgs1 is the gate charge needed to bring the gate-to-source
voltage Vgs to the threshold voltage Vgs_th
,
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16
SC2446
POWER MANAGEMENT
Application Information (Cont.)
The conduction losses are then
Integrated Power MOSFET Drivers
In SC2446 there are four internally integrated gate
drivers to drive all the MOSFETs in dual channels. With
the device bipolar process, emitter-follower based
Darlington bipolar transistors are used for the output
stage. The key advantage of the Darlington configuration
is that the total current gain is greatly improved which
leads to larger driving current Igs. This in turn will help
reduce the MOSFETs switching losses. In order to
estimate the losses associated with the gate driver, we
first measured the gate driver waveform (typical
waveforms of Vce and Igs) as shown in Figure12.
2
Pbc=IQ2,rms Rds(on)
.
where Rds(on) is the channel resistance of bottom MOSFET.
If the input voltage to output voltage ratio is high (e.g.
Vin=12V, Vo=1.5V), the duty ratio D will be small. Since the
bottom switch conducts with duty ratio (1-D), the
corresponding conduction losses can be quite high.
Due to non-overlapping conduction between the top and
the bottom MOSFET’s, the internal body diode or the
external Schottky diode across the drain and source
terminals always conducts prior to the turn on of the bottom
MOSFET. The bottom MOSFET switches on with only a diode
voltage between its drain and source terminals. The
switching loss
1
δ
2
P = (tr + tf )(1+ )IoVdfs
bs
2
is negligible due to near zero-voltage switching.
The gate losses are estimated as
Rg
Rgt
Pbg
=
QgVccfs.
The total bottom switch losses are then
Pb=Pbc+Pbs+Pbg.
Figure 12. Measured gate driver output waveforms
with 2.2Ω current limit resistor.
Once the power losses Ploss for the top (Pt) and bottom (Pb)
MOSFET’s are known, thermal and package design at It is clear that the saturation voltage is not a constant. It
component and system level should be done to verify that changes with the driving current in a nonlinear fashion.
the maximum die junction temperature (Tj,max, usually A simple formula to calculate the losses with a reasonable
125oC) is not exceeded under the worst-case condition. accuracy is not available. But, we use a curve fitting
The equivalent thermal impedance from junction to technique to estimate the power losses in gate driver.
ambient (θja) should satisfy
First, the saturation voltage vce(t) is approximated as
Tj,max − Ta,max
θja
≤
.
1
2
t
2
(
)
vce (t) = Vcc 2−
.
P
T
loss
1
θja depends on the die to substrate bonding, packaging
material, the thermal contact surface, thermal compound
property, the available effective heat sink area and the air
flow condition (free or forced convection). Actual temperature
measurement of the prototype should be carried out to
verify the thermal design.
Where, Vcc is the gate driver collector voltage, T1 is a time
constant related to the fall time of vce. For the example
in Fig. 12, Vcc=12V, T1=0.5Tf with Tf being measured as
~50 ns. With these parameters, the approximated vce(t) is
plotted as in Figure 13 a).
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17
SC2446
POWER MANAGEMENT
Application Information (Cont.)
T
s
1
Ts
Pgd
=
vce(t)igs (t)dt.
∫
20
12
0
For SC2446, there are 4 gate drivers, the total gate driver
losses is then 4Pgd. For the example in Figure 12, the
power losses for each gate driver is estimated as 122
mW when the operating frequency is about 300kHz. The
total losses for the 4 gate drivers is then about 488
mW.
v
(t)
ce
10
0
0
8
.
0
0
5 10
7
−
t
1 10
⋅
time (s)
Remark 3: It is beneficial to select low gate charge
MOSFET’s for lower switching losses in the MOSFET
package and lower power dissipation in the gate-driving
IC. Once the MOSFET is chosen with a specified input gate
charge, one can adjust the gate driving resistor to balance
the driver IC losses and the power MOSFET switching losses.
To the first order of approximation, smaller gate resistance
leads to higher gate driving current and faster MOSFET
switching. But, the driver incurs more power losses. On
the other hand, larger gate drive resistance limits the gate
drive current, which leads to low Vce and less power losses.
But, the MOSFET suffers more switching losses.
Using low gate charge MOSFET’s reduces switching loss.
To prevent shoot-through between the top and the bottom
MOSFET’s during commutation, one MOSFET should be
completely turned off before the other is turned on. In the
SC2446 the top and the bottom gate drive pulses are
made non-overlapping. When not driving any load, the non-
overlapping commutation intervals from the top to the
bottom and from the bottom to the top gate drives are set
at 90ns. If MOSFET’s are driven from the SC2446, the
non-overlapping commutation times will decrease due to
finite gate-source voltage rise and fall times. The gate-
source voltage waveforms of the MOSFET’s should not
overlap above their respective thresholds when driven from
the SC2446. Use of low gate charge MOSFET’s reduces
transition times and the tendency of shoot-through. The
combined rise and fall times during both commutations
should be less than the preset non-overlapping intervals.
Figure 13 a). Approximated gate driver vce(t) waveform.
Similarly, the gate drive current is approximated as
t
2
)
igs (t) = Igsp
(
)2 e−(
.
t
T
2
T2
Where, Igsp is a scaling parameter proportional to the gate
drive peak current, T2 is a time constant proportional to
the fall time of vce. For the example in Figure 13,
Igsp=3.15A, T2=0.77Tf with Tf being measured as ~50 ns.
1.5
1.158
1
i
(t)
gs
0.5
0
0
8
.
0
0
5 10
7
−
t
1⋅10
time (s)
Figure 13 b). Approximated gate drive current igs(t)
waveform.
Current Sensing (Combi-Sense)
Inductor current sensing is required for the current-mode
control. Although the inductor current can be sensed with
a precision resistor in series with the inductor, a novel
lossless Combi-sense technique is used in the SC2446.
This SEMTECH proprietary technique has the advantages
of
With these parameters, the approximated igs(t) is plotted
as in Figure 13 b).
Based on the approximation formulae of vce(t) and igs(t),
one can calculate the power losses for each gate driver
pair as
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SC2446
POWER MANAGEMENT
Application Information (Cont.)
1) lossless current sensing,
2) higher signal-to-noise ratio, and
3) preventing thermal run-away.
Vin
Rds1
iL(t)
L
RL
Cs
The basic arrangement of the Combi-sense is shown in
Figure 14.
PN
Cin
Rs
Vo
VPN
Cout
Rload
Where, RL is the equivalent series resistance of the output
inductor. The added Rs and Cs form a RC branch for
inductor current sensing. This branch is driven from a
small totem pole driver (Q3 and Q4) integrated within
SC2446. The base driving signals Vbe3 and Vbe4
vC(t)
Figure 15 a). Equivalent sub-circuit.
Vin
Q1
Vgs1
iL (t)
L
RL
Cs
PN
Cin
Rs
V o
Vin
Q2
Cou t
Rload
v C (t)
Vgs2
iL(t)
L
RL
Cs
PN
C
i
n
Rs
Vo
VPN
Vbe 3
Vbe 4
Q 3
Q 4
C out
Rds2
Rload
vC (t)
VP N
Figure 15 b). Equivalent sub-circuit.
Figure 14. The basic structure of Combi-Sense.
are designed to follow the gate drive signals Vgs1 and
Vgs2, respectively, with minimal delay drive. Ideally, the
leading and falling edges of the Virtual Phase Node (VPN)
follow that of the Phase Node (PN) when Q1~Q4 switch
accordingly.
Specifically, when Q1/Q3 are ON and Q2/Q4 are OFF,
the equivalent circuit of Figure 14 reduces to Figure 15
a). Where, Rds1 is the on-resistance of the top MOSFET.
The two branches, consisting of {(Rds1+RL), L} and {Rs,
CS}, are in parallel. The DC voltage drop (Rds1+RL)Io
equals VCs. In this way, the output current is sensed from
VCs when (Rds1+RL) is known.
VCs=[D(Rds1+RL)+(1-D)(Rds2+RL)]Io,
or equivalently
VCs=[D Rds1+(1-D)Rds2+RL]Io=ReqIo.
It is noted that the DC value of VCs is independent of the
value of L, Rs and Cs. This means that, if only the average
load current information is needed (such as in average
current mode control), this current sensing method is
effective without time constant matching requirement.
In the current mode control as implemented in SC2446,
the voltage ripple on Cs is critical for PWM operation. In
fact, the AC voltage ripple peak-to-peak value of VCs
(denoted as ∆VCs) directly effects the signal-to-noise ratio
of the PWM operation. In general, smaller ∆VCs leads to
lower signal-to-noise ratio and more noise sensitive
operation. Larger ∆VCs leads to more circuit (power stage)
When Q1/Q3 are OFF and Q2/Q4 are ON, the equivalent
circuit of Figure 14 becomes the sub-circuit as shown in
Figure 15 b). Where, Rds2 is the channel resistance of
the bottom MOSFET. In this case, the branch {Rs,Cs} is in
parallel with {(Rds2+RL), L} and VCs=(Rds2+RL)Io. In
average,
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SC2446
POWER MANAGEMENT
Application Information (Cont.)
parameter sensitive operation. A good engineering In the following design steps, the capacitor CS in the
compromise is to make
current sensing part is commonly selected in the range
of 22nF ~ 68nF.
∆VCs~ReqδIo.
The prerequisite for such relation is the so called time
constant matching condition
Vin
Q1
L
Req
Vgs1
≈ RsCs.
iL(t)
L
RL
Rs1
PN
Cin
Rs
Vo
When Rds1=Rds2, the above relations become
equations.
Q2
Cs
C out
Rload
Vgs2
vC(t)
For an example of application circuit, L=1.3µH,
RL=1.56mΩ and Rds1=Rds2=8mΩ , the time constant
RsCs should be set as 136µs. If one selects Cs=33 nF,
then Rs=4.12 kΩ.
Vbe3
Vbe4
Q3
Q4
VPN
Scaling the Current Limit
1
+
-
Rs2
2
ISEN
R s3
Over-current is handled differently in the SC2446
depending on the direction of the inductor current. If the
differential sense voltage between CS+ and CS- exceeds
+75mV, the top MOSFET will be turned off and the bottom
MOSFET will be turned on to limit the inductor current.
This +75mV is the cycle-by-cycle peak current limit when
the load is drawing current from the converter. There is
no cycle-by-cycle current limit when the inductor current
flows in the reverse direction. If the voltage between
CS1+ and CS- falls below -113mV, the controller will
undergo overload shutdown and time-out with both the
top and the bottom MOSFETs shut off. (See the section
Overload Protection and Hiccup).
Figure 16. Scaling the equivalent current limit.
a) When the required current limit value ILM is greater
than ILMcp, one just needs to remove Rs3, and solve the
following equations
L
Req
(Rs //Rs1) Cs =
,
Rs1
ILMR
= 75mV,
eq Rs + Rs1
In the circuit of Figure 14, the equivalent inductor current
limits are set according to
75mV
Req
and
for
Rs2 = Rs //Rs1 .
ILMcp
=
,
Rs,Rs1 and Rs2.
when the load is sourcing current from the converter and
Note that RS2 is selected as RS//RS1 in order to reduce
the bias current effect of the current amplifier in SC2446.
If the current limit is to be set to ILM = 15A with the existing
power circuit parameter and Cs = 33nF, it is calculated
that Rs2 = 4.12 kΩ, Rs = 7.87 kΩ and Rs1 = 8.66 kΩ.
110mV
ILMcn = −
,
Req
when the load is forcing current back to the input power
source. If Req = 9.56mW, then ILM = 7.8/-11.8A. The circuit
in Figure 16 allows the user to scale the equivalent current
limit with the same Req.
b) When the required current limit ILM is less than ILMcp
,
one just needs to remove Rs1 and solve
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SC2446
POWER MANAGEMENT
Application Information (Cont.)
off until it is no longer overloaded. This hiccup mode of
overload protection is a form of foldback current limiting.
The following calculations estimate the average inductor
current when the converter output is shorted to the
ground.
L
Req
RsCs =
,
Rs
Rs3
ILMReq
+
VO = 75mV,
a) The time taken to discharge the capacitor from 3.2V
to 0.5V
for Rs and RS3.
(3.2 − 0.5)V
tssf = C32
.
Rs2 is then obtained from
1.4µA
Rs3Rs
.
If C32 = 0.1µF, tssf is calculated as 193ms.
Rs2
=
Rs3 − Rs
b) The soft start time from 0.5V to 3.2V
(3.2 − 0.5)V
tssr = C32
.
If the current limit is to be set to ILM = 5A with the existing
power circuit parameter and Cs, it is calculated that
Rs=4.12 kΩ, Rs3=190 kΩ and Rs2=4.22 kΩ.
Similar steps and equations apply to the current limit
setting and scaling for current sinking mode.
2µA
When C32 = 0.1µF, tssr is calculated as 135ms. Note that
during soft start, the converter only starts switching when
the voltage at SS/EN exceeds 1.2V.
c) The effective start-up time is
Remark 4: When the current limit ILM is lower than ILMcp
,
the designer has the freedom of selecting higher Rds(ON)
MOSFETs to reduce cost. As a result, Reg is increased
and ILMcp is reduced. Although the use of low-cost
MOSFET’s is always preferred, the current-limit setting
technique described above allows quick adjustment on a
well-tested prototype without the need to replace the
power MOSFETs.
(3.2 −1.2)V
tsso = C32
.
2µA
The average inductor current is then
tsso
tssf + tssr
ILeff = ILMcp
.
Overload Protection and Hiccup
During start-up, the capacitor from the SS/EN pin to
ground functions as a soft-start capacitor. After the
converter starts and enters regulation, the same
capacitor operates as an overload shutoff timing
capacitor. As the load current increases, the cycle-by-
cycle current-limit comparator will first limit the inductor
current. Further increase in loading will cause the output
voltage (hence the feedback voltage) to fall. If the
feedback voltage falls to less than (75% for Ch1, 72%
for Ch2) of the reference voltage, the controller will shut
off both the top and the bottom MOSFET’s. Meanwhile
an internal 1.4µA current source discharges the soft-start
capacitor C32(C33) connected to the SS/EN pin.
ILeff ≈ 0.30 ILMcp and is independent of the soft start
capacitor value. The converter will not overheat in hiccup.
Setting the Output Voltage
The non-inverting input of the channel-one error amplifier
is internally tied the 0.5V voltage reference output (Pin
8). The non-inverting input of the channel-two error
amplifier is brought out as a device pin (Pin 10) to which
the user can connect Pin 8 or an external voltage
reference. A simple voltage divider (Ro1 at top and Ro2 at
bottom) sets the converter output voltage. The voltage
feedback gain h=0.5/Vo is related to the divider resistors
value as
When the capacitor is discharged to 0.5V, a 2µA current
source recharges the SS/EN capacitor and converter
restarts. If overload persists, the controller will shut down
the converter when the soft start capacitor voltage
exceeds 3.2V. The converter will repeatedly start and shut
h
1− h
Ro2
=
Ro1.
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SC2446
POWER MANAGEMENT
Application Information (Cont.)
complex high-Q poles of the output LC networks is split
into a dominant pole determined by the output capacitor
and the load resistance and a high frequency pole. This
pole-splitting property of current-mode control greatly
simplifies loop compensation.
The inner current-loop is unstable (sub-harmonic
oscillation) unless the inductor current up-slope is steeper
than the inductor current down-slope. For stable
operation above 50% duty-cycle, a compensation ramp
is added to the sensed-current. In the SC2446 the
compensation ramp is made duty-ratio dependent. The
compensation ramp is approximately
Once either Ro1 or Ro2 is chosen, the other can be
calculated for the desired output voltage Vo. Since the
number of standard resistance values is limited, the
calculated resistance may not be available as a standard
value resistor. As a result, there will be a set error in the
converter output voltage. This non-random error is
caused by the feedback voltage divider ratio. It cannot
be corrected by the feedback loop.
The following table lists a few standard resistor
combinations for realizing some commonly used output
voltages.
Iramp = De1.76D * 30µA.
Vo (V)
(1-h)/h
0.6
0.2
0.9
0.8
1.2
1.4
1.5
2
1.8
2.6
2.5
4
3.3
5.6
The slope of the compensation ramp is then
Se = (1+1.76D)e1.76Dfs * 30µA.
Ro1 (Ohm) 200 806 1.4K 2K
Ro2 (Ohm) 1K 1K 1K 1K
2.61K 4.02K 5.62K
1K 1K 1K
The slope of the internal compensation ramp is well above
the minimal slope requirement for current loop stability
and is sufficient for all the applications.
With the inner current loop stable, the output voltage is
then regulated with the outer voltage feedback loop. A
simplified equivalent circuit model of the synchronous
Buck converter with current mode control is shown in
Figure 17.
Only the voltages in boldface can be precisely set with
standard 1% resistors.
From this table, one may also observe that when the
value
Vo − 0.5
0.5
1− h
h
=
and its multiples fall into the standard resistor value
chart (1%, 5% or so), it is possible to use standard value
resistors to exactly set up the required output voltage
value.
The input bias current of the error amplifier also causes
an error in setting the output voltage. The maximum
inverting input bias currents of error amplifiers 1 and 2
is -250nA. Since the non-inverting input is biased to 0.5V,
the percentage error in the second output voltage will be
–100% · (0.25µA) · R
R
/[0.5 · (R +R ) ]. To keep
< 4kΩ.
o1 o2
o1 o2
k
this error below 0.2%, R
o2
Loop Compensation
SC2446 uses current-mode control for both step-down
channels. Current-mode control is a dual-loop control
system in which the inductor peak current is loosely
controlled by the inner current-loop. The higher gain outer
loop regulates the output voltage. Since the current loop
makes the inductor appear as a current source, the
Figure 17. A simple model of synchronous buck converter
with current mode control.
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SC2446
POWER MANAGEMENT
Application Information (Cont.)
The transconductance error amplifier (in the SC2446)
has a gain gm of 260µA/V. The target of the compensation
design is to select the compensation network consisting
of C2, C3 and R2, along with the feedback resistors Ro1,
Ro2 and the current sensing gain, such that the converter
output voltage is regulated with satisfactory dynamic
performance.
1
sz2
=
,
R2C2
and
1
sp2
=
.
C2C3
R
2 C2 + C3
With the output voltage Vo known, the feedback gain h
and the feedback resistor values are determined using
the equations given in the “Output Voltage Setting” section
with
The loop transfer function is then
T(s)=Gvc(s)C(s).
0.5
Vo
h =
.
To simplify design, we assume that C3<<C2, Roesr<<Ro,
selects Sp1=Sz2 and specifies the loop crossover
frequency fc. It is noted that the crossover frequency
determines the converter dynamic bandwidth. With these
assumptions, the controller parameters are determined
as following.
For the rated output current Io, the current sensing gain
k is first estimated as
Io
2.1
k =
.
gmhkRo
2πfc
From Figure 17, the transfer function from the voltage
error amplifier output vc to the converter output vo is
C2 =
,
RoCo
C2
s
R2 =
,
1+
Vo (s)
Vc (s)
sz1
s
:= Gvc (s) = kRo
.
and
1+
sp1
Roesr
C
C3 =
o K,
R2
where, the single dominant pole is
1
sp1
=
,
with a constant K.
For example, if Vo=2.5V, Io=15A, fs=300kHz, Co=1.68mF,
(Ro + Roesr )Co
Roesr=4.67mΩ, one can calculate that
and the zero due to the output capacitor ESR is
1
sz1
=
.
Vo
Io
Ro =
= 167mΩ,
RoesrCo
0.5
Vo
The dominant pole moves as output load varies.
The controller transfer function (from the converter
output vo to the voltage error amplifier output vc) is
h =
= 0.2,
and
s
1+
Io
2.1
gmh
s(C2 + C3 )
sz2
s
k =
= 7.14.
C(s) =
,
1+
sp2
where
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SC2446
POWER MANAGEMENT
Application Information (Cont.)
If the converter crossover frequency is set around 1/10
of the switching frequency, fc = 30kHz, the controller
parameters then can be calculated as
88
89
90
91
92
93
88.78
−
gmhkRo
2πfc
C2 =
≈ 0.328nF.
180
argG (f) C(f)
⋅
⋅
(
)
vc
π
where, gm is the error amplifier transconductance gain
(260 µΩ−1).
If we use C2 = 0.33 nF,
92.702
−
RoCo
C2
3
4
5
6
R2 =
≈ 848.5kΩ,
.
.
.
.
10
10
100
1 10
1 10
1 10
1 10
×
5
f
3 10
use R2 = 770kΩ.
With K = 1, it is further calculated that
Figure 18. The loop transfer function Bode plot of the
example.
Roesr
R2
C
C3 =
o K ≈ 10.2pF,
It is clear that the resulted crossover frequency is about
27.1 kHz with phase margin 91o.
use C3 = 10pF. The Bode plot of the loop transfer function
(magnitude and phase) is shown in Figure 18
It is noted that the current sensing gain k was first
estimated using the DC value in order to quickly get the
compensation parameter value. When the circuit is
operational and stable, one can further improve the
compensation parameter value using AC current sensing
gain. One simple and practical method is to effectively
measure the output current at two points, e.g. Io1 and Io2
and the corresponding error amplifier output voltage Vc1
and Vc2. Then, the first order AC gain is
100
69.241
50
20⋅log G (f) C(f)
(
)
vc
0
∆Io
Io1 −Io2
=
k =
∆Vc Vc1 − Vc2
− 20.73
50
3
4
5
6
With this k value, one can further calculate the improved
compensator parameter value using the previous
equations.
.
.
.
.
10
10
100
1 10
1 10
1 10
1 10
5
f
3×10
For example, if one measured that Io1=1A, Io2=15A and
Vc1=2.139V, Vc2=2.457V. k is then calculated as 44.
Substituting this parameter to the equations before, one
can derive that
C2 ≈ 2.024nF. Select C2 = 2.2nF.
R2 ≈ 127.3kΩ. Select R2 = 127kΩ.
C3 ≈ 61.78pF. Select C3 = 47pF
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24
SC2446
POWER MANAGEMENT
Application Information (Cont.)
4) Shorten the gate driver path. Integrity of the gate drive
(voltage level, leading and falling edges) is important for
circuit operation and efficiency. Short and wide gate drive
traces reduce trace inductances. Bond wire inductance
is about 2~3nH. If the length of the PCB trace from the
gate driver to the MOSFET gate is 1 inch, the trace
inductance will be about 25nH. If the gate drive current
is 2A with 10ns rise and falling times, the voltage drops
across the bond wire and the PCB trace will be 0.6V and
5V respectively. This may slow down the switching
transient of the MOSFET’s. These inductances may also
ring with the gate capacitance.
In some initial prototypes, if the circuit noise makes the
control loop jittering, it is suggested to use a bigger C3
value than the calculated one here. Effectively, the
converter bandwidth is reduced in order to reject some
high frequency noises. In the final working circuit, the
loop transfer function should be measured using network
analyzer and compared with the design to ensure circuit
stability under different line and load conditions. The load
transient response behavior is further tested and
measured to meet the specification.
PC Board Layout Issues
5) Put the decoupling capacitor for the gate drive power
supplies (BST and PVCC) close to the IC and power
ground.
Circuit board layout is very important for the proper
operation of high frequency switching power converters. A
power ground plane is required to reduce ground bounces.
The followings are suggested for proper layout.
Control Section
6) The frequency-setting resistor Rosc should be placed
close to Pin 3. Trace length from this resistor to the analog
ground should be minimized.
Power Stage
1) Separate the power ground from the signal ground. In
SC2446, the power ground PGND should be tied to the
source terminal of lower MOSFETs. The signal ground
AGND should be tied to the negative terminal of the
output capacitor.
7) Solder the bias decoupling capacitor right across the
AVCC and analog ground AGND.
8) Place the Combi-sense components away from the
power circuit and close to the corresponding CS+ and CS-
pins. Use X7R type ceramic capacitor for the Combi-sense
capacitor because of their temperature stability.
2) Minimize the size of high pulse current loop. Keep the
top MOSFET, bottom MOSFET and the input capacitors
within a small area with short and wide traces. In addition
to the aluminum energy storage capacitors, add multi-
layer ceramic (MLC) capacitors from the input to the power
ground to improve high frequency bypass.
9) Use an isolated local ground plane for the controller
and tie it to the negative side of output capacitor bank.
3) Reduce high frequency voltage ringing. Widen and
shorten the drain and source traces of the MOSFET’s to
reduce stray inductances. Add a small RC snubber if
necessary to reduce the high frequency ringing at the phase
node. Sometimes slowing down the gate drive signal also
helps in reducing the high frequency ringing at the phase
node.
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2004 Semtech Corp.
25
SC2446
POWER MANAGEMENT
Application Information
VIN
C92
D11
D12
PVCC
Q21
Q23
Q22
Q24
BST2
BST1
R73
R77
R74
R78
GDH2
GDH1
VO2
VO1
L11
C93
C94
L12
C99
C95
C98
C100
CFILTER
RFILTER
CFILTER
RFILTER
+
+
GDL2
GDL1
PGND
VPN1
CS1+
C96
R75
R76
C97
R79
R81
R80
R82
VPN2
RCS+
RCS+
CS2+
RCS-
RCS-
CS2-
CS1-
IN2-
IN1-
C101
C103
C102
C105
COMP2
REFIN
VIN2
COMP1
REF
R83
REF
VIN
C104
R84
AGND
Rosc
SYNC
R85
SYNC
SS1/EN1
SS2/EN2
VIN
AVCC
REFOUT
C106
C107
C108
C109
U1
SC2446
Dual Independant Outputs
Figure 19
VIN
C38
D5
D6
PVCC
BST2
GDH2
Q9
Q10
Q12
BST1
R32
R36
R33
R37
GDH1
VO1
VO1
L5
C39
C40
L6
C45
C41
Q11
C44
C46
CFILTER
RFILTER
CFILTER
RFILTER
+
+
GDL2
GDL1
PGND
VPN1
CS1+
C42
R34
R35
C43
R38
R39
VPN2
RCS+
RCS+
CS2+
RCS-
RCS-
CS2-
CS1-
AVCC
IN2-
IN1-
C48
REFIN
VIN2
COMP1
REF
REF
VIN
C50
R42
C51
R41
AGND
Rosc
SYNC
SYNC
SS1/EN1
SS2/EN2
VIN
AVCC
REFOUT
C52
C54
C55
U1
SC2446
Single Output, Current Share Mode
Figure 20
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2004 Semtech Corp.
26
SC2446
POWER MANAGEMENT
Application Information (Cont.)
VIN
C56
D7
D8
PVCC
Q13
Q14
Q16
BST2
BST1
R43
R47
R44
R48
GDH2
GDH1
VTT
VDDQ
L7
C57
C58
L8
C63
C59
Q15
C62
C64
CFILTER
RFILTER
CFILTER
RFILTER
+
+
GDL2
GDL1
PGND
VPN1
CS1+
C60
R45
R46
C61
R49
R51
R50
R52
VPN2
RCS+
RCS+
CS2+
RCS-
RCS-
CS2-
CS1-
IN2-
IN1-
C65
C67
C66
C69
COMP2
REFIN
VIN2
COMP1
REF
VDDQ
R53
C68
R57
R55
R54
R56
VIN
AGND
Rosc
SYNC
SYNC
SS1/EN1
SS2/EN2
VIN
AVCC
REFOUT
C70
C71
C72
C73
U1
SC2446
DDR Memory Applications (Common Input Voltage)
Figure 21
VIN
VDDQ
C74
D9
D10
PVCC
BST2
GDH2
Q17
Q19
Q18
Q20
BST1
R58
R62
R59
R63
GDH1
VTT
VDDQ
L9
C75
C76
L10
C81
C77
C80
C82
CFILTER
RFILTER
CFILTER
RFILTER
+
+
GDL2
GDL1
PGND
VPN1
CS1+
C78
R60
R61
C79
R64
R66
R65
R67
VPN2
RCS+
RCS+
CS2+
RCS-
RCS-
CS2-
CS1-
IN2-
IN1-
C83
C85
C84
C87
COMP2
REFIN
VIN2
COMP1
REF
VDDQ
R68
C86
R72
R70
R69
R71
VDDQ
AGND
Rosc
SYNC
SYNC
SS1/EN1
SS2/EN2
VIN
AVCC
REFOUT
C88
C89
C90
C91
U1
SC2446
DDR Memory Applications (Separate Input Voltage)
Figure 22
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2004 Semtech Corp.
27
SC2446
POWER MANAGEMENT
Typical Performance Characteristics
4.6
502.5
502
501.5
501
500.5
500
AVCC (Rising)
AVCC (Falling)
4.55
4.5
4.45
4.4
499.5
499
498.5
498
4.35
4.3
-50
0
50
Ta (degree)
100
-50
0
50
Ta (degree)
100
AVCC UVLO vs. Temperature
REF Voltage vs. Temperature
512
510
508
506
504
502
500
498
1.26
1.25
1.24
1.23
1.22
1.21
1.2
Rosc=51.1 kOhm
REFin=1.25V
100
-50
0
50
Ta (degree)
-50
0
50
100
Ta (degree)
REFout Voltage vs. Temperature
Switching Frequency vs. Temperature
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2004 Semtech Corp.
28
SC2446
POWER MANAGEMENT
Typical Performance Characteristics
-107.5
-108
75.00
Ch1
Ch2
Ch1
Ch2
74.00
73.00
72.00
71.00
70.00
69.00
-108.5
-109
-109.5
-110
-110.5
-111
-111.5
-112
-50
0
50
100
-112.5
Ta (degree)
-50
0
50
100
Ta (degree)
Source Current Limit Threshold vs. Temperature
Sink Current Limit Threshold vs. Temperature
112
111
110
109
108
107
106
105
104
103
112
110
108
106
104
102
100
-60
-40
-20
0
20
40
60
80
100
-60
-40
-20
0
20
40
60
80
100
Ta (degree)
Ta (degree)
Ch1, Low Side Off to High Side On
Ch1, High Side Off to Low Side On
Ch2, Low Side Off to High Side On
Ch2, High Side Off to Low Side On
Ch1 Non-overlapping Delay Time
Ch2 Non-overlapping Delay Time
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2004 Semtech Corp.
29
SC2446
POWER MANAGEMENT
Typical Performance Characteristics
Channel 1: Vo = 2.5V @ 15A
Load Regulation
Efficiency vs. Load Current (%)
Vin=12V
10
Vin=5V
Vin=5V
Vin=12V
0.1
0
95
90
85
80
75
70
65
0
20
30
-0.1
-0.2
-0.3
-0.4
-0.5
-0.6
0
10
20
30
Load Current (A)
Load Current (A)
Soft-Start
Line Regulation @ Io=15A
0
0
5
10
15
-0.05
-0.1
-0.15
-0.2
-0.25
-0.3
-0.35
-0.4
Input Voltage (V)
Load Transient
Output Characteristics @ Vin=12V
3
2.5
2
1.5
1
0.5
0
0
10
20
30
40
Load Current (A)
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2004 Semtech Corp.
30
SC2446
POWER MANAGEMENT
Typical Performance Characteristics
Channel 2: Vo = 1.8V @ 15A
Load Regulation
Efficiency vs. Load Current
Vin=5V
Vin=12V
Vin=5V
Vin=12V
0.1
0
95
90
85
80
75
70
65
60
-0.1 0
-0.2
-0.3
-0.4
-0.5
-0.6
-0.7
-0.8
10
20
30
0
10
20
30
Load Current (A)
Load Current (A)
Fig. 18
Soft-Start
Line Regulation at Io=15A
0
0
5
10
15
-0.05
-0.1
-0.15
-0.2
-0.25
-0.3
-0.35
-0.4
Input Voltage (V)
Load Transient
Output Characteristics @ Vin=12V
2
1.5
1
0.5
0
0
10
20
30
40
Load Current (A)
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2004 Semtech Corp.
31
SC2446
POWER MANAGEMENT
Typical Application Circuit
Figure 23
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2004 Semtech Corp.
32
SC2446
POWER MANAGEMENT
Evaluation Board - Bill of Materials
Ref
Qty
Reference
Part Number/Value
Manufacturer
1
2
3
4
2
4
2
6
C1,C4
47uF, 16V, 70 mohm, PosCap
10uF, 16V, X5R, Ceramic 1206
680uF, 4V, PosCap
Sanyo P/N: 16TPB47M
C2,C3,C6,C38
C8,C12
Taiyo Yuden P/N: EMK316BJ106MM
Sanyo P/N: 4TPB680M
C9,C10,C11,
100uF, 6.3V, Ceramic 1210
TDK P/N: C3225XR5R0J107M
C13,C14,C15,
5
6
1
2
2
2
4
2
3
1
1
2
2
C16
1uF, 16V, X5R , Ceramic 0805
0.33uF, 50V, X5R, 1206
2.2nF, Ceramic, 0805
22nF, Ceramic, 0805
Taiyo Yuden P/N: EMK316BJ105MM
C17,C18
C18,C19
C20,C21
C22,C24,C25,C26
C27,C28
C29,C34,C35
C30
Vishay P/N: VJ1206Y334KXAAT
7
Any
8
Any
9
10uF, 4V, X5R, Ceramic, 1206
68pF, Ceramic, 0805
0.1uF, Ceramic, 0805
1nF, Ceramic, 0805
Taiyo Yuden P/N: AMK325BJ106MM
10
11
12
13
14
15
Any
Any
Any
Any
Any
C31
2.2nF, Ceramic, 0805
100nF, Ceramic, 0805
40V, 1A, Schottky
C32,C33
D1,D2
General Semi. P/N: 1N5819M, MELF
or
Motorola P/N: MBRS140T3
16
17
2
1
D7,D10
D11
40V, 3A, Schottky
Diodes Inc. P/N: B340A
ZMM5234B
6.2V, 500mW, 5%, Zener, SOD-
123
18
2
L1,L2
1.8uH, 14A, 3.3 mohm (1.8uH,
15.5A, 3.4 mohm)
Panasonic P/N: ETQP6F1R8BFA, or
Sumdia P/N: CEP1251R8MC-SJ
19
20
21
22
23
24
25
6
2
2
4
2
1
2
Q2,Q3,Q5,Q6,Q7
RCS+1,RCS+2
RCS-1,RCS-2
R3,R4,R7,R8
R5,R6
30V, 16A, 8 mohm, 18nC, SO-8
49.9k, 0805
Vishay P/N: Si4860DY
Any
Any
Any
Any
Any
Any
100k. 0805
1.0 ohm, 5%, 0805
20k, 0805
R9
3.40k, 1%, 0805
5.1, 0805
R10,R13
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2004 Semtech Corp.
33
SC2446
POWER MANAGEMENT
Evaluation Board - Bill of Materials
Ref
Qty
Reference
Part Number/Value
4.02k, 1%, 0805
Manufacturer
25
26
27
28
29
30
31
32
33
34
1
3
1
1
2
1
1
1
1
1
R11
Any
Any
Any
Any
Any
Any
Any
Any
Any
R15,R23,R27
R16
0 ohm, 0805
1k, 1%, 0805
1.3k, 1%, 805
20k, 0805
95.3k, 1%
R17
R18,R19
R20
R21
5.1
R31
110, 5%, 1206
300, 5%, 1206
SC2446
R32
U1
Semtech Corp.
www.semtech.com
2004 Semtech Corp.
34
SC2446
POWER MANAGEMENT
Typical Characteristics
Typical waveforms in the evaluation board circuit #2A
Channel 1: Vo=2.5V @ 15A
Over current protection
Output short applied
Steady state
Load transient response
Loading: 0A to 15A
Output short removed
Un-loading: 15A to 0A
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2004 Semtech Corp.
35
SC2446
POWER MANAGEMENT
Typical Characteristics (Cont.)
Channel 2: Vo=1.8V @ 15A
Typical waveforms in the evaluation board circuit #2A
Load transient response
Loading: 0A to 15A
Steady state
Un-loading: 15A to 0A
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2004 Semtech Corp.
36
SC2446
POWER MANAGEMENT
Typical Characteristics (Cont.)
Over current protection
Output short applied
Output short removed
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2004 Semtech Corp.
37
SC2446
POWER MANAGEMENT
Outline Drawing - TSSOP-28-EDP
A
D
E
e
N
DIMENSIONS
INCHES MILLIMETERS
2X E/2
DIM
A
MIN NOM MAX MIN NOM MAX
E1
-
-
-
-
-
-
-
-
-
-
-
-
.047
1.20
0.15
1.05
0.30
0.20
A1 .002
A2 .031
.006 0.05
.042 0.80
.012 0.19
.007 0.09
PIN 1
INDICATOR
b
c
D
.007
.003
ccc
C
1 2 3
.378 .382 .386 9.60 9.70 9.80
e/2
E1 .169 .173 .177 4.30 4.40 4.50
2X N/2 TIPS
E
e
.252 BSC
.026 BSC
6.40 BSC
0.65 BSC
B
F
H
.210 .216 .220 5.35 5.50 5.60
.112 .118 .122 2.85 3.00 3.10
.018 .024 .030 0.45 0.60 0.75
L
D
F
aaa
C
(.039)
(1.0)
L1
N
28
28
A2
A
-
-
01
0°
8°
0°
8°
SEATING
aaa
PLANE
.004
.004
.008
0.10
0.10
0.20
C
A1
C
bbb
ccc
bxN
bbb
A-B D
SEE DETAIL A
SIDE VIEW
EXPOSED PAD
H
H
c
GAGE
PLANE
0.25
L
(L1)
BOTTOM VIEW
01
DETAIL A
NOTES:
1. CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES).
2. DATUMS -A- AND -B- TO BE DETERMINED AT DATUM PLANE -H-
3. DIMENSIONS "E1" AND "D" DO NOT INCLUDE MOLD FLASH, PROTRUSIONS
OR GATE BURRS.
4. REFERENCE JEDEC STD MO-153, VARIATION AE.
Land Pattern - TSSOP-28-EDP
F
X
DIMENSIONS
DIM
INCHES
(.222)
.224
MILLIMETERS
(5.65)
5.70
4.10
3.20
0.65
0.40
1.55
7.20
C
F
(C)
H
G
Y
Z
G
H
P
X
Y
Z
.161
.126
.026
.016
.061
P
.283
NOTES:
1.
THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY.
CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR
COMPANY'S MANUFACTURING GUIDELINES ARE MET.
Contact Information
Semtech Corporation
Power Management Products Division
200 Flynn Road, Camarillo, CA 93012
Phone: (805)498-2111 FAX (805)498-3804
www.semtech.com
2004 Semtech Corp.
38
相关型号:
SC2446ITSTR
Dual Switching Controller, Current-mode, 3A, 1000kHz Switching Freq-Max, PDSO28, MO-153-AE, TSSOP-28
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SC2446ITSTRT
Dual Switching Controller, Current-mode, 3A, 1000kHz Switching Freq-Max, PDSO28, LEAD FREE, MO-153-AE, TSSOP-28
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