SC2595_09 [SEMTECH]
Integrated Linear DDR Termination Regulator; 集成线性DDR终端稳压器
| 型号： | SC2595_09 |
| 厂家： | 
SEMTECH CORPORATION |
| 描述： | Integrated Linear DDR Termination Regulator |
| 文件： | 总12页 (文件大小：441K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SC2595
Integrated Linear DDR
Termination Regulator
POWER MANAGEMENT
Description
Features
The SC2595 is an integrated linear DDR termination
device, which provides a complete solution for DDR
termination designs; while meeting the JEDEC require-
ments of SSTL-2 specifications for DDR-SDRAM termi-
nation.
Regulates while sourcing or sinking 1.5A
AVCC range is from 2.5V to 5V
Reference output
Minimum number of external components
Accurate internal voltage divider
SOIC8-EDP package.Pb-free,Halogen free, and RoHS/
WEEE compliant
The SC2595 can source and sink 1.5A current at the
output VTT while maintaining excellent load regulation.
Applications
VTT is designed to track the VREF voltage with a tight
tolerance over the entire current range while preventing
shoot through on the output stage.
DDR memory termination
High speed data line termination
PC motherboards
Graphics boards
Disk drives
CD-ROM drives
A VSENSE pin is incorporated to provide excellent load
regulation, along with a buffered reference voltage.
The SC2595 incorporates a disable function built into
the AVCC pin to tri-state the output during Suspend To
Ram (STR) states.
(Multiple patents pending.)
Typical Application Circuit
VDD
SC2595
1
2
3
4
8
VTT
NC
VTT
PVCC
AVCC
VDDQ
7
6
5
GND
VSENSE
VREF
VREF
September 24, 2009
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SC2595
POWER MANAGEMENT
Absolute Maximum Ratings
Exceeding the specifications below may result in permanent damage to the device, or device malfunction. Operation outside of the parameters
specified in the Electrical Characteristics section is not implied.
Parameter
Symbol
VCC
Maximum
-0.3 to +6.0
Units
V
PVCC, AVCC, VDDQ to GND
Thermal Resistance Junction to Case
SOIC8-EDP
θ
°C/W
°C/W
5.5
JC
Thermal Resistance Junction to Ambient
SOIC8-EDP
θ
JA
36.5
-40 to +105
-40 to +150
-65 to +150
240
Operating Temperature Range
TA
°C
°C
°C
°C
°C
KV
Operating Junction Temperature Range
Storage Temperature Range
TJ
TSTG
TLEAD
TLEAD
ESD
Peak IR Reflow Temperature 10 - 40s
Peak IR Reflow Temperature 10 - 40s
ESD Rating (Human Body Model)
260
2
Operating Range
Parameter
Symbol
TJ
Maximum
-40 to +150
2.3 to 5.5
2.3 to AVCC
Units
Junction Temperature Range
AVCC to GND
°C
V
AVCC
PVCC to GND
PVCC
V
Electrical Characteristics
Specifications with standard typeface are for TJ = 25oC and limits in boldface type apply over the full Operating Temperature Range
(TJ = -40oC to +150oC). Unless otherwise specified, AVCC = PVCC = 2.5V, VDDQ = 2.5V.
Parameter
Symbol
VREF
Test Conditions
IREF_OUT = 0mA
Min
Typ
Max
Units
V
Reference Voltage
VDDQ/2
- 40mV
1.25
VDDQ/2
+ 40mV
(1)
Load Regulation
REGLOAD
ILOAD : 0 to +1.5A
ILOAD : 0 to -1.5A
-0.5
+0.5
%
VTT Output Voltage Offset
Quiescent Current
VOSVTT
IQ
IOUT=0A, VTT- VREF
ILOAD = 0A
-20
0
+20
mV
μA
V
400
2.1
100
AVCC Enable Threshold
VDDQ Input Impedance
ZVDDQ
kΩ
Note:
(1) For Load Regulation, use a 10ms current pulse width when measuring VTT.
©2009 Semtech Corp.
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SC2595
POWER MANAGEMENT
Pin Configuration
Ordering Information
Part Number
Package
Temp. Range (TA)
-40 to +105OC
TOP VIEW
SC2595STRT(1)(2) SOIC8-EDP
SC2595EVB
Evaluation Board
VTT
NC
GND
1
2
3
4
8
7
6
5
Notes:
(1) Only available in tape and reel packaging. Areel contains
2500 devices for SOIC8-EDP package.
(2) Pb-free,Halogen free, and RoHS and WEEE compliant.
PVCC
AVCC
VDDQ
VSENSE
VREF
(SOIC8-EDP)
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SC2595
POWER MANAGEMENT
Pin Descriptions
SOIC-8L EDP Pin Name
Pin #
Pin Function
(1)
1
2
3
NC
No internal connection.
Ground.
GND
VSENSE VSENSE is a feedback pin. VTT plane is always a narrow and long strip plane in most
motherboard applications. This long strip plane will cause a large trace
inductance and trace resistance. Consider the load transient condition; a fast
load current going through VTT strip plane can create voltage spikes on the VTT
plane. The load current can also cause a DC voltage drop on the VTT plane. It is
recommended that VSENSE should be connected to the center of VTT plane to
improve the load regulation and the noise immunity. In case that one can't
connect the VSENSE pin to the center of the VTT plane, one should connect it to the
SC2595 VTT pin directly. A longer trace of VSENSE may pick up noise and cause the
error of load regulation; hence the longer trace must be avoided.
A 10nF to 100nF ceramic capacitor close to the VSENSE pin is required to avoid
oscillation during transient condition.
4
5
VREF
VREF is an output pin, which provides the buffered output of the internal reference
voltage. System designer can use the VREF output voltage for Northbridge chipset
and memory. Because these input pins are typically high impedance, there
should be a small amount of current drawn from the VREF pin [figure 9, 10]. To
improve the noise immunity, a ceramic capacitor (10nF - 100nF) should be added
from the VREF pin to ground with short distance.
VDDQ(2)
The VDDQ pin is an input for creating internal reference voltage to regulate VTT. The
VDDQ voltage is connected to internal 100Kohm resistor divider. The central tap
of resistor divider (VDDQ/2) is connected to the internal voltage buffer, which
output is connected to VREF pin and the non-inverting input of the error amplifier
as the reference voltage. With the feedback loop closed, the VTT output voltage
will always track the VDDQ/2 precisely. It is recommended to use 5.1 ohm + a
1uF ceramic capacitor for VDDQ pin's filter to increase the noise immunity.
6
7
AVCC (2)
PVCC (2)
The AVCC pin is used to supply all of the internal control circuitry. AVCC voltage
has to be greater than its UVLO threshold voltage (2.1V typical) to allow the
SC2595 be in normal operation. If AVCC voltage is lower than the UVLO threshold
voltage, the VTT output voltage will remain at 0V.
The PVCC pin provides the rail voltage from where the VTT pin draws load current.
There is a limitation between AVCC and PVCC. The PVCC voltage must be less or
equal to AVCC voltage to ensure the correct output voltage regulation. The VTT
source current capability is dependent on PVCC voltage. Higher the voltage on
PVCC, higher the source current; however, it will cause more power loss and higher
temperature rise [figure 5, 11, 12].
8
VTT
The VTT pin is the output of SC2595. It can sink and source 1.5A continuous
current and 3A peak current while keeping excellent load regulation. It is
recommended that one should use at least 220uF low ESR capacitors (ESR
should be lower than 250m ohm) and 10uF ceramic capacitors, which are
uniformly spread on the VTT strip plane to reduce the voltage spike under load
transient condition.
Thermal Thermal pad should be connected to GND.
Pad
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SC2595
POWER MANAGEMENT
Notes:
(1) Can be used for vias.
(2) Power up of AVCC, PVCC and VDDQ supplies.
(a) The preferred mode of operation is when the AVCC, PVCC and VDDQ pins are tied together to a single supply.
(b) If and when AVCC, PVCC pins are tied to a supply separate to that of the VDDQ supply pin; then the VDDQ supply should
lead AVCC, PVCC supply or the VDDQ supply and the AVCC, PVCC supply should rise simultaneously.
(c) If the AVCC, PVCC and VDDQ supply pins are connected in a way such that, AVCC, PVCC supplies precedes VDDQ supply;
then VTT output precedes VDDQ. This can cause the SDRAM device to latch-up, which may cause permanent
damage to the SDRAM.
Block Diagram
AVCC
VDDQ
PVCC
UVLO
-
OUT
+
-
Driver
Circuit
+
OUT
VTT
VREF
GND
VSENSE
NC
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SC2595
POWER MANAGEMENT
Application Information
Overview
Application_2: Lower Power Loss Configuration
for SSTL-2
Double Data Rate (DDR) SDRAM was defined by JEDEC
1997. Its clock speed is the same as previous SDRAM
but data transfers speed is twice than previous SDRAM.
By now, the requirement voltage range is changed from
3.3V to 2.5V; the power dissipation is smaller than
SDRAM. For above reasons, it is very popular and widely
used in M/B, N/B, Video-cards, CD ROM drives, Disk
drives.
If power loss is a major concern, separated the PVCC form
the AVCC and the VDDQ will be a good choice. The PVCC can
operate at lower voltage (1.8V to 2.5V). If 2.5V voltage
is applied on AVCC and the VDDQ, but the source current is
lower due to the lower operating voltage applied on the
PVCC. Please find the relative test result in Figures 5, 11
and 12.
Regarding the DDR power management solution, there
are two topologies can be selected for system design-
ers. One is switching mode regulator that has bigger sink/
source current capability, but the cost is higher and the
board space needed is bigger. Another solution is linear
mode regulator, which costs less, and needs the less
board space. For two DIMM motherboards, system de-
signers usually choose the linear mode for DDR power
management solution.
SC2595
1
2
3
4
8
7
6
5
NC
VTT
PVCC
AVCC
VDDQ
VTT
1.8V to 2.5V
1.25V
GND
2.5V
VDD
Vin
VSENSE
VREF
Cin1
Cout1
220uF
R2
R
Cin2
1uF
Cin2
Csense
2.2uF
Cref
10nF
68uF
10uF
Cddq
1uF
Applications
Typical Application Circuits & Waveforms
Figure 2: Lower power loss for SSTL-2 application
Two different application circuits are shown below in Fig-
ure 1 to Figure 2. Each circuit is designed for specific
condition. More details are described below. See Note
1. Below for recommended power up sequencing.
Notes:
(1) Power up of AVCC, PVCC and VDDQ supplies.
(a) The preferred mode of operation is when the
AVCC, PVCC and VDDQ pins are tied together to a
single supply.
Application_1: Standard SSTL-2 Application
(b) If and when AVCC, PVCC pins are tied to a supply
separate to that of the VDDQ supply pin; then
the VDDQ supply should lead AVCC, PVCC supply or
the VDDQ supply and the AVCC, PVCC supply should
rise simultaneously.
(c) If the AVCC, PVCC and VDDQ supply pins are con
nected in a way such that, AVCC, PVCC supplies
precedes VDDQ supply; then VTT output precedes
VDDQ. This can cause the SDRAM device to latch-
up, which may cause permanent damage to the
SDRAM.
The AVCC pins, the PVCC pin, and the VDDQ pin can be tied
together for SSTL-2 application. It only needs a 2.5V
power rail for normal operation. System designer can
save the PCB space and reduce the cost. Please refer
to figures 3 to 4 for test waveforms.
SC2595
1
2
3
4
8
7
6
5
VTT
NC
VTT
PVCC
AVCC
VDDQ
1.25V
VDD
GND
2.5V
VSENSE
VREF
R1
5.1
Cout1
Cin1
68uF
Cout2
Csence Cref
220uF 10uF
Cin2
1uF
10nF
2.2uF
Figure 1: Standard SSTL-2 application
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SC2595
POWER MANAGEMENT
Application Information (Cont.)
Layout guidelines
1)The SC2595 has a SOIC8-EDP package. It can improve
the thermal impedance (θJC) significantly. A suitable ther-
mal pad should be added when PCB layout. Some ther-
mal vias are required to connect the thermal pad to the
PCB ground layer. This will improve the thermal perfor-
mance .
2)To increase the noise immunity, a ceramic capacitor of
10nf to 100nf is required to decouple the VREF pin with
the shortest connection trace, also A 10nF to 100nF
ceramic capacitor close to the VSENSE pin is required to
avoid oscillation during transient condition.
3)To reduce the noise on the input power rail for stan-
dard SSTL-2 application, a 68μF low ESR capacitor and
a 1μF ceramic capacitor have to be used on the input
power rail with shortest possible connection.
4)For lower power loss SSTL-2 application, a 220μF AL.
capacitor (ESR should be lower than 250m ohm) and a
10μF ceramic has to be added on the PVCC pin and a 1μF
ceramic capacitor +5.1 ohm filter has to be added on
the VDDQ pin with shortest possible connection.
5)VTT output copper plane should be as large as possible.
6)VSENSE trace should be as short as possible.
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SC2595
POWER MANAGEMENT
Test Waveforms
Test condition: Avcc=PVcc=VDDQ=2.5V,VTT=1.25V
Cout1=220uF, Cout2=10uF, Sink 2A.
Test condition: Avcc=PVcc=VDDQ=2.5V,VTT=1.25V
Cout1=220uF, Cout2=10uF, Source 2A.
VDDQ
AVcc
PVcc
VDDQ
AVcc
PVcc
VTT
VTT
VREF
VREF
Figure 3
Figure 4
Typical Characteristics
AVcc vs IQ
AVCC=VDDQ=2.5V
600
3.00
2.75
2.50
2.25
2.00
1.75
1.50
1.25
1.00
550
500
450
400
350
300
250
200
150
100
50
VDDQ
=2.5V
VDDQ
MAX
SOURCE
CURRENT
=1.8V
0
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
1.8 1.9
2
2.1 2.2 2.3 2.4 2.5
PVCC(V)
AVcc(V)
Figure 6
Figure 5
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SC2595
POWER MANAGEMENT
Typical Characteristics (Cont.)
Temp vs UVLO
Quiescent Current(AVCC= 2.5V)
800
2.00
1.99
1.98
1.97
1.96
1.95
1.94
1.93
1.92
1.91
1.90
700
600
500
400
300
200
2.5V
1.8V
UVLO
(Typical)
0
20 40 60 80 100 120 140
Temperature (
20 30 40 50 60 70 80 90 100 110
Temperature(
)
℃
)
℃
Figure 8
Figure 7
VREF_max vs IREF(VDDQ=2.5V)
VDDQ=PVCC=AVCC=2.5V
1.250
1.250
1.245
1.240
1.235
1.230
1.225
1.220
1.215
1.210
1.245
1.240
1.235
1.230
1.225
1.220
1.215
1.210
-40
℃
0
℃
25
75
℃
℃
150
℃
0
100 200 300 400 500 600 700 800 900
IREF(uA)
0
100 200 300 400 500 600 700 800 900
IREF(uA)
Figure 10
Figure 9
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SC2595
POWER MANAGEMENT
Typical Characteristics (Cont.)
VDDQ=1.8V
VDDQ=2.5V
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
6.5
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
MA X
SOURCE
CURRENT
MA X
SOURCE
CURRENT
2.0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
AVCC=PVCC(V)
AVCC=PVCC(V)
Figure 12
Figure 11
AVCC=PVCC=VDDQ=2.5V
140
120
100
80
60
40
20
0
SOURCE
SINK
0.0
0.5
1.0
1.5
2.0
2.5
DC CURRENT (A)
Figure 13
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SC2595
POWER MANAGEMENT
Outline Drawing - SOIC8-EDP
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SC2595
POWER MANAGEMENT
Land Pattern - SOIC8-EDP
Contact Information
Semtech Corporation
Power Management Products Division
200 Flynn Road, Camarillo, CA 93012
©2009 Semtech Corp.
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