SC411MLTRT [SEMTECH]
Synchronous Buck Pseudo-Fixed Frequency Power Supply Controller; 同步降压伪固定频率电源控制器
| 型号： | SC411MLTRT |
| 厂家： | 
SEMTECH CORPORATION |
| 描述： | Synchronous Buck Pseudo-Fixed Frequency Power Supply Controller |
| 文件： | 总27页 (文件大小：476K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SC411
Synchronous Buck Pseudo-Fixed
Frequency Power Supply Controller
POWER MANAGEMENT
Description
Features
The SC411 is a constant on-time synchronous buck PWM
controller in a space-saving MLPQ package intended for
use in notebook computers and other battery operated
portable devices. Features include high efficiency and
a fast dynamic response with no minimum on-time. The
excellent transient response means that SC411 based solu-
tions will require less output capacitance than competing
fixed frequency converters.
ꢀ Constant on-time for fast dynamic response
ꢀ Programmable VOUT range = 0.5 – VCCA
ꢀ VBAT range = 1.8V – 25V
ꢀ DC current sense using low-side RDS(ON)
Sensing or sense resistor
ꢀ Resistor programmable frequency
ꢀ Cycle-by-cycle current limit
ꢀ Digital soft-start
ꢀ Powersave option
The switching frequency is constant until a step-in load or
line voltage occurs. During this time the pulse density and
frequency will increase or decrease to counter the change
in output or input voltage. After the transient event, the
controller frequency will return to steady-state operation.
At light loads, Powersave Mode enables the SC411 to skip
PWM pulses for better efficiency.
ꢀ Over-voltage/under-voltage fault protection
ꢀ 10μA typical shutdown current
ꢀ Low quiescent power dissipation
ꢀ Power good indicator
ꢀ 1.2% reference
ꢀ Integrated gate drivers with soft switching
ꢀ Enable pin
ꢀ 16 pin MLPQ (4mm x 4mm)
ꢀ Output soft discharge upon shutdown
The output voltage can be adjusted from 0.5V to VCCA. A
frequency setting resistor sets the on-time for the controller.
The integrated gate drivers feature adaptive shoot-through
protection and soft-switching. Additional features include
cycle-by-cycle current limit, digital soft-start, over-voltage
and under-voltage protection, a Power Good output and
soft discharge upon shutdown.
Applications
ꢀ Notebook Computers
ꢀ CPU/IO Supplies
ꢀ Handheld Terminals and PDAs
ꢀ LCD Monitors
ꢀ Network Power Supplies
Typical Application Circuit
VBAT
5VSUS
5VSUS
VBAT
R1
RTON1
D1
C1 0.1uF
R2
10R
U1
Q1
C2
VOUT
R3
1
2
3
4
12
11
10
9
10uF
VOUT
VCCA
FB
DH
LX
C3
L1
R4
R5
SC411
VOUT
ILIM
VDDP
C4
+
PGOOD
PGD
Q2
R6
C5
C6
1nF
1uF
C7
1uF
June 2007
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SC411
POWER MANAGEMENT
Absolute Maximum Ratings(1)
Exceeding the specifications below may result in permanent damage to the device or device malfunction. Operation outside of the parameters
specified in the Electrical Characteristics section is not implied. Exposure to Absolute Maximum rated conditions for extended periods of time
may affect device reliability.
Parameter
Symbol
Maximum
Units
V
V
TON to VSSA
-0.3 to +25.0
-0.3 to +30.0
-2.0 to +25.0
-0.3 to +0.3
-0.3 to +6.0
-0.3 to +6.0
-0.3 to +6.0
-0.3 to +6.0
31
DH, BST to PGND
V
LX to PGND
V
PGND to VSSA
V
BST to LX
V
DL, ILIM, VDDP to PGND
EN/PSV, FB, PGD, VCCA, VOUT to VSSA
VCCA to EN/PSV, FB, PGD, VOUT
Thermal Resistance Junction to Ambient(2)(2)
V
V
°C/W
°C
°C
°C
θJA
Operating Junction Temperature Range
Storage Temperature Range
TJ
-40 to +125
-65 to +150
TSTG
IR Reflow (Soldering) 10s to 30s
TPKG
260
Notes:
1) This device is ESD sensitive. Use of standard ESD handling precautions is required.
2) Calculated from package in still air, mounted to 3” to 4.5”, 4 layer FR4 PCB with thermal vias under the exposed pad per JESD51
standards.
Electrical Characteristics
Test Conditions: VBAT = 15V, EN/PSV = 5V, VCCA = VDDP = 5V, VOUT =1.25V, RTON = 1MΩ.
25°C
Typ
-40°C to 125°C
Parameter
Conditions
Units
Min
Max
Min
Max
Input Supplies
VCCA
5.0
5.0
4.5
4.5
5.5
5.5
V
V
V
VDDP
VBAT Voltage
Off-time > 800ns
1.8
25
FB > regulation point,
ILOAD = 0A
VDDP Operating Current
VCCA Operating Current
70
150
μA
μA
FB > regulation point,
ILOAD = 0A
700
1100
© 2007 Semtech Corp.
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SC411
POWER MANAGEMENT
Electrical Characteristics (Cont.)
25°C
Typ
-40°C to 125°C
Parameter
Conditions
Units
Min
Max
Min
Max
Input Supplies (Cont.)
TON Operating Current
R
TON = 1M
15
-5
5
μA
μA
μA
μA
EN/PSV = 0V
VCCA
-10
10
1
Shutdown Current
VDDP, TON
0
Controller
VCCA = 4.5V to 5.5V
Includes variations of
internal x3 gain stage, com-
parator, and 1.5V REF
Error Comparator Threshold
(FB Turn-on Threshold)(1)
V
0.500
-1.2%
+1.2%
Output Voltage Range
On-Time, VBAT = 2.5V
0.5
1409
749
VCCA
2113
1123
550
V
RTON = 1MΩ
1761
936
400
500
ns
RTON = 500kΩ
Minimum Off-Time
ns
VOUT Input Resistance
kΩ
VOUT Shutdown
Discharge Resistance
EN/PSV = GND
22
Ω
FB Input Bias Current
Over-Current Sensing
ILIM Source Current
Current Comparator Offset
PSAVE
-1.0
+1.0
μA
DL high
10
5
9
11
10
μA
PGND - ILIM
-10
mV
(PGND - LX),
EN/PSV = 5V
Zero-Crossing Threshold
mV
Fault Protection
© 2007 Semtech Corp.
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SC411
POWER MANAGEMENT
Electrical Characteristics (Cont.)
25°C
Typ
50
-40°C to 125°C
Parameter
Conditions
Units
Min
Max
Min
35
Max
65
(PGND - LX), RILIM = 5kΩ
(PGND - LX), RILIM = 10kΩ
(PGND - LX), RILIM = 20kΩ
mV
mV
mV
Current Limit (Positive)(2)
100
200
80
120
230
170
Fault Protection (Cont.)
Current Limit (Negative)
Output Under-Voltage Fault
Output Over-Voltage Fault
(PGND - LX)
-125
-30
-160
-40
-90
-25
+20
mV
%
With respect to internal ref.
With respect to internal ref.
+16
+12
%
FB forced above
OV Threshold
Over-Voltage Fault Delay
5
μs
PGD Low Output Voltage
PGD Leakage Current
PGD UV Threshold
Sink 1mA
0.4
1
V
FB in regulation,
PGD = 5V
μA
%
With respect to internal ref.
-10
5
-12
3.7
-8
FB forced outside
PGD window
PGD Fault Delay
μs
VCCA
Under-Voltage Threshold
Falling
(100mV Hysteresis)
4.0
4.3
1.2
V
Over-Temperature Lockout
Inputs/Outputs
10°C Hysteresis
EN/PSV Low
165
°C
Logic Input Low Voltage
V
V
V
EN High,
PSV Low (Floating)
Logic Input High Voltage
Logic Input High Voltage
2.0
EN/PSV High
R Pullup to VCCA
R Pulldown to VSSA
3.1
1.5
1.0
EN/PSV Input Resistance
MΩ
© 2007 Semtech Corp.
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SC411
POWER MANAGEMENT
Electrical Characteristics (Cont.)
25°C
Typ
-40°C to 125°C
Parameter
Conditions
Units
Min
Max
Min
Max
Soft-Start
Soft-Start Ramp Time
Under-Voltage Blank Time
Gate Drivers
EN/PSV High to PGD High
EN/PSV High to UV High
440
440
clks(3)
clks(3)
Shoot-Through Delay(4)
DL Pull-Down Resistance
DL Sink Current
DH or DL Rising
DL Low
30
0.80
3.1
2
ns
Ω
A
1.75
4
DL = 2.5V
DL High
DL Pull-Up Resistance
DL Source Current
Notes:
Ω
A
DL = 2.5V
1.3
1) When the inductor is in continuous and discontinuous conduction mode, the output voltage will have a DC regulation level higher than the
error-comparator threshold by 50% of the ripple voltage.
2) Using a current sense resistor, this measurement relates to PGND minus the voltage of the source on the low-side MOSFET. These values
guaranteed by the ILIM Source Current and Current Comparator Offset tests.
3) clks = Switching cycles.
4) Guaranteed by design. See Shoot-Through Delay Timing Diagram on Page 8.
5) Semtech’s SmartDriverTM FET drive first pulls DH high with a pull-up resistance of 10Ω (typ) until LX = 1.5V (typ). At this point, an additional
pull-up device is activated, reducing the resistance to 2Ω (typ). This negates the need for an external gate or boost resistor.
© 2007 Semtech Corp.
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SC411
POWER MANAGEMENT
Block Diagram
VCCA (2)
POR / SS
OT
EN/PSV (15)
DSCHG
BST (13)
DH (12)
LX (11)
TON (16)
VOUT (1)
ON
TON
TOFF
HI
OFF
PWM
CONTROL
LOGIC
DSCHG
OC
ZERO
1.5V REF
ISENSE
ILIM (10)
+
-
VDDP (9)
DL (8)
FB (3)
X3
LO
Error Comparator
PGD (4)
PGND (7)
OV
UV
FAULT
MONITOR
VSSA (6)
NC (5)
NC (14)
REF + 16%
REF - 10%
REF - 30%
Note: the Error Comparator tolerances are approximately
x3 gain stage = +/- 0.1% gain error
comparator = +/- 3mV offset error
1.5V REF = +/- 1.0%
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SC411
POWER MANAGEMENT
Pin Configuration
Ordering Information
Device
Package(1)
SC411MLTRT(2)
SC411EVB
MLPQ-16
16
15
14
13
Evaluation Board
1
2
3
4
12
11
10
9
DH
VOUT
VCCA
Notes:
TOP VIEW
1) Only available in tape and reel packaging. A reel contains 3000
devices.
(2) Lead free product. This product is fully WEEE, RoHS and
J-STD-020B compliant.
LX
ILIM
VDDP
FB
T
PGD
5
6
7
8
MLPQ16: 4X4 BODY
Pin Descriptions
Pin #
Pin Name
Pin Function
1
2
VOUT
VCCA
Output voltage sense input. Connect to the output at the load.
Supply voltage input for the analog supply. Use a 10Ω /1μF RC filter from 5VSUS to VSSA.
Feedback input. Connect to a resistor divider located at the IC from VOUT to VSSA to
set the output voltage from 0.5V to VCCA.
3
4
FB
Power Good open drain NMOS output. Goes high after a fixed clock cycle delay
(440 cycles) following power up.
PGD
5
6
7
8
NC
VSSA
PGND
DL
Not Connected.
Ground reference for analog circuitry. Connect directly to thermal pad.
Power ground. Connect directly to thermal pad.
Gate drive output for the low side MOSFET switch.
+5V supply voltage input for the gate drivers. Decouple this pin with a 1μF ceramic
capacitor to PGND.
9
VDDP
Current limit input. Connect to drain of low-side MOSFET for RDS(on) sensing or the
source for resistor sensing through a threshold sensing resistor.
10
11
ILIM
LX
Phase node (junction of top and bottom MOSFETs and the output inductor) connection.
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SC411
POWER MANAGEMENT
Pin Descriptions (Cont.)
12
13
14
DH
BST
NC
Gate drive output for the high side MOSFET switch.
Boost capacitor connection for the high side gate drive.
Not connected.
Enable/Power Save input. Pull down to VSSA to shut down VOUT and discharge it through
22Ω (nom.). Pull up to enable VOUT and activate PSAVE mode. Float to enable VOUT ac-
tivate continuous conduction mode (CCM). If floated, bypass to VSSA with a 10nF ceramic
capacitor.
15
EN/PSV
This pin is used to sense VBAT through a pullup resistor, RTON, and to set the top MOSFET
on-time. Bypass this pin with a 1nF ceramic capacitor to VSSA.
16
-
TON
Thermal
Pad
Pad for heatsinking purposes. Connect to ground plane using multiple vias.
Not connected internally.
Shoot-Through Delay Timing Diagram
LX
DH
DL
DL
tplhDL
tplhDH
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SC411
POWER MANAGEMENT
Application Information
+5V Bias Supplies
in a nearly constant switching frequency without the need
for a clock generator.
The SC411 requires an external +5V bias supply in addi- For VOUT < 3.3V:
tion to the battery. If stand-alone capability is required,
⎛
⎞
VOUT
VBAT
the +5V supply can be generated with an external linear
tON = 3.3x10−12 • (RTON + 37x10 )•
+ 50ns
3
⎜
⎜
⎟
⎟
regulator such as the Semtech LP2951.
⎝
⎠
For optimal operation, the controller has its own ground
reference, VSSA, which should be tied along with PGND
directly to the thermal pad under the part, which in turn
should connect to the ground plane using multiple vias.
All external components referenced to VSSA in the Typical
Application Circuit on Page 1 located near their respec-
tive pins. Supply decoupling capacitors should be located
adjacent to their respective pins. A 10Ω resistor should
be used to decouple VCCA from the main VDDP supply. All
ground connections are connected directly to the ground
plane as mentioned above. VSSA and PGND should be
starred at the thermal pad. The VDDP input provides
power to the upper and lower gate drivers; a decoupling
capacitor is required. No series resistor between VDDP
and 5V is required. See Layout Guidelines on page 17 for
more details.
For 3.3V ≤ VOUT ≤ 5V:
⎛
⎞
VOUT
tON = 0.85 • 3.3x10−12 • (RTON + 37x10 )•
+ 50ns
3
⎜
⎜
⎟
⎟
VBAT
⎝
⎠
RTON is a resistor connected from the input supply (VBAT)
to the TON pin. Due to the high impedance of this resistor,
the TON pin should always be bypassed to VSSA using a
1nF ceramic capacitor.
EN/PSV: Enable, PSAVE and Soft Discharge
The EN/PSV pin enables the supply. When EN/PSV is
tied to VCCA the controller is enabled and power save will
also be enabled. When the EN/PSV pin is tri-stated, an
internal pull-up will activate the controller and power save
will be disabled. If PSAVE is enabled, the SC411 PSAVE
comparator will look for the inductor current to cross zero
on eight consecutive switching cycles by comparing the
phase node (LX) to PGND. Once observed, the controller
will enter power save and turn off the low side MOSFET
when the current crosses zero. To improve light-load ef-
ficiency and add hysteresis, the on-time is increased by
50% in power save. The efficiency improvement at light-
loads more than offsets the disadvantage of slightly high-
er output ripple. If the inductor current does not cross
zero on any switching cycle, the controller will immediately
exit power save. Since the controller counts zero cross-
ings, the converter can sink current as long as the cur-
rent does not cross zero on eight consecutive cycles. This
allows the output voltage to recover quickly in response
to negative load steps even when PSAVE is enabled. If
the EN/PSV pin is pulled low, the related output will be
shut down and discharged using a switch with a nominal
resistance of 22 Ohms. This will ensure that the output is
in a defined state next time it is enabled and also ensure,
since this is a soft discharge, that there are no danger-
ous negative voltage excursions to be concerned about. In
order for the soft discharge circuitry to function correctly,
the chip supply must be present.
Pseudo-Fixed Frequency Constant On-Time PWM
Controller
The PWM control architecture consists of a constant on-
time, pseudo fixed frequency PWM controller (Block Dia-
gram, Page 6). The output ripple voltage developed across
the output filter capacitor’s ESR provides the PWM ramp
signal eliminating the need for a current sense resistor.
The high-side switch on-time is determined by a one-shot
whose period is directly proportional to output voltage and
inversely proportional to input voltage. A second one-shot
sets the minimum off-time which is typically 400ns.
On-Time One-Shot (tON)
The on-time one-shot comparator has two inputs. One
input looks at the output voltage, while the other input
samples the input voltage and converts it to a current.
This input voltage-proportional current is used to charge
an internal on-time capacitor. The on-time is the time re-
quired for the voltage on this capacitor to charge from zero
volts to VOUT, thereby making the on-time of the high-side
switch directly proportional to output voltage and inversely
proportional to input voltage. This implementation results
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SC411
POWER MANAGEMENT
Application Information (Cont.)
Output Voltage Selection
tor. In an extreme over-current situation, the top MOSFET
will never turn back on and eventually the part will latch
The output voltage is set by the feedback resistors R3 & off due to output under-voltage (see Output Under-voltage
R5 of Figure 2 below. The internal reference is 1.5V, so Protection).
the voltage at the feedback pin is multiplied by three to
match the 1.5V reference. Therefore the output can be The current sensing circuit actually regulates the induc-
set to a minimum of 0.5V. The equation for setting the tor valley current (see Figure 3). This means that if the
output voltage is:
current limit is set to 10A, the peak current through the
inductor would be 10A plus the peak ripple current, and
the average current through the inductor would be 10A
plus 1/2 the peak-to-peak ripple current. The equations
for setting the valley current and calculating the average
current through the inductor are shown below:
R3
R5
VOUT = ( 1 + ――― ) • 0.5
U1
VOUT
R3
1
12
11
10
9
VOUT
DH
C5
20k0
2
VCCA
LX
56p
0402
0402
SC411
3
FB
ILIM
4
PGD
VDDP
R5
14k3
0402
Figure 2: Setting The Output Voltage
Current Limit Circuit
Figure 3: Valley Current Limiting
Current limiting of the SC411 can be accomplished in two
ways. The on-state resistance of the low-side MOSFET
can be used as the current sensing element or sense
resistors in series with the low-side source can be used
if greater accuracy is desired. RDS(ON) sensing is more ef-
ficient and less expensive. In both cases, the RILIM resis-
tor between the ILIM pin and LX pin sets the over current
threshold. This resistor RILIM is connected to a 10μA cur-
rent source within the SC411 which is turned on when
the low side MOSFET turns on. When the voltage drop
across the sense resistor or low side MOSFET equals the
voltage across the RILIM resistor, positive current limit
will activate. The high side MOSFET will not be turned on
until the voltage drop across the sense element (resistor
or MOSFET) falls below the voltage across the RILIM resis-
The equation for the current limit threshold is as follows:
ILIMIT = 10μA × RILIM / RSENSE (Amps)
Where (referring to Figure 4 on Page 17) RILIM is R4 and
RSENSE is the RDS(ON) of Q2.
For resistor sensing, a sense resistor is placed between
the source of Q2 and PGND. The current through the
source sense resistor develops a voltage that opposes the
voltage developed across RILIM. When the voltage devel-
oped across the RSENSE resistor reaches the voltage drop
across RILIM, a positive over-current exists and the high
side MOSFET will not be allowed to turn on. When using
an external sense resistor RSENSE is the resistance of the
sense resistor.
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SC411
POWER MANAGEMENT
Application Information (Cont.)
The current limit circuitry also protects against negative resets the fault latch and soft-start counter, and allows
over-current (i.e. when the current is flowing from the load switching to occur if the device is enabled. Switching al-
to PGND through the inductor and bottom MOSFET). In ways starts with DL to charge up the BST capacitor. With
this case, when the bottom MOSFET is turned on, the the soft-start circuit (automatically) enabled, it will pro-
phase node, LX, will be higher than PGND initially. The gressively limit the output current (by limiting the current
SC411 monitors the voltage at LX, and if it is greater than out of the ILIM pin) over a predetermined time period of
a set threshold voltage of 125mV (nom) the bottom MOS- 440 switching cycles.
FET is turned off. The device then waits for approximately
2.5μs and then DL goes high for 300ns (typ) once more The ramp occurs in four steps:
to sense the current. This repeats until either the over-
current condition goes away or the part latches off due to 1) 110 cycles at 25% ILIM with double minimum off-time
output over-voltage (see Output Over-voltage Protection). (for purposes of the on-time one-shot, there is an internal
positive offset of 120mV to VOUT during this period to aid
Power Good Output
in startup).
2) 110 cycles at 50% ILIM with normal minimum off-
The power good output is an open-drain output and re- time.
quires a pull-up resistor. When the output voltage is 16% 3) 110 cycles at 75% ILIM with normal minimum off-time.
above or 10% below its set voltage, PGD gets pulled low. It 4) 110 cycles at 100% ILIM with normal minimum off-
is held low until the output voltage returns to within these time.
tolerances once more. PGD is also held low during start-
up and will not be allowed to transition high until soft start At this point the output under-voltage and power good cir-
is over (440 switching cycles) and the output reaches 90% cuitry is enabled.
of its set voltage. There is a 5μs delay built into the PGD
circuitry to prevent false transitions.
There is 100mV of hysteresis built into the UVLO circuit
and when VCCA falls to 4.1V (nom) the output drivers are
shut down and tri-stated.
Output Over-Voltage Protection
When the output exceeds 16% of the its set voltage the MOSFET Gate Drivers
low-side MOSFET is latched on. It stays latched on and
the controller is latched off until reset*. There is a 5μs The DH and DL drivers are optimized for driving moder-
delay built into the OV protection circuit to prevent false ate-sized high-side, and larger low-side power MOSFETs.
transitions.
An adaptive dead-time circuit monitors the DL output and
prevents the high-side MOSFET from turning on until DL is
fully off (below ~1V). Semtech’s SmartDriverTM FET drive
first pulls DH high with a pull-up resistance of 10Ω (typ)
Output Under-Voltage Protection
When the output is 30% below its set voltage the output until LX = 1.5V (typ). At this point, an additional pull-up
is latched in a tri-stated condition. It stays latched and device is activated, reducing the resistance to 2Ω (typ);
the controller is latched off until reset*. There is a 5μs This negates the need for an external gate or boost re-
delay built into the UV protection circuit to prevent false sistor. The adaptive dead time circuit also monitors the
transitions.
phase node, LX, to determine the state of the high side
MOSFET, and prevents the low side MOSFET from turning
on until DH is fully off (LX below ~1V). Be sure there is
low resistance and low inductance between the DH and
POR, UVLO and Soft-Start
An internal power-on reset (POR) occurs when VCCA ex- DL outputs to the gate of each MOSFET.
ceeds 3V, starting up the internal biasing. VCCA under-
voltage lockout (UVLO) circuitry inhibits the controller until
VCCA rises above 4.2V. At this time the UVLO circuitry
* Note: to reset from any fault, VCCA or EN/PSV must be toggled.
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SC411
POWER MANAGEMENT
Application Information (Cont.)
Dropout Performance
Switching frequency variation with load can be minimized
by choosing MOSFETs with lower RDS(ON). High RDS(ON)
The output voltage adjust range for continuous-conduction MOSFETs will cause the switching frequency to increase
operation is limited by the fixed 550ns (maximum) mini- as the load current increases. This will reduce the ripple
mum off-time one-shot. For best dropout performance, and thus the DC output voltage.
use the slowest on-time setting of 200kHz. When work-
ing with low input voltages, the duty-factor limit must be Design Procedure
calculated using worst-case values for on and off times.
The IC duty-factor limitation is given by:
Prior to designing an output and making component selec-
tions, it is necessary to determine the input voltage range
and the output voltage specifications. For purposes of
demonstrating the procedure the output for the schemat-
ic in Figure 4 on Page 17 will be designed.
t
ON(MIN )
DUTY =
t
+
t
OFF(MAX )
ON(MIN )
Be sure to include inductor resistance and MOSFET on-
state voltage drops when performing worst-case dropout The maximum input voltage (VBAT(MAX)) is determined by the
duty-factor calculations.
highest AC adaptor voltage. The minimum input voltage
(VBAT(MIN)) is determined by the lowest battery voltage after
accounting for voltage drops due to connectors, fuses and
battery selector switches. For the purposes of this design
SC411 System DC Accuracy
Two IC parameters affect system DC accuracy, the error example we will use a VBAT range of 8V to 20V.
comparator threshold voltage variation and the switching
frequency variation with line and load. The error com- Four parameters are needed for the output:
parator threshold does not drift significantly with supply 1) nominal output voltage, VOUT (we will use 1.2V).
and temperature. Thus, the error comparator contributes 2) static (or DC) tolerance, TOLST (we will use +/-4%).
1.2% or less to DC system inaccuracy. Board components 3) transient tolerance, TOLTR and size of transient (we will
and layout also influence DC accuracy. The use of 1% use +/-8% and 6A for purposes of this demonstration).
feedback resistors contribute 1%. If tighter DC accuracy 4) maximum output current, IOUT (we will design for 6A).
is required use 0.1% feedback resistors.
Switching frequency determines the trade-off between
The on-pulse in the SC411 is calculated to give a pseu- size and efficiency. Increased frequency increases the
do- fixed frequency. Nevertheless, some frequency varia- switching losses in the MOSFETs, since losses are a func-
tion with line and load can be expected. This variation tion of VIN2. Knowing the maximum input voltage and
changes the output ripple voltage. Because constant-on budget for MOSFET switches usually dictates where the
regulators regulate to the valley of the output ripple, ½ of design ends up. A default RtON value of 1MΩ is suggested
the output ripple appears as a DC regulation error. For as a starting point, but this is not set in stone. The first
example, if the feedback resistors are chosen to divide thing to do is to calculate the on-time, tON, at VBAT(MIN) and
down the output by a factor of five, the valley of the output VBAT(MAX), since this depends only upon VBAT, VOUT and RtON.
ripple will be VOUT. For example: if VOUT is 2.5V and the
ripple is 50mV with VBAT = 6V, then the measured DC For VOUT < 3.3V:
output will be 2.525V. If the ripple increases to 80mV
with VBAT = 25V, then the measured DC output will be
2.540V.
VOUT
VBAT(MIN)
RtON + 37 103
3.3 10-12
=
+ 50 10-9
s
tON_VBAT(MIN)
The output inductor value may change with current. This
will change the output ripple and thus the DC output volt-
age but it will not change the frequency.
© 2007 Semtech Corp.
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SC411
POWER MANAGEMENT
Application Information (Cont.)
and,
and,
IRIPPLE_VBAT(MAX) = VBAT(MAX) VOUT
tON_VBAT(MAX)
VOUT
VBAT(MAX)
3.3 10-12
=
RtON + 37 103
+ 50 10-9
s
AP-P
tON_VBAT(MAX)
L
From these values of tON we can calculate the nominal For our example:
switching frequency as follows:
IRIPPLE_VBAT(MIN) = 1.74AP-P and IRIPPLE_VBAT(MAX) = 2.18AP-P
VOUT
fSW _ VBAT(MIN )
=
Hz
(
VBAT(MIN ) • tON _ VBAT(MIN )
)
From this we can calculate the minimum inductor current
rating for normal operation:
and,
IRIPPLE_ VBAT(MAX )
VOUT
IINDUCTOR(MIN ) = IOUT(MAX )
+
A(MIN )
fSW _ VBAT(MAX )
=
Hz
2
(
VBAT(MAX ) • tON _ VBAT(MAX )
)
For our example:
tON is generated by a one-shot comparator that samples
VBAT via RtON, converting this to a current. This current is IINDUCTOR(MIN) = 7.1A(MIN)
used to charge an internal 3.3pF capacitor to VOUT. The
equations above reflect this along with any internal com- Next we will calculate the maximum output capacitor
ponents or delays that influence tON. For our example we equivalent series resistance (ESR). This is determined by
select RtON = 1MΩ:
calculating the remaining static and transient tolerance
allowances. Then the maximum ESR is the smaller of the
calculated static ESR (RESR_ST(MAX)) and transient ESR
(RESR_TR(MAX)):
tON_VBAT(MIN) = 563ns and tON_VBAT(MAX) = 255ns
fSW_VBAT(MIN) = 266kHz and fSW_VBAT(MAX) = 235kHz
(
ERRST − ERRDC • 2
)
RESR_ST(MA X )
=
Ohms
IRIPPLE_ VBAT(MA X )
Now that we know tON we can calculate suitable values for
the inductor. To do this we select an acceptable inductor
ripple current. The calculations below assume 50% of IOUT Where ERRST is the static output tolerance and ERRDC is
which will give us a starting place.
the DC error. The DC error will be 1.2% plus the tolerance
of the feedback resistors, thus 2.2% total for 1% feedback
resistors.
tON_VBAT(MIN)
H
H
LVBAT(MIN) = VBAT(MIN) VOUT
0.5 IOUT
For our example:
and,
ERRST = 48mV and ERRDC = 26.4mV, therefore,
RESR_ST(MAX) = 19.8mΩ
tON_VBAT(MAX)
LVBAT(MAX) = VBAT(MAX) VOUT
0.5 IOUT
For our example:
(
ERRTR − ERRDC
)
RESR_TR(MAX )
=
Ohms
IRIPPLE_ VBAT(MAX )
⎛
⎞
⎜
⎜
⎟
⎟
IOUT
+
LVBAT(MIN) = 1.3μH and LVBAT(MAX) = 1.6μH
2
⎝
⎠
We will select an inductor value of 2.2μH to reduce the Where ERRTR is the transient output tolerance. Note that
ripple current, which can be calculated as follows:
this calculation assumes that the worst case load tran-
sient is full load. For half of full load, divide the IOUT term
by 2.
tON_VBAT(MIN)
AP-P
IRIPPLE_VBAT(MIN) = VBAT(MIN) VOUT
L
© 2007 Semtech Corp.
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SC411
POWER MANAGEMENT
Application Information (Cont.)
For our example:
Firstly calculating the value of ZTOP required:
ERRTR = 96mV and ERRDC = 26.4mV, therefore,
RBOT
ZTOP
=
•
(
VRIPPLE_ VBAT(MIN ) − 0.015 Ohms
)
0.015
RESR_TR(MAX) = 9.8mΩ for a full 6A load transient
We will select a value of 12.5mΩ maximum for our de-
sign, which would be achieved by using two 25mΩ output
capacitors in parallel.
Secondly calculating the value of CTOP required to achieve
this:
⎛
⎞
1
1
⎜
⎜
⎟
⎟
−
ZTOP RTOP
⎝
⎠
CTOP
=
F
Note that for constant-on converters there is a minimum
2 • π • fSW _ VBAT(MIN )
ESR requirement for stability which can be calculated as
follows:
For our example we will use RTOP = 20.0kΩ and RBOT
14.3kΩ, therefore,
=
3
RESR(MIN )
=
2 • π • COUT • fSW
ZTOP = 6.67kΩ and CTOP = 60pF
This criteria should be checked once the output
capacitance has been determined.
We will select a value of CTOP = 56pF. Calculating the
value of VFB based upon the selected CTOP:
Now that we know the output ESR we can calculate the
output ripple voltage:
⎛
⎜
⎞
⎟
⎜
⎟
⎟
⎟
⎟
⎟
⎜
⎜
⎜
⎜
RBOT
VFB _ VBAT(MIN ) = VRIPPLE_ VBAT(MIN )
•
VP−P
1
VRIPPLE_ VBAT(MAX ) = RESR •IRIPPLE_ VBAT(MAX )VP−P
RBOT +
1
+ 2 • π • fSW _ VBAT(MIN ) • CTOP
⎜
⎝
⎟
⎠
RTOP
and,
For our example:
VRIPPLE_ VBAT(MIN ) = RESR •IRIPPLE_ VBAT(MIN )VP−P
VFB_VBAT(MIN) = 14.8mVP-P - good
For our example:
Next we need to calculate the minimum output capaci-
tance required to ensure that the output voltage does not
exceed the transient maximum limit, POSLIMTR, starting
from the actual static maximum, VOUT_ST_POS, when a load
release occurs:
VRIPPLE_VBAT(MAX) = 27mVP-P and VRIPPLE_VBAT(MIN) = 22mVP-P
Note that in order for the device to regulate in a controlled
manner, the ripple content at the feedback pin, VFB, should
be approximately 15mVP-P at minimum VBAT, and worst
case no smaller than 10mVP-P. If VRIPPLE_VBAT(MIN) is less than
15mVP-P the above component values should be revisited
in order to improve this. Quite often a small capacitor,
CTOP, is required in parallel with the top feedback resis-
tor, RTOP, in order to ensure that VFB is large enough. CTOP
should not be greater than 100pF. The value of CTOP can
be calculated as follows, where RBOT is the bottom feed-
back resistor.
VOUT _ST_POS = VOUT + ERRDC
V
For our example:
VOUT_ST_POS = 1.226V
POSLIM TR = VOUT • TOL TR
V
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SC411
POWER MANAGEMENT
Application Information (Cont.)
Where TOLTR is the transient tolerance. For our example: Finally, we calculate the current limit resistor value. As
described in the current limit section, the current limit
POSLIMTR = 1.296V
looks at the “valley current”, which is the average output
current minus half the ripple current. We use the maxi-
mum room temperature specification for MOSFET RDS(ON)
at VGS = 4.5V for purposes of this calculation:
The minimum output capacitance is calculated as
follows:
IRIPPLE_ VBAT(MIN )
2
IVALLEY = IOUT
−
A
IRIPPLE_VBAT(MAX)
2
IOUT
+
2
CCOUT(MIN)
=
L
F
The ripple at low battery voltage is used because we want
to make sure that current limit does not occur under nor-
mal operating conditions.
2
2
VOUT_ST_POS
POSLIMTR
RDS(ON) •1.4
10 •10−6
RILIM
=
(
IVALLEY •1.2
)
•
Ohms
This calculation assumes the absolute worst case condi-
tion of a full-load to no load step transient occurring when
the inductor current is at its highest. The capacitance For our example:
required for smaller transient steps may be calculated by
substituting the desired current for the IOUT term.
IVALLEY = 5.13A, RDS(ON) = 9mΩ and RILIM = 7.76kΩ
We select the next lowest 1% resistor value: 7.68kΩ
Thermal Considerations
For our example:
COUT(MIN) = 626μF.
We will select 440μF, using two 220μF, 25mΩ capacitors The junction temperature of the device may be calculated
in parallel. For smaller load release overshoot, 660μF as follows:
may be used. Alternatively, one 15mΩ or 12mΩ, 220μF,
330μF or 470μF capacitor may be used (with the appro-
TJ = TA + PD • θJA °C
priate change to the calculation for CTOP), depending upon
the load transient requirements.
Where:
Next we calculate the RMS input ripple current, which is
largest at the minimum battery voltage:
TA = ambient temperature (°C)
PD = power dissipation in (W)
θJA = thermal impedance junction to ambient
from absolute maximum ratings (°C/W)
IOUT
IIN(RMS)
=
VOUT
•
(
VBAT(MIN ) − VOUT
)
•
ARMS
VBAT_MIN
The power dissipation may be calculated as follows:
For our example:
IIN(RMS) = 2.14ARMS
PD = VCCA •IVCCA + VDDP •IVDDP
+ Vg • Qg • f + VBST •1mA •D
W
Where:
Input capacitors should be selected with sufficient ripple
current rating for this RMS current, for example a 10μF,
1210 size, 25V ceramic capacitor can handle approxi-
mately 3ARMS. Refer to manufacturer’s data sheets and
derate appropriately.
VCCA = chip supply voltage (V)
IVCCA = operating current (A)
VDDP = gate drive supply voltage (V)
© 2007 Semtech Corp.
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SC411
POWER MANAGEMENT
Application Information (Cont.)
IVDDP
Vg
Qg
f
= gate drive operating current (A)
= gate drive voltage, typically 5V (V)
= FET gate charge, from the FET datasheet (C)
= switching frequency (kHz)
VBST = boost pin voltage during tON (V)
= duty cycle
D
Inserting the following values for VBAT(MIN) condition (since
this is the worst case condition for power dissipation in
the controller) as an example (VOUT = 1.2V),
TA
= 85°C
θJA
= 100°C/W
VCCA = VDDP = 5V
IVCCA
IVDDP
Vg
= 1100μA (data sheet maximum)
= 150μA (data sheet maximum)
= 5V
Qg
f
= 60nC
= 266kHz
VBAT(MIN) = 8V
VBST(MIN) = VBAT(MIN)+VDDP = 13V
D(MIN) = 1.2/8 = 0.15
gives us,
PD = 5 •1100 •10−6 + 5 •150 •10−6
+ 5 • 60 •10−9 • 266 •103 +13 •1•10−3 • 0.15
= 0.088
W
and,
TJ = 85 + 0.088 •100 = 93.8 °C
As can be seen, the heating effects due to internal power
dissipation are practically negligible, thus requiring no
special thermal consideration during layout.
The Reference Design is shown in Figure on Page 17.
An additional design optimized for efficiency and capable
of a higher load current of 10A is shown in Figure 11 on
Page 21.
© 2007 Semtech Corp.
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SC411
POWER MANAGEMENT
Layout Guidelines
VBAT
5VSUS
5VSUS
VBAT
R1
1M
0402
D1
SOD323
C1 0u1
R2
10R
0402
0603
U1
Q1
IRF7811AV
C2
C3
C4
VOUT
1
2
3
4
12
11
10
9
2n2/50V
0402
0u1/25V
0603
10u/25V
1210
VOUT
VCCA
FB
DH
LX
C5
R3
20k0
0402
56p
L1 2u2
0402
R4 7k87
0402
SC411
VOUT
ILIM
VDDP
C6
C7
+
+
Q2
FDS6676S
PGOOD
PGD
220u/25m 220u/25m
7343
7343
R5
C8
14k3
0402
C9
1nF
1uF
0402
0603
C10
VBAT = 8V to 20V
VOUT = 1.2V @ 6A
1uF
0603
Figure 4: Reference Design
One (or more) ground planes is/are recommended to minimize the effect of switching noise and copper losses, and
maximize heat dissipation. The IC ground reference, VSSA, and the power ground pin, PGND, should both connect
directly to the device thermal pad. The thermal pad should connect to the ground plane(s) using multiple vias.
The VOUT feedback trace must be kept far away from noise sources such as switching nodes, inductors and gate
drives. Route the feedback trace in a quiet layer (if possible) from the output capacitor back to the chip. All compo-
nents should be located adjacent to their respective pins with an emphasis on the chip decoupling capacitors (VCCA
and VDDP) and the components that are shown connecting to VSSA in the above schematic. Make any ground con-
nections simply to the ground plane.
Power sections should connect directly to the ground plane(s) using multiple vias as required for current handling (in-
cluding the chip power ground connections). Power components should be placed to minimize loops and reduce loss-
es. Make all the connections on one side of the PCB using wide copper filled areas if possible. Do not use “minimum”
land patterns for power components. Minimize trace lengths between the gate drivers and the gates of the MOSFETs
to reduce parasitic impedances (and MOSFET switching losses), the low-side MOSFET is most critical. Maintain a
length to width ratio of <20:1 for gate drive signals. Use multiple vias as required by current handling requirements
(and to reduce parasitics) if routed on more than one layer. Current sense connections must always be made using
Kelvin connections to ensure an accurate signal, with the current limit resistor located at the device.
We will examine the reference design used in the Design Procedure section while explaining the layout guidelines in
more detail.
© 2007 Semtech Corp.
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SC411
POWER MANAGEMENT
The layout can be considered in two parts, the control section referenced to VSSA and the power section. Looking at
the control section first, locate all components referenced to VSSA on the schematic and place these components at
the chip. Drop vias to the ground plane as needed.
VBAT
5VSUS
5VSUS
R1
1M
0402
R2
10R
0402
U1
VOUT
1
2
3
4
12
11
10
9
VOUT
VCCA
FB
DH
LX
C5
R3
20k0
0402
56p
0402
SC411
ILIM
VDDP
PGD
R5
14k3
0402
C8
C9
1nF
0402
1uF
0603
C10
1uF
0603
Figure 5: Components Connected to VSSA
Figure 6: Control Section Example
In Figure 6 above, all components referenced to VSSA have been placed and connected to the ground plane with
vias. Decoupling capacitors C9 and C10 are as close as possible to their pins and connected to the ground plane
with vias. Note how the VSSA and PGND pins are connected directly to the thermal pad, which has 4 vias to the
ground plane (not shown).
© 2007 Semtech Corp.
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SC411
POWER MANAGEMENT
As shown below, VOUT should be routed away from noisy traces (such as BST, DH, DL and LX) and in a quiet layer (if
possible) to the output capacitor(s).
U1
VOUT
1
2
3
4
12
11
10
9
VOUT
VCCA
FB
DH
LX
C5
R3
20k0
0402
56p
0402
SC411
VOUT
ILIM
VDDP
C6
C7
+
+
PGD
220u/25m 220u/25m
7343 7343
R5
14k3
0402
Figure 7: VOUT Sense Trace Routing
Next, the schematic in Figure 8 below shows the power section. The highest di/dts occur in the input loop (highlight-
ed in red) and thus this loop should be kept as small as possible.
VBAT
Q 1
IR F 7811AV
C 2
C 3
C 4
2n2/50V
0402
0u1/25V
0603
10u/25V
1210
L1 2u2
VO U T
C 6
C 7
+
+
Q 2
F D S6676S
220u/25m
7343
220u/25m
7343
Figure 8: Power Section and Input Loop
The input capacitors should be placed with the highest frequency capacitors closest to the loop to reduce EMI. Use
large copper pours to minimize losses and parasitics. See Figure 9 for an example.
© 2007 Semtech Corp.
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SC411
POWER MANAGEMENT
Figure 9: Power Component Placement and Copper Pours
Key points for the power section:
1) There should be a very small input loop, well decoupled.
2) The phase node should be a large copper pour, but compact since this is the noisiest node.
3) Input power ground and output power ground should not connect directly, but through the ground planes instead.
4) The current limit resistor should be placed as close as possible to the ILIM and LX pins.
Connecting the control and power sections should be accomplished as follows (see Figure 10 on the following page):
1) Route VOUT in a “quiet” layer away from noise sources.
2) Route DL, DH and LX (low side FET gate drive, high side FET gate drive and phase node) to chip using wide traces
with multiple vias if using more than one layer. These connections to be as short as possible for loop minimization,
with a length to width ratio less than 20:1 to minimize impedance. DL is the most critical gate drive, with power ground
as its return path. LX is the noisiest node in the circuit, switching between VBAT and ground at high frequencies, thus
should be kept as short as practical. DH has LX as its return path.
3) BST is also a noisy node and should be kept as short as possible.
4) Connect PGND and VSSA directly to the thermal pad, and connect the thermal pad to the ground plane using mul-
tiple vias.
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SC411
POWER MANAGEMENT
U1
Q1
IRF7811AV
1
12
11
10
9
VOUT
DH
LX
2
VCCA
L1 2u2
R4 7k87
0402
SC411
3
4
FB
ILIM
Q2
FDS6676S
PGD
VDDP
Figure 10: Connecting the Control and Power Sections
Phase nodes (black) to be copper islands (preferred) or wide copper traces. Gate drive traces (red) and phase node
traces (blue) to be wide copper traces (L:W < 20:1) and as short as possible, with DL the most critical.
VBAT
5VSUS
5VSUS
VBAT
R1
806k
0402
D1
SOD323
R2
10R
C1
0u1
0603
U1
0402
Q1
IRF7821
C2
C3
C4
VOUT
2n2/50V
0402
0u1/25V
0603
10u/25V
1210
1
2
3
4
12
11
10
9
VOUT
VCCA
FB
DH
LX
C5
R3
28k
0402
220p
0402
R4 7k15
0402
VOUT
SC411
ILIM
L1
1u5
C6
C7
+
+
Q2
IRF7832
PGOOD
PGD
VDDP
470u/15m 470u/15m
7343
7343
R5
20k
0402
C8
C9
1nF
0402
1uF
0603
L1 = 1.5uH Vishay IHLP 5050CE
C6, C7 = 470uF / 15milli ohm
Sanyo POS Cap 2R5TPE470MF
C10
VBAT = 8V to 20V
VOUT = 1.2V @ 10A
1uF
0603
Figure 11: High Efficiency Design
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SC411
POWER MANAGEMENT
Typical Characteristics
For efficiency charts, refer to High Efficiency Design, Figure 11 on page 21.
For all other data, refer to the Reference Design, Figure 4 on Page 17.
1.2V Efficiency (Power Save Mode)
1.2V Efficiency (Continuous Conduction Mode)
(High Efficiency Design, Page 21)
(High Efficiency Design, Page 21)
100
95
90
85
80
75
70
65
60
55
50
100
95
90
85
80
75
70
65
60
55
50
VBAT = 8V
VBAT = 8V
VBAT = 20V
VBAT = 20V
0
1
2
3
4
5
6
7
8
9
10
0
1
2
3
4
5
6
7
8
9
10
I
OUT (A)
I
OUT (A)
1.2V Output Voltage (Power Save Mode)
vs. Output Current vs. Input Voltage
1.2V Output Voltage (Continuous Conduction Mode)
vs. Output Current vs. Input Voltage
1.220
1.216
1.212
1.208
1.204
1.200
1.196
1.192
1.188
1.184
1.180
1.220
1.216
1.212
1.208
VBAT = 20V
VBAT = 20V
1.204
1.200
1.196
VBAT = 8V
VBAT = 8V
1.192
1.188
1.184
1.180
0
1
2
3
OUT (A)
4
5
6
0
1
2
3
IOUT (A)
4
5
6
I
1.2V Switching Frequency (Power Save Mode)
vs. Output Current vs. Input Voltage
1.2V Switching Frequency (Continuous Conduction
Mode) vs. Output Current vs. Input Voltage
400
400
VBAT = 8V
VBAT = 8V
350
300
250
200
150
100
50
350
300
250
VBAT = 20V
VBAT = 20V
200
150
100
50
0
0
0
1
2
3
4
5
6
0
1
2
3
4
5
6
IOUT (A)
IOUT (A)
© 2007 Semtech Corp.
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SC411
POWER MANAGEMENT
Typical Characteristics
Load Transient Response,
Continuous Conduction Mode, 0A to 6A to 0A
Trace 1: 1.2V, 50mV/div., AC coupled
Trace 2: LX, 20V/div
Trace 3: not connected
Trace 4: load current, 5A/div
Timebase: 40μs/div.
Load Transient Response,
Continuous Conduction Mode, 0A to 6A Zoomed
Trace 1: 1.2V, 20mV/div., AC coupled
Trace 2: LX, 10V/div
Trace 3: not connected
Trace 4: load current, 5A/div
Timebase: 10μs/div.
Load Transient Response,
Continuous Conduction Mode, 6A to 0A Zoomed
Trace 1: 1.2V, 50mV/div., AC coupled
Trace 2: LX, 10V/div
Trace 3: not connected
Trace 4: load current, 5A/div
Timebase: 10μs/div.
Please refer to Figure 4 on Page 17 for test schematic
© 2007 Semtech Corp.
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SC411
POWER MANAGEMENT
Typical Characteristics
Load Transient Response,
Power Save Mode, 0A to 6A to 0A
Trace 1: 1.2V, 50mV/div., AC coupled
Trace 2: LX, 20V/div
Trace 3: not connected
Trace 4: load current, 5A/div
Timebase: 40μs/div.
Startup (CCM), EN/PSV 0V to Floating
Trace 1: 1.2V, 20mV/div., AC coupled
Trace 2: LX, 10V/div
Trace 3: not connected
Trace 4: load current, 5A/div
Timebase: 10μs/div.
Load Transient Response,
Power Save Mode, 6A to 0A Zoomed
Trace 1: 1.2V, 50mV/div., AC coupled
Trace 2: LX, 10V/div
Trace 3: not connected
Trace 4: load current, 5A/div
Timebase: 10μs/div.
Please refer to Figure 4 on Page 17 for test schematic
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SC411
POWER MANAGEMENT
Typical Characteristics
Startup (PSV), EN/PSV Going High
Trace 1: 1.2V, 0.5V/div.
Trace 2: LX, 10V/div
Trace 3: EN/PSV, 5V/div
Trace 4: PGD, 5V/div.
Timebase: 1ms/div.
Startup (CCM), EN/PSV 0V to Floating
Trace 1: 1.2V, 0.5V/div.
Trace 2: LX, 10V/div
Trace 3: EN/PSV, 5V/div
Trace 4: PGD, 5V/div.
Timebase: 1ms/div.
Please refer to Figure 4 on Page 17 for test schematic
© 2007 Semtech Corp.
25
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SC411
POWER MANAGEMENT
Outline Drawing - MLPQ-16
DIMENSIONS
INCHES MILLIMETERS
DIM
MIN NOM MAX MIN NOM MAX
A
D
-
-
-
-
A
.031
A1 .000
.040 0.80
.002 0.00
1.00
0.05
-
B
E
-
(.008)
-
-
(0.20)
A2
b
D
.010 .012 .014 0.25 0.30 0.35
.153 .157 .161 3.90 4.00 4.10
PIN 1
INDICATOR
(LASER MARK)
D1 .079 .085 .089 2.00 2.15 2.25
.153 .157 .161 3.90 4.00 4.10
E1 .079 .085 .089 2.00 2.15 2.25
E
e
.026 BSC
0.65 BSC
L
N
.012 .016 .020 0.30 0.40 0.50
16
16
aaa
bbb
.003
.004
0.08
0.10
A2
A
SEATING
PLANE
aaa
C
A1
C
D1
e/2
LxN
E/2
E1
2
1
N
e
bxN
bbb
C
A B
D/2
NOTES:
1. CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES).
2. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS.
Marking Information
Top Marking
SC411
yyww
xxxxx
xxxxx
yyww = Date Code (Example: 0552)
xxxxx = Semtech Lot Number (Example: E9010)
xxxxx = (Example: 1-100)
© 2007 Semtech Corp.
26
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SC411
POWER MANAGEMENT
Land Pattern - MLPQ-16
K
DIMENSIONS
DIM
INCHES
MILLIMETERS
(.152)
.114
.091
.091
.026
.016
.037
.189
(3.85)
2.90
2.30
2.30
0.65
0.40
0.95
4.80
C
G
H
K
P
X
Y
Z
2x Z
H
2x G
Y
2x (C)
X
P
NOTES:
1.
THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY.
CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR
COMPANY'S MANUFACTURING GUIDELINES ARE MET.
Contact Information
Semtech Corporation
Power Management Products Division
200 Flynn Road, Camarillo, CA 93012
Phone: (805) 498-2111 Fax: (805) 498-3804
© 2007 Semtech Corp.
27
www.semtech.com
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