SC412AMLTRT [SEMTECH]
Synchronous Buck Controller; 同步降压控制器
| 型号： | SC412AMLTRT |
| 厂家： | 
SEMTECH CORPORATION |
| 描述： | Synchronous Buck Controller |
| 文件： | 总22页 (文件大小：639K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SC412A
Synchronous Buck Controller
POWER MANAGEMENT
Description
Features
The SC412A is a versatile, constant on-time synchronous VBAT Range 3V to 25V
buck, pseudo fixed-frequency, PWM controller intended Soft-Shutoff at Output
for notebook computers and other battery operated Current Sense Using Low-Side RDS(ON) or Resistor
portable devices. The SC412A contains all the features
needed to provide cost-effective control of switch-mode Fixed-Frequency 325kHz
power outputs. Constant On-Time for Fast Dynamic Response and
Reduced Output Capacitance
Sensing with Adjustable Cycle-by-Cycle Current Limit
The output voltage is programmable from 0.75 to 5.25 Automatic Smart Power Save†
volts using external resistors. Switching frequency is Internal Soft-Start
internally preset to 325kHz. Additional features cycle- Over-Voltage/Under-Voltage Fault Protection
by-cycle current limit, voltage soft-start, under-voltage Power Good Output
protection, programmable over-current protection, soft 1μA Typical Shutdown Current
shutdown, automatic power save and non-overlapping Tiny 3x3mm, 16 Pin MLP, Lead-free Package
gate drive. The SC412A also provides an enable input Low External Part Count
and a power good output.
Industrial Temperature Range
1% Internal Reference
The constant on-time topology provides fast, dynamic 1A/3A Non-Overlapping Gate Drive with SmartDrive™
response. The excellent transient response means that High Efficiency > 90%
SC412A based solutions require less output capacitance Fully WEEE and RoHS Compliant
than competing fixed-frequency converters. Switching
†
frequency is constant until a step in load or line voltage
occurs, at which time the pulse density and frequency
will increase or decrease to counter the change in
output voltage. After the transient event, the controller
frequency returns to steady state operation. At light loads,
the automatic power save mode reduces the switching
frequency for improved efficiency.
Patent pending
Applications
Notebook and Sub-Notebook Voltage Controllers
Tablet PCs
Embedded Applications
Typical Application Circuit
VCC
VCC
C1
D1
VBAT
RLIM
CIN
Q1
R1
C2
L1
1
2
3
4
12
11
10
9
EN
VOUT
LX
EN
PGOOD
VOUT
FB
BST
VCC
DL
PGOOD
U1
COUT
VCC
SC412A VOUT
Q2
FB
R2
R3
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September 19, 2006
1
SC412A
POWER MANAGEMENT
Absolute Maximum Ratings
Exceeding the specifications below may result in permanent damage to the device or device malfunction. Operation outside of the parameters
specified in the Electrical Characteristics section is not implied. Exposure to Absolute Maximum rated conditions for extended periods of time
may affect device reliability.
Parameter
Symbol
Min
Max
Units
DH, BST to GND (DC)
DH, BST to GND (transient - 100nsec max)
-0.3
-2.0
+30
+33
V
DL to GND (DC)
DL to GND (transient - 100nsec max)
-0.3
-2.0
+6.0
+6.0
V
V
LX to GND (DC)
LX to GND (transient - 100nsec max)
-0.3
-2.0
+25
+28
BST to LX
-0.3
-0.3
-0.3
-0.3
-40
-60
45
+6.0
+0.3
V
RTN to GND
V
VCC to RTN
+6.0
V
V
EN, FB, ILIM, PGOOD, VCC, VOUT to RTN
Operating Junction Temperature Range
Storage Temperature Range
Thermal Resistance, Junction to Ambient(1)
VCC + 0.3
+125
TJ
oC
TSTG
θJA
+150
oC
oC/Watt
Peak IR Reflow Temperature, 10-40 Second
TPKG
+260
oC
ESD Rating (Human Body Model)
2
kV
Note:
(1) Calculated from package in still air, mounted 3” to 4.5”, 4 layer FR4 PCB with thermal vias under the exposed pad per JESD51 standards.
Electrical Characteristics
Test Conditions: VBAT = 15V, VOUT = 1.5V, TA = 25oC, 0.1% resistor dividers; VCC = 5.0V, unless otherwise noted.
25°C
Typ
-40° to 85°C
Parameter
Conditions
Units
Min
Max
Min
Max
Input Supplies
VBAT Input Voltage
VCC Shutdown Current
VCC Operating Current
Controller
3.0
25
V
EN = 0V
5
μA
μA
1
1000
FB > REF
500
FB On-Time Threshold
Regulation
0.7425 0.7575
0.75
V
Line Regulation Error
Load Regulation Error
Typical Application Circuit
Typical Application Circuit
0.04
0.3
%/V
%
© 2006 Semtech Corp.
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SC412A
POWER MANAGEMENT
Electrical Characteristics (continued)
25°C
Typ
-40° to 85°C
Parameter
Conditions
Units
Min
Max
Min
Max
Timing
Continuous Mode Operation
VOUT = 1.1V
On-Time
250
225
275
ns
ns
Minimum On-Time
Minimum Off-Time
100
350
VBAT < VOUT +0.2
VOUT < On-Time Threshold
Maximum Duty Cycle
85
80
%
Soft-Start
Soft-Start Time
IOUT = ILIM/2
1000
500
μs
Analog Inputs/Outputs
VOUT Input Resistance
Current Sense
kΩ
Zero-Crossing
Detector Threshold
LX - GND
0
-7
+7
mV
Power Good
Power Good Threshold
Threshold Delay Time(1)
Leakage
1% HysteresisTypical
-12%
5
-9%
-15%
1
%
μs
μA
Fault Protection
ILIM Source Current
ILIM Comparator Offset
Current Limit (Negative)
Output Under-Voltage Fault
10
0
9
11
μA
mV
mV
%
-10
60
+10
100
-25
LX - GND
80
-30
FB with Respect to REF
-35
Steady-State
Over-Voltage Fault
FB with Respect to REF
20
+17
+23
%
FB Forced 50mV Above
Over-Voltage Fault Threshold
Over-Voltage Fault Delay(1)
5
4
μs
V
VCCA Under-Voltage
(UVLO)
Conditions = Falling Edge
(Hysteresis 100mV)
3.7
4.35
Over-Temperature
Shutdown(1)
160
°C
Logic Inputs/Outputs
Logic Input Hgh Voltage
EN
EN
1.2
V
V
Logic Input Low Voltage
© 2006 Semtech Corp.
0.4
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SC412A
POWER MANAGEMENT
Electrical Characteristics (continued)
25°C
Typ
-40° to 85°C
Parameter
Conditions
Units
Min
Max
Min
Max
Logic Inputs/Outputs (continued)
EN Input Bias Current
EN = VCC or RTN
FB = VCC or RTN
-1
-1
+1
+1
μA
μA
FB Input Bias Current
Power Good Output
Low Voltage
R
PWRGD = 10kΩ to VCC
0.4
V
Gate Drivers
Shoot-Through
Protection Delay(1)
DH or DL Rising
30
ns
DL Pull-Down Resistance
DL Sink Current
DL Low
VDL = 2.5V
DL High
0.8
3.1
2
1.6
4
Ω
A
Ω
A
DL Pull-Up Resistance
DL Source Current
VDL = 2.5V
1.3
DH Pull-Down Resistance
DH Pull-Up Resistance(2)
DH Sink/Source Current
DH Low, BST - LX = 5V
DH High, BST - LX = 5V
2
2
4
4
Ω
Ω
A
V
DH = 2.5V
1.3
Notes:
(1) Guaranteed by design.
(2) Semtech’s SmartDriver™ FET drive first pulls DH high with a pull-up resistance of 10Ω (typical) until LX = 1.5V (typical). At this point,
an additional pull-up device is activated, reducing the resistance to 2Ω (typical). This negates the need for an external gate or boost
resistor.
© 2006 Semtech Corp.
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SC412A
POWER MANAGEMENT
Pin Configuration
Ordering Information
Device
Package(2)
SC412AMLTRT(1)
SC412AEVB
MLPQ-16 3X3
16
15
14
13
Evaluation Board
1
2
3
4
12
11
10
9
LX
BST
VCC
DL
EN
TOP VIEW
Notes:
1) Available in tape and reel packaging only. A reel contains 3000
devices.
2) Available in lead-free packaging only. This product is fully WEEE,
RoHS and J-TD-020B compliant. This component and all homog-
enous sub-components are RoHS compliant.
PGOOD
VOUT
FB
T
5
6
7
8
MLPQ16: 3X3 16 LEAD
Marking Information
412A
yyww
xxxx
Marking for the 3 x 3mm MLPQ 16 Lead Package
nnnn = Part Number (example: 412A)
yyww = Date Code (example: 0652)
xxxx = Semtech Lot No. (example: E901)
© 2006 Semtech Corp.
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SC412A
POWER MANAGEMENT
Pin Descriptions
Pin #
Pin Name
LX
Pin Function
1
2
3
4
Switching (phase) node
BST
Boost capacitor connection for high-side gate drive
5V power input for internal analog circuits and gate drive outputs
Gate drive output for the low-side external MOSFET
VCC
DL
Power ground — the return point for the DL driver output and the reference point
for the ILIM and Zero Cross circuits
5
GND
6
7
8
RTN
NC
Return or analog ground for VOUT sense — connect to GND at the chip
Not connected internally — leave unconnected or connect to GND
Not connected internally — leave unconnected or connect to GND
NC
Feedback input — connect to an external resistor divider from
VOUT to program the output voltage
9
FB
10
VOUT
Output voltage sense point for determining the on-time
Open-drain Power Good indicator — high impedance indicates power is good —
an external pull-up resistor is required.
11
12
13
PGOOD
EN
Enable input — connect EN to RTN to disable the SC412A
Current limit sense point — to program the current limit connect a resistor from ILIM to
LX or to a current sense resistor
ILIM
14
15
16
NC
NC
DH
Not connected internally — leave unconnected or connect to GND
Not connected internally — leave unconnected or connect to GND
Gate drive output for the high-side external FET
Thermal pad for heatsinking purposes — not connected internally — connect to system
ground through preferably one large via or multiple smaller vias
T
PAD
© 2006 Semtech Corp.
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SC412A
POWER MANAGEMENT
Block Diagram
+5V
Enable
Power Good
+5V
EN
VCC
PGOOD
BST
RTN
Reference
Startup
VBAT
Control and Status
DH
LX
VOUT
DRV
FB
TON
Generator
FB
Gate Drive
Control
FB Comparator
DL
VOUT
DRV
VOUT
Zero Cross/Negative
I-limit Detect
ILIM
Valley I-Limit
PAD
GND
Block Diagram
© 2006 Semtech Corp.
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SC412A
POWER MANAGEMENT
Applications Information
SC412A Synchronous Buck Controller
On-Time One-Shot (TON)
The SC412A is a synchronous power supply controller which The internal on-time one-shot comparator has two inputs.
simplifies the task of designing a power supply suitable for One input looks at the output voltage via the VOUT pin,
powering low voltage circuits.
while the other input samples the input voltage via the LX
pin and converts it to a proportional current which charges
an internal on-time capacitor.
Battery and +5V Bias Supplies
The SC412A requires an external +5V bias supply in ad-
dition to the battery. If stand-alone capability is required,
the +5V supply can be generated with an external linear
regulator.
The TON time is the time required for this capacitor to
charge from zero volts to VOUT, thereby making the on-
time directly proportional to output voltage and inversely
proportional to input voltage. This implementation results
in a fairly constant switching frequency without the need of
a clock generator. The internal frequency is optimized for
325kHz. The general equation for the on-time is:
Pseudo-Fixed-Frequency Constant On-Time
PWM Controller
The PWM control method is a constant-on-time, pseudo-
fixed-frequency PWM controller, see Figure 1. The ripple
voltage seen across the output capacitor’s ESR provides
the PWM ramp signal, eliminating the need for a current
sense resistor. The on-time is determined by an internal
one-shot whose period is proportional to output voltage,
and inversely proportional to input voltage. A separate
one-shot sets the minimum off-time (typically 350ns).
TON (nsec) = 2560 • (VOUT/VBAT) + 35
VOUT Voltage Selection
Output voltage is regulated by comparing VOUT as seen
through a resistor divider to the internal 0.75V reference,
see Figure 2. The output voltage is set by the equation:
The typical operating frequency is 325kHz. It is possible
to raise or lower the operating frequency with external
components, refer to the section on Switching Frequency
Variations.
VOUT = 0.75 • (1 + R1/R2)
TON
VBAT
VOUT
To FB pin
VPHASE
R1
CIN
R2
V
OUT/FB Ripple
Q1
Q2
FB Threshold
0.75V
VPHASE
VOUT
L
ESR
+
COUT
Figure 2.
Figure 1.
© 2006 Semtech Corp.
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SC412A
POWER MANAGEMENT
Applications Information (continued)
Enable Input
Current Limit Circuit
The EN is used to disable or enable the SC412A. When
EN is low (grounded), the SC412A is off and in its lowest-
power state. When EN is high the controller is enabled and
switching will begin.
Current limiting can be accomplished in two ways. The RD-
SON of the lower MOSFET can be used as a current sensing
element, or a sense resistor at the lower MOSFET source
can be used if greater accuracy is needed. RDSON sensing
is more efficient and less expensive. In both cases, the RILIM
resistor sets the over-current threshold. The RILIM connects
from the ILIM pin to either the lower MOSFET drain (for RD-
SON sensing) or the high side of the current-sense resistor.
RILIM connects to a 10μA current source from the ILIM pin
which turns on when the low-side MOSFET turns on, after
the on-time DH pulse has completed. If the voltage drop
across the sense resistor or low-side MOSFET exceeds the
voltage across the RILIM resistor, current limit will activate.
The high-side MOSFET will then not turn on until the voltage
drop across the sense element (resistor or MOSFET) falls
below the voltage across the RILIM resistor.
PSAVE Operation
The SC412A provides automatic power save operation at
light loads. The internal Zero-Cross comparator looks for
inductor current (via the voltage across the lower MOSFET)
to fall to zero on 8 consecutive cycles. Once observed, the
controller then enters power save and turns off the low-side
MOSFET on each cycle when the current crosses zero. To
add hysteresis, the on-time is increased by 25% in power-
save. The efficiency improvement at light loads more than
offsets the disadvantage of slightly higher output ripple. If
the inductor current does not cross zero on any switching
cycle, the controller immediately exits power save. Since
the controller counts zero crossings, the converter can
sink current as long as the current does not cross zero on
eight consecutive cycles. This allows the output voltage to
recover quickly in response to negative load steps.
This current sensing scheme actually regulates the inductor
valley current, see Figure 3. This means that if the current
limit is set to 10A, the peak current through the inductor
would be 10A plus the peak ripple current, and the average
current through the inductor would be 10A plus 1/2 the
peak-to-peak ripple current.
Smart Power Save Protection
In some applications, active loads can leak current from a
higher voltage and thereby cause VOUT to slowly rise and
reach the OVP threshold, leading to a hard shutdown. The
SC412A uses Smart Power Save to prevent this. When the
feedback signal exceeds 8% above nominal (810mV), the IC
exits power save operation (if already active) and DL drives
high to turn on the low-side MOSFET, which draws current
from VOUT via the inductor. When FB drops back to the
0.75V trip point, a normal TON switching cycle begins. This
method cycles energy from VOUT back to VBAT and prevents
a hard OVP shutdown, and also minimizes operating power
by avoiding continuous conduction-mode operation.
IPEAK
ILOAD
I LIMIT
TIME
Valley Current Limit
Figure 3.
© 2006 Semtech Corp.
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SC412A
POWER MANAGEMENT
Applications Information (continued)
The RDSON sensing circuit is shown in Figure 4 with RILIM
R1 and RDSON of Q2.
=
The following over-current equation can be used for both
RDSON or resistive sensing. For RDSON sensing, the MOSFET
RDSON rating is used for the value of RSENSE
.
VBAT
+5V
RILIM
ILOC(Valley) = 10μA • ———
RSENSE
D1
Q1
+
C1
C2
BST
DH
L
Power Good Output
LX
ILIM
VDD
DL
VOUT
The power good (PGD) output is an open-drain output
which requires a pull-up resistor. When the output voltage
is 12% below its nominal voltage (660mV), PGD is pulled
low. It is held low until the output voltage returns above
approximately -11% of nominal. PGD is held low during
start-up and will not be allowed to transition high until
soft-start is completed (when FB reaches 0.75V). There
is a 5μs delay built into the PGD circuit to prevent false
transitions.
R1
GND
D2
+
Q2
C3
SC412A
Figure 4.
The resistor sensing circuit is shown in Figure 5 with RILIM
= R1 and RSENSE = R4.
PGD also transitions low if the FB pin exceeds +20% of
nominal, which is also the over-voltage shutdown point. If
EN is low with VCC supplied, PGD is also pulled low.
Resistive sensing operates similar to MOSFET sensing,
except that a resistor is used to improve accuracy. The
resistor connects between the MOSFET source and GND,
and the RILIM connects from the ILIM pin to the sense
resistor, as in Figure 5.
Output Over-Voltage Protection
In steady state operation, when FB exceeds 20% of nomi-
nal, DL latches high and the low-side MOSFET is turned on.
DL stays high and the SMPS stays off until the EN input is
toggled or VCC is recycled. There is a 5μs delay built into
the OVP detector to prevent false transitions. PGD is also
low after an OVP.
VBAT
+5V
D1
C2
+
Q1
Q2
C1
Output Under-Voltage Protection
When FB falls 30% below its trip point for eight consecutive
clock cycles, the output is shut off; the DL/DH drives are
pulled low to tri-state the MOSFETS, and the SMPS stays
off until the EN input is toggled or VCC is recycled.
BST
DH
LX
ILIM
VDD
DL
L1
Vout
+
GND
C3
D2
SC412A
POR and UVLO
R1
Under-voltage lockout circuitry (UVLO) inhibits switching
and tri-states the DH/DL drivers until VCC rises above 4.4V.
An internal power-on reset (POR) occurs when VCC exceeds
4.4V, which resets the fault latch and soft-start counter, to
prepare the PWM for switching. At this time the SC412A
will come out of UVLO and begin the soft-start cycle.
R4
Figure 5.
© 2006 Semtech Corp.
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SC412A
POWER MANAGEMENT
Applications Information (continued)
Design Procedure
Soft-Start
Prior to designing a switch mode supply, the input voltage,
load current, switching frequency and inductor ripple cur-
rent must be specified.
The soft-start is accomplished by ramping the FB com-
parator’s internal reference from zero to 0.75V in 30mV
increments. Each 30mV step typically lasts for eight clock
cycles.
For notebook systems the maximum input voltage (VINMAX
)
During the soft-start period, the Zero Cross Detector is
active to monitor the voltage across the lower MOSFET
while DL is high. If the inductor current reaches zero, the
FB comparator’s internal ramp reference is immediately
overridden to match the voltage at the FB pin. This soon
causes the FB comparator to trip which forces DL to turn
off and a DH on-time will begin. This prevents the inductor
current from going too negative which would cause droop
in the VOUT start-up waveform. The next 30mV step on the
internal reference ramp occurs from the new point at the
FB pin. Since any of the internal 30mV steps can be over-
ridden by the FB waveform, the start-up time is therefore
dependent upon operating conditions. This override feature
will stop when the FB pin reaches approximately 660mV.
is determined by the highest AC adaptor voltage, and the
minimum input voltage (VINMIN) is determined by the lowest
battery voltage after accounting for voltage drops due to
connectors, fuses and battery selector switches.
In general, four parameters are needed to define the
design:
1) Nominal output voltage (VOUT)
2) Static or DC output tolerance
3) Transient response
4) Maximum load current (IOUT)
There are two values of load current to consider: continu-
ous load current and peak load current. Continuous load
current is concerned with thermal stresses which drive
the selection of input capacitors, MOSFETs and commuta-
tion diodes. Peak load current determines instantaneous
component stresses and filtering requirements such as
inductor saturation, output capacitors and design of the
current limit circuit.
At start-up, during the first 32 switching cycles, the over-
current threshold is reduced by 50%, to reduce overshoot
caused by the first set of switching pulses.
MOSFET Gate Drivers
The DH and DL drivers are optimized for driving moderate
high-side and larger low-side power MOSFETs. An adaptive
dead-time circuit monitors the DL output and prevents the
high-side MOSFET from turning on until DL is fully off, and
conversely, monitors the DH output and prevents the low-
side MOSFET from turning on until DH is fully off. Be sure
there is low resistance and low inductance between the DH
and DL outputs to the gate of each MOSFET.
Design example:
VBAT = 10V min, 20V max
VOUT = 1.15V +/- 4%
Load = 20A maximum
Inductor Selection
The SC412A utilizes SmartDriveTM to achieve fast switching
with reduced noise. At the start of the DH on-time when
LX is typically below GND, the DH output drives the high-
side MOSFET through a pull-up resistance of 10 ohms,
which results in a soft reverse-recovery of the low-side
diode. The high-side MOSFET conducts and causes LX to
rise; when LX reaches 1.5volts, the DH drive resistance is
reduced to 2 ohms to provide fast switching and reduce
switching loss.
Low inductor values result in smaller size, but create high-
er ripple current and are less efficient because of the high
AC current flowing in the inductor. Higher inductor values
will reduce the ripple current and are more efficient, but
are larger and more costly. The inductor selection is gen-
erally based on the ripple current which is typically set
between 20% to 50% of the maximum load current. Cost,
size, output ripple and efficiency all play a part in the se-
lection process.
© 2006 Semtech Corp.
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SC412A
POWER MANAGEMENT
Applications Information (continued)
The switching frequency is optimized for 325kHz. The
equation for on-time is:
Capacitor Selection
The output capacitors are chosen based on required ESR
and capacitance. The ESR requirement is driven by the
output ripple requirement and the DC tolerance. The
output voltage has a DC value that is equal to the valley
of the output ripple, plus 1/2 of the peak-to-peak ripple.
Change in the ripple voltage will lead to a change in DC
voltage at the output.
TON (nsec) = 2560 • (VOUT/VBAT) + 35
During the DH on-time, voltage across the inductor is (VBAT
- VOUT). To determine the inductance, the ripple current
must be defined. Smaller ripple current will give smaller
output ripple and but will lead to larger inductors. The ripple
current will also set the boundary for PSAVE operation: the
switching will typically enter PSAVE operation when the
load current decreases to 1/2 of the ripple current; (i.e.
if ripple current is 4A then PSAVE operation will typically
start for loads less than 2A. If ripple current is set at 40%
of maximum load current, then PSAVE will commence for
loads less than 20% of maximum current).
The design goal is +/-4% output regulation. The internal
0.75V reference tolerance is 1%, assuming 1% tolerance
for the FB resistor divider, this allows 2% tolerance due to
VOUT ripple. Since this 2% error comes from 1/2 of the
ripple voltage, the allowable ripple is 4%, or 46mV for a
1.15V output.
The maximum ripple current of 4.05A creates a ripple
voltage across the ESR. The maximum ESR value allowed
would be 44mV:
The equation for determining inductance is:
L = (VBAT - VOUT) • TON / IRIPPLE
ESRMAX = VRIPPLE/IRIPPLEMAX = 46mV / 4.91A
Use the maximum value for VBAT, and for TON use the value
associated with maximum VBAT.
ESRMAX = 9.4 mΩ
TON = 182 nsec at 20VBAT, 1.1VOUT
The output capacitance is typically chosen based on tran-
sient requirements. A worst-case load release, from maxi-
mum load to no load at the exact moment when inductor
current is at the peak, defines the required capacitance.
If the load release is instantaneous (load changes from
maximum to zero in a very small time), the output capaci-
tor must absorb all the inductor’s stored energy. This will
cause a peak voltage on the capacitor according to the
equation:
L = (20 - 1.15) • 182 nsec / 5A = 0.69μH
We will select a slightly larger value of 0.7μH, which will
decrease the maximum IRIPPLE to 4.91A.
Note: the inductor must be rated for the maximum DC load cur-
rent plus 1/2 of the ripple current.
COUTMIN = L • (IOUT + 1/2 • IRIPPLEMAX)2 / (VPEAK2 - VOUT2)
The ripple current under minimum VBAT conditions is also
checked.
TONVBATMIN = 2560 • (1.15/10) + 35 = 329 nsec
IRIPPLE = (VBAT - VOUT) • TON / L
Assuming a peak voltage VPEAK of 1.230 (80mV rise upon
load release), and a 10 amp load release, the required
capacitance is:
COUTMIN = 0.7μH•(10 + 1/2 • 4.91)2 / (1.232 - 1.152)
COUTMIN = 570μF
IRIPPLE_VBATMIN = (10 - 1.15)• 329 nsec / 0.7μH = 4.16A
© 2006 Semtech Corp.
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12
SC412A
POWER MANAGEMENT
Layout Guidelines
seen at the FB input or because the ESR is too low, caus-
ing insufficient voltage ramp in the FB signal. This causes
the error amplifier to trigger prematurely after the 350ns
minimum off-time has expired. double-pulsing will result
in higher ripple voltage at the output, but in most cases
is harmless. In some cases, however, double-pulsing can
indicate the presence of loop instability, which is caused
by insufficient ESR.
These requirements (650μF, 10.8mΩ) can be met using
two capacitors, 330μF 20mΩ.
If the load release is relatively slow, the output capacitance
can be reduced. At heavy loads during normal switching,
when the FB pin is above the 0.75V reference, the DL output
is high and the low-side mosfet is on. During this time, the
voltage across the inductor is approximately - VOUT. This
causes a downslope or falling di/dt in the inductor. If the
load di/dt is not much faster than the di/dt in the inductor,
then the inductor current can track change in load current,
and there will be relatively less overshoot from a load
release. The following can used to calculate the needed
capacitance for a given dILOAD/dt:
One simple way to solve this problem is to add some trace
resistance in the high current output path. A side effect of
doing this is output voltage droop with load. Another way
to eliminate doubling-pulsing is to add a small (e.g. 10pF)
capacitor across the upper feedback resistor divider net-
work, (this capacitor is shown in Figure 6). This capacitance
should be left out until confirmation that double-pulsing
exists. Adding this capacitance will add a zero in the trans-
fer function and should eliminate the problem. It is best to
leave a spot on the PCB in case it is needed.
Peak inductor current,
ILPEAK = ILOADMAX + 1/2 • IRIPPLEMAX
ILPEAK = 10 + 1/2 • 4.05 = 12.02A
Rate of change of Load current = dILOAD/dt
IMAX = maximum load release = 10A
C
VOUT
To FB pin
R1
COUT = ILPEAK• (L •ILPEAK / VOUT - IMAX/dILOAD/dt)
2 • (VPEAK - VOUT)
R2
Example: Load dI/dt = 2.5A/usec
This would cause the output current to move from 10A to
zero in 4μsec.
Figure 6.
COUT = 12.45•(0.7μH•12.45/1.15 - 10/(2.5/1μsec)
2 •(1.23 - 1.15)
Loop instability can cause oscillations at the output as a
response to line or load transients. These oscillations can
trip the over-voltage protection latch or cause the output
voltage to fall below the tolerance limit.
COUT = 278 μF
Stability Considerations
The best way for checking stability is to apply a zero-to-
full load transient and observe the output voltage ripple
envelope for overshoot and ringing. Over one cycle of ring-
ing after the initial step is a sign that the ESR should be
increased.
Unstable operation shows up in two related but distinctly
different ways: double-pulsing and fast-feedback loop
instability. double-pulsing occurs due to switching noise
© 2006 Semtech Corp.
www.semtech.com
13
SC412A
POWER MANAGEMENT
Layout Guidelines (continued)
SC412A ESR Requirements
The on-time pulse in the SC412A is calculated to give a
The constant on-time control used in the SC412A regulates pseudo-fixed frequency of 325kHz. Nevertheless, some
the valley of the output ripple voltage. This signal consists of frequency variation with line and load is expected. This
a term generated by the output ESR of the capacitor and a variation changes the output ripple voltage. Because con-
term based on the increase in voltage across the capacitor stant on-time converters regulate to the valley of the output
due to charging and discharging during the switching cycle. ripple, ½ of the output ripple appears as a DC regulation
The minimum ESR is set to generate the required ripple error. For example, If the output ripple is 50mV with VIN =
voltage for regulation. For most applications the minimum 6 volts, then the measured DC output will be 25mV above
ESR ripple voltage is dominated by PCB layout and the the comparator trip point. If the ripple increases to 80mV
properties of SP or POSCAP type output capacitors. For with VIN = 25 volts, then the measured DC output will be
applications using ceramic output capacitors, the absolute 40mV above the comparator trip. The best way to minimize
minimum ESR must be considered. If the ESR is low enough this effect is to minimize the output ripple.
the ripple voltage is dominated by the charging of the output
capacitor. This ripple voltage lags the on-time due to the To compensate for valley regulation it is often desirable
LC poles and can cause double pulsing if the phase delay to use passive droop. Take the feedback directly from the
exceeds the off-time of the converter. To prevent double output side of the inductor, placing a small amount of trace
pulsing, the ripple voltage present at the FB pin should be resistance between the inductor and output capacitor. This
10-15mV minimum over the on-time interval.
trace resistance should be optimized so that at full load the
output droops to near the lower regulation limit. Passive
droop minimizes the required output capacitance because
the voltage excursions due to load steps are reduced.
Dropout Performance
The output voltage adjust range for continuous-conduction
operation is limited by the fixed 350nS (typical) Minimum
Off-time One-shot. When working with low input voltages,
the duty-factor limit must be calculated using worst-case
values for on and off times.
The use of 1% feedback resistors contributes up to 1% er-
ror. If tighter DC accuracy is required use 0.1% resistors.
The output inductor value may change with current. This
will change the output ripple and thus the DC output volt-
age. The output ESR also affects the ripple and thus the
DC output voltage.
The IC duty-factor limitation is given by:
TON(MIN)
DUTY = ————————
TON(MIN) + TOFF(MAX)
Switching Frequency Variations
The switching frequency will vary somewhat due to line and
load conditions. The line variations are a result of a fixed
offset in the on-time one-shot, as well as unavoidable delays
in the external MOSFET switching. As VBAT increases, these
factors make the actual DH on-time slightly longer than the
idealized on-time. The net effect is that frequency tends
to falls slightly as with increasing input voltage.
Be sure to include inductor resistance and MOSFET on-
state voltage drops when performing worst-case dropout
duty-factor calculations.
SC412A System DC Accuracy (VOUT Controller)
Three factors affect VOUT accuracy: the trip point of the
FB error comparator, the switching frequency variation
with line and load, and the external resistor tolerance. The
error comparator offset is trimmed so that it trips when the
feedback pin is 0.75V, 1%.
The load variations are due to losses in the power train
due to IR drop and switching losses. For a conventional
PWM constant-frequency topology, as load increases the
duty cycle also increases slightly to compensate for IR and
switching losses in the MOSFETs and inductor. A constant
on-time topology must also overcome the same losses
© 2006 Semtech Corp.
www.semtech.com
14
SC412A
POWER MANAGEMENT
Applications Information (continued)
by increasing the duty cycle (more time is spent drawing It is also possible to lower the frequency using a resistive
divider to the 5V bias supply, see Figure 3. This raises the
voltage at the VOUT pin which will increase the on-time.
Note that this results in a small leakage path from the 5V
supply to the output voltage. The resistor values should be
fairly large (>50kOhm) large to prevent the output voltage
from drifting up during shutdown conditions. Note that
the feedback resistors act as a dummy load to limit how
far the output can rise.
energy from VBAT as losses increase). Since the on-time
is constant for a given VOUT/VBAT combination, the way
to increase duty cycle is to gradually shorten the off-time.
The net effect is that switching frequency increases slightly
with increasing load.
The typical operating frequency is 325kHz. It is possible to
raise the frequency by placing a resistor divider between
the output and the VOUT pin, see Figure 7. This reduces
the voltage at the VOUT pin which is used to generate the
on-time according to the previous equation. Note that
this places a small minimum load on the output. The new
frequency is approximated by the following equation:
The new operating frequency is approximated by the
equation:
FREQ (kHz) = 325 ∙ ((R1 + R2) / (R1 + R2 ∙ VCC/VOUT))
FREQ (kHz) = 325 ∙ (1 + R1/R2)
VCC
Power Output
VOUT
VLX
Power Output
VLX
L
VOUT
L
R1
R2
R1
ESR
ESR
pin 10
(VOUT)
pin 10
(VOUT)
+
+
COUT
COUT
1nF
R2
1nF
Figure 8.
Figure 7.
© 2006 Semtech Corp.
www.semtech.com
15
SC412A
POWER MANAGEMENT
Layout Guidelines
For an accurate ILIM current sense connection, connect
the ILIM trace to the current sense element (MOSFET or
resistor) directly at the pin of the element, and route that
trace over to the ILIM resistor on another layer if needed.
The layout can be generally considered in two parts; the
control section referenced to RTN, and the switcher power
section referenced to GND.
Layout Guidelines
One or more ground planes are recommended to minimize
the effect of switching noise and copper losses and to
maximize heat removal. The analog ground reference, RTN,
should connect directly to the thermal pad, which in turn
connects to the ground plane through preferably one large
via. There should be a RTN plane or copper are near the
chip; all components that are referenced to RTN should
connect to this plane directly, not through the ground plane,
and located on the chip side of the PCB if possible.
Looking at the control section first, locate all components
referenced to RTN on the schematic and place these
components near the chip and on the same side if possible.
Connect RTN using a wide trace. Very little current flows
in the RTN path and therefore large areas of copper are
not needed. Connect the RTN pin directly to the thermal
pad under the device as the only connection between RTN
and GND.
GND should be a separate plane which is not used for
routing analog traces. The VCC input provides power to
the internal analog circuits and the upper and lower gate
drivers.
The VCC supply decoupling capacitor should be tied be-
tween VCC and GND with short traces. All power GND
connections should connect directly to this plane with
special attention given to avoiding indirect connections
between RTN and GND which will create ground loops. As
mentioned above, the RTN plane must be connected to the
GND plane at the chip near the RTN/GND pins.
The chip supply decoupling capacitor (VCC/GND) should
be located near to the pins. Since the DL pin is directly
between VCC and GND, and the DL trace must be a wide,
direct trace, the VCC decoupling capacitor is best placed
on the opposite side of the PCB, routed with traces as short
as possible and using at least two vias when connecting
through the PCB.
The switcher power section should connect directly to the
ground plane(s) using multiple vias as required for current
handling (including the chip power ground connections).
Power components should be placed to minimize loops
and reduce losses. Make all the power connections on
one side of the PCB using wide copper filled areas if
possible. Do not use “minimum” land patterns for power
components. Minimize trace lengths and maximize trace
widths between the gate drivers and the gates of the
MOSFETs to reduce parasitic impedances (and MOSFET
switching losses); the low-side MOSFET is most critical.
Maintain a length to width ratio of <20:1 for gate drive
signals. Use multiple vias as required by current handling
requirement (and to reduce parasitic) if routed on more
than one layer.
There are two sensitive, feedback-related pins at the chip:
VOUT and FB. Proper routing is needed to keep noise
away from these signals. All components connected to
FB should be located directly at the chip, and the copper
area of the FB node minimized. The VOUT trace that
feeds into the VOUT pin, which also feeds the FB resistor
divider, must be kept far away from noise sources such
as switching nodes, inductors and gate drives. Route the
VOUT trace in a quiet layer if possible, from the output
capacitor back to the chip.
For the switcher power section, there are a few key
guidelines to follow:
© 2006 Semtech Corp.
www.semtech.com
16
SC412A
POWER MANAGEMENT
Layout Guidelines (continued)
1) There should be a very small input loop between 2) Route DL, DH and LX (low side FET gate drive, high side
the input capacitors, MOSFETs, inductor, and output
capacitors. Locate the input decoupling capacitors
directly at the MOSFETs.
FET gate drive and phase node) to the chip using wide
traces, with multiple vias if using more than one layer.
These connections are to be as short as possible for
loop minimization, with a length to width ratio less than
20:1 to minimize impedance. DL is the most critical
gate drive, with power GND as its return path. LX is the
noisiest node in the circuit, switching between VBAT and
ground at high frequencies, thus should be kept as short
as practical. DH has LX as its return path. DL, DH, LX,
and BST are high-noise signals and should be kept well
away from sensitive signals, particularly FB and VOUT.
2) The phase node should be a large copper pour, but still
compact since this is the noisiest node.
3) The power GND connection between the input capacitors,
low-side MOSFET, and output capacitors should be as
small as is practical, with wide traces or planes.
4) The impedance of the power GND connection between
the low-side MOSFET and the GND pin should be
minimized. This connection must carry the DL drive
current, which has high peaks at both rising and
falling edges. Use multiple layers and multiple vias to
minimize impedance, and keep the distance as short
as practical.
3) BST is also a noisy node and should be kept as short as
possible. The high-side DH driver is relies on the boost
capacitor to provide the DH drive current, so the boost
capacitor must be placed near the IC and connect to the
BST and LX pins using short, wide traces to minimize
impedance.
4) Connect the GND pin on the chip to the VCC decoupling
capacitor and then drop vias directly to the ground
plane.
Finally, connecting the control and switcher power sections
should be accomplished as follows:
1) Route the VOUT feedback trace in a “quiet” layer, away
from noise sources.
Locate the current limit resistor RLIM at the chip with a
kelvin connection to the drain of the lower MOSFET at the
phase node, and minimize the copper area of the ILIM
trace.
© 2006 Semtech Corp.
www.semtech.com
17
SC412A
POWER MANAGEMENT
Typical Characteristics
TON vs. VBAT - VOUT > 2.5V
TON vs. VBAT - VOUT < 1.8V
2600
2400
2200
2000
1800
1600
1400
1200
1000
800
1000
900
800
700
600
500
400
300
200
100
1.8V
1.1V
5V
3.3V
1.5V
600
2.5V
400
0.75V
200
5
10
15
20
5
10
15
20
VBAT (V)
VBAT (V)
Frequency vs. VBAT
Efficiency vs. Load - 1.15V Output
400
390
380
370
360
350
340
330
320
310
300
95%
10V
1.5V
1.8V
90%
85%
1.25V
15V
19V
1.1V
80%
75%
1.0V
0.9V
0.75V
5
7
9
11
13
15
17
19
21
23
0
2
4
6
8
10
12
14
16
18
20
VBAT (V)
Load (A)
Load Regulation
Line Regulation
1.13
1.12
1.11
1.10
1.09
1.08
1.07
1.13
1.12
1.11
1.10
1.09
1.08
1.07
3A
No Load
19V
15V
10V
10A
15A
10
12
14
16
18
0
2
4
6
8
10
12
14
16
18
20
VBAT (V)
Load (A)
Note: See Reference schematic on Page 20.
© 2006 Semtech Corp.
www.semtech.com
18
SC412A
POWER MANAGEMENT
Typical Characteristics (continued)
Startup 1.15V 19VBAT No load
Startup 1.15V 19VBAT 20A load
Load Transient Response 0A to 20A
Load Transient Response 20A to 0A
Note: See Reference schematic on Page 20
© 2006 Semtech Corp.
www.semtech.com
19
SC412A
POWER MANAGEMENT
Reference Design
VBAT
VCC
EN
VCC
C1
10UF
C2
10UF
C3
10UF
D1
BAT54A
D
4
R3
10K
Q1
RJK0305DP
R4
10K
PGD
VOUT
VOUT
C4
100NF
L1
0.7uH
1
12
11
10
9
LX
BST
VCC
DL
EN
PGD
VOUT
FB
VCC
U1
2
3
R1
10K
C10
NO_POP
SC412A
D
C5*
C6*
4
4
+
+
C7
1UF
D2
MBRS140L
17
Q2
PAD
R2
RJK0302DP
18.7K
C8
1UF
C9
10NF
*330uF/6mohm
Reference Design 1.15V 20A
Bill of Materials
Component
C1, C2, C3
C5, C5
L1
Value
Manufacturer
Part Number
Web
10uF, 25V
Murata
GRM32DR71E106KA12L www.murata.com
330uF/6mohm/2V Panasonic
EEFSX0D331XR
C-PI-1350-0R7S
RJK0305DBP
RJK0302
www.panasonic.com
0.7uH, 24A
10mohm/30V
3.5mohm/30V
200mA/30V
1A/40V
NEC Tokin
Renesas
Renesas
OnSemi
OnSemi
http://www.nec-tokin.com
www.renesas.com
www.renesas.com
www.onsemi.com
Q1
Q2
D1
BAT54C
D2
MBSR140LT3
www.onsemi.com
© 2006 Semtech Corp.
www.semtech.com
20
SC412A
POWER MANAGEMENT
Outline Drawing - MLPQ-16 3x3
DIMENSIONS
INCHES MILLIMETERS
A
D
B
E
DIM
A
MIN NOM MAX MIN NOM MAX
-
-
-
-
.031
A1 .000
.040 0.80
.002 0.00
1.00
0.05
-
-
-
-
(.008)
(0.20)
A2
b
D
PIN 1
INDICATOR
.007 .009 .012 0.18 0.23 0.30
.114 .118 .122 2.90 3.00 3.10
(LASER MARK)
D1 .061 .067 .071 1.55 1.70 1.80
.114 .118 .122 2.90 3.00 3.10
E1 .061 .067 .071 1.55 1.70 1.80
E
e
.020 BSC
0.50 BSC
L
N
aaa
.012 .016 .020 0.30 0.40 0.50
A2
C
16
16
.003
.004
0.08
0.10
A
bbb
SEATING
PLANE
aaa C
A1
D1
e/2
LxN
E/2
E1
2
1
N
e
bxN
D/2
bbb
C A B
NOTES:
1. CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES).
2.
3.
COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS.
DAP IS 1.90 x 1.90mm.
© 2006 Semtech Corp.
www.semtech.com
21
SC412A
POWER MANAGEMENT
Land Pattern - MLPQ-16 3x3
H
R
DIMENSIONS
INCHES MILLIMETERS
DIM
(.114)
.083
.067
.067
.020
.006
.012
.031
.146
(2.90)
2.10
1.70
1.70
0.50
0.15
0.30
0.80
3.70
C
G
H
K
P
R
X
Y
Z
Z
(C)
K
G
Y
X
P
NOTES:
1.
THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY.
CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR
COMPANY'S MANUFACTURING GUIDELINES ARE MET.
2. THERMAL VIAS IN THE LAND PATTERN OF THE EXPOSED PAD
SHALL BE CONNECTED TO A SYSTEM GROUND PLANE.
FAILURE TO DO SO MAY COMPROMISE THE THERMAL AND/OR
FUNCTIONAL PERFORMANCE OF THE DEVICE.
Contact Information
Semtech Corporation
Power Management Products Division
200 Flynn Road, Camarillo, CA 93012
Phone: (805) 498-2111 Fax: (805) 498-3804
www.semtech.com
© 2006 Semtech Corp.
www.semtech.com
22
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