SC4607IMSTRT [SEMTECH]
Very Low Input, MHz Operation, High Efficiency Synchronous Buck; 极低的输入，兆赫操作，高效率同步降压
| 型号： | SC4607IMSTRT |
| 厂家： | 
SEMTECH CORPORATION |
| 描述： | Very Low Input, MHz Operation, High Efficiency Synchronous Buck |
| 文件： | 总17页 (文件大小：319K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SC4607
Very Low Input, MHz Operation,
High Efficiency Synchronous Buck
POWER MANAGEMENT
Description
Features
The SC4607 is a voltage mode step down (buck) regula-
tor controller that provides accurate high efficiency power
conversion from an input supply range of 2.25V to 5.5V.
The SC4607 is capable of producing an output voltage
as low as 0.5V and has a maximum duty cycle of 97%. A
high level of integration reduces external component
count, and makes it suitable for low voltage applications
where cost, size, and efficiency are critical.
Asynchronous start up
BiCMOS voltage mode PWM controller
Operation of frequency to 1MHz
2.25V to 5.5V input voltage range
Output voltages as low as 0.5V
+/-1% reference accuracy
Sleep mode (Icc = 10µA typ)
Adjustable lossless short circuit current limiting
Combination pulse by pulse & hiccup mode
current limit
The SC4607 drives external, N-channel MOSFETs with a
peak gate current of 1A. The SC4607 prevents shoot
through currents by offering nonoverlap protection for
the gate drive signals of the external MOSFETs. The
SC4607 features lossless current sensing of the voltage
drop across the drain to source resistance of the high
side MOSFET during its conduction period.
High efficiency synchronous switching
Up to 97% duty cycle
1A peak current driver
10-pin MSOP package
Applications
Distributed power architecture
The quiescent supply current in sleep mode is typically
lower than 10µA. A 1.2ms soft start is internally provided Servers/workstations
to prevent output voltage overshoot during start-up.
Local microprocessor core power supplies
DSP and I/O power supplies
The SC4607 is an ideal choice for converting 2.5V, 3.3V,
5V or other low input supply voltages. It’s available in 10
pin MSOP package
Battery-powered applications
Telecommunications equipment
Data processing applications
Typical Application Circuit
Vin = 2.25V - 5.5V
C10
C11
C12
D2
1u
22u
22u
C71
220u
M1
M2
R13
1
C14
0.1u
R6
0
R3
U1
1
2
3
4
5
10
9
BST
DRVH
PHASE
DRVL
GND
L1
C3
4.7u
Vout = 1.5V (as low as 0.5V * ) / 12A
VCC
ISET
COMP
1.8u
8
7
C6
C5
C4
C9
4.7n
C20
560pF
2.2n
6
22u
C2
330u
C1
22u
R7
FS/SYNC VSENSE
R5
0
10k
180p
R8
SC4607
200
R1
14.3k
R9
4.99k
*External components can be modified to provide a Vout as low as 0.5V
Revision: June 1, 2005
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SC4607
POWER MANAGEMENT
Absolute Maximum Ratings
Exceeding the specifications below may result in permanent damage to the device, or device malfunction. Operation outside of the parameters specified
in the Electrical Characteristics section is not implied.
Parameter
Symbol
Maximum
Units
Supply Voltage (VCC)
7
V
A
Output Drivers (DRVH, DRVL) Currents
+/-0.25
Continuous
Peak
+/-1.00
A
Inputs (VSENSE, COMP, FS/SYNC, ISET)
BST
-0.3 to 7
13
V
V
PHASE
-0.3 to 7.5
-2 to 7.5
-40 to +85
-65 to +150
-55 to +150
+300
V
PHASE Pulse tpulse < 50ns
Operating Ambient Temperature Range
Storage Temperature Range
Junction Temperature
V
TA
TSTG
TJ
°C
°C
°C
°C
kV
Lead Temperature (Soldering) 10 Sec.
ESD Rating (Human Body Model)
TLEAD
ESD
4
All voltages with respect to GND. Currents are positive into, negative out of the specified terminal.
Electrical Characteristics
Unless otherwise specified, VCC = 3.3V, CT = 270pF, TA = -40°C to 85°C, TA=TJ
Parameter
Test Conditions
Min
Typ
Max
Unit
Overall
Supply Voltage
5.5
15
V
µA
mA
V
Supply Current, Sleep
Supply Current, Operating
VCC Turn-on Threshold
FS/SYNC = 0V
VCC = 5.5V
10
2
3.5
2.2
2.25
TA = 25°C
2.05
TA = -40°C to 85°C
VCC Turn-off Hysteresis
100
mV
V
Error Amplifier
VSENSE Input Voltage
(Internal Reference)
TA = 25°C
0.495
0.5
0.5
0.505
VCC = 2.25V - 5.5V, TA = 25°C
TA = -40°C to 85°C
0.4925
0.4915
0.5075
0.5085
VSENSE Bias Current
Open Loop Gain (1)
Unity Gain Bandwidth (1)
200
90
8
nA
dB
VCOMP = 0.5 to 2.5V
80
MHz
Slew Rate (1)
2.4
V/µs
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SC4607
POWER MANAGEMENT
Electrical Characteristics (Cont.)
Unless otherwise specified, VCC = 3.3V, CT = 270pF, TA = -40°C to 85°C, TA=TJ
Parameter
Test Conditions
Min
Typ
Max
Unit
Error Amplifier (Cont.)
VOUT High
I
COMP = -5.5mA
VCC - 0.5 VCC - 0.3
0.3
V
VOUT Low
I
COMP = 5.5mA
0.45
625
Oscillator
Initial Accuracy
TA = 25°C
525
50
575
0.5
kHz
%/V
%/°C
kHz
Hz
Voltage Stability
TA = 25°C, VCC = 2.25V to 5.5V
TA = -40°C to 85°C
Temperature Coefficient
Minimum Operation Frequency (1)
Maximum Operation Frequency (1)
Ramp Peak to Valley
Ramp Peak Voltage
Ramp Valley Voltage
Sleep, Soft Start, Current Limit
Sleep Threshold
0.02
1M
1
V
1.3
0.3
V
V
Measured at FS
VSYNC = 0V
75
mV
µA
Sleep Input Bias Current
Soft Start Time (1)
-1
1.2
FSW = 575 KHz
TJ = 25°C
ms
ISET Bias Current
-45
-50
0.28
130
-55
µA
Temperature Coefficient of ISET
Current Limit Blank Time (1)
Gate Drive
%/°C
ns
Duty Cycle
97
%
Ω
Pull-Up Resistance (DRVH)(2)
VBST - VPHASE = 3.3V, ISOURCE = -100mA
VBST - VPHASE = 3.3V, ISINK = 100mA
VCC = 3.3V, ISOURCE = -100mA
VCC = 3.3V, ISINK = 100mA
2.7
2.4
2.2
1.5
35
(2)
Pull-Down Resistance (DRVH)
Ω
(1)
Pull-Up Resistance (DRVL)
Ω
(2)
Pull-Down Resistance (DRVL)
Ω
Output Rise Time
VCC = 3.3V, COUT = 4.7nF
ns
ns
ns
Output Fall Time
VCC = 3.3V, COUT = 4.7nF
27
Minimum Non-Overlap (1)
40
Notes:
(1). Guaranteed by design.
(2). Guaranteed by characterization.
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SC4607
POWER MANAGEMENT
Pin Configuration
Ordering Information
Top View
Part Number
SC4607IMSTR
SC4607IMSTRT(2)
Device
MSOP-10
Notes:
(1) Only available in tape and reel packaging. A reel
contains 2500 devices.
(2) Lead free product. This product is fully WEEE and
RoHS compliant.
(10 Pin MSOP)
Pin Descriptions
Pin #
Pin Name
Pin Function
1
BST
This pin enables the converter to drive an N-Channel high side MOSFET. BST connects to
the external charge pump circuit. The charge pump circuit boosts the BST pin voltage to a
sufficient gate-to-source voltage level for driving the gate of the high side MOSFET.
2
3
VCC
ISET
Positive supply rail for the IC. For improved noise immunity, bypass this pin to GND with a
0.1 to 4.7µF low ESL/ESR ceramic capacitor.
The ISET pin is used to limit current in the high side MOSFET. The SC4607 uses the
voltage across the Vin and ISET pins in order to set the current limit. The current limit
threshold is set by the value of an external resistor (R3 in the Typical Application Circuit
Diagram). Current limiting is performed by comparing the voltage drop across the sense
resistor with the voltage drop across the drain to source resistance of the high side
MOSFET during the MOSFET's conduction period. The voltage drop across the drain to
source resistance of the high side MOSFET is obtained from the Vin and PHASE pins.
4
5
COMP
This is the output of the voltage amplifier. The voltage at this output is inverted internally and
connected to the non-inverting input of the PWM comparator. A lead-lag network from the
COMP pin to the VSENSE pin compensates for the two pole LC filter characteristics
inherent to voltage mode control. The lead-lag network is required in order to optimize the
dynamic performance of the voltage mode control loop.
FS/SYNC
The FS/SYNC pin sets the PWM oscillator frequency through an external timing capacitor
that is connected from the FS/SYNC pin to the GND pin. Sleep mode operation is invoked
by clamping the FS/SYNC pin to a voltage below 75mV. The typical supply current during
sleep mode is 10µA. The SC4607 can be operated in synchronous mode by inserting a
resistor in series between the timing capacitor and GND pin. The other terminal of the
timing capacitor will remain connected to the FS/SYNC pin.
6
7
VSENSE
GND
This pin is the inverting input of the voltage amplifier and serves as the output voltage
feedback point for the Buck converter. VSENSE is compared to an internal reference value
of 0.5V. VSENSE is hardwired to the output voltage when an output of 0.5V is desired.
For higher output voltages, a resistor divider network is necessary (R7 and R9 in the Typical
Application Circuit Diagram).
Signal and power ground for the IC. All voltages are measured with respect to this pin. All
bypass and timing capacitors connected to GND should have leads as short and direct as
possible.
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SC4607
POWER MANAGEMENT
Pin Descriptions (Cont.)
Pin #
Pin Name
Pin Function
8
DRVL
Gate drive pin. DRVL drives the gate of the low side (synchronous rectifier) MOSFET. The
output driver is rated for 1A peak current. The PWM circuitry provides complementary drive
signals to the output stages. The cross conduction of the external MOSFETs is prevented
by monitoring the voltage on the DRVH and DRVL driver pins of the MOSFET pair in
conjunction with a time delay optimized for FET turn-off characteristics
9
PHASE
DRVH
The PHASE pin is used to limit current in the high side MOSFET. The SC4607 uses the
voltage across the Vin and ISET pins in order to set the current limit. The current limit
threshold is set by the value of an external resistor (R3 in the Typical Application Circuit
Diagram). Current limiting is performed by comparing the voltage drop across the sense
resistor with the voltage drop across the drain to source resistance of the high side
MOSFET during the MOSFET’s conduction period. The voltage drop across the drain to
source resistance of the high side MOSFET is obtained from the Vin and PHASE pins.
10
Gate drive pin. DRVH drives the gate of the high side (main switch) MOSFET. The output
driver is rated for 1A peak current. The PWM circuitry provides complementary drive
signals to the output stages. The cross conduction of the external MOSFETs is prevented
by monitoring the voltage on the DRVH and DRVL driver pins of the MOSFET pair in
conjunction with a time delay optimized for FET turn-off characteristics
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SC4607
POWER MANAGEMENT
Block Diagram
Marking Information
4607
nnnn = Part Number (Example: 1456)
yyww = Datecode (Example: 0012)
xxxx = Semtech Lot # (Example: E901
xxxx
01-1)
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SC4607
POWER MANAGEMENT
Typical Characteristics
Oscillator Internal Accuracy
Oscillator Internal Accuracy
vs
vs
Input Voltage
Temperature
584
583
582
581
580
579
578
577
588
586
584
582
580
578
576
574
Vcc = 3.3V
TA = 25°C
2.5
3
3.5
4
4.5
5
5.5
-40
-20
0
20
40
60
80
Vcc (V)
Temperature (°C)
Sense Voltage
vs
Sense Voltage
vs
Input Voltage
Temperature
500.0
499.9
499.8
499.7
499.6
499.5
499.4
500.5
500.0
499.5
499.0
498.5
498.0
A
T
= 25°C
Vcc = 3.3V
-20
2.5
3
3.5
4
4.5
5
5.5
-40
0
20
40
60
80
Vcc (V)
Temperature (°C)
Current Limit Bias Current
Current Limit Bias Current
vs
vs
Input Voltage
Temperature
55
54
53
52
51
50
65
60
55
50
45
40
TA = 25°C
Vcc = 3.3V
2.5
3
3.5
4
4.5
5
5.5
-40
-20
0
20
40
60
80
Vcc (V)
Temperature (°C)
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SC4607
POWER MANAGEMENT
Application Information
Enable:
then connected to the junction of the external timing
capacitor and the added resistor as shown in Figure 1.
The SC4607 is enabled by applying a voltage greater than
2.25 volts to the VCC pin. The SC4607 is disabled when
VCC falls below 1.95 volts or when sleep mode opera-
tion is invoked by clamping the FS/SYNC pin to a voltage
below 75mV. 10µA is the typical current drawn through
the VCC pin during sleep mode. During the sleep mode,
the high side and low side MOSFETs are turned off and
the internal soft start voltage is held low.
SC4607
FS/SYNC
Ctiming
External
Clock
Signal
Rsync
Oscillator:
100 ohm
The FS/SYNC pin is used to set the PWM oscillator fre-
quency through an external timing capacitor that is con-
nected from the FS/SYNC pin to the GND pin. The re-
sulting ramp waveform on the FS/SYNC pin is a triangle
at the PWM frequency with a peak voltage of 1.3V and a
valley voltage of 0.3V. The PWM duty ratio is limited by
the ramp to a maximum of 97%, which allows the boot-
strap capacitor to be charged during each cycle. The ca-
pacitor tolerance adds to the accuracy of the oscillator
frequency. The approximate operating frequency and soft
start time are both determined by the value of the exter-
nal timing capacitor as shown in Table 1.
Figure 1
UVLO:
When the FS/SYNC pin is not pulled and held below 75mV,
the voltage on the Vcc pin determines the operation of
the SC4607. As Vcc increases during start up, the UVLO
block senses Vcc and keeps the high side and low side
MOSFETs off and the internal soft start voltage low until
Vcc reaches 2.25V. If no faults are present, the SC4607
will initiate a soft start when Vcc exceeds 2.25V. A hys-
teresis (100mV) in the UVLO comparator provides noise
immunity during its start up.
External Timing Frequency Soft Start Time (µs)
Capacitor Value
(pF)
(kHz)
Soft Start:
120
270
560
1000
580
628
The soft start function is required for step down control-
lers to prevent excess inrush current through the DC bus
during start up. Generally this can be done by sourcing a
controlled current into a timing capacitor and then using
the voltage across this capacitor to slowly ramp up the
error amp reference. The closed loop creates narrow
width driver pulses while the output voltage is low and
allows these pulses to increase to their steady state duty
cycle as the output voltage reaches its regulated value.
With this, the inrush current from the input side is con-
trolled. The duration of the soft start in the SC4607 is
controlled by an internal timing circuit which is used dur-
ing start up and over current to set the hiccup time. The
soft start time can be obtained from Table 1.
1220
1838
350
Table 1: Operating Frequency and Soft Start Time
Values Based On the Value of the External Timing
Capacitor Placed Across the FS/SYNC and GND Pins
Synchronous mode operation is invoked by using a sig-
nal from an external clock. A low value resistor (100Ω
typical) must be inserted in series with the timing capaci-
tor between the timing capacitor and the GND pin. The
other terminal of the timing capacitor will remain con-
nected to the FS/SYNC pin. The external clock signal is
The SC4607 implements its soft start by ramping up the
error amplifier reference voltage providing a controlled
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SC4607
POWER MANAGEMENT
current protection. Because the RDS(ON) has a positive
temperature coefficient, the 50µA current source has a
positive coefficient of about 0.28%/C° providing first or-
der correction for current sensing vs temperature. This
compensation depends on the high amount of thermal
transferring that typically exists between the high side N-
MOSFET and the SC4607 due to the compact layout of
the power supply.
Application Information (Cont.)
slew rate of the output voltage, then preventing over-
shoot and limiting inrush current during its start up. Dur-
ing start up of a converter with a big capacitive load, the
load current demands large supply current. To avoid this
an external soft start scheme can be implemented as
shown in Figure 2. Cs can be adjusted for different appli-
cations.
When the converter detects an over current condition (I
> IMAX) as shown in Figure 3, the first action the SC4607
takes is to enter the cycle by cycle protection mode (Point
B to Point C), which responds to minor over current cases.
Then the output voltage is monitored. If the over current
and low output voltage (set at 70% of nominal output
voltage) occur at the same time, the Hiccup mode op-
eration (Point C to Point D) of the SC4607 is invoked
and the internal soft start capacitor is discharged. This is
like a typical soft start cycle:
Pin COMP
Cs
Rs
Q
MMBT2222A-7
2.05k
330n
Vo
Output of a converter
Rp
47.5k
Figure 2
Over Current Protection:
The SC4607 detects over current conditions by sensing
the voltage across the drain-to-source of the high side
MOSFET. The SC4607 determines the high side MOSFET
current level by sensing the drain-to-source conduction
voltage across the high side MOSFET via the Vin (see the
Typical Application Circuit on page 1) and PHASE pin dur-
ing the high side MOSFET’s conduction period. This volt-
age value is then compared internally to a user pro-
grammed current limit threshold. Note that user should
place Kelvin sensing connections directly from the high
side MOSFET source to the PHASE pin.
A
B
VO −nom
0.6 ⋅VO−nom
C
0.7
VO
IMAX
D
IO
The current limit threshold is programmed by the user
based on the RDS(on) of the high side MOSFET and the
value of the external set resistor RSET (where RSET is
represented by R3 in the applications schematics of this
document). The SC4607 uses an internal current source
to pull a 50µA current from the input voltage to the ISET
pin through external resistor RSET.
Figure 3. Over current protection characteristic of
SC4607
Power MOSFET Drivers:
The current limit threshold resistor (RSET) value is calcu-
lated using the following equation:
The SC4607 has two drivers which are optimized for driv-
ing external power N-Channel MOSFETs.. The driver block
consists two 1 Amp drivers. DRVH drives the high side
N-MOSFET (main switch), and DRVL drives the low side
N-MOSFET (synchronous rectifier transistor).
The output drivers also have gate drive non-overlap
mechanism that provides a dead time between DRVH
and DRVL transitions to avoid potential shoot through
problems in the external MOSFETs. By using the proper
design and the appropriate MOSFETs, the SC4607 is
capable of driving a converter with up to 12A of output
IMAX RDS(ON)
RSET
=
50µA
The RDS(ON) sensing used in the SC4607 has an addi-
tional feature that enhances the performance of the over
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SC4607
POWER MANAGEMENT
Application Information (Cont.)
The peak to peak inductor current is:
current. As shown in Figure 4, t
top MOSFET off to the bottom MOSFET on is adaptive by
the delay from the
d1,
Ip−p = ∆I• IOMAX
detecting the voltage of the phase node. t , the delay
from the bottom MOSFET off to the top MOSFET on is
d2
fixed, is 40ns for the SC4607. This control scheme guar-
antees avoidance of cross conduction or shoot through
between the upper and lower MOSFETs and also mini-
mizes the conduction loss in the body diode of the bot-
tom MOSFET for high efficiency applications.
After the required inductor value is selected, the proper
selection of the core material is based on the peak in-
ductor current and efficiency requirements. The core
must be able to handle the peak inductor current IPEAK
without saturation and produce low core loss during the
high frequency operation is:
Ip−p
2
IPEAK = IOMAX
+
TOP MOSFET Gate Drive
BOTTOM MOSFET Gate Drive
The power loss for the inductor includes its core loss and
copper loss. If possible, the winding resistance should
be minimized to reduce inductor’s copper loss. The core
loss can be found in the manufacturer’s datasheet. The
inductor’ copper loss can be estimated as follows:
Ground
Phase node
td2
td1
PCOPPER = I2
RWINDING
LRMS
Figure 4. Timing Waveforms for Gate Drives and Phase
Node
Where:
ILRMS is the RMS current in the inductor. This current can
be calculated as follow is:
Inductor Selection:
1
3
ILRMS = IOMAX 1+
∆I2
The factors for selecting the inductor include its cost,
efficiency, size and EMI. For a typical SC4607 applica-
tion, the inductor selection is mainly based on its value,
saturation current and DC resistance. Increasing the in-
ductor value will decrease the ripple level of the output
voltage while the output transient response will be de-
graded. Low value inductors offer small size and fast tran-
sient responses while they cause large ripple currents,
poor efficiencies and more output capacitance to smooth
out the large ripple currents. The inductor should be able
to handle the peak current without saturating and its
copper resistance in the winding should be as low as
possible to minimize its resistive power loss. A good trade-
off among its size, loss and cost is to set the inductor
ripple current to be within 15% to 30% of the maximum
output current.
Output Capacitor Selection:
Basically there are two major factors to consider in se-
lecting the type and quantity of the output capacitors.
The first one is the required ESR (Equivalent Series Re-
sistance) which should be low enough to reduce the volt-
age deviation from its nominal one during its load changes.
The second one is the required capacitance, which should
be high enough to hold up the output voltage. Before the
SC4607 regulates the inductor current to a new value
during a load transient, the output capacitor delivers all
the additional current needed by the load. The ESR and
ESL of the output capacitor, the loop parasitic inductance
between the output capacitor and the load combined
with inductor ripple current are all major contributors to
the output voltage ripple. Surface mount speciality poly-
mer aluminum electrolytic chip capacitors in UE series
from Panasonic provide low ESR and reduce the total
capacitance required for a fast transient response.
POSCAP from Sanyo is a solid electrolytic chip capacitor
that has a low ESR and good performance for high fre-
quency with a low profile and high capacitance. Above
mentioned capacitors are recommended to use in
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The inductor value can be determined according to its
operating point and the switching frequency as follows:
Vout (V − Vout
)
in
L =
V
fs ∆I IOMAX
in
Where:
fs = switching frequency and
∆I = ratio of the peak to peak inductor current to the
maximum output load current.
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SC4607
POWER MANAGEMENT
Application Information (Cont.)
SC4607 application:
Where:
fs = the switching frequency and
Dmax = maximum duty ratio, 0.97 for the SC4607.
Input Capacitor Selection:
The required minimum capacitance for boost capacitor
will be:
The input capacitor selection is based on its ripple cur-
rent level, required capacitance and voltage rating. This
capacitor must be able to provide the ripple current by
the switching actions. For the continuous conduction
mode, the RMS value of the input capacitor can be cal-
culated from:
IB
VD
Cboost
=
TW
Where:
IB = the boost current and
VD= discharge ripple voltage.
Vout (V − Vout
)
in
ICIN
= IOMAX
(RMS)
2
V
in
With fs = 300kH, VD=0.3V and IB=50mA, the required
capacitance for the boost capacitor is:
This current gives the capacitor’s power loss as follows:
IB
VD fs
1
0.05
0.3 300k
1
PCIN = I2
RCIN(ESR)
Cboost
=
Dmax
=
0.97 = 540nF
CIN(RMS)
This capacitor’s RMS loss can be a significant part of the
total loss in the converter and reduce the overall con-
verter efficiency. The input ripple voltage mainly depends
on the input capacitor’s ESR and its capacitance for a
given load, input voltage and output voltage. Assuming
that the input current of the converter is constant, the
required input capacitance for a given voltage ripple can
be calculated by:
Power MOSFET Selection:
The SC4607 can drive an N-MOSFET at the high side
and an N-MOSFET synchronous rectifier at the low side.
The use of the high side N-MOSFET will significantly re-
duce its conduction loss for high current. For the top
MOSFET, its total power loss includes its conduction loss,
switching loss, gate charge loss, output capacitance loss
and the loss related to the reverse recovery of the bot-
tom diode, shown as follows:
D (1−D)
fs (∆V −IOMAX RCIN
CIN = IOMAX
)
I
(ESR)
Where:
D = Vout/Vin , duty ratio and
∆VI = the given input voltage ripple.
ITOP _PEAK
V
fs
in
PTOP _TOTAL = I2
RTOP _ON
+
TOP _RMS
V
GATE RG
Because the input capacitor is exposed to the large surge
current, attention is needed for the input capacitor. If
tantalum capacitors are used at the input side of the
converter, one needs to ensure that the RMS and surge
ratings are not exceeded. For generic tantalum capaci-
tors, it is wise to derate their voltage ratings at a ratio of
2 to protect these input capacitors.
(QGD + QGS2 ) + QGT VGATE fs + (QOSS + Qrr ) V fs
in
Where:
RG = gate drive resistor,
QGD = the gate to drain charge of the top MOSFET,
QGS2 = the gate to source charge of the top MOSFET,
QGT = the total gate charge of the top MOSFET,
QOSS = the output charge of the top MOSFET and
Qrr = the reverse recovery charge of the bottom diode.
Boost Capacitor Selection:
The boost capacitor selection is based on its discharge
ripple voltage, worst case conduction time and boost
current. The worst case conduction time Tw can be esti-
mated as follows:
For the top MOSFET, it experiences high current and high
voltage overlap during each on/off transition. But for the
1
fs
Tw =
Dmax
2005 Semtech Corp.
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SC4607
POWER MANAGEMENT
Application Information (Cont.)
voltage according to
bottom MOSFET, its switching voltage is the body diode’s
forward drop of the bottom MOSFET during its on/off
transition. So the switching loss for the bottom MOSFET
is negligible. Its total power loss can be determined by:
R7
R9
Vout = 0.5 (1+
)
PBOT _TOTAL = I2
RBOT _ON + QGB VGATE fs +ID _AVG VF
BST
DRVH
PHASE
DRVL
GND
L1
BOT _RMS
Vout
VCC
ISET
COMP
Where:
C9
QGB = the total gate charge of the bottom MOSFET and
VF = the forward voltage drop of the body diode of the
bottom MOSFET.
C1
C2
FS/SYNC VSENSE
C4
R
R7
SC4607
R8
R1
For a low voltage and high output current application such
as the 3.3V/1.5V@12A case, the conduction loss is of-
ten dominant and selecting low RDS(ON) MOSFETs will no-
ticeably improve the efficiency of the converter even
though they give higher switching losses.
R9
Figure 4. Compensation network provides 3
poles and 2 zeros.
Figure 5. Compensation network provides 3 poles and
2 zeros.
The gate charge loss portion of the top/bottom MOSFET’s
total power loss is derived from the SC4607. This gate
charge loss is based on certain operating conditions (fs,
VGATE, and IO).
For voltage mode step down applications as shown in
Figure 5, the power stage transfer function is:
s
The thermal estimations have to be done for both
MOSFETs to make sure that their junction temperatures
do not exceed their thermal ratings according to their
total power losses PTOTAL, ambient temperature TA and their
1+
1
RC C4
1+ s + s2L1C4
GVD (s) = V
I
L1
R
thermal resistance R JA as follows:
θ
Where:
R = load resistance and
RC = C4’s ESR.
PTOTAL
TJ(max) < TA +
RθJA
Loop Compensation Design:
The compensation network will have the characteristic
as follows:
For a DC/DC converter, it is usually required that the
converter has a loop gain of a high cross-over frequency
for fast load response, high DC and low frequency gain
for low steady state error, and enough phase margin for
its operating stability. Often one can not have all these
properties at the same time. The purpose of the loop
compensation is to arrange the poles and zeros of the
compensation network to meet the requirements for a
specific application.
s
ωZ1
s
s
ωZ2
s
1+
1+
1+
1+
ωI
GCOMP (s) =
s
ωP1
ωP2
Where
1
ωI =
R7 (C1 + C2 )
The SC4607 has an internal error amplifier and requires
the compensation network to connect among the COMP
pin and VSNSE pin, GND, and the output as shown in
Figure 5. The compensation network includes C1, C2,
R1, R7, R8 and C9. R9 is used to program the output
1
ωZ1
=
R1 C2
1
ωZ2
=
(R7 + R8 ) C9
2005 Semtech Corp.
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SC4607
POWER MANAGEMENT
Application Information (Cont.)
C1 + C2
R1 C1 C2
ωP1
=
Layout Guidelines:
1
=
In order to achieve optimal electrical, thermal and noise
performance for high frequency converters, special at-
tention must be paid to the PCB layouts. The goal of lay-
out optimization is to identify the high di/dt loops and
minimize them. The following guideline should be used to
ensure proper functions of the converters.
ωP2
R8 C9
After the compensation, the converter will have the fol-
lowing loop gain:
s
1+
1
s
s
ωZ2
s
1
ωI
V
1+
1+
1+
1+
I
VM
ωZ1
s
RC C4
1+ s + s2L1C
T(s) = GPWM GCOMP(s) GVD(s) =
L1
R
s
1. A ground plane is recommended to minimize noises
and copper losses, and maximize heat dissipation.
2. Start the PCB layout by placing the power compo-
nents first. Arrange the power circuit to achieve a
clean power flow route. Put all the connections on
one side of the PCB with wide copper filled areas if
possible.
ωP1
ωP2
Where:
GPWM = PWM gain
VM = 1.0V, ramp peak to valley voltage of SC4607
The design guidelines for the SC4607 applications are
as following:
3. The Vcc bypass capacitor should be placed next to
the Vcc and GND pins.
1. Set the loop gain crossover corner frequency ω C
for given switching corner frequency ωS = 2πfs,
2. Place an integrator at the origin to increase DC
and low frequency gains.
4. The trace connecting the feedback resistors to the
output should be short, direct and far away from the
noise sources such as switching node and switching
components.
3. Select ωZ1 and ωZ2 such that they are placed near
ωO to damp the peaking and the loop gain has a
-20dB/dec rate to go across the 0dB line for
obtaining a wide bandwidth.
4. Cancel the zero from C4’s ESR by a compensator
pole ωP1 (ωP1 = ωESR = 1/( RCC4)).
5. Place a high frequency compensator pole ωp2 (ωp2
= πfs) to get the maximum attenuation of the switch-
ing ripple and high frequency noise with the adequate
phase lag at ωC.
5. Minimize the traces between DRVH/DRVL and the
gates of the MOSFETs to reduce their impedance to
drive the MOSFETs.
6. Minimize the loop including input capacitors, top/bot-
tom MOSFETs. This loop passes high di/dt current.
Make sure the trace width is wide enough to reduce
copper losses in this loop.
7. ISET and PHASE connections to the top MOSFET for
current sensing must use Kelvin connections.
8. Maximize the trace width of the loop connecting the
inductor, bottom MOSFET and the output capacitors.
The compensated loop gain will be as given in Figure 6:
9. Connect the ground of the feedback divider and the
compensation components directly to the GND pin
of the SC4607 by using a separate ground trace.
Then connect this pin to the ground of the output
capacitor as close as possible
T(s)
Loop gain T(s)
ωz1
ωo
ωz2
-20dB/dec
Gvd
0dB
ωc
ωp1
ωp2
Power stage
GVD(s)
ωESR
-40dB/dec
Figure 6. Asymptotic diagrams of power stage and its
loop gain.
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SC4607
POWER MANAGEMENT
Application Information (Cont.)
Design Example 1: 3.3V to1.5V @12A application with SC4607
Vin=3.3V
C13
C10
22u
C11
C14
D2
22u
100u
100u
R3
1u
C71
R13
1
M1
M2
0
U1
R6
1
2
3
4
5
10
9
BST
DRVH
PHASE
DRVL
GND
L1
C3
Vo=1.5V/12A
VCC
ISET
COMP
4.7u
2.3u
8
7
C7
C5
C4
C9
C16
560pF
2.2n
C2
C1
6
22u
22u
330u
5.6n
R7
8.25k
FS/SYNC VSENSE
0
270p
R5
R8
169
SC4607
R1
14.3k
R9
4.12k
Design Example 2: 3.3V to 2.5V @ 20A application with SC4607
2 x 4TPE150M
Vin=3.3V
C10
C11
C13
22u
C14
22u
150u
150u
D2
1u
C17
4 x C3216X5R0J226M
C18
0.1u
R13
1
R3
M12
M22
M11
1.05k
U1
R6
0
1
2
3
4
5
10
9
BST
DRVH
PHASE
DRVL
GND
ETQPAF1R3EA
C3
4.7u
Vo=2.5V/20A
VCC
ISET
COMP
R5
L1 1.3u
8
0
C7
C5
22u
7
C4
C9
M21
C16
560pF
330u
1.5n
6
22u
C2
R7
16.5k
2.7n
FS/SYNC VSENSE
C1
R8
365
SC4607
270p
R1
4 x Si7882
4TPD330M
20k
R9
4.12k
2005 Semtech Corp.
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SC4607
POWER MANAGEMENT
Bill of Materials - 3.3V to 1.5V @ 12A
Item
1
Qty
1
Reference
Value
Part No./Manufacturer
C1
270pF
2.2nF
2
1
C2
3
1
C17
1uF
4
4
C4,C5, C10, C11
22uF, 1210
TDK P/N: C3225X5R0J226M
Sanyo P/N: 6TPD330M
5
1
C7
330uF, 2870
5.6nF
6
1
C9
7
1
C18
C16
D2
0.1nF
8
1
560pF
9
1
MBR0520LT1
ON Semi P/N: MBR0520LT1
Cooper Electronic
P/N: HC1-2R3
10
1
L1
2.3uH
11
12
13
14
15
16
17
18
19
20
21
2
1
1
2
1
1
1
1
1
2
1
M1,M2
R1
Powerpack, SO-8
Vishay P/N: Si7882DP
14.3K
1.4K
R3
R5, R6
R7
0
8.25K
169
R8
R9
4.12K
1
R13
C3
4.7uF, 0805
100uF, 2870
SC4607
C13,C14
U1
Sanyo P/N: 6TPB100M
Semtech P/N: SC4607IMSTR
Unless specified, all resistors and capacitors are in SMD 0603 package.
Resistors are +/-1% and all capacitors are +/-20%
2005 Semtech Corp.
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SC4607
POWER MANAGEMENT
PCB Layout - 3.3V to 1.5V @ 12A
TOP
TOP
BOTTOM
BOTTOM
2005 Semtech Corp.
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SC4607
POWER MANAGEMENT
Outline Drawing - MSOP-10
DIMENSIONS
INCHES MILLIMETERS
e
DIM
A
A
MIN NOM MAX MIN NOM MAX
D
E
-
-
-
-
-
-
-
-
-
-
-
-
.043
1.10
0.15
0.95
0.27
0.23
N
A1 .000
A2 .030
.006 0.00
.037 0.75
.011 0.17
.009 0.08
b
c
D
.007
.003
2X
E/2
.114 .118 .122 2.90 3.00 3.10
E1
E1 .114 .118 .122 2.90 3.00 3.10
PIN 1
E
e
.193 BSC
.020 BSC
4.90 BSC
0.50 BSC
INDICATOR
L
L1
N
.016 .024 .032 0.40 0.60 0.80
ccc C
2X N/2 TIPS
1 2
(.037)
10
-
(.95)
10
-
B
01
aaa
0°
8°
0°
8°
.004
.003
.010
0.10
0.08
0.25
bbb
ccc
D
aaa C
H
A2
A
SEATING
PLANE
c
GAGE
A1
bxN
bbb
C
PLANE
C
A-B D
0.25
L
01
(L1)
DETAIL A
SEE DETAIL A
SIDE VIEW
NOTES:
1. CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES).
2. DATUMS -A- AND -B- TO BE DETERMINED AT DATUM PLANE -H-
3. DIMENSIONS "E1" AND "D" DO NOT INCLUDE MOLD FLASH, PROTRUSIONS
OR GATE BURRS.
4. REFERENCE JEDEC STD MO-187, VARIATION BA.
Land Pattern - MSOP-10
X
DIMENSIONS
DIM
INCHES
(.161)
.098
MILLIMETERS
(4.10)
2.50
0.50
0.30
1.60
5.70
C
G
P
X
Y
Z
(C)
G
Y
Z
.020
.011
.063
.224
P
NOTES:
1. THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY.
CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR
COMPANY'S MANUFACTURING GUIDELINES ARE MET.
Contact Information
Semtech Corporation
Power Management Products Division
200 Flynn Road, Camarillo, CA 93012
Phone: (805)498-2111 FAX (805)498-3804
2005 Semtech Corp.
17
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