SC480IMLTRT_技术文档

SC480

Complete DDR1/2/3

Memory Power Supply

POWER MANAGEMENT

Description

Features

The SC480 is a combination switching regulator and Constant On-Time Controller for Fast Dynamic

linear source/sink regulator intended for DDR1/2/3 Response on VDDQ

memory systems. The purpose of the switching regulator DDR1/DDR2/DDR3 Compatible

is to generate the supply voltage, VDDQ, for the memory VDDQ = Fixed 1.8V or 2.5V, or Adjustable from

system. It is a pseudo-ﬁxed frequency constant on-

1.5V to 3.0V

time controller designed for high efﬁciency, superior DC 1% Internal Reference (2% System Accuracy)

accuracy, and fast transient response. The purpose of the Resistor Programmable On-Time for VDDQ

linear source/sink regulator is to generate the memory VCCA/VDDP Range = 4.5V to 5.5V

termination voltage, VTT, with the ability to source and VIN Range = 2.5V to 25V

sink a 3A peak current.

VDDQ DC Current Sense Using Low-Side R_DS(ON)

Sensing or External R_SENSEin Series with Low-Side

FET

FortheVDDQregulator,theswitchingfrequencyisconstant

until a step in load or line voltage occurs at which time the Cycle-by-Cycle Current Limit for VDDQ

pulse density, i.e., frequency, will increase or decrease to Digital Soft-Start for VDDQ

counter the transient change in output or input voltage. Analog Soft-Start for VTT/REF

After the transient, the frequency will return to steady-state Smart Over-Voltage VDDQ Protection Against Source-

operation. At lighter loads, the selectable Power-Save

Current Loads

Mode enables the PWM converter to reduce its switching Combined EN and PSAVE Pin for VDDQ

frequency and improve efﬁciency. The integrated gate Over-Voltage/Under-Voltage Fault Protection

drivers feature adaptive shoot-through protection and Power Good Output

soft-switching. Additional features include cycle-by-cycle Separate VCCA and VDDP Supplies

current limiting, digital soft-start, over-voltage and under- VTT/REF Range = 0.75V – 1.5V

voltage protection and a power good ﬂag.

VTT Source/Sink 3A Peak

Internal Resistor Divider for VTT/REF

For the VTT regulator, the output voltage tracks REF, VTT is High Impedance in S3

which is ½ VDDQ to provide an accurate termination VDDQ, VTT, REF Are Actively Discharged in S4/S5

voltage. The VTT output is generated from a 1.2V to VDDQ 24 Lead MLPQ (4x4 mm) Lead-Free Package

input by a linear source/sink regulator which is designed Fully WEEE and RoHS Compliant

for high DC accuracy, fast transient response, and low

external component count. All three outputs (VDDQ, VTT

Applications

¡ Notebook Computers

¡ CPU I/O Supplies

¡ Handheld Terminals and PDAs

¡ LCD Monitors

and REF) are actively discharged when VDDQ is disabled,

reducing external component count and cost. The SC480

is available in a 24-pin MLPQ (4x4 mm) package.

Typical Application Circuit

¡ Network Power Supplies

5V

VBAT

D1

C2

0.1uF

C3

2x10uF

VDDQ

Q1

VTT

VBAT

VDDQ

L1

C1

1uF

C4

10uF

C5

10uF

+

Q2

C6

1

2

3

4

5

6

18

PGND2

VTTS

VSSA

TON

PGND1

ILIM

R1

1Meg

U1

17

RILIM

16

VTTSNS

SC480

15

VDDP

14

C7

1nF

REF

13

VCCA

PGOOD

PGD

PAD

R6

10R

C10

1uF

PAD

R4

REF

C9

1uF

R7

10R

5V

C8

0.1uF

C11

1uF

EN/PSV

VTT_EN

VDDQ

1

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November 3, 2006

SC480

POWER MANAGEMENT

Absolute Maximum Ratings

Exceeding the speciﬁcations below may result in permanent damage to the device or device malfunction. Operation outside of the parameters speciﬁed in the

Electrical Characteristics section is not implied. Exposure to absolute maximum rated conditions for extended periods of time may affect device reliability.

Parameter

Symbol

Maximum

Units

TON to VSSA

-0.3 to +25.0

-0.3 to +31.0

-0.3 to +6.0

-2.0 to +25.0

-0.3 to +6.0

-0.3 to +0.3

29

V

DH, BST to PGND1

BST, DH to LX

V

LX to PGND1

V

DL, ILIM, VDDP to PGND1

V

VDDP to DL

V

VTTIN to PGND2; VTT to PGND2; VTTIN to VTT

EN/PSV, FB, PGD, REF, VCCA, VDDQS, VTTEN, VTTS to VSSA

VCCA to EN/PSV, FB, REF, VDDQS, VTT, VTTEN, VTTIN, VTTS

PGND1 to PGND2; PGND1 to VSSA; PGND2 to VSSA

Thermal Resistance Junction to Ambient⁽¹⁾

Operating Junction Temperature Range

Storage Temperature Range

V

θ_JA

T_J

°C/W

°C

kV

-40 to +150

-65 to +150

260

T_STG

T_PKG

V_ESD

Peak IR Reﬂow Temperature, 10s - 40s

ESD Protection Level⁽²⁾

2

Notes:

1) Calculated from package in still air, mounted to 3” x 4.5”, 4 layer FR4 PCB with thermal vias under the exposed pad per JESD51 standards.

2) Tested according to JEDEC standard JESD22-A114-B.

Electrical Characteristics

TEST CONDITIONS: V_IN= 15V, VCCA = VDDP = VTTEN = EN/PSV = 5V, VDDQ = VTTIN = 1.8V, R_TON= 1MΩ. T_AMB= -40 TO +85C.

25°C

Typ

-40°C to 85°C

Parameter

Conditions

Units

Min

Max

Min

Max

Input Supplies

S0 State (VTT on);

EN/PSV = VCCA;

FB > Regulation Point, IVDDQ = 0A

VCCA Operating Current

1500

800

2500

1400

μA

S3 State (VTT off);

EN/PSV = VCCA;

VCCA Operating Current

FB > Regulation Point, IVDDQ = 0A

VCCA Operating Voltage

VDDP Operating Current

TON Operating Current

VTTIN Operating Current

5

70

15

1

4.5

5.5

V

FB > Regulation Point, IVDDQ = 0A

RTON = 1MΩ

150

μA

IVTT = 0A

5

VCCA + VDDP + TON

Shutdown Current

EN/PSV = VTTEN = 0V

5

1

11

μA

VTTIN Shutdown Current

2

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SC480

POWER MANAGEMENT

Electrical Characteristics (Cont.)

TEST CONDITIONS: V_IN= 15V, VCCA = VDDP = VTTEN = EN/PSV = 5V, VDDQ = VTTIN = 1.8V, R_TON= 1MΩ. T_AMB= -40 TO +85C.

25°C

-40°C to 85°C

Min Max

Parameter

Conditions

Units

Min

Typ

Max

VDDQ Controller

FB Error Comparator Threshold⁽¹⁾

With Adjustable Resistor Divider

FB = AGND

1.500

2.5

1.485 1.515

2.475 2.525

1.782 1.818

V

VDDQS Regulation Threshold

FB = VCCA

1.8

RTON = 1MΩ, VDDQ = 1.8V

RTON = 500kΩ, VDDQ = 1.8V

460

265

425

80

368

212

552

318

550

On-Time

ns

Minimum Off-Time

VDDQS Input Resistance

ns

kΩ

FB < 0.3V

FB > 0.3V

91

VDDQS Shutdown

Discharge Resistance

EN/PSV = GND

16

8

Ω

FB Leakage Current

VDDQ Smart Psave Threshold

VTT Controller

-1.0

1.0

μA

%

REF Source Current

REF Sink Resistance

REF Output Accuracy

10

mA

kΩ

mV

Ω

50

900

0.25

8

IREF = 0 to 10mA

882

918

VTT

REF

Shutdown Discharge Resistance

(EN/PSV = GND)

Ω

VTT Output Accuracy

(with respect to REF)

-2A < I_VTT< 2A⁽⁹⁾

0

-40

+40

1.0

mV

VTTS Leakage Current

Current Sensing

ILIM Current

-1.0

μA

DL High

10

5

9

11

10

μA

mV

Current Comparator Offset

PGND1 - ILIM

-10

Zero-Crossing Threshold

PGND1 - LX, EN/PSV = 5V

VDDQ Fault Protection

PGND1 - LX, RLIM = 5kΩ

PGND1 - LX, RLIM = 10kΩ

PGND1 - LX, RLIM = 20kΩ

50

35

80

65

Current Limit (Positive)⁽²⁾

100

200

120

230

mV

170

Current Limit (Negative)

PGND1 - LX

-125

-30

-160

-35

-90

-25

mV

%

Output Under-Voltage Fault

With Respect to FB Regulation Point

3

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SC480

POWER MANAGEMENT

Electrical Characteristics (Cont.)

TEST CONDITIONS: V_IN= 15V, VCCA = VDDP = VTTEN = EN/PSV = 5V, VDDQ = VTTIN = 1.8V, R_TON= 1MΩ. T_AMB= -40 TO +85C.

25°C

-40°C to 85°C

Parameter

Conditions

Units

Min

Typ

8

Max

Min

Max

Under-Voltage Fault Delay

Under-Voltage Blank Time

Output Over-Voltage Fault

Over-Voltage Fault Delay

PGD Low Output Voltage

PGD Leakage Current

PGD UV Threshold

FB Forced Below UV V_TH

From EN High

clks⁽³⁾

%

440

+16

5

With Respect to FB Regulation Point

FB Above Over-VoltageThreshold

Sink 1mA

+12

+20

μs

0.1

1

V

FB in Regulation, PGD = 5V

With Respect to FB Regulation Point

FB Forced Outside PGD Window

μA

%

-10

5

-12

-8

PGD Fault Delay

μs

VCCA Under-Voltage (UVLO)

Falling Edge (Hysteresis 100 mV)

4

3.70

4.35

V

VTT Fault Protection

UV Lower Threshold

OV Upper Threshold

Fault Shutdown Delay

Thermal Shutdown⁽⁴⁾⁽⁵⁾

Inputs/Outputs

VTT w/rt REF

-12

+12

50

-16

+8

-8

%

+16

VTT Outside OV/UV Window

μs

°C

160

150

170

EN/PSV Low/Low (Disabled)

VTTEN Low (VTT Disabled)

1.2

0.6

Logic Input Low Voltage

Logic Input High Voltage

V

EN/PSV Low/High

(Enabled, Psave Disabled)

1.2

2.4

3.1

2.4

V

VTTEN High (VTT Enabled)

EN/PSV High/High

(Enabled, Psave Enabled)

Logic Input High Voltage

EN/PSV Input Resistance

Sourcing

Sinking

1.5

1.0

MΩ

μA

VTTEN Leakage Current

-1

+1

Soft-Start

VDDQ Soft-Start Ramp Time

VTT Soft-Start Ramp Rate⁽⁶⁾

EN/PSV High to PGD High

440

5.5

clks⁽³⁾

mV/μs

4

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SC480

POWER MANAGEMENT

Electrical Characteristics (Cont.)

TEST CONDITIONS: V_IN= 15V, VCCA = VDDP = VTTEN = EN/PSV = 5V, VDDQ = VTTIN = 1.8V, R_TON= 1MΩ. T_AMB= -40 TO +85C.

25°C

-40°C to 85°C

Parameter

Conditions

Units

Min

Typ

Max

Min

Max

FB Input Thresholds

FB Logic Input Low

VDDQ Set for 2.5V (DDR1)

VDDQ Set for 1.8V (DDR2)

0.3

V

VCCA

- 0.7

FB Logic Input High

Gate Drives

Shoot-Thru Protection Delay⁽⁴⁾⁽⁷⁾

DL Pull-Down Resistance

DL Sink Current

DH or DL Rising

DL Low

30

0.8

3.1

2

ns

Ω

A

V_DL= 2.5V

DL Pull-Up Resistance

DL Source Current

DL High

Ω

A

V_DL= 2.5V

1.3

2

DH Pull-Down Resistance

DH Pull-Up Resistance⁽⁸⁾

DH Sink/Source Current

VTT Pull-Up Resistance

DH Low, BST - LX = 5V

DH High, BST - LX = 5V

V_DH= 2.5V

Ω

A

2

1.3

0.25

VTTS < REF

Ω

VTT Pull-Down Resistance

VTT Peak Sink/Source Current⁽⁹⁾

Notes:

VTTS > REF

0.25

3.6

Ω

2.0

A

1) The VDDQ DC regulation level is higher than the FB error comparator threshold by 50% of the ripple voltage.

2) Using a current sense resistor, this measurement relates to PGND1 minus the source of the low-side MOSFET.

3) clks = switching cycles, consisting of one high side and one low side gate pulse.

4) Guaranteed by design.

5) Thermal shutdown latches both outputs (VTT and VDDQ) off, requiring VCCA or EN/PSV cycling to reset.

6) VTT soft-start ramp rate is limited to 5.5mV/μs typical. If the VDDQ/2 ramp rate is slower than 5.5mV/μsec, the VTT soft-start ramp will follow the VDDQ/2

ramp.

7) See Shoot-Through Delay Timing Diagram on Page 6.

8) Semtech’s SmartDriver™ FET drive ﬁrst pulls DH high with a pull-up resistance of 10Ω (typ.) until LX = 1.5V (typ.). At this point, an additional pull-up device is

activated, reducing the resistance to 2Ω (typical). This creates a softer turn-on with minimal power loss, eliminating the need for an external gate or boost

resistor.

9) Provided operation below T_J(MAX)is maintained. VTT output current is also limited by internal MOSFET resistance which is typically 0.25Ω at 25°C and which

increases with temperature, and by available source voltage (typically VDDQ/2).

5

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SC480

POWER MANAGEMENT

Shoot-Through Delay Timing Diagram

LX

DH

DL

tplhDL

tplhDH

6

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SC480

POWER MANAGEMENT

Pin Conﬁguration

Ordering Information

Device⁽²⁾

Package⁽¹⁾

SC480 MLP24 Pin Out

SC480IMLTRT

MLPQ-24

SC480EVB

Evaluation Board

1

2

3

4

5

6

PGND2

VTTS

VSSA

TON

PGND1

ILIM

18

17

16

Notes:

1) Only available in tape and reel packaging. A reel contains 3000 devices.

2) This product is fully WEEE and RoHS compliant.

T

15

14

VDDP

PGD

REF

13

VCCA

Pin Description

Pin #

Pin Name Pin Function

1

2

3

PGND2

VTTS

Power ground for VTT output. Connect to thermal pad and ground plane.

Sense pin for VTT. Connect to VTT at the load.

VSSA

Ground reference for analog circuitry. Connect to thermal pad.

This pin is used to sense VBAT through a pull-up resistor, RTON, which sets the top MOSFET

on-time. Bypass this pin with a 1nF capacitor to VSSA.

4

5

TON

REF

Reference output. An internal resistor divider from VDDQS sets this voltage to 50% VDDQ (nomi-

nal). Bypass this pin with a series 10Ω/1μF to VSSA.

6

7

8

9

VCCA

NC

Analog supply voltage input. Use a 10Ω/1μF RC ﬁlter from +5V to VSSA.

No Connect.

VDDQS

FB

Sense input for VDDQ. Used to set the on-time for the top MOSFET and also to set REF/VTT.

Feedback select input for VDDQ. See FB Conﬁguration Table.

Enable pin for VTT. Pull this pin low to disable VTT (REF remains present as long as VDDQ is

present).

10

11

VTTEN

Enable/Power Save input pin. Tie to ground to disable VDDQ. Tie to +5V to enable VDDQ and

activate PSAVE mode. Float to enable VDDQ and activate continous conduction mode. If ﬂoated,

bypass to VSSA with a 10nF capacitor.

EN/PSV

12

13

NC

No Connect.

Power good output for VDDQ. PGD is low if VDDQ is outside the power good thresholds. This

pin is an open drain NMOS output and requires an external pull-up resistor.

PGD

14,15

VDDP

+5V supply voltage input for the VDDQ gate drivers.

7

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SC480

POWER MANAGEMENT

Pin Description (Cont.)

Current limit input pin. Connect to drain of low-side MOSFET for RDS(on) sensing or the source

for resistor sensing through a threshold sensing resistor.

16

ILIM

17,18

19

PGND1

DL

Power ground for VDDQ switching circuits. Connect to thermal pad and ground plane.

Gate drive output for the low side MOSFET switch.

20

LX

Phase node - the junction between the top and bottom FETs and the output inductor.

Gate drive output for the high side MOSFET switch.

21

DH

22

BST

Boost capacitor connection for the high side gate drive.

Input supply for the high side switch for VTT regulator. Decouple with a 1μF capacitor to

PGND2.

23

24

T

VTTIN

VTT

Output of the linear regulator. Decouple with two (minimum) 10μF ceramic capacitors to

PGND2, locating them directly across pins 24 and 1.

THERMAL

PAD

Pad for heatsinking purposes. Connect to ground plane using multiple vias. Not connected

internally.

Enable Control Logic

Enable Pin Status

Output Status

EN/PSV⁽¹⁾

VTTEN

VDDQ⁽³⁾

VTT⁽²⁾

REF⁽²⁾

OFF, Discharged (2)

3(

)

OFF, Discharged2(

)

OFF, Discharged (2)

0

1

0

1

0

1

3(

)

OFF, Discharged2(

)

ON

OFF, High Impedance

ON

Notes:

1) EN/PSV = 1 = EN/PSV high or ﬂoating.

2) Typical discharge resistances: VTT = 0.25Ω. REF = 8Ω.

3) VDDQ is discharged via external series resistance which must be added to SC480 internal discharge resistance to calculate discharge times.

This is separate from any external load on VDDQ.

FB Conﬁguration Table

The FB pin can be conﬁgured for ﬁxed or adjustable output voltage as shown.

FB

GND

VDDQ(V)

2.5

VREF & VTT (V)

VDDQS/2

Note

DDR1

VCCA

1.8

VDDQS/2

DDR2

FB Resistors

Adjustable

VDDQS/2

1.5V < VDDQ < 3.0V

8

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SC480

POWER MANAGEMENT

Block Diagram

VTTEN

VTTIN

VCCA

OTSD

DRVH

VDDQS

+12%

POR/SS

VTT

NOVLP

DRVL

-12%

PGND2

REF

DSCHG

DRVH

DRVL

+12%

FEDLY

VCCA

VTTS

VTTRUN

VTTPGD

EN/PSV

OTSD

TON/ TOFF

TON

DSCHG

POR/SS

-12%

VDDQS

BST

DH

DSCHG

HI

1.5V

REF

-10%

+16%

VMON

CONTROL

-30%

LX

SHOOT

THRU

VDDP

LX

DL

OV

SD

LO

DL

1.5V

PGND1

FB

PWM

SENSE

-10%

UV

OV

-30%

ILIM

SD

PGD

+16%

FAULTMON

VSSA

Figure 1

9

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SC480

POWER MANAGEMENT

Application Information

+5V Bias Supplies

§ V

OUT

·

ꢁ12

3

¨

¸

¹

T

3.3x10

x (RTONꢀ 37x10 ) x

ꢀ 50ns

ON

TheSC480requiresanexternal+5Vbiassupplyinaddition

to the battery. If stand-alone capability is required, the

+5V supply can be generated with an external linear

regulator. To minimize crosstalk, the controller has seven

supply pins: VDDP (2 pins), PGND1 (2 pins), PGND2,

VCCA and AGND.

¨

V

IN

©

RTON is a resistor connected between the input supply and

the TONpin.

VDDQ/VTT Enable & Power-Save

The EN/PSV pin controls the VDDQ supply and the REF

output (1/2 of VDDQ). VTTEN enables the VTT supply. The

VTT and VDDQ supplies may be enabled independently.

When EN/PSV is tied to VCCA the VDDQ controller is

enabled in power-save mode. When the EN/PSV pin is

ﬂoated, an internal resistor divider activates the VDDQ

controller with power-save disabled. If PSAVE is enabled,

the SC480 PSAVE comparator looks for inductor current

to cross zero on eight consecutive cycles. Once observed,

the controller enters power-save and turns off the low-

side MOSFET when the current crosses zero. To improve

the efﬁciency and add hysteresis, the on-time is increased

by 20% in power-save. The efﬁciency improvement at light

loads more than offsets the disadvantage of slightly higher

output ripple. If the inductor current does not cross zero

on any switching cycle, the controller immediately exits

power-save. Since the controller counts zero crossings,

the converter can sink current as long as the current does

not cross zero on eight consecutive cycles. This allows the

output voltage to recover quickly in response to negative

load steps even when power-save is enabled.

The controller requires its own AGND plane which should

be tied by a single trace to the negative terminal of the

output capacitor. All external components referenced

to AGND in the schematic should then be connected to

the AGND plane. The supply decoupling capacitor should

be tied between VCCA and AGND. A single 10Ω resistor

should be used to decouple the VCCA supply from the

main VDDP supply. PGND can then be a separate plane

which is not used for routing analog traces. All PGND

connections should connect directly to this plane with

special attention given to avoiding indirect connections

between AGND and PGND which will create ground loops.

As mentioned above, the AGND plane must be connected

to the PGND plane at the negative terminal of the output

capacitor. The VDDP input provides power to the upper

and lower gate drivers. A decoupling capacitor for the

VDDP supply and PGND is recommended. No series

resistor between VDDP and the 5 volt bias is required.

Pseudo-Fixed Frequency Constant On-Time

PWM Controller

The PWM control method is a constant-on-time, pseudo-

ﬁxed frequency PWM controller, see Figure 1. The ripple

voltage seen across the output capacitor’s ESR provides

the PWM ramp signal, eliminating the need for a current

sense resistor. The on-time is determined by a one-shot

whose period is proportional to output voltage, and

inversely proportional to input voltage. A separate one-

shot sets the minimum off-time (typically 425ns).

VDDQ Voltage Selection

VDDQ voltage is set using the FB pin. Grounding FB sets

VDDQ to ﬁxed 2.5V. Connecting FB to +5V sets VDDQ to

ﬁxed 1.8V. VDDQ can also be adjusted from 1.5 to 3.0V

using external resistors, see Figure 2. The voltage at FB is

then compared to the internal 1.5V reference.

To VDDQ output capacitor

On-Time One-Shot (T_ON)

The on-time one-shot comparator has two inputs. One

input looks at the output voltage, while the other input

samples the input voltage and converts it to a proportional

current. This current charges an internal on-time capacitor.

The TON time is the time required for this capacitor to

charge from zero volts to VOUT, thereby making the on-

time of the high-side switch directly proportional to output

voltage and inversely proportional to input voltage. This

implementation results in a nearly constant switching

frequency without the need of a clock generator.

C

R2

To SC480 FB (pin 9)

R3

Figure 2

10

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SC480

POWER MANAGEMENT

Application Information

Referencing Figure 2, the equation for setting the output

voltage is:

+5V

+VIN

+

R

2

D1

C2

C1

VOUT (1 ꢀ

) x 1.5

R3

Q1

BST

DH

LX

ILIM

VDDP

DL

L1

Current Limit Circuit

Vout

Current limiting of the SC480 can be accomplished in two

ways. The on-state resistance of the low-side MOSFETs

can be used as the current sensing element, or a sense

resistor in the low-side source can be used if greater ac-

curacy is desired. RDSON sensing is more efﬁcient and

less expensive. In both cases, the R_ILIMresistor between

the ILIM pin and LX sets the over-current threshold. This

resistor R_ILIMis connected to a 10μA current source within

the SC480 which is turned on when the low-side MOSFET

turns on. When the voltage drop across the sense resistor

or low-side MOSFET equals the voltage across the R_ILIMresis-

tor, current limit will activate. The high-side MOSFET will

not be allowed to turn on until the voltage drop across the

sense element (resistor or MOSFET) falls below the voltage

across the R_ILIMresistor.

R1

PGND

D2

+

C3

SC480

Q2

Figure 4

The schematic of RDS_ONsensing circuit is shown in Figure

4 with R_ILIM= R1 and RDS_ONof Q2.

Similarly, for resistor sensing, the current through the lower

MOSFET and the source sense resistor develops a voltage

that opposes the voltage developed across R_ILIM. When the

voltage developed across the R_SENSEresistor reaches voltage

drop across R_ILIM,an over-current exists and the high-side

MOSFET will not be allowed to turn on. The over-current

equation when using an external sense resistor is:

The current sensing circuit actually regulates the inductor

valley current, see Figure 3. This means that if the current

limit is set to 10A, the peak current through the inductor

would be 10A plus the peak ripple current, and the average

current through the inductor would be 10A plus 1/2 the

peak-to-peak ripple current.

R

ILIM

IL

ꢂ

Valley 10ƫA x

ꢃ

OC

R

SENSE

Schematic of resistor sensing circuit is shown in Figure 5

with R_ILIM= R1 and R_SENSE= R4.

I_PEAK

+5V

+VIN

I_LOAD

+

D1

C2

C1

I _LIMIT

Q1

BST

DH

LX

L1

Vout

ILIM

VDDP

DL

PGND

D2

+

C3

SC480

Q2

TIME

Valley Current - Limit Threshold Point

R4

R1

Figure 3

Figure 5

11

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SC480

POWER MANAGEMENT

Application Information (Cont.)

Power Good Output

POR, UVLO and Soft-Start

The VDDQ controller has a power good (PGD) output. An internal power-on reset (POR) occurs when VCCA ex-

Power good is an open-drain output and requires a pull- ceeds 3V, resetting the fault latch and soft-start counter,

up resistor. When the output voltage is +16%/-10% from and preparing the PWM for switching. VCCAunder-voltage

its nominal voltage, PGD gets pulled low. It is held low lockout (UVLO), circuitry inhibits switching and tristates the

until the output voltage returns to within +16%/-10% of drivers until VCCA rises above 4.2V. At this time the circuit

nominal. PGD is also held low during start-up and will not will come out of UVLO and begin switching and the soft-

be allowed to transition high until soft-start is over and the start circuit will progressively limit the output current over

output reaches 90% of its set voltage. There is a 5μs delay a pre-determined time period. The ramp occurs in four

built into the PGD circuit to prevent false transitions.

steps: 25%, 50%, 75% and 100%, thereby limiting the slew

rate of the output voltage. There is 100mV of hysteresis

built into the UVLO circuit and when VCCAfalls to 4.1V the

output drivers are shutdown and tristated.

Output Over-Voltage Protection

When the VDDQ output exceeds 16% of its set voltage,

the low-side MOSFET is latched on. It stays latched and

the SMPS stays off until the EN/PSV input is toggled or

VCCA is recycled. There is a 5μs delay built into the OV

protection circuit to prevent false transitions. During a

VDDQ OV shutdown, VTT is alive until VDDQ falls to typically

0.4V, at which point VTT is tri-stated.

MOSFET Gate Drivers

The DH and DL drivers are optimized for moderate, high-

side, and larger low-side power MOSFETs. An adaptive

dead-time circuit monitors the DL output and prevents the

high-side MOSFET from turning on until DL is fully off, and

conversely, monitors the DH output and prevents the low-

side MOSFET from turning on until DH is fully off. (Note:

be sure there is low resistance and low inductance between the

DH and DL outputs to the gate of each MOSFET.)

When VTT exceeds 12% above its set voltage, the VTT

regulatorwilltristate. Thereisa50μsdelaytopreventfalse

OV trips due to transients or noise. The VDDQ regulator

continues to operate after VTT OV shutdown. The VTT OV

condition is removed by toggling VTTEN or EN/PSV, or by

recycling VCCA.

Design Procedure

Prior to designing a switch mode supply for a notebook com-

puter, the input voltage, load current, switching frequency

and inductor ripple current must be speciﬁed.

Smart Over-Voltage Protection

In some applications, the active loads on VDDQ can

actually leak current into VDDQ. If PSAVE mode is enabled

at very light loading, this leak can cause VDDQ to slowly

rise and reach the OV threshold, causing a hard shutdown.

To prevent this, the SC480 uses Smart OVP to prevent

this. When VDDQ exceeds 8% above nominal, DL drives

high to turn on the low-side MOSFET, which starts to draw

current from VDDQ via the inductor. When VDDQ drops

to the FB trip point, a normal TON switching cycle begins.

This prevents a hard OV shutdown.

Input Voltage Range

The maximum input voltage (VIN_MAX) is determined by the

highest AC adaptor voltage. The minimum input voltage

(VIN_MIN) is determined by the lowest battery voltage after

accounting for voltage drops due to connectors, fuses and

battery selector switches.

Maximum Load Current

There are two values of load current to consider: continu-

ous load current and peak load current. Continuous load

current has more to do with thermal stresses and there-

fore drives the selection of input capacitors, MOSFETs

and commutation diodes. Peak load current determines

instantaneous component stresses and ﬁltering require-

ments such as, inductor saturation, output capacitors and

design of the current limit circuit.

Output Under-Voltage Protection

When VDDQ falls 30% below its set point for eight clock

cycles, the VDDQ output is shut off; the DL/DH drives are

pulled low to tristate the MOSFETS, and the SMPS stays

off until the Enable input is toggled or VCCA is recycled.

When VTT is 12% below its set voltage the VTT output is

tristated. There is a 50μs delay for VTT built into the UV

protection circuits to prevent false transitions.

12

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SC480

POWER MANAGEMENT

Application Information (Cont.)

Switching Frequency

The best way for checking stability is to apply a zero to

Switching frequency determines the trade-off between full load transient and observe the output voltage ripple

size and efﬁ ciency. Higher frequency increases switch- envelope for overshoot and ringing. Over one cycle of

ing losses in the MOSFETs, since losses are a function of ringing after the initial step is a sign that the ESR should

F*VIN2. Knowing the maximum input voltage and budget be increased.

for MOSFET switches usually dictates the ﬁnal design.

+5V

+VIN

Inductor Ripple Current

+

Low inductor values result in smaller size, but create high-

er ripple current and are less efﬁcient because of the high

AC current ﬂowing in the inductor. Higher inductor values

do reduce the ripple current and are more efﬁcient, but

are larger and more costly. The selection of the ripple cur-

rent is based on the maximum output current and tends

to be between 20% to 50% of the maximum load current.

Again, cost, size and efﬁciency all play a part in the selec-

tion process.

D1

C2

C1

Q1

14

13

12

11

10

9

BST

DH

LX

ILIM

VDDP

DL

L1

0.5V - 5.5V

8

R1

R2

R3

C4

10pF

PGND

D2

+

C3

SC480

Q2

FBK

Stability Considerations

Unstable operation shows up in two related but distinctly

different ways: double pulsing and fast-feedback loop in-

stability. Double-pulsing occurs due to noise on the output

or because the ESR is too low, causing insufﬁcient voltage

ramp in the output signal. This causes the error ampliﬁer to

trigger prematurely after the 400ns minimum off-time has

expired. Double-pulsing will result in higher ripple voltage at

the output, but in most cases is harmless. In some cases,

however, double-pulsing can indicate the presence of loop

instability, which is caused by insufﬁcient ESR. One simple

way to solve this problem is to add some trace resistance

in the high current output path. A side effect of doing this

is output voltage droop with load. Another way to eliminate

doubling-pulsing is to add a 10pF capacitor across the

upper feedback resistor divider network. This is shown in

Figure 6, by capacitor C4 in the schematic. This capacitance

should be left out until conﬁrmation that double-pulsing ex-

ists. Adding this capacitance will add a zero in the transfer

function and should eliminate the problem. It is best to

leave a spot on the PCB in case it is needed.

Figure 6

SC480 ESR Requirements

The constant on-time control used in the SC480 regulates

the ripple voltage at the output capacitor. This signal

consists of a term generated by the output ESR of the

capacitor and a term based on the increase in voltage

across the capacitor due to charging and discharging

during the switching cycle. The minimum ESR is set to

generate the required ripple voltage for regulation. For most

applications the minimum ESR ripple voltage is dominated

by PCB layout and the properties of SP or POSCAP type

output capacitors. For applications using ceramic output

capacitors, the absolute minimum ESR must be considered.

If the ESR is low enough the ripple voltage is dominated

by the charging of the output capacitor. This ripple voltage

lags the on-time due to the LC poles and can cause double

pulsing if the phase delay exceeds the off-time of the

converter. Referring to Figure 5 on Page 11, the equation

for the minimum ESR as a function of output capacitance

and switching frequency and duty cycle is:

Loop instability can cause oscillations at the output as a

response to line or load transients. These oscillations can

trip the over-voltage protection latch or cause the output

voltage to fall below the tolerance limit.

Fs - 200000

Fs

§

¨

·

¸

§

¨

©

·

¸

¹

1 ꢀ 3 x

VOUT

1.5V

§

¨

©

·

¸

¹

¨

¸

ESR !

x

2

2 x Ư x Cout xFs x 1 ꢁ D

ꢂ

ꢃ

¨

©

¸

¹

13

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SC480

POWER MANAGEMENT

Application Information (Cont.)

Dropout Performance

of trace resistance between the inductor and output

capacitor. This trace resistance should be optimized

so that at full load the output droops to near the lower

regulation limit. Passive droop minimizes the required

output capacitance because the voltage excursions due

to load steps are reduced.

The output voltage adjust range for continuous-conduction

operation is limited by the ﬁxed 400nS (typical) Minimum

Off-time One-shot. For best dropout performance, use the

slowest on-time setting of 200KHz. When working with

low input voltages, the duty-factor limit must be calculated

using worst-case values for on and off times. The IC duty-

factor limitation is given by:

Board components and layout also inﬂuence DC accuracy.

The use of 1% feedback resistors contributes up to 1%

error. If tighter DC accuracy is required use 0.1% feedback

resistors.

TON(MIN)

DUTY

TON(MIN) ꢀ TOFF(MAX)

The output inductor value may change with current. This

will change the output ripple and thus the DC output

voltage (it will not change the frequency).

Be sure to include inductor resistance and MOSFET on-

state voltage drops when performing worst-case dropout

duty-factor calculations.

Switching frequency variation with load can be minimized

by choosing lower RDS_ONMOSFETs. High RDS_ONMOSFETS

will cause the switching frequency to increase as the load

current increases. This will reduce the ripple and thus

the DC output voltage. This inherent droop should be

considered when deciding if passive droop is required, or

if passive droop is desired in order to further reduce the

output capacitance.

SC480 System DC Accuracy (VDDQ Controller)

Three IC parameters affect VDDQ accuracy: the internal

1.5V reference, the error comparator offset voltage, and

the switching frequency variation with line and load.

The internal 1%, 1.5V reference contains two error

components, a 0.5% DC error and a 0.5% supply and

temperature error. The error comparator offset is trimmed

so that it trips when the feedback pin is nominally 1.5

volts +/-1% at room temperature. The comparator offset

trim compensates for any DC error in the reference. Thus,

the percentage error is the sum of the reference variation

over supply and temperature and the offset in the error

comparator, or 1.5% total.

Output DC Accuracy (VTT Output)

The VTT accuracy compared to VDDQ is determined by

two parameters: the REF output accuracy, and the VTT

output accuracy with respect to REF. The REF output

is generated internally from the VDDQS (sense input),

and tracks VDDQS with 2% accuracy. This REF output

becomes the reference for the VTT regulator. The VTT

regulator then tracks REF within +/-40mV (typically zero).

The total VTT/VDDQ tracking accuracy is then:

The on-time pulse in the SC480 is calculated to give a

pseudo-ﬁxed frequency. Nevertheless, some frequency

variation with line and load can be expected. This variation

changes the output ripple voltage. Because constant on-

time converters regulate to the valley of the output ripple,

½ of the output ripple appears as a DC regulation error.

For example, If the output ripple is 50mV with VIN = 6

volts, then the measured DC output will be 25mV above

the comparator trip point. If the ripple increases to 80mV

with VIN = 25 volts, then the measured DC output will

be 40mV above the comparator trip. The best way to

minimize this effect is to minimize the output ripple.

VDDQS

VTT error

x r 0.02 r 40mV

2

DDR Reference Buffer

The reference buffer is capable of sourcing 10mA. The

reference buffer has a class A output stage and therefore

will not sink signiﬁcant current; there is an internal 50 kΩ

(typical) pulldown to ground. If higher current sinking is

required, an external pulldown resistor should be added.

Make sure that the ground side of this pulldown is tied to

the VTT ground plane near the PGND2 pin.

To compensate for valley regulation it is often desirable

to use passive droop. Take the feedback directly from the

output side of the inductor, incorporating a small amount

14

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SC480

POWER MANAGEMENT

Application Information (Cont.)

For stability, place a 10Ω/1μF series combination from

REF to VSSA. If REF load capacitance exceeds 1μF, place

at least 10Ω in series with the load capacitance to prevent

instability. It is possible to use only one 10Ω resistor, by

connecting the load capacitors in parallel with the 1μF,

and connecting the load REF to the capacitor side of the

10Ω resistor. (See the Typical Application Circuit on Page

1.) Note that this resistor creates an error term when REF

has a DC load. In most applications this is not a concern

since the DC load on REF is negligible.

ª

«

º

V

ꢁ12

3

OUT

ꢁ 9

s

»

t

3.3 x 10

x

ꢂ

R

ꢀ 37 x 10

tON

ꢃ

x

ꢀ 50 x 10

ON_VBAT(MIN)

V

«

¬

»

BAT(MIN)

¼

and,

ª

º

V

OUT

ꢁ 9

s

«

»

t

3.3 x 10

ꢂ

R

ꢀ 37 x 10

tON

ꢀ 50 x 10

ON_VBAT(MAX)

V

«

¬

»

¼

BAT(MAX)

From these values of t_ONwe can calculate the nominal

switching frequency as follows:

V

OUT

f

Hz

SW_VBAT(MIN)

Design Procedure

§

¨

·

¸

V

x t

BAT(MIN) ON_VBAT(MIN)

©

¹

Prior to designing a switching output and making com-

ponent selections, it is necessary to determine the input

voltage range and output voltage speciﬁcations. To dem-

onstrate the procedure, the output for the schematic in

Figure 7 on page 18 will be designed.

and,

V

OUT

f

Hz

SW_VBAT(MAX)

§

¨

·

¸

V

x t

ON_VBAT(MAX)

BAT(MAX)

©

¹

The maximum input voltage (V_BAT(MAX)) is determined by the

highest AC adaptor voltage. The minimum input voltage

(V_BAT(MIN)) is determined by the lowest battery voltage af-

ter accounting for voltage drops due to connectors, fuses

and battery selector switches. For the purposes of this

design example we will use a VBAT range of 8V to 20V to

design VDDQ.

t_ONis generated by a one-shot comparator that samples

V_BATvia R_tON, converting this to a current. This current is

used to charge an internal 3.3pF capacitor to V_OUT. The

equations above reﬂect this along with any internal com-

ponents or delays that inﬂuence t_ON. For our example we

select R_tON= 1MΩ:

Four parameters are needed for the design:

t_{ON_VBAT(MIN)}= 820ns and, t_{ON_VBAT(MAX)}= 358ns

f_{SW_VBAT(MIN)}= 274kHz and f_{SW_VBAT(MAX)}= 251kHz

1. Nominal output voltage, V_OUT. We will use 1.8V with

internal feedback resistors (FB pin tied to VCCA).

2. Static (or DC) tolerance, TOL_ST(we will use +/-2%).

3. Transient tolerance, TOL_TRand size of transient (we

will use +/-8% for a 10A to 5A load release for this

demonstration).

Now that we know t_ONwe can calculate suitable values for

the inductor. To do this we select an acceptable inductor

ripple current. The calculations below assume 50% of I_OUT

which will give us a starting place.

4. Maximum output current, I_OUT(we will design for 10A).

t

ON_VBAT(MIN)

L

ꢂ

V

ꢁ V

ꢃ

x

H

VBAT(MIN)

BAT(MIN) OUT

§

¨

·

¸

0.5 xI

OUT

Switching frequency determines the trade-off between

size and efﬁciency. Increased frequency increases

the switching losses in the MOSFETs, and losses are a

function of VBAT². Knowing the maximum input voltage

and budget for MOSFET switches usually dictates where

the design ends up. The default R_tONvalues of 1MΩ and

715kΩ are suggested only as a starting point.

©

¹

and,

t

ON_VBAT(MAX)

L

ꢂ

V

ꢁ V

OUT

ꢃ

x

H

VBAT (MAX)

BAT(MAX)

§

¨

·

¸

0.5 xI

OUT

©

¹

For our example:

L_VBAT(MIN)= 1.02μH and L_VBAT(MAX)= 1.30μH,

The ﬁrst thing to do is to calculate the on-time, t_ON, at

V_BAT(MIN)and V_BAT(MAX), since this depends only upon V_BAT, V_OUT

and Rt_ON.

15

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SC480

POWER MANAGEMENT

Application Information (Cont.)

We will select an inductor value of 1.5μH to reduce the where ERR_TRis the transient output tolerance. For this

ripple current, which can be calculated as follows:

case, I_TRANSis the load transient of 5A (10A - 5A).

t

For our example:

ON_ VBAT ( MIN )

§

¨

·

¸

I

V

ꢁ V

x

A

RIPPLE_VBAT(MIN)

BAT (MIN)

PꢁP

OUT

©

¹

L

ERR_TR= 144mV and ERR_DC= 18mV, therefore,

R_{ESR_TR(MAX)}= 17.6mΩ for a full 5A load transient.

and,

ON_ VBAT ( MAX )

L

§

·

x

I

V

ꢁ V

A

¨

¸

RIPPLE_VBAT(MAX)

BAT (MAX)

PꢁP

OUT

©

¹

We will select a value of 6mΩ maximum for our design,

which would be achieved by using two 12mΩ output ca-

pacitors in parallel. Now that we know the output ESR we

can calculate the output ripple voltage:

For our example:

_{RIPPLE_VBAT(MIN)}= 3.39A_P-Pand I_{RIPPLE_VBAT(MAX)}= 4.34A_P-P

I

V

R

x I

V

RIPPLE_VBAT(MIN)

RIPPLE_VBAT(MIN) PꢁP

ESR

From this we can calculate the minimum inductor current

rating for normal operation:

and,

I

RIPPLE_VBAT( MAX )

I

ꢀ

A

(MIN)

INDUCTOR ( MIN )

OUT (MAX)

2

V

R

x I

V

RIPPLE_VBAT(MAX)

RIPPLE_VBAT(MAX) PꢁP

ESR

For our example:

_{INDUCTOR(MIN)}= 12.2A_(MIN)

For our example:

I

V_{RIPPLE_VBAT(MAX)}= 20mV_P-Pand V_{RIPPLE_VBAT(MIN)}= 26mV_P-P

Next we will calculate the maximum output capacitor

equivalent series resistance (ESR). This is determined by

calculating the remaining static and transient tolerance

allowances. Then the maximum ESR is the smaller of the

calculated static ESR (R_{ESR_ST(MAX)}) and transient ESR

(R_{ESR_TR(MAX)}):

Note that in order for the device to regulate in a controlled

manner, the ripple content at the feedback pin, V_FB, should

be approximately 15mV_P-Pat minimum V_BAT, and worst case

no smaller than 10mV_P-P. Note that the voltage ripple at

FB is smaller than the voltage ripple at the output capaci-

tor, due to the resistor divider. Also, when using internal

feedback (FB pin tied to 5V or GND), the FB resistor di-

vider is actually inside the IC. If V_{RIPPLE_VBAT(MIN)}as seen at

the FB point is less than 15mV_P-P- whether internal or ex-

ternal FB is used - the above component values should be

revisited in order to improve this. For our example, since

the internal divider reduces the ripple signal by a factor of

(1.5V/1.8V), the internal FB ripple values are then 17mV

and 22mV, which is above the 15mV minimum.

ꢂ

ERR ꢁ ERR

ST

ꢃ

x 2

DC

RIPPLE _ VBAT(MAX)

R

Ohms

ESR_ ST(MAX)

I

Where ERR_STis the static output tolerance and ERR_DCis

the DC error. The DC error will be 1% plus the tolerance

of the internal feedback. (Use 2% for external feedback,

which is 1% plus another 1% for the external resistors.)

For our example:

When using external feedback, and with VDDQ greater

than 1.5V, a small capacitor, C_TOP, can be used in parallel

with the top feedback resistor, R_TOP, in order to ensure that

ripple at VFB is large enough. C_TOPshould not be greater

than 100pF. The value of C_TOPcan be calculated as fol-

lows, where R_BOTis the bottom feedback resistor. Firstly

calculating the value of Z_TOPrequired:

ERR_ST= 36mV and, ERR_DC= 18mV, therefore,

R_{ESR_ST(MAX)}= 8.3mΩ

§

¨

·

¸

ERR ꢁ ERR

TR

DC

©

¹

R

Ohms

ESR_ TR (MAX)

I

§

¨

·

¸

RIPPLE_VBAT( MAX)

2

I

ꢀ

TRANS

¨

©

¸

¹

16

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SC480

POWER MANAGEMENT

Application Information (Cont.)

at its highest. The capacitance required for smaller tran-

sient steps my be calculated by substituting the desired

current for the I_ﬁnalterm. In this case I_ﬁnalis set for 5A.

For our example:

R

BOT

Z

x

ꢂ

V

ꢁ 0.015

RIPPLE_VBAT (MIN)

ꢃ

Ohms

TOP

0.015

Secondly calculating the value of C_TOPrequired to achieve

this:

C_OUT(MIN)= 392μF.

§

¨

©

·

¸

¹

1

We will select 440μF, using two 220μF, 12mΩ capacitors

in parallel.

ꢁ

Z

R

TOP

C

F

TOP

2 x Ư x f

SW_VBAT(MIN)

Next we calculate the RMS input ripple current, which is

largest at the minimum battery voltage:

Since our example uses internal feedback ,this method

cannot be used, however the voltage seen at the internal

FB point is already greater than 15mV.

I

OUT

I

V

x

ꢂ

V

ꢁ V

ꢃ

x

A

RMS

IN (RMS)

OUT

BAT (MIN)

OUT

V

BAT _MIN

Next we need to calculate the minimum output capaci-

tance required to ensure that the output voltage does not

exceed the transient maximum limit, POSLIM_TR, starting

from the actual static maximum, V_{OUT_ST_POS}, when a load

release occurs:

For our example:

I_IN(RMS)= 4.17A_RMS

Input capacitors should be selected with sufﬁcient ripple

current rating for this RMS current, for example a 10μF,

1210 size, 25V ceramic capacitor can handle approxi-

mately 3A_RMS. Refer to manufacturer’s data sheets and

derate appropriately.

V

ꢀ ERR

V

OUT_ST_POS

OUT

DC

For our example:

V

_{OUT_ST_POS}= 1.818V,

Finally, we calculate the current limit resistor value. As de-

scribed in the current limit section, the current limit looks

at the “valley current”, which is the average output cur-

rent minus half the ripple current.

POSLIM

V

x TOL

V

TR

OUT

Where TOL_TRis the transient tolerance. For our example:

POSLIM_TR= 1.944V,

I

RIPPLE_VBAT(MIN)

I

ꢁ

A

VALLEY

OUT

2

The minimum output capacitance is calculated as fol-

lows:

The ripple at low battery voltage is used because we want

to make sure that current limit does not occur under nor-

mal operating conditions.

I

RIPPLE_VBAT(MAX)

I

ꢀ

A

init

OUT(MAX)

2

R

x 1.4

ꢁ6

and,

C

DS (ON)

R

ꢂ

I

x 1.2

VALLEY

ꢃ

x

Ohms

ILIM

10 x10

2

ꢂ

Iinit

ꢃ

ꢁ

ꢂ

Ifinal

ꢃ

L x

F

OUT(MIN)

2

ꢂ

POSLIM

ꢁ V

ꢃ

TR

OUT_ST_POS

For our example:

I_VALLEY= 8.31A, R_DS(ON)= 4mΩ, giving R_ILIM= 5.62kΩ

This calculation assumes the condition of a full-load to no-

load step transient occurring when the inductor current is

17

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SC480

POWER MANAGEMENT

Application Information (Cont.)

Thermal Considerations

Layout Guidelines

The junction temperature of the device may be calculated

as follows:

One (or more) ground planes are recommended to

minimize the effect of switching noise and copper losses,

and maximize heat dissipation. The IC ground reference,

VSSA, should be connected to PGND1 and PGND2 as a

star connection at the thermal pad, which in connects

using 4 vias to the ground plane. All components that are

T_J= T_AMB+ θ_JA

where T_Jis the junction temperature, T_AMBis the ambient

temperature, PD is the total SC480 device dissipation,

:

referenced to VSSA should connect to it directly on the

chip side, and not through the ground plane.

The SC480 device dissipation can be determined using:

VDDQ: The feedback trace must be kept far away from

noise sources such as switching nodes, inductors and

gate drives. Route the feedback trace in a quiet layer if

possible, from the output capacitor back to the chip. Chip

supply decoupling capacitors (VCCA, VDDP) should be

located next to the pins (VCCA/VSSA, VDDP/PGND1) and

connected directly to them on the same side.

PD = VCCA • ICCA + VDDP • IDDP + VTT • |ITT|

The ﬁrst two terms are losses for the analog and gate drive

circuits and generally do not present a thermal problem.

Typical ICCA (VCCA operating current) is roughly 1.5mA,

which creates 7.5mW loss from the 5V VCCA supply. The

VDDP supply current is used to drive the MOSFETs and

can be much higher, on the order of 30mA, which can

create up to 150mW of dissipation.

VTT: Because of the high bandwidth of the VTT regulator,

proper component placement and routing is essential to

prevent unwanted high-frequency oscillations which can

be caused by parasitic inductance and noise. The input

capacitors should be located at the VTT input pins (VTTIN

and PGND2), as close as possible to the chip to minimize

parasitics. Output capacitors should be directly located at

the VTT output pins (VTT and PGND2). The routing of the

feedback signal VTTS is critical. The trace from VTTS (pin

2) should be connected directly to the output capacitor

that is farthest from VTT (pin24); route this signal away

from noise sources such as the VDDQ power train or high-

speed digital signals.

The last term, VTT * |ITT|, is the most signiﬁcant term

from a thermal standpoint. The VTT regulator is a linear

device and will dissipate power proportional to the VTT

current and the voltage drop across the regulator. If VTT

= VDDQ/2, then the voltage drop across the regulator

is always VDDQ2, regardless of whether the regulator is

sinking or sourcing current. In either case the power lost

in the VTT regulator is VTT * |ITT|. The average or long-

term value for ITT should be used.

The thermal resistance of the MLPQ package is affected

by PCB layout and the available ground planes and vias

which conduct heat away. A typical value is 29°C/watt.

The switcher power section should connect directly to the

ground plane(s) using multiple vias as required for current

handling (including the chip power ground connections).

Power components should be placed to minimize loops

and reduce losses. Make all the connections on one side

of the PCB using wide copper ﬁlled areas if possible. Do

not use “minimum” land patterns for power components.

Minimize trace lengths between the gate drivers and the

gates of the MOSFETs to reduce parasitic impedances

(and MOSFET switching losses); the low-side MOSFET is

most critical. Maintain a length to width ratio of <20:1 for

gate drive signals. Use multiple vias as required by current

handling requirement (and to reduce parasitics) if routed

on more than one layer. Current sense connections must

always be made using Kelvin connections to ensure an

Example:

ICCA = 1.5mA

IDDP = 25mA

VCCA = VDDP = 5V

VTT = 1.25V

ITT = 0.75A (average)

Ambient = 45 degrees C

Thermal resistance = 29

P_D= 5V • 0.0015 A + 5V • 0.025A + 0.9V • |0.75|A

P_D= 0.808W

T_J= T_AMB+ P_D• T_JA= 45 + 0.808W • 29°C/W = 68.4°C

18

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SC480

POWER MANAGEMENT

Application Information (Cont.)

accurate signal. The layout can be generally considered Finally, connectingthecontrolandswitcherpowersections

in three parts; the control section referenced to VSSA, the should be accomplished as follows:

VTT output, and the switcher power section.

1. Route VDDQ feedback trace in a “quiet” layer, away

Looking at the control section ﬁrst, locate all components

from noise sources.

referenced to VSSA on the schematic and place these 2. Route DL, DH and LX (low side FET gate drive, high

components at the chip. Connect VSSA using a wide

(>0.020”) trace. Very little current ﬂows in the chip ground

therefore large areas of copper are not needed. Connect

the VSSA pin directly to the thermal pad under the device

as the only connection from PGND1 and PGND2 from

VSSA.

side FET gate drive and phase node) to the chip using

wide traces with multiple vias if using more than one

layer. These connections are to be as short as possible

for loop minimization, with a length to width ratio less

than 20:1 to minimize impedance. DL is the most

critical gate drive, with power ground as its return

path. LX is the noisiest node in the circuit, switching

between VBAT and ground at high frequencies, thus

should be kept as short as practical. DH has LX as its

return path.

Decoupling capacitors for VCCA/VSSA and VDDP/PGND1

should be placed is as close as possible to the chip. The

feedback components connected to FB, along with the

VDDQ sense components, should also be located at the 3. BST is also a noisy node and should be kept as short

chip. The feedback trace from the VDDQ output should as possible.

route from the top of the output capacitors, in a quiet 4. Connect PGND1 pins on the chip directly to the VDDP

layer back to the FB components.

decoupling capacitor and then drop vias directly to

theground plane. Locate the current limit resistor at

the chip with a kelvin connection to the phase node.

Next, looking at the switcher power section, there are a

few key guidelines to follow:

1. There should be a very small input loop, well

decoupled.

2. The phase node should be a large copper pour, but

still compact since this is the noisiest node.

3. Input power ground and output power ground should

not connect directly, but through the ground planes

instead.

19

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SC480

POWER MANAGEMENT

Application Information (Cont.)

D1

C1

0.1uF

5V

VBAT

Q1

IRF7811

C2

10uF/25V

1210

C3

10uF/25V

1210

MBR0530

L1

1.5uH

VDDQ

C4

1uF

Vishay IHLP-5050

Q2

VDDQ

IRF7832

VTT

C8

0.1uF

R1

C5

10uF

0805

C6

10uF

0805

C7

10uF

0805

5.62K

+

C10*

C9*

C11

1

2

3

4

5

6

18

PGND2

VTTS

VSSA

TON

PGND1

ILIM

220uF/12m 220uF/12m

0.1uF

17

*Sanyo 4TPL220MC

U1

16

R2

1MEG

SC480

15

VBAT

5V

VDDP

R3

10R

C12

1uF

14

REF

5V

REF

R4

R5

10R

13

10K

VCCA

PGD

PAD

PGOOD

PAD

C15

1uF

C13

1nF

C14

1uF

EN/PSV

VTT_EN

C16

0.1uF

VDDQ

1.8V fixed: connect to 5V

2.5V fixed: connect to VSSA

Adjustable 1.5V-3.0V: connect to divider network

Figure 7 - Reference Design

20

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SC480

POWER MANAGEMENT

Typical Characteristics

1.8V Efﬁciency vs. Output Current

Powersave Mode

1.8V Efﬁciency vs. Output Current

Continuous Conduction Mode

100%

90%

80%

70%

60%

50%

100%

90%

80%

70%

60%

50%

VBAT = 10

VBAT = 20

0

2

4

6

8

10

0

2

4

6

8

10

I_OUT(A)

2.5V Efﬁciency vs. Output Current

Continuous Conduction Mode

Powersave Mode

100%

90%

80%

70%

60%

50%

100%

90%

80%

70%

60%

50%

VBAT = 10

VBAT = 20

0

2

4

6

8

10

0

2

4

6

8

10

I_OUT(A)

1.5V Efﬁciency vs. Output Current

Powersave Mode

Continuous Conduction Mode

100%

90%

80%

70%

60%

50%

100%

90%

80%

70%

60%

50%

VBAT = 10

VBAT = 20

VBAT = 10

VBAT = 20

0

2

4

6

8

10

0

2

4

6

8

10

I_OUT(A)

21

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SC480

POWER MANAGEMENT

Typical Characteristics (Cont.)

Load Transient Response, 0 to 5A,

Load Transient Response, 0 to 5A, Psave Mode

Continuous Conduction Mode

Load Transient Response, 5 to 0A,

Continuous Conduction Mode

Load Transient Response, 5 to 0A, Psave Mode

Load Transient Response, 5 to 10A

Load Transient Response, 10 to 5A

22

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SC480

POWER MANAGEMENT

Typical Characteristics (Cont.)

VTT Load Transient Response,

1A Sink/Source, Psave Mode

VTT Load Transient Response, 1A Sink/Source,

Continuous Conduction Mode

Startup (PSV), EN/PSV Going High

Startup (PSV), EN/PSV Going Low, VDDQ = 5A

23

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SC480

POWER MANAGEMENT

Outline Drawing - MLPQ 24 (4x4mm)

A

D

B

E

DIMENSIONS

INCHES MILLIMETERS

MIN NOM MAX MIN NOM MAX

DIM

A

.031

.040

0.90 1.00

.035

.001

0.80

A1 .000

.002 0.00 0.02 0.05

-

(.008)

(0.20)

0.25 0.30

A2

b

D

D1

E

PIN 1

INDICATOR

(LASER MARK)

.007

.010 .012 0.18

.151 .157 .163 3.85 4.00 4.15

2.70

.100 .106 .110 2.55

.151 .157 .163 3.85 4.00 4.15

2.70 2.80

2.80

E1 .100

.106 .110 2.55

e

.020 BSC

0.50 BSC

L

.011 .016 .020 0.30 0.40 0.50

N

24

aaa

.004

0.10

A2

bbb

A

SEATING

PLANE

aaa

C

A1

C

D1

LxN

E/2

E1

2

1

N

bxN

bbb

C A B

e

D/2

NOTES:

1.

CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES).

COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS.

2.

24

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SC480

POWER MANAGEMENT

Land Pattern - MLPQ 24 (4x4mm)

K

DIMENSIONS

DIM

INCHES

MILLIMETERS

(.155)

.122

.106

.021

.010

.033

.189

(3.95)

3.10

2.70

0.50

0.25

0.85

4.80

C

G

H

K

P

X

Y

Z

G

Z

(C)

H

X

P

NOTES:

1.

THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY.

CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR

COMPANY'S MANUFACTURING GUIDELINES ARE MET.

Contact Information

Semtech Corporation

Power Management Products Division

200 Flynn Road, Camarillo, CA 93012

Phone: (805) 498-2111 Fax: (805) 498-3804

www.semtech.com

25

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型号：	SC480IMLTRT
厂家：	SEMTECH CORPORATION
描述：	Complete DDR1/2/3 Memory Power Supply 完整的DDR1 / 2/3存储器电源存储双倍数据速率
文件：	总25页 (文件大小：847K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

SC480IMLTRT [SEMTECH]

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