SC4810EIMLTRT [SEMTECH]
High Performance Current Mode PWM Controller with Complementary Output, Programmable Delay; 高性能电流模式PWM控制器，带有互补输出，可编程延迟
| 型号： | SC4810EIMLTRT |
| 厂家： | 
SEMTECH CORPORATION |
| 描述： | High Performance Current Mode PWM Controller with Complementary Output, Programmable Delay |
| 文件： | 总24页 (文件大小：362K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SC4810B/E
High Performance Current Mode PWM Controller
with Complementary Output, Programmable Delay
POWER MANAGEMENT
Description
Features
Operation to 1MHz
Accurate programmable maximum duty cycle
Line voltage monitoring
External frequency synchronization
Bi-phase mode of operation for low ripple
Independent programmable delays
Hiccup mode current limit
Under 250µA start-up current
Programmable maximum volt-second clamp
Accessible reference voltage
The SC4810B/E is a 16 pin BICMOS primary side PWM
controller for use in Isolated DC-DC and off-line switching
power supplies. It is a highly integrated solution, requiring
few external components. It features a high frequency
of operation, accurately programmable maximum duty
cycle, current mode control, line voltage monitoring, supply
UVLO, low start-up current, and programmable soft start
with user accessible reference. It operates in a fixed
frequency, highly desirable for Telecom applications. The
output for switch is complementary to each other with
programmable delay between each transition. The active
technique allows single ended converters beyond 50%
duty cycle and greater flux swing for the power
transformer while reducing voltage stresses on the
switches. The separate sync pin simplifies synchronization
to an external clock. Feeding the oscillator of one device
to the sync of another forces biphase operation which
reduces input ripple and filter size.
VDD undervoltage lockout
-40°C to 105°C operating temperature
16 lead TSSOP or MLPQ lead free packages. Both
fully WEEE and RoHS compliant
Applications
Telecom equipment and power supplies
Networking power supplies
Power over LAN applications
Industrial power supplies
Isolated power supplies
VoIP phones
The SC4810B/E has a turn-on voltage threshold of 7V.
In the SC4810B, OUT2 is inverted to drive the N-MOSFET.
In the SC4810E, OUT2 is non-inverted to drive the
P-MOSFET. These devices are available in a TSSOP-16 or
MLPQ-16 lead package.
Typical Application Circuit
D1
T1
R1
D3
D4
L1
C1
D2
Q1
Vout
C2
+48V
C3
C4
C5
R2
C6
Q2
Q3
C7
U1
R3
R6
T2
SC1302A
R4
D5
C8
R7
C9
R5
2
4
7
U2
C10
R10
6
3
4
5
7
13
15
10
11
16
9
R9
RAMP
OUT2
OUT1
CS
5
SYNC
RCT
R11
SC4810
U3
C11
DMAX
FB
R8
R12
R13
1
2
6
5
DELAY1
DELAY2
VREF
SS
R15
R14
C12
C13
8
R16
R21
C14
C15
Q4
U4
SC431L
R17
R18
R19
R20
R22
R23
C16
Revision: July 27, 2006
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SC4810B/E
POWER MANAGEMENT
Absolute Maximum Ratings
Exceeding the specifications below may result in permanent damage to the device, or device malfunction. Operation outside of the parameters specified
in the Electrical Characteristics section is not implied. Exposure to Absolute Maximum rated conditions for extended periods of time may affect device
reliability.
Parameter
Symbol
VDD
Maximum
Units
V
Supply Voltage
19
Supply Current
IDD
25
mA
V
LUVLO
VLUVLO
10
SS, DMAX, RCT, FB, CS, RAMP, SYNC
Current VREF
-0.3V to VREF + 0.3V
V
IREF
ILUVLO
TSTG
TJ
15
-1
mA
mA
°C
Current LUVLO
Storage Temperature Range
Junction Temperature Range
Lead Temperature (Soldering) 10 Sec.
Peak IR Reflow Temperature 20 - 40 Sec.
-65 to +150
-40 to +150
300
°C
TLEAD
TPKG
°C
260
°C
Electrical Characteristics
Unless specified: VDD = 12V, CSS = 1nF, FOSC = 420kHz, RT = 10k, CT = 220pF, DMAX = 2V, RDELAY = 75kΩ, TA = TJ = -40ºC to 105ºC
Parameter
Test Conditions
Min
Typ
Max
Unit
Supply Section
Supply Voltage
IDD
15
4.5
250
V
VDD = 15V, N
O
L
OAD
3.5
mA
µA
IDD Shutdown
SS = 0V
100
Ramp Section
Ramp Clamp Threshold Voltage
UVLO Section (B/E version)
Start Threshold
Hysteresis
3
V
8
8.4
2
8.8
V
V
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SC4810B/E
POWER MANAGEMENT
Electrical Characteristics (Cont.)
Unless specified: VDD = 12V, CSS = 1nF, FOSC = 420kHz, RT = 10k, CT = 220pF, DMAX = 2V, RDELAY = 75kΩ, TA = TJ = -40ºC to 105ºC
Parameter
Test Conditions
Min
4.85
2.91
Typ
Max
5.15
3.09
Unit
VREF Section
VREF (B/E version)
Line Under Voltage Lockout
Start Threshold
0 - 5mA
5
V
3
V
Hysteresis
150
-100
mV
nA
Input Bias Current(1)
Comparator Section
CS Input Current(1)
LUVLO = 3.2V
-200
75
nA
ns
PWM to OUT Propagation Delay
(No Load)(1)
Current Limit Section
Current Limit Threshold
590
625
75
660
-7.5
mV
ns
(1)
ILIM to OUT Propagation Delay
Soft Start Section
ISS
VSS = 0V
-2.5
500
-5
µA
Shutdown Threshold
Oscillator Section
Frequency Range (2)
RCT Peak Voltage
RCT Valley Voltage
Maximum Duty Cycle
Maximum Duty Cycle
Frequency
mV
50
1100
kHz
V
3.00
0.05
85
V
DMAX = 2.8V, OUT1
DMAX = 1.25V, OUT1
%
29
%
380
2
420
460
kHz
Sync/CLOCK
Clock SYNC Threshold
Minimum Sync Input Pulse Width(1)
Positive Edge Triggered
FSYNC > Fosc
V
50
ns
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SC4810B/E
POWER MANAGEMENT
Electrical Characteristics (Cont.)
Unless specified: VDD = 12V, CSS = 1nF, FOSC = 420kHz, RT = 10k, CT = 220pF, DMAX = 2V, RDELAY = 75kΩ, TA = TJ = -40ºC to 105ºC
Parameter
Test Conditions
Min
Typ
Max
Unit
Output Section (OUT1 and OUT2)
Output VSAT Low
I
OUT = 5mA sinking
IOUT = 5mA sourcing
COUT = 20pF
500
mV
V
Output VSAT High
VREF - 0.6
Rise Time(1)
10
10
ns
ns
Fall Time(1)
COUT = 20pF
Program Delay Section
OUT1 Fall to OUT2 Rise (SC4810B)
OUT2 Fall to OUT1 Rise (SC4810B)
OUT1 Fall to OUT2 Fall (SC4810E)
OUT2 Rise to OUT1 Rise (SC4810E)
120
140
120
140
ns
ns
ns
ns
Notes:
(1) Guaranteed by design.
(2) Guaranteed by characterization.
(3) This device is ESD sensitive. Use of standard ESD handling precautions is required.
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SC4810B/E
POWER MANAGEMENT
Pin Configurations
Ordering Information
Part Number(2)
Package(1)
Temp. Range (TJ)
TOP VIEW
SC4810BITSTRT
SC4810EITSTRT
SC4810BIMLTRT
SC4810EIMLTRT
TSSOP-16
MLPQ-16
VDD
LUVLO
SYNC
RCT
DMAX
RAMP
DELAY 1
DELAY 2
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VREF
OUT1
PGND
OUT2
GND
FB
-40°C to 105°C
Notes:
(1) Only available in tape and reel packaging. A reel
contains 2500 devices for TSSOP and 3000 parts
for MLP package.
(2) Lead free product. This product is fully WEEE and
RoHS compliant.
CS
SS
(16 Pin TSSOP )
TOP VIEW
(16 Pin MLPQ)
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SC4810B/E
POWER MANAGEMENT
Pin Descriptions
Pin #
Pin #
Pin Name
Pin Function
TSSOP
MLPQ
1
15
VDD
The power input connection for this device. This pin is shunt regulated at 17.5V which
is sufficiently below the voltage rating of the DMOS output driver stage. VDD should
be bypassed with a 1µF ceramic capacitor.
2
16
LUVLO
SYNC
Line undervoltage lock out pin. An external resistive divider will program the
undervoltage lock out level. During the LUVLO, the Driver OUT1 is disabled and the
softstart is reset. OUT2 continues with a fixed on time of DELAY 1 + DELAY2
approximately.
3
4
1
2
SYNC is a positive edge triggered input with a threshold set to 2.1V. In the Bi-Phase
operation mode the SYNC pin should be connected to the CT (Timing Capacitor) of
the second controller. This will force a out of phase operation. In a single controller
operation, SYNC could be grounded or connected to an external synchronization clock
with a frequency higher than the on-board oscillator frequency. The external OSC
frequency should be 30% greater for guaranteed SYNC operation.
RCT
The oscillator frequency is configured by connecting resistor RT from VREF to RCT
and capacitor CT from RCT to ground. Using the equation below values for RT and
CT can be selected to provide the desired OUT frequency.
1
F =
VP−K
VREF
− (RT +1k)• CT • ln 1−
where VP-K = RCT peak voltage
5
6
3
4
DMAX
RAMP
Duty cycle up to 95% can be programmed via R18 and R12 (the resistor divider from
Vref in the Application Circuit). When DMAX pin is taken above 3V, 100% duty cycle
is achieved.
A resistor from the RAMP to the input voltage and a capacitor from the RAMP to
GND forms the ramp signal of maximum allowable volt-second product. The RAMP is
discharged to GND when OUT1 is low and allowed to charge when OUT1 is high. A
volt-second comparator compares the ramp signal to 3V to limit the maximum
clamp = 3 • Rramp • Cramp.
allowable volt-second product: Volt-second product
7
8
5
6
DELAY 1 A resistor from these pins to GND programs the non-overlap delay time between
OUT1 and OUT2.
DELAY 2 A resistor from these pins to GND programs the non-overlap delay time between
OUT2 and OUT1.
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SC4810B/E
POWER MANAGEMENT
Pin Descriptions (Cont.)
Pin #
Pin #
Pin Name
Pin Function
TSSOP MLPQ
9
7
SS
This pin serves two functions. The soft start timing capacitor connects to SS and is
charged by an internal 5µA current source. Under normal soft start SS is discharged
to less than 0.65V and then ramps positive to 1V during which time the OUT1 is held
low. As SS charges from 1V to 2.5V, soft start is implemented by an increasing
output duty cycle. If SS is taken below 0.5V, the output driver is inhibited and held low.
The user accessible 4V (A and D) or 5V (B, C and E) voltage reference also goes
low and IDD = 100µA.
10
11
8
9
CS
FB
Current sense input is provided via the CS pin. The current sense input from a sense
resistor provides current feedback to the PWM comparator and current limit signal to
terminate the PWM pulse. When a pulse peak voltage provided at this pin exceeds
600mV, a soft-restart sequence will follow. Slope compensation is derived from the
rising voltage at the timing capacitor and can be buffered with an external small signal
PNP transistor.
This pin is used to generate a reset signal when compared to CS for the PWM
comparator with an offset voltage of 600mV and 1/2 attenuation. The feedback
analog signal from the output of an error amplifier or an opto-coupler will be connected
to this pin to provide regulation.
12
13
10
11
GND
Signal ground for all functions.
OUT2
This pin is the logic level drive output to the external MOSFET driver circuit (similar to
SC1302) for the complementary switch.
14
15
12
13
PGND
OUT1
Ground connection for the gate drivers. Connect PGND and GND at a single point.
This pin is the logic level drive output to the external MOSFET driver circuit (similar to
SC1302) for the main switch.
16
14
VREF
The 5V reference output. This reference is buffered and is available on the VREF pin.
VREF should be bypassed with a 0.47 - 1.0µF ceramic capacitor.
N/A
THERMAL Pad for heatsinking purposes only. Connect to ground plane using multiple vias. Not
PAD connected internally.
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SC4810B/E
POWER MANAGEMENT
Block Diagram
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SC4810B/E
POWER MANAGEMENT
Application Information
Introduction
Circuit Description
The SC4810B/E is a 16 pin BICMOS peak current mode
controlled PWM controller for isolated DC-DC and off-
line switching power supplies. It features a high switching
frequency of operation, programmable limits for both
power transformer voltage-second product and maximum
PWM duty cycle, line under-voltage lockout, auxiliary switch
activation complementary to main power switch drive,
programmable leading-edge delay time between
activation of each switch, multiple protection features
with programmable cycle -by-cycle current limit and hiccup
mode over-current protection plus soft-restart. It
operates in a fixed frequency programmed by external
components. The separate sync pin simplifies
synchronization to an external clock. Feeding the oscillator
of one device to the sync of another forces biphase
operation which reduces input ripple and input and output
filter size.
The schematic of the active clamp forward converter is
illustrated in Figure. 1 below. T4 is the power transformer.
M17 is the N-channel main switching MOSFET and M15
is the auxiliary N-channel MOSFET. C35 is the reset
capacitor for resetting the power transformer’s core. M14
and M16 construct the synchronous rectification circuit.
L2 and C32 and C33 construct the low-pass output
filtering circuit. T6 is the current sensing transformer. R62
is the reset resistor for resetting the magnetic core of
the current sensing transformer. D18 is the rectifying
diode. R63 is the current sensing resistor. R60 and C41
construct the low-pass filtering circuit for the sensed
current signal. The primary bias circuit consists of R55,
R58, D17, Q8, C40, C31, D14 and R51. R55 and R58
construct a voltage divider, which limits the bias voltage
to 6.9V until the line voltage reach 36V. D17 is a zener
diode that limits the bias voltage to under 8V. R51, D14
and C31 construct the peak charge circuit. The peak
charge circuit will provide bias to the PWM IC U9 (SC4810)
and the driver U8 (SC1302A) after the converter starts
The SC4810 can be applied in an active clamp forward
topology with the input voltage ranging from 36V to 72V.
This topology allows the converter to achieve an efficiency
of 92.4% at normal input voltage of 48V.
Figure 1: Active Clamp Forward Converter
1N4148WS
D13
R50
3.3V/30A
T4
10
D14
1N4148WS
M14
R51
1
6
2
5.11
Si4842DY
11
7
C31
5.11
0.1uF
1.3uH
L2
100uF
C32
48V
8
9
C33
680uF
C35
3300pF
8
7
6
5
1
2
3
4
M15
Si4488DY
C34
1u, 100V
4
R53
10K
10K
R52
D15
1N4148WS
R54
20K
M16
Q7
FZT458
C36
0.1uF
Si4842DY
R55
30K
8
7
6
5
1
2
3
4
R56
10K
R57
Q8
FZT458
T5
PE68386
0.1uF
C38
5.11K
C39
0.1uF
C37
0.1uF
D16
R58
8K
1K
R60
D17
open
1N4148WS
D18
open
C40
10uF
P8208T
T6
R59
10
8
7
1
3
R61
1.1M
D19
1N5819HW
R62
10K
330pF
C41
R63
6.8
C42
open
M17
Si4488DY
SC1302A
U8
C43
R65
R66
open
R67
50
R64
165k
100pF
100K
2
4
7
5
U9
R68
1K
C44 220pF
6
13
15
10
11
16
9
RAMP
OUT2
3
4
5
7
8
R69
10K
SYNC
RCT
OUT1
CS
D20
1N5819HW
C45
R70
open
R71
10K
open
SC4810
R72
5.11K
R73
C46
open
DMAX
FB
3.01K
C47
0.01uF
R74
4.3K
U10
100K
R75
DELAY1
DELAY2
VREF
SS
U11
MOC207
SC431
C49
180pF
0.1uF
C48
1
R76
3.01K
6
Q9
FMMT718
R77
18K
5
2
R78
5.6K
1000pF
C50
R79
100K
R80
1.47K
R81
4.7K
R82
C51
5.11K
0.01uF
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SC4810B/E
POWER MANAGEMENT
Application Information (Cont.)
A self-driven configuration was adopted on the secondary
side for driving the synchronous rectification FETs. One
extra winding (Pin8~Pin9) was added at the bottom side
of the power transformer’s secondary side to drive the
freewheeling FET. The forward FET was driven directly
from the top of the power winding. Primary side auxiliary
winding was used to generate primary side bias to improve
the converter’s efficiency.
up so that the total power loss is less. D19, R59, C37,
T5, C36, D15 and R53 construct the driving circuit for
the auxiliary reset switch M15. The secondary side bias
circuit composed of R50, D13 and C38 is regulated to
about 7.5V via a linear regulator composed of R57, Q7
D16 and C39. The feedback of the converter is composed
of U10 (SC431), U11, R73, C47, C45, R72, R76, R70
and C46.
The final configuration of the power transformer is
illustrated as Fig. 2.
SC4810 is the PWM controller which processes the
voltage feedback plus current signal and generates
driving signals to drive the main switch and auxiliary reset
switch. SC1302A is a dual driver IC which is capable of
sourcing 3A peak current. To obtain the best performance,
SC1302A is adopted to drive M17 and M15 in the
Semtech application circuits. SC4810 features dual
complementary driving signals. And SC4810 also provides
adjustable leading-edge delay time for the driving signals,
which helps to achieve zero-voltage switching in active
clamp forward converter. R75 and R79 are the two
resistors available to adjust the delay for the
complementary driving. C50 is the soft-start capacitor.
R61 and R65 construct the voltage divider for the line
under voltage lock out protection. R64 and C44 construct
the circuit for the programmable power transformer
voltage-second production protection limits. This special
protection function provide the voltage-second balance
for the power transformer under different input line
conditions. R78 and R74 also provide an extra maximum
duty cycle protection for the power converter.
2
11
6T(PRI)
1T(SEC)
4
1
10
9
1T(SEC AUX)
2T(PRI AUX)
6
8
1T(SEC)
7
Fig.2 Illustration of the power transformer
PA0944G (PUSLE ENGINEERING)
Power MOSFET Selection
The selection of the switching power MOSFET is based
on the peak & RMS current rating, the total gate charge,
Rds and drain to source voltage rating. In this application,
SI4842 was chosen for the secondary side synchronous
rectification MOSFET. And SI4488 was chosen for the
primary side main switching and reset MOSFET.
The clock signal is generated by C49 and R77. When VDD
of SC4810 hits the threshold voltage, VREF jumps up to
5.0V. VREF charges C49 via R77. C49 will be discharged
via an internal FET whenever the voltage on C49 reaches
3.0V. The selection of C49 and R77 is described in the
“Set Clock Frequency” section on the following page. Q9
works as a buffer between the clock signal and the slope
compensation signal to minimize the interference on the
system clock signal. R80 is a pull-up resistor tied to VREF.
Since SYNC function is not utilized, SYNC pin is grounded
via R71.
Output Filter Design
The output filtering circuit consists of the output inductor
and output capacitors. The design of the output capacitor
usually depends on the specification of the requirement
of the output ripple. Given the worst case output ripple
requirement and peak to peak output current ripple plus
the duty ratio under the different line and load condition,
output capacitance is calculated to meet the output ripple
requirement. After all, ESR and ESL of the output
capacitor under certain switching frequency should also
be considered during the calculation. The value of the
output inductance would affect the peak to peak value
of the output current, which would also influence the
Power Transformer Design
A power transformer with the turns ratio of 6 to 1 was
designed for this application. With the turns ratio of 6:1,
the duty ratio under different input line and load conditions
were calculated to verify feasibility.
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SC4810B/E
POWER MANAGEMENT
Application Information (Cont.)
output voltage ripple. The designer needs to take the
output inductance and output capacitance and the ESL
and ESR of the output capacitor into consideration during
the design.
VRCT
3V
0V
V
PK
t
For this application, one Panasonic power choke output
inductor was selected and three 6.3V, 100uF TDK
ceramic capacitors were adopted in the design.
Fig.4 Voltage Waveform on RCT Pin
As illustrated, the capacitor C is charged via the resistor
R from VREF. Whenever the voltage on the RCT pin
reaches 3V, the capacitor C will be discharged through
an internal FET shorted to ground. When the clock signal
circuit is connected as in Fig.3, the frequency of the clock
signal is defined, as in equation 2.
Selection of the Current Sensing Resistor
The selection of the current sensing resistor is based on
the over-current protection triggering point. SC4810
employs a Hiccup mode over-current protection with an
overcurrent threshold of 600mV. A voltage signal above
600mV on the CS pin will trigger hiccup mode overcurrent
protection. Suppose the over-current protection setpoint
is set to be Iov. The threshold voltage of SC4810 is
Vthreshold. The turns ratio of the power transformer is
Ns/Np. The turns ratio of the current sensing transformer
is Ncs:1. Then the Rsense would be calculated as:
1
F =
........(2)
VP−K
VREF
− (RT +1k)• CT • ln 1−
VREF is the reference voltage of the SC4810, 4V for
SC4810A/D and 5V for SC4810B/C/E.
In this application, to get 600kHz, C = 180pF,
(R + 1k) = 10k ohms and VP-K = 3V.
V
Threshold ×NP ×N
Rsense
=
CS ......(1)
IOV ×NS
Maximum Duty Ratio Limit
Set Clock Frequency
SC4810 features maximum duty ratio limitation for ex-
tra protection. The maximum duty ratio is determined by
the voltage on DMAX pin. As illustrated as in Fig. 5, VDMAX
will be compared with VRCT and DMAX is determined by
the comparison of the two signals.
The SC4810 uses a pair of resistors and capacitors to
generate a triangle signal as the clock signal, as illustrated
in Fig. 3.
VRCT
RCT
VREF
R
C
Fig. 3 Configuration for Clock Signal
The voltage waveform on the RCT pin is illustrated as in
Fig. 4.
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SC4810B/E
POWER MANAGEMENT
Application Information (Cont.)
Voltage waveform on RAMP pin
Clock Signal of SC4810
VRAMP
VRCT
3V
3V
VDMAX
0V
t
t
0V
t
t
OUT1
Maximum OUT1 of SC4810
DMAX
0V
0V
Fig. 6 Illustration of the programmable limits for power
transformer voltage-second product
Fig. 5 Illustration for DMAX
In this application, VDMAX was designed to be 2.8V. So the
DMAX = 90%.
VIN
R
Limit for Power Transformer
Voltage Second Product
The SC4810 also features programmable limits for power
transformer voltage-second product. As illustrated in Fig.
6 and Fig. 7 RAMP pin is charged up via a resistor R from
the input line voltage. The capacitor C will be discharged
via an internal FET shorted to ground and the output
OUT1 will be pulled low whenever the voltage on RAMP
pin hits 3V. By adjusting the values of the resistor R and
the value of the capacitor C, the maximum voltage-sec-
ond product imposed on the power transformer is pre-
set. The maximum voltage-second product limitation helps
prevent saturation of the power transformer.
RAMP
C
Fig. 7 Illustration for Maximum voltage-
second product on the power transformer
The selection of the R and C should consider the maxi-
mum voltage rating of the main switching FET. In this
application, the voltage rating of SI4488 is 150V. Since
Vin*D/(1-D) = 150V, D = 0.8 for low line 36V. So to get
80% at low line, R = 165kOhms and C = 220pF were
selected using volt-second product equation:
3 • Ramp • Cramp.
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SC4810B/E
POWER MANAGEMENT
Application Information (Cont.)
VDD and LUVLO
SC4810 features three different input turn-on voltage
thresholds, as specified in the Electrical Characteristics
on page 2. V starts to regulate when the supply voltage
REF
on the VDD pin is above the turn-on voltage threshold.
V drops to ground when VDD is lower than the turn-on
REF
threshold minus the hysteresis value. The soft start cap
remains grounded as long as LUVLO is below the thresh-
old voltage 3V. The soft start cap will be charged up
through an internal 5uA current source when LUVLO is
above the threshold voltage.
Soft Start
The soft-start function is implemented by charging the
soft-start cap through an internal 5uA current source.
Under normal soft-start, the SS pin is discharged below
0.65V and ramps up to 1V, during which time the output
driving signals OUT1 and OUT2 are held low. During the
time when the SS pin is charged from 1V to 2.5V, soft-
start is implemented by an increasing output duty ratio.
The duty ratio is completely under the control of the
feedback after the SS pin is above 2.5V.
When the SS pin is pulled down below 0.5V, OUT1 and
OUT2 will be held low and the VREF pin will be grounded
via an internal FET.
Complementary Driving with Programmable Delays
The SC4810 features dual driving signals to drive two
power switches complementarily. This feature makes the
SC4810 suitable for a variety of applications in which
dual complimentary driving signals are needed. The
SC4810 even provides programmable driving delay as
an extra feature for applications such as active-clamp
forward topology. The users can program the driving delay
by adjusting the resistors tied to pin DELAY1 and pin
DELAY2 respectively to achieve the optimum delay for
each output. The delay of OUT1 is controlled by the
resistor tied to pin DELAY1 and the delay of OUT2 is
controlled by the resistor tied to pin DELAY2. For
illustration, see Fig. 8.
Over Current Protection
The SC4810 provides Hiccup mode over-current
protection when the sensed current signals are beyond
0.6V. When the hiccup mode over-current protection is
triggered, the soft-start cap will be discharged
immediately by an internal grounded FET. When the soft-
start pin SS is pulled down below 1V, OUT1 and OUT2 will
be disabled, and a soft re-start sequence will follow.
SC4810 can also be configured to implement cycle-by-
cycle over-current limit. As illustrated in Fig. 9, cycle-by-
cycle over-current limitation can be achieved by adjusting
the values of R1 and R2 to limit the voltage of FB pin to
less than the threshold voltage (0.6Volt) of the hiccup
over-current protection, using equations (3) and (4).
13 www.semtech.com
2006 Semtech Corp.
SC4810B/E
POWER MANAGEMENT
Application Information (Cont.)
guaranteed synchronization. SYNC pin should be
grounded if synchronization is unused. (The patent for
the synchronization scheme is pending).
VREF
V
Bias
The synchronous function is illustrated as in Fig. 10.
R3
R1
R2
V
out
FB
Clock Signal of the Master SC4810
VRCT
R4
R5
3V
2.1V
SC431
GND
0V
t
Fig.9 Cycle-by-cycle over-current limitation
OUT1 of the Master SC4810
VFB = 2 • VCS +1.3V........(3)
R2
R1 + R2
VFB = VREF
•
........(4)
0V
t
Synchronization
SC4810 features a special synchronization function
which is leading-edge triggered with a threshold set to
2.1V. Applications like multi-phase interleaving can be
achieved using the SYNC pin. When the SYNC pin is con-
nected to the RCT pin of the master SC4810, the out-
puts of the two SC4810’s will be out of phase. The fre-
quency of the master SC4810 clock signal should be at
least 30% faster than that of the slave SC4810 for the
OUT1 of the Slave SC4810
0V
t
Fig. 10 Illustration for Synchronization
2006 Semtech Corp.
14
www.semtech.com
SC4810B/E
POWER MANAGEMENT
Applications Information (Cont.)
PCB Layout Guidelines
PCB layout is very critical, and the following should be
used to insure proper operation of the SC4810. High
switching currents are present in applications and their
effect on ground plane must be understood and
minimized.
6) The feed back connection between the error ampli-
fier and the FB pin should be kept as short as possible,
and the GND connections should be to the quiet GND
used for the SC4810.
7) If an opto-coupler is used for isolation, quiet primary
and secondary ground planes should be used. The same
precautions should be followed for the primary GND plane
as mentioned in item 5. For the secondary GND plane,
the GND plane method mentioned in item 4 should be
followed.
8) All the noise sensitive components such as VDD by-
pass capacitor, RCT oscillator resistor/capacitor network,
DMAX resistive divider, VREF by pass capacitor, delay
setting resistors, current sensing circuitry and feedback
circuitry should be connected as close as possible to the
SC4810. The GND return should be connected to the
quiet SC4810 GND plane.
9) The connection from the OUT of the SC4810 should
be minimized to avoid any stray inductance. If the layout
can not be optimized due to constraints, a small Schottky
diode may be connected from the OUT pin to the ground
directly at the IC. This will clamp excessive negative volt-
ages at the IC.
1) The high power parts of the circuit should be placed
on a board first. A ground plane should be used. Isolated
or semi-isolated areas of the ground plane may be delib-
erately introduced to constrain ground currents to par-
ticular areas, for example the input capacitor and the
main switch FET ground.
2) The loop formed by the Input Capacitor(s) (Cin), the
main transformer and the main switch FET must be kept
as small as possible. This loop contains all the high fast
transient switching current. Connections should be as
wide and as short as possible to minimize loop induc-
tance. Minimizing this loop area will a) reduce EMI, b)
lower ground injection currents, resulting in electrically
“cleaner” grounds for the rest of the system and c) mini-
mize source ringing, resulting in more reliable gate switch-
ing signals.
3) The connection between FETs and the main trans-
former should be a wide trace or copper region. It should
be as short as practical. Since this connection has fast
voltage transitions, keeping this connection short will
minimize EMI.
10) If the SYNC function is not used, the SYNC pin should
be grounded at the SC4810 GND to avoid noise pick up.
4) The output capacitor(s) (Cout) should be located as
close to the load as possible. Fast transient load cur-
rents are supplied by Cout only. Connections between
Cout and the load must be short, wide copper areas to
minimize inductance and resistance.
5) A 0.1uF to 1uF ceramic capacitor should be directly
connected between VDD and PGND and a 1uF to 4.7uF
ceramic capacitor between VREF and PGND. The SC4810
is best placed over a quiet ground plane area. Avoid pulse
currents in the Cin and the main switch FET loop flowing
in this area. GND should be returned to the ground plane
close to the package and close to the ground side of
(one of) the VDD supply capacitor(s). Under no
circumstances should GND be returned to a ground inside
the Cin and the main switch FET loop. This can be
achieved by making a star connection between the quiet
GND planes that the SC4810 will be connected to and
the noisy high current GND planes connected to the FETs.
2006 Semtech Corp.
15
www.semtech.com
SC4810B/E
POWER MANAGEMENT
SC4810B Evaluation Board - Schematic
8
7
6
5
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
1
2
3
4
4
6
3
1
3
8
1
6
D
V D
D N P G
G N
1
2
1 4
1 2
O L V L U
D
2006 Semtech Corp.
16
www.semtech.com
SC4810B/E
POWER MANAGEMENT
SC4810B Evaluation Board - BOM
Item Quantity
Reference
Part
2.2nF/630V
Package
SM0805
Manufacturer
P/N
1
1
C1
TDK
C3216X7R2J222K
C2,C3,C4,C5,
2
11
C15,C18,C19,
0.1uF
SM0805
C20,C50,C52,C53
3
4
5
6
8
1
3
3
1
1
1
1
2
1
1
1
C6
C7,C8,C9
C10,C11,C12
C13
680uF
100uF
1u,100V
22nF/100V
47uF/16V
180pF
100pF
220pF
1uF
47nF
SM/CT_7343_12
SM/C_1812
SM/C_1210
SM1206
SM/CT_7343
SM0805
Sanyo
TDK
TDK
TDK
Sanyo
4TPB680M
C4532X5ROJ107MT
C3225X7R2A105K
C3216X7R2J223M
16TQC47M
C16
C17
C21
9
10
11
12
13
14
SM0805
SM0805
SM0805
SM0805
C25,C22
C24
C26
C27
0(short)
SM0805
D1,D2,D5,
D6,D7,D10,D21
15
7
1N4148WS
SOD123
Vishay
1N4148WS
16
17
18
19
20
22
23
24
25
26
27
28
29
30
31
1
2
2
1
1
4
2
3
1
3
1
1
1
4
1
D3
D4,D8
D9,D11
D20
MMSZ4702(15V)
MMSZ4698(11V)
SL04
MMSZ4697(10V)
1.3uH
SOD123
SOD123
SOD123
SOD123
PCC-S1
SO-8
SO-8
SOT-23
SOT-23
SOT-23
On Semi
On Semi
Vishay
On Semi
Panasonic
Vishay
Vishay
Vishay
Zetex
MMSZ4702T1
MMSZ4698T1
SL04
MMSZ4697T1
ETQPAF1R3EFA
Si4842DY
Si4488DY
SI2308
L1
M3,M4,M8,M10
M5,M13
M7,M9,M14
Q1
Si4842DY
Si4488DY
SI2308
FMMT618
FMMT718
FZT853
FMMT493
5.11
5.1K
5.11K
FMMT618
FMMT718
FZT853
Q2,Q5,Q6
Q3
Zetex
Zetex
Zetex
SM/SOT223_BCEC
SOT-23
Q10
R1
FMMT493
SM0805
SM0805
SM0805
R2,R12,R25,R32
R3
R8,R9,R10,R19,
R28,R30,R35,R43,R63
32
9
10K
SM0805
33
34
35
1
1
3
R13
R16
R17,R18,R34
open
1K
1K
SM1206
RC0805
SM0805
2006 Semtech Corp.
17
www.semtech.com
SC4810B/E
POWER MANAGEMENT
SC4810B Evaluation Board - BOM
(Cont.)
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
53
54
55
56
57
58
59
1
1
1
1
1
1
2
2
1
1
1
1
1
3
1
1
1
1
1
1
1
1
2
R20
R21
8.2
1.1M
10
160K
100K
6.34K
7.5K
100K
1.47K
15.8K
2.4K
SM0805
SM0805
SM0805
SM0805
SM0805
SM0805
SM0805
SM0805
SM0805
SM0805
SM0805
SM0805
SM0805
SM0805
SM0805
SM0805
PA0646
PE68386
P8208
R22
R23
R24
R29
R31,R36
R33,R37
R38
R40
R42
R44
R52
1.5K
51
5.1
200K
R54,R56,R57
R61
R62
T1
T2
T3
U1
U2
U3
U4,U6
4.75K
PA0944G
PE68386
P8208T
MOCD207
SC1302A
SC4810
SC431
Pulse
Pulse
Pulse
PA0944G
PE68386
P8208T
SO-8
Fairchild
Semtech
Semtech
Semtech
MOCD207
SC1302A
SC4810
SC431
MSOP-8
TSSOP16
SOT-23
2006 Semtech Corp.
18
www.semtech.com
SC4810B/E
POWER MANAGEMENT
SC4810E Evaluation Board - Schematic
8
7
6
5
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
1
2
3
4
3
8
1
6
D
V D
D N P G
1
2
1 4
1 2
O L V L U
D
G N
2006 Semtech Corp.
19
www.semtech.com
SC4810B/E
POWER MANAGEMENT
SC4810E Evaluation Board - BOM
Item Quantity
Reference
Part
2.2nF/630V
Package
SM0805
Manufacturer
P/N
1
1
C1
TDK
C3216X7R2J222K
C2,C3,C4,C5,C18,
2
10
0.1uF
SM0805
C19,C20,C50,C52,C53
3
1
3
3
1
1
1
1
2
1
1
1
5
1
2
3
1
1
4
1
3
1
1
1
2
1
1
4
1
C6
C7,C8,C9
C10,C11,C12
C13
680uF
100uF
SM/CT_7343
SM/C_1812
SM/C_1210
SM1206
SM/CT_7343
SM0805
SM0805
SM0805
SM0805
SM0805
SM0805
SOD123
SOD123
SOD123
SOD123
SOD123
PCC-S1
SO-8
Sanyo
TDK
4TPB680M
C4532X5ROJ107MT
C3225X7R2A105K
C3216X7R2J223M
16TQC47M
4
5
1u,100V
22nF/100V
47uF/16V
180pF
TDK
6
TDK
Sanyo
8
C16
9
C17
10
11
12
13
14
15
16
17
18
19
20
22
23
24
25
26
27
28
29
30
31
32
C21
100pF
C25,C22
C24
220pF
1uF
C26
C27
47nF
0(short)
D1,D2,D5,D10,D21
D3
1N4148WS
MMSZ4702(15V)
MMSZ4698(11V)
SL04
Vishay
On Semi
On Semi
Vishay
On Semi
Panasonic
Vishay
I. R.
1N4148WS
MMSZ4702T1
MMSZ4698T1
SL04
D4,D8
D6,D9,D11
D20
MMSZ4697(10V)
1.3uH
MMSZ4697T1
ETQPAF1R3EFA
Si4842DY
IRF6216
L1
M3,M4,M8,M10
Si4842DY
IRF6216
SI2308
Si4488DY
FMMT618
FZT853
FMMT718
FMMT493
5.11
M5
SO-8
M7,M9,M14
SOT-23
Vishay
Vishay
Zetex
SI2308
M13
SO-8
Si4488DY
FMMT618
FZT853
Q1
SOT-23
Q3
SM/SOT223
SOT-23
Zetex
Q5,Q6
Zetex
FMMT718
FMMT493
Q10
SOT-23
Zetex
R1
R2,R12,R25,R32
R3
SM0805
SM0805
SM0805
5.1K
5.11K
R8,R9,R10,R19,
R28,R30,R35,R43,R63
R16
33
35
9
1
10K
1K
SM0805
SM0805
2006 Semtech Corp.
20
www.semtech.com
SC4810B/E
POWER MANAGEMENT
SC4810E Evaluation Board - BOM
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
54
55
56
57
58
59
3
1
1
1
1
1
1
2
2
1
1
1
1
1
3
1
1
1
1
1
1
1
2
R17,R18,R34
R20
1K
8.2
SM0805
SM0805
SM0805
SM0805
SM0805
SM0805
SM0805
SM0805
SM0805
SM0805
SM0805
SM0805
SM0805
SM0805
SM0805
SM0805
SM0805
PA0646
P8208
R21
1.1M
R22
2
R23
160K
R24
100K
R29
6.34K
7.5K
R31,R36
R33,R37
R38
80.6K
1.47K
15.8K
2.4K
R40
R42
R44
1.5K
R52
51
R54,R56,57
R61
5.1
200K
R62
4.75K
PA0944G
P8208T
MOCD207
SC1302A
SC4810
SC431
T1
Pulse
PA0944G
P8208T
MOCD207
SC1302A
SC4810
SC431
T3
Pulse
U1
SO-8
Fairchild
Semtech
Semtech
Semtech
U2
MSOP-8
TSSOP16
SOT-23
U3
U4,U6
2006 Semtech Corp.
21
www.semtech.com
SC4810B/E
POWER MANAGEMENT
Outline Drawing - TSSOP-16
DIMENSIONS
INCHES MILLIMETERS
A
DIM
A
D
E
MIN NOM MAX MIN NOM MAX
e
-
-
-
-
-
-
-
-
-
-
-
-
.047
1.20
0.15
1.05
0.30
0.20
N
A1 .002
.006 0.05
.042 0.80
.012 0.19
.007 0.09
.031
.007
.003
A2
b
2X E/2
c
E1
D
.192 .196 .201 4.90 5.00 5.10
E1 .169 .173 .177 4.30 4.40 4.50
PIN 1
E
.252 BSC
.026 BSC
6.40 BSC
0.65 BSC
INDICATOR
e
L
L1
N
.018 .024 .030 0.45 0.60 0.75
(.039)
(1.0)
3
1 2
ccc C
2X N/2 TIPS
e/2
16
16
-
-
01
aaa
0°
8°
0°
8°
B
.004
.004
.008
0.10
0.10
0.20
bbb
ccc
D
aaa C
A2
A
SEATING
PLANE
H
C
A1
bxN
c
bbb
C A-B D
GAGE
PLANE
0.25
L
(L1)
01
DETAIL A
SEE DETAIL A
SIDE VIEW
NOTES:
1. CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES).
2. DATUMS AND TO BE DETERMINED AT DATUM PLANE
-A-
-B-
-H-
DIMENSIONS "E1" AND "D" DO NOT INCLUDE MOLD FLASH, PROTRUSIONS
OR GATE BURRS.
3.
4. REFERENCE JEDEC STD MO-153, VARIATION AB.
Land Pattern - TSSOP-16
X
DIMENSIONS
DIM
INCHES
MILLIMETERS
(.222)
.161
.026
.016
.061
.283
(5.65)
4.10
0.65
0.40
1.55
7.20
C
G
P
X
Y
Z
(C)
G
Y
Z
P
NOTES:
1.
THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY.
CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR
COMPANY'S MANUFACTURING GUIDELINES ARE MET.
2006 Semtech Corp.
22
www.semtech.com
SC4810B/E
POWER MANAGEMENT
Outline Drawing - MLPQ-16, 4 x 4
DIMENSIONS
INCHES MILLIMETERS
DIM
A
MIN NOM MAX MIN NOM MAX
A
D
-
-
-
-
.031
A1 .000
.040 0.80
.002 0.00
1.00
0.05
-
B
E
-
(.008)
-
-
(0.20)
A2
b
D
.010 .012 .014 0.25 0.30 0.35
.153 .157 .161 3.90 4.00 4.10
PIN 1
INDICATOR
D1 .100 .106 .110 2.55 2.70 2.80
E
.153 .157 .161 3.90 4.00 4.10
(LASER MARK)
E1 .100 .106 .110 2.55 2.70 2.80
e
.026 BSC
0.65 BSC
L
N
.012 .016 .020 0.30 0.40 0.50
16
.003
.004
16
0.08
0.10
aaa
bbb
A2
A
SEATING
PLANE
aaa C
A1
C
D1
e/2
LxN
E/2
E1
2
1
N
e
bxN
bbb
C A B
D/2
NOTES:
1. CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES).
2. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS.
2006 Semtech Corp.
23
www.semtech.com
SC4810B/E
POWER MANAGEMENT
Land Pattern - MLPQ-16, 4 x 4
K
DIMENSIONS
INCHES MILLIMETERS
DIM
(.156)
.122
.106
.106
.026
.016
.033
.189
(3.95)
3.10
2.70
2.70
0.65
0.40
0.85
4.80
C
G
H
K
P
X
Y
Z
2x Z
H
2x G
Y
2x (C)
X
P
NOTES:
1.
THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY.
CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR
COMPANY'S MANUFACTURING GUIDELINES ARE MET.
Contact Information
Semtech Corporation
Power Management Products Division
200 Flynn Road, Camarillo, CA 93012
Phone: (805)498-2111 FAX (805)498-3804
2006 Semtech Corp.
24
www.semtech.com
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