SC486 [SEMTECH]
Complete DDR1/2/3 Memory Power Supply; 完整的DDR1 / 2/3存储器电源
| 型号： | SC486 |
| 厂家： | 
SEMTECH CORPORATION |
| 描述： | Complete DDR1/2/3 Memory Power Supply |
| 文件： | 总26页 (文件大小：369K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SC486
Complete DDR1/2/3
Memory Power Supply
POWER MANAGEMENT
Description
Features
The SC486 is a combination switching regulator and linear
source/sink regulator intended for DDR1/2/3 memory
systems. The switching regulator is used to generate the
supply voltage, VDDQ, for the memory system. It is a
pseudo-fixed frequency constant on-time controller
designed for high efficiency, superior DC accuracy, and
fast transient response. The linear source/sink regulator
is used to generate the memory termination voltage, VTT,
with the ability to source and sink a 3A peak current.
For the VDDQ regulator, the switching frequency is
constant until a step in load or line voltage occurs at
which time the pulse density, i.e. frequency, will increase
or decrease to counter the transient change in output or
input voltage. After the transient, the frequency will return
to steady-state operation. At lighter loads, the selectable
Power-Save Mode enables the PWM converter to reduce
its switching frequency and improve efficiency. The
integrated gate drivers feature adaptive shoot-through
protection and soft-switching.
For the VTT regulator, the output voltage tracks VREF,
which is ½ VDDQ to provide an accurate termination
voltage. The VTT output is generated from a 1.2V to VDDQ
input by a linear source/sink regulator which is designed
for high DC accuracy, fast transient response, and low
external component count. Additional features include
cycle-by-cycle current limiting, digital soft-start, power
good (all VDDQ only) and over-voltage and under-voltage
DDR1, DDR2 and DDR3 compatible
Constant on-time controller for fast dynamic
response on VDDQ
Programmable VDDQ range - 1.5V to 3V
1% Internal Reference (2% System Accuracy)
Resistor programmable on time for VDDQ
VCCA/VDDP range = 4.5V to 5.5V
VBAT range = 2.5V to 25V
VDDQ DC current sense using low-side RDS(ON)
sensing or external RSENSE in series with low-side
FET
Cycle-by-cycle current limit for VDDQ
Digital soft-start for VDDQ
Combined EN and PSAVE pin for VDDQ
Over-voltage/under-voltage fault protection for
both outputs and PGD output (VDDQ only)
Separate VCCA and VDDP supplies
VTT/REF range = 0.75V – 1.5V
VTT source/sink 3A peak
Internal resistor divider for VTT/REF
VTT is high impedance in S3
VDDQ, VTT and REF are actively discharged in
S4/S5
24-pin MLPQ (4 x 4mm) Lead-free package, fully
WEEE and RoHS compliant
protection (VDDQ and VTT). All 3 outputs (VDDQ, VTT and Applications
REF) are actively discharged when VDDQ is disabled,
reducing external component count and cost. The SC486
is available in a 24 pin MLPQ 4mmx4mm Lead-free
package.
Notebook computers
CPU I/O supplies
Handheld terminals and PDAs
LCD monitors
Typical Application Circuit
Network power supplies
VBAT 5VSUS 5VRUN
5VSUS
VBAT
R3 470k
R1
R2
U1
SC486
PGD
10R
11
3
7
1
PGOOD
VTTEN
R4 10R
VDDQ
VDDQS
TON
C2
D1
EN/PSV
C1
2
R5
1uF
no-pop
6
FB
8
5
6
REF
REF
R7 10R
C5
9
24
COMP
BST
R6
C3
C4
10uF
10R
no-pop
R8 0R
10
5
0.1uF
VTTS
23
21
22
4
3
8
DH
ILIM
LX
R9
R10
VCCA
C6
C7
C8
C9
L1
1uF
no-pop
1nF
1uF
4
7
VDDQ
C10
VSSA
14
15
VTT
VTT
+
VTT
19
20
2
DL
12
13
VDDQ
VTTIN
VTTIN
VDDP
C11
C12
1uF
C13
1uF
Q1
1
16
17
PGND2
PGND2
20uF
18
PGND1
Revision: September 13, 2006
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SC486
POWER MANAGEMENT
Absolute Maximum Ratings (10)
Exceeding the specifications below may result in permanent damage to the device, or device malfunction. Operation outside of the parameters
specified in the Electrical Characteristics section is not implied. Exposure to Absolute Maximum rated conditions for extended periods of time may
affect device reliability.
Parameter
Symbol
Maximum
-0.3 to +25.0
-0.3 to +30.0
-2.0 to +25.0
-0.3 to +6.0
-0.3 to +6.0
-0.3 to +6.0
-0.3 to +6.0
-0.3 to +6.0
Units
TON to VSSA
V
V
V
V
V
V
V
V
DH, BST to PGND1
LX to PGND1
DL, ILIM, VDDP to PGND1
VDDP to DL
VTTIN, VTT to PGND2
VTTIN to VTT
COMP, EN/PSV, FB, PGD, REF, VCCA, VDDQS, VTTEN,
VTTS TO VSSA
VCCA to COMP, EN/PSV, FB, REF, VDDQS, VTT, VTTEN,
VTTIN, VTTS
-0.3 to +6.0
V
PGND1 to PGND2, PGND1 to VSSA
BST, DH to LX
-0.3 to +0.3
-0.3 to +6.0
29
V
V
Thermal Resistance Junction to Ambient
Operating Junction Temperature Range
Storage Temperature Range
°C/W
°C
θJA
TJ
-40 to +150
-65 to +150
260
TSTG
TPKG
°C
Peak IR Reflow Temperature, 10s - 40s
°C
Electrical Characteristics
Test Conditions: VBAT = 15V, VCCA = VDDP = VTTEN = EN/PSV = 5V, VDDQ = VTTIN = 1.8V, RTON = 1MΩ
Parameter
Conditions
25°C
Typ
-40°C to 125°C Units
Min
Max
Min
Max
Input Supplies
VCCA Operating Current
FB > regulation point, IVDDQ = 0A
1500
1000
2500
µA
µA
VCCA Operating Current, S3
FB > regulation point, I
VTTEN = 0VVDDQ
= 0A,
VDDP Operating Current
TON Operating Current
VTTIN Operating Current
FB > regulation point, IVDDQ = 0A
RTON = 1MΩ
70
15
1
150
µA
µA
µA
µA
IVTT = 0A
5
VCCA + VDDP + TON
Shutdown Current
EN/PSV = VTTEN = 0V
5
11
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SC486
POWER MANAGEMENT
Electrical Characteristics (Cont.)
Test Conditions: VBAT = 15V, VCCA = VDDP = VTTEN = EN/PSV = 5V, VDDQ = VTTIN = 1.8V, RTON = 1MΩ
Parameter
Conditions
25°C
Typ
-40°C to 125°C Units
Min
Max
Min
Max
VDDQ Controller
FB Error Comparator Threshold(1)
On-Time
VCCA = 4.5V to 5.5V
1.500
460
1.485 1.515
V
RTON = 1MΩ
390
225
225
530
305
320
550
R
TON = 500kΩ, -10°C ≤ TA ≤ 125°C
TON = 500kΩ, -40°C ≤ TA ≤ 125°C
265
ns
R
Minimum Off-Time
400
150
22
ns
kΩ
Ω
VDDQS Input Resistance
VDDQS Shutdown
EN/PSV = GND
Discharge Resistance
FB Leakage Current
VTT Controller
-1.0
1.0
1.0
µA
COMP Leakage Current
REF Source Current
REF Output Accuracy
-1.0
10
µA
mA
mV
Ω
I
REF = 0 to 10mA
900
22
882
918
REF Shutdown
EN/PSV = GND
Discharge Resistance
VTT Output Accuracy
-2A < IVTT < 2A
REF
22
-20
+20
1.0
mV
VTT Shutdown
EN/PSV = GND
Ω
Discharge Resistance
VTTS Leakage Current
Current Sensing
-1.0
µA
ILIM Current
10
5
9
11
10
µA
mV
mV
Current Comparator Offset
Zero-Crossing Threshold
VDDQ Fault Protection
Current Limit (Positive)(2)
PGND1 - ILIM
-10
PGND1 - LX, EN/PSV = 5V
PGND1 - LX, RILIM = 5kΩ
PGND1 - LX, RILIM = 10kΩ
PGND1 - LX, RILIM = 20kΩ
PGND1 - LX
50
100
200
-125
-30
8
35
80
65
120
230
-90
-25
mV
170
-160
-35
Current Limit (Negative)
Output Under Voltage Fault
Under Voltage Fault Delay
mV
%
clks(3)
With respect to internal reference
FB forced below UV Vth
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SC486
POWER MANAGEMENT
Electrical Characteristics (Cont.)
Test Conditions: VBAT = 15V, VCCA = VDDP = VTTEN = EN/PSV = 5V, VDDQ = VTTIN = 1.8V, RTON = 1MΩ
Parameter
Conditions
25°C
-40°C to 125°C Units
Min Typ Max
Min
Max
VDDQ Fault Protection (Cont.)
Under Voltage Blank Time
Output Over Voltage Fault
Over Voltage Fault Delay
PGD Low Output Voltage
PGD Leakage Current
PGD UV Threshold
From EN high
440
+16
5
clks(3)
%
With respect to internal reference
FB forced above OV Vth
Sink 1mA
+12
+20
µs
V
0.4
1
FB in regulation, PGD = 5V
With respect to internal reference
FB forced outside PGD window
Falling edge, hysteresis 100mV
µA
%
-10
5
-12
3.7
-8
PGD Fault Delay
µs
V
VCCA Under Voltage
VTT Fault Protection
Output Under Voltage Fault
Output Over Voltage Fault
Fault Shutdown Delay
Thermal Shutdown (4)(5)
Inputs/Outputs
4.0
4.3
VTT w/rt REF
VTT w/rt REF
-12
+12
50
-16
+8
-8
%
%
+16
VTT outside UV/OV window
µs
°C
160
150
170
Logic Input Low Voltage
EN & PSV low
VTTEN low
1.2
0.6
V
V
Logic Input High Voltage
EN high, PSV low
VTTEN high
EN high, PSV high
Sourcing
2.0
2.4
3.1
Logic Input High Voltage
EN/PSV Input Resistance
V
1.5
1.0
MΩ
Sinking
Soft Start
VDDQ Soft Start Ramp Time
VTT Soft Start Ramp Rate (6)
Gate Drives
EN/PSV high to PGD high
440
6
clks(3)
mV/µs
Shoot-thru Protection Delay (4)(7)
DH or DL rising
DL low
30
0.8
3.1
ns
Ω
A
DL Pull-Down Resistance
1.6
DL Sink Current
VDL = 2.5V
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SC486
POWER MANAGEMENT
Electrical Characteristics (Cont.)
Test Conditions: VBAT = 15V, VCCA = VDDP = VTTEN = EN/PSV = 5V, VDDQ = VTTIN = 1.8V, RTON = 1MΩ
Parameter
Conditions
25°C
-40°C to 125°C Units
Min Typ Max
Min
Max
Gate Drives (Cont.)
DL Pull-Up Resistance
DL Source Current
DL high
2
1.3
2
4
Ω
A
Ω
Ω
A
V
DL = 2.5V
DH Pull-Down Resistance
DH Pull-Up Resistance(8)
DH Sink/Source Current
VTT Pull-Up Resistance
VTT Pull-Down Resistance
DH low, BST - LX = 5V
DH high, BST - LX = 5V
4
4
2
V
DH = 2.5V
1.3
0.25
0.25
3.6
VTTS < REF
VTTS > REF
0.45
0.45
Ω
Ω
A
VTT Peak Sink/Source Current (9)
2.0
Notes:
(1) The output voltage will have a DC regulation level higher than the error-comparator threshold by 50% of the
ripple voltage.
(2) Using a current sense resistor, this measurement relates to PGND1 minus the voltage of the source on the
low-side MOSFET.
(3) clks = switching cycles, consisting of one high side and one low side gate pulse.
(4) Guaranteed by design.
(5) Thermal shutdown latches both outputs (VTT and VDDQ) off, requiring VCCA or EN/PSV cycling to reset.
(6) VTT soft start ramp rate is 6mV/µs typical unless VDDQ/2 ramp rate is slower. If this is true, VTT soft start
ramps at 6mV/µs (typ.) until it reaches VDDQ/2, and then tracks it.
(7) See Shoot-Through Delay Timing Diagram below.
(8) Semtech’s SmartDriver™ FET drive first pulls DH high with a pull-up resistance of 10Ω (typ.) until LX = 1.5V
(typ.). At this point, an additional pull-up device is activated, reducing the resistance to 2Ω (typ.). This negates the
need for an external gate or boost resistor.
(9) Provided operation below TJ(MAX) is maintained.
(10) This device is ESD sensitive. Use of standard ESD handling precautions is required.
Shoot-Through Delay Timing Diagram
LX
DH
DL
DL
tplhDL
tplhDH
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SC486
POWER MANAGEMENT
Pin Configuration
Ordering Information
PACKAGE(1)
Top View
DEVICE
SC486IMLTRT(2)
SC486EVB
MLPQ-24
Evaluation Board
Note:
(1) Only available in tape and reel packaging. A reel
contains 3000 devices.
(2) Lead-free product. This product is fully WEEE and
RoHS compliant.
(MLPQ-24)
Pin Descriptions
Pin # Pin Name
Pin Function
1
EN/PSV
Enable/Power Save input pin. Tie to ground to disable VDDQ. Tie to +5V to enable VDDQ and
activate PSAVE mode. Float to enable VDDQ and activate continous conduction mode. If floated,
bypass to VSSA with a 10nF capacitor.
2
3
4
TON
VDDQS
VSSA
This pin is used to sense VBAT through a pullup resistor, RTON, and set the top MOSFET on-
time. Bypass this pin with a 1nF capacitor to VSSA.
Sense pin for VDDQ. Used to set the on-time for the top MOSFET and also to set VREF/VTT. Use
a 10Ω/1µF RC filter from VDDQ to VSSA.
Ground reference for analog circuitry. Connect directly to R9, C6, C7, C8, and C9 (see Page 1) on
same side of PCB as I.C. Connect to thermal pad.
5
6
VCCA
FB
Supply voltage input for the analog supply. Use a 10Ω/1µF RC filter from 5VSUS to VSSA.
Feedback input for VDDQ. Connect to a resistor divider from the output to VSSA to set the output
voltage between 1.5V and VCCA.
7
8
PGD
REF
Power good output for VDDQ. PGD is low if VDDQ is outside the power good thresholds. This pin
is an open drain NMOS output and requires an external pull-up resistor.
Reference output. An internal resistor divider from VDDQS sets this voltage to 50% VDDQ
(nominal). Bypass this pin with a series 10Ω/1µF to VSSA. The connection to R6 (see Page 1)
should be made close to pin 8.
9
COMP
VTTS
Error amplifier compensation for VTT output.
Sense pin for VTT. Connect to VTT at the load.
10
11
VTTEN
Enable pin for VTT. Pull this pin low to disable VTT (VREF remains present as long as VDDQ is
present).
12,13
VTTIN
Input supply for the high side switch for VTT regulator. Decouple this pin with a 1µF capacitor to
PGND2.
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SC486
POWER MANAGEMENT
Pin Descriptions (Cont)
14,15
VTT
Output of the linear regulator. Decouple with two (minimum) 10µF ceramic capacitors to PGND2,
locating them directly across pins 14, 15, 16, and 17.
16,17
18
PGND2
PGND1
DL
Power ground for VTT output. Connect to thermal pad and ground plane.
Power ground for VDDQ output. Connect to thermal pad and ground plane.
Gate drive output for the low side MOSFET switch.
19
20
VDDP
ILIM
+5V supply voltage input for the VDDQ gate drivers.
21
Current limit input pin. Connect to drain of low-side MOSFET for RDS(on) sensing or the source
for resistor sensing through a threshold sensing resistor.
22
23
24
-
LX
DH
Phase node - the junction between the top and bottom FETs and the output inductor.
Gate drive output for the high side MOSFET switch.
BST
Boost capacitor connection for the high side gate drive.
THERMAL Pad for heatsinking purposes. Connect to ground plane using multiple vias. Not connected
PAD internally.
Marking Information
Top View
Part Number
yyww = Date Code (Example: 0012)
xxxxx = Semtech Lot No. (Example: E9010
xxx
1-1)
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SC486
POWER MANAGEMENT
Block Diagram
Figure 1 - SC486 Block Diagram
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SC486
POWER MANAGEMENT
Enable Control Logic
Enable Pin Status
Output Status
EN/PSV (1)
VTTEN
VDDQ
OFF, Discharged (2)(3)
OFF, Discharged (2)(3)
ON
VTT
REF
0
0
1
1
0
1
0
1
OFF, Discharged (2)
OFF, Discharged (2)
OFF, High Impedance
ON
OFF, Discharged (2)
OFF, Discharged (2)
ON
ON
ON
Notes:
(1) EN/PSV = 1 = EN/PSV high or floating.
(2) Discharge resistance = 22Ω typ.
(3) VDDQ is discharged via R4 (see Page 1) so this resistance must be added when calculating discharge times.
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SC486
POWER MANAGEMENT
Application Information
+5V Bias Supply
On-Time One-Shot (tON)
The SC486 requires an external +5V bias supply in The on-time one-shot comparator has two inputs. One
addition to the battery. This is connected to VDDP for input looks at the output voltage, while the other input
the VDDQ switching drive power and via an RC filter to samples the input voltage and converts it to a current.
VCCA for the chip supply. If stand-alone capability is This input voltage-proportional current is used to charge
required, the +5V supply can be generated with an an internal on-time capacitor. The on-time is the time
external linear regulator.
required for the voltage on this capacitor to charge from
zero volts to VOUT, thereby making the on-time of the
high-side switch directly proportional to output voltage
VTTIN Supply
The VTTIN pins provide the input power for the high side and inversely proportional to input voltage. This
(sourcing) section of the VTT LDO. These pins should be implementation results in a nearly constant switching
decoupled to PGND2. If the output capacitors for the frequency without the need for a clock generator.
input supply for VTTIN (whether it is VDDQ or a different
VOUT
tON = 3.3x10−12 • (RTON + 37x103 )•
+ 50ns
supply) are not close to the chip, additional local bulk
capacitance may be required.
V
IN
Grounding
RTON is a resistor connected from the input supply to the
TON pin. Due to the high impedance of this resistor, the
TON pin should always be bypassed to VSSA using a 1nF
ceramic capacitor.
The SC486 has three ground connections, VSSA, PGND1
and PGND2 (2 pins). These should all be starred together
at the thermal pad under the device, which in turn will be
connected to the ground plane using multiple vias. VSSA
is the controller ground reference, to avoid interference
between the power and reference sections. PGND1 is
the power ground connection for the switching
controller for VDDQ. PGND2 is the power ground
connection for the sink-source LDO for VTT. All external
components referenced to VSSA in the schematic should
be connected directly to the VSSA trace. The supply
decoupling capacitor should be tied between VCCA and
VSSA. A 10Ω resistor should be used to decouple the
VCCA supply from the main VDDP supply. The VDDP
input provides power to the upper and lower gate
drivers of the switching supply. A decoupling capacitor
with no series resistor between VDDP and 5V is required.
See layout guidelines for more details.
EN/PSV: Enable, PSAVE and Soft Discharge
The EN/PSV pin enables the VDDQ (2.5V or 1.8V) output
and the REF output. VTTEN enables the VTT (1.25V or
0.9V) output provided that VDDQ is present. See Enable
Control Logic on Page 9.
When EN/PSV is pulled high the VDDQ controller is
enabled and power save will also be enabled. When the
EN/PSV pin is tri-stated (allowed to float, a 10nF
capacitor is required in this instance), an internal pull-up
will activate the VDDQ controller and power save will be
disabled. If PSAVE is enabled, the SC486 PSAVE
comparator will look for the inductor current to cross
zero on eight consecutive switching cycles by comparing
the phase node (LX) to PGND1. Once observed, the
controller will enter power save and turn off the low side
MOSFET when the current crosses zero. To improve light-
load efficiency and add hysteresis, the on-time is
increased by 50% in power save. The efficiency
improvement at light-loads more than offsets the
disadvantage of slightly higher output ripple. If the
inductor current does not cross zero on any switching
cycle, the controller will immediately exit power save. Since
the controller counts zero crossings, the converter can
sink current as long as the current does not cross zero
on eight consecutive cycles. This allows the output
voltage to recover quickly in response to negative load
steps even when psave is enabled.
Pseudo-fixed Frequency Constant On-Time PWM
Controller (VDDQ)
The PWM control architecture consists of a constant on-
time, pseudo fixed frequency PWM controller (see Figure
1, SC486 Block Diagram). The output ripple voltage
developed across the output filter capacitor’s ESR
provides the PWM ramp signal eliminating the need for a
current sense resistor. The high-side switch on-time is
determined by a one-shot whose period is directly
proportional to output voltage and inversely proportional
to input voltage. A second one-shot sets the minimum
off-time which is typically 400ns.
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SC486
POWER MANAGEMENT
EN/PSV: Enable, PSAVE and Soft Discharge (Cont.)
If the EN/PSV pin is pulled low, all three outputs will be
shut down and discharged using switches with a nominal
resistance of 22 Ohms, regardless of the state of the
VTTEN pin. This will ensure that the outputs will be in a
defined state next time they are enabled and also
ensure, since this is a soft discharge, that there are no
dangerous negative voltage excursions to be concerned
about. In order for the soft discharge circuitry to
function correctly, the chip supply must be present.
VDDQ Current Limit Circuit
Current limiting of the SC486 can be accomplished in
two ways. The on-state resistance of the low-side
MOSFETs can be used as the current sensing element or
sense resistors in series with the low-side sources can
be used if greater accuracy is desired. RDS(ON)
sensing is more efficient and less expensive. In both
cases, the RILIM resistors between the ILIM pin and LX pin
set the over current threshold. This resistor RILIM is
connected to a 10µA current source within the SC486
which is turned on when the low side MOSFET turns on.
When the voltage drop across the sense resistor or low
side MOSFET equals the voltage across the RILIM
resistor, positive current limit will activate. The high side
MOSFET will not be turned on until the voltage drop across
the sense element (resistor or MOSFET) falls below the
voltage across the RILIM resistor. In an extreme over-
current situation, the top MOSFET will never turn back
on and eventually the part will latch off due to output
undervoltage (see Output Undervoltage Protection).
VTTEN
The VTTEN pin is used to enable the VTT regulator only.
Pulling it high enables the regulator as long as VDDQ/
REF are present. Pulling VTTEN low while EN/PSV is
floating or high will turn off the VTT regulator and leave it
in a high-impedance state for S3 mode (VDDQ and REF
present, VTT high-Z).
VDDQ Output Voltage Selection and Output Sense
The output voltage is set by the feedback resistors R5 &
R9 of Figure 2 below. The internal reference is 1.5V, so
the voltage at the feedback pin will match the 1.5V
reference. Therefore the output can be set to a
minimum of 1.5V. The equation for setting the output
voltage is:
The current sensing circuit actually regulates the
inductor valley current (see Figure 3). This means that if
the current limit is set to 10A, the peak current through
the inductor would be 10A plus the peak ripple current,
and the average current through the inductor would be
10A plus 1/2 the peak-to-peak ripple current. The
equations for setting the valley current and calculating
the average current through the inductor are shown
overleaf.
R5
R8
VOUT = 1+
• 1.5
VDDQS is used to sense the output voltages for the on-
time one-shot, tON, and also to generate REF, which is 1/
2 of VDDQ. An RC filter consisting of 10Ω and 1µF from
VDDQ to VSSA is required (R4 and C2 in Figure 2) to filter
switching frequency ripple.
VBAT
5VSUS 5VRUN
5VSUS
VBAT
R3 470k
R1
R2
U1
SC486
PGD
10R
11
3
7
1
PGOOD
VTTEN
R4 10R
VDDQ
VDDQS
TON
C2
D1
EN/PSV
C1
2
R5
1uF
no-pop
6
FB
8
5
6
REF
REF
R7 10R
C5
9
24
COMP
BST
R6
C3
C4
10uF
10R
no-pop
R8 0R
10
5
0.1uF
VTTS
VCCA
23
21
22
4
3
8
DH
ILIM
LX
R9
R10
C6
C7
C8
C9
L1
1uF
no-pop
1nF
1uF
4
7
VDDQ
C10
VSSA
14
15
VTT
VTT
+
VTT
19
20
2
DL
12
13
VDDQ
VTTIN
VTTIN
VDDP
C11
20uF
C12
1uF
C13
1uF
Q1
1
16
17
PGND2
PGND2
18
PGND1
Figure 2
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SC486
POWER MANAGEMENT
VDDQ Current Limit Circuit (Cont.)
Power Good Output
The VDDQ output has its own power good output. Power
good is an open-drain output and requires a pull-up
resistor. When VDDQ is 16% above or 10% below its set
voltage, PGD gets pulled low. It is held low until the
output voltage returns to within these thresholds. PGD
is also held low during start-up and will not be allowed to
transition high until soft start is over (440 switching
cycles) and the output reaches 90% of its set voltage.
There is a 5µs delay built into the PGD circuitry to
prevent false transitions.
IPEAK
ILOAD
ILIMIT
Output Overvoltage Protection
VDDQ: when the output exceeds 16% of its set
voltage the low-side MOSFET is latched on. It stays
latched on and the controller is latched off until reset
(see below). There is a 5µs delay built into the OV
protection circuit to prevent false transitions. An OV fault
in VDDQ will cause REF and VTT to turn off (high-Z) also
when VDDQ drops below 0.5V. Note: to reset from any
fault, VCCA or EN/PSV must be toggled.
TIME
Valley Current-Limit Threshold Point
Figure 3: Valley Current Limiting
The equation for the current limit threshold is as follows:
RILIM
RSENSE
ILIMIT = 10e-6 •
A
VTT: when the output exceeds 12% of its set voltage the
output is latched in a tri-stated condition (high-Z). The
controller stays latched off until reset (see below). There
is a 50µs delay built into the OV protection circuit to
prevent false transitions. An OV fault in VTT will not
affect VDDQ or REF. To reset VTT from a fault, VCCA or
VTTEN or EN/PSV must be toggled.
Where (referring to Figure 2) RILIM is R10 and RSENSE is the
RDS(ON) of the bottom of Q1.
For resistor sensing, a sense resistor is placed between
the source of Q1 and PGND1. The current through the
source sense resistor develops a voltage that opposes
the voltage developed across RILIM. When the voltage
developed across the RSENSE resistor reaches the voltage
drop across RILIM, a positive over-current exists and the
high side MOSFET will not be allowed to turn on. When
using an external sense resistor RSENSE is the resistance
of the sense resistor.
Output Undervoltage Protection
VDDQ: when the output is 30% below its set voltage the
output is latched in a tri-stated condition. It stays latched
and the controller is latched off until reset (see below).
There is a 5µs delay built into the UV protection circuit to
prevent false transitions. An UV fault in VDDQ will cause
REF and VTT to turn off (high-Z) also when VDDQ drops
below 0.5V.
The current limit circuitry also protects against negative
over-current (i.e. when the current is flowing from the
load to PGND1 through the inductor and bottom MOSFET).
In this case, when the bottom MOSFET is turned on, the
phase node, LX, will be higher than PGND initially. The
SC486 monitors the voltage at LX, and if it is greater
than a set threshold voltage of 125mV (nom.) the
bottom MOSFET is turned off. The device then waits for
approximately 2.5µs and then DL goes high for 300ns
(typ.) once more to sense the current. This repeats until
either the over-current condition goes away or the part
latches off due to output overvoltage (see Output
Overvoltage Protection).
VTT: when the output is 12% below its set voltage the
output is latched in a tri-stated condition (high-Z). The
controller stays latched off until reset (see below). There
is a 50µs delay built into the UV protection circuit to
prevent false transitions. An UV fault in VTT will not
affect VDDQ or REF. To reset VTT from a fault, VCCA or
VTTEN or EN/PSV must be toggled.
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SC486
POWER MANAGEMENT
POR, UVLO and Softstart
DDR Reference Buffer
An internal power-on reset (POR) occurs when VCCA The reference buffer is capable of driving 10mA and
exceeds 3V, starting up the internal biasing. VCCA sinking 25µA. Since the output is class A, if additional
undervoltage lockout (UVLO) circuitry inhibits the whole sinking is required an external pulldown resistor can be
controller until VCCA rises above 4.2V. At this time the added. Make sure that the ground side of this pulldown
UVLO circuitry enables the REF buffer, resets the fault is tied to VSSA. As with most opamps, a small resistor is
latch and soft start timer, and allows switching to occur, required when driving a capacitive load. To ensure stability
if enabled. Switching always starts with DL to charge up use either a 10Ω resistor in series with a 1µF capacitor
the BST capacitor. With the softstart circuit or a 100Ω resistor in series with a 0.1µF capacitor from
(automatically) enabled, it will progressively limit the REF to VSSA.
output current (by limiting the current out of the ILIM pin)
over a predetermined time period of 440 switching cycles. VTT Sink/Source Output
The VTT regulator is a sink/source LDO capable of
The ramp occurs in four steps:
supplying peak currents up to 3.6A. It has been designed
1) 110 cycles at 25% ILIM with double minimum off-time to operate with output capacitances as low as 20µF (two
(for purposes of the on-time one-shot, there is an 10µF 1210 ceramic capacitors). These capacitors need
internal positive offset of 120mV to VOUT during this to be placed directly across the VTT and PGND2 pins to
period to aid in startup)
minimize parasitic resistance and inductance. Additional
2) 110 cycles at 50% ILIM with normal minimum off-time ceramic capacitors may be used to improve transient
3) 110 cycles at 75% ILIM with normal minimum off-time response further if desired. The VTT input requires a 1µF
4) 110 cycles at 100% ILIM with normal minimum ceramic capacitor for bypass purposes located right at
off-time. At this point the output undervoltage and power the pin. If the output capacitors for the power rail being
good circuitry is enabled.
used for VTTIN are far from the part then additional bulk
capacitance of two 10µF ceramic capacitors should be
When VDDQ reaches 0.5V, the REF output is enabled added.
and rises to VDDQS/2. VTT attempts to track REF but its
own soft start circuitry will limit its rise rate to 6mV/µs. If COMP Pin
VDDQ is rising slow enough, VTT will rise at 6mV/µs until The VTT COMP pin is provided to permit the addition of a
it reaches VDDQ/2 and then track VDDQ.
zero into the VTT control loop by adding a resistor (less
than 100Ω) between COMP and REF and a capacitor
There is 100mV of hysteresis built into the UVLO circuit from COMP to VTTS (R7 and C3 in Figure 2). The zero
and when VCCA falls to 4.1V (nom.) the output drivers frequency should be set to approximately 10 times the
are shut down and tri-stated.
unity gain bandwidth, which is ~1MHz, therefore fZ should
be ~10MHz. fZ is given by the following equation:
MOSFET Gate Drivers
1
The DH and DL drivers are optimized for driving
moderate-sized high-side, and larger low-side power
MOSFETs. An adaptive dead-time circuit monitors the DL
output and prevents the high-side MOSFET from turning
on until DL is fully off (below ~1V). Semtech’s
SmartDriver™ FET drive first pulls DH high with a pull-up
resistance of 10Ω (typ.) until LX = 1.5V (typ.). At this
point, an additional pull-up device is activated, reducing
the resistance to 2Ω (typ.). This negates the need for an
external gate or boost resistor. The adaptive dead-time
circuit also monitors the phase node, LX, to determine
the state of the high side MOSFET, and prevents the low-
side MOSFET from turning on until DH is fully off (LX
below ~1V). Be sure to have low resistance and low
inductance between the DH and DL outputs to the gate
of each MOSFET.
fZ =
2• π • R • C
Typically this compensation will not be required, so C3
should be no-pop and R7 should be 0Ω or 10Ω.
VTTS Pin
The VTTS pin is used to kelvin sense the VTT output. An
RC filter (with R from VTT to VTTS less than 100Ω and C
from VTTS to VSSA, R8 and C7 in Figure 2) may be used
to compensate any zeroes created by less than optimal
ESR at the output. With the recommended output
capacitors they are not necessary so R should be 0Ω
and C should be no-pop.
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SC486
POWER MANAGEMENT
Dropout Performance
VBAT = 6V, then the measured DC output will be 2.525V.
VDDQ: the output voltage adjust range for If the ripple increases to 80mV with VBAT = 25V, then
continuous-conduction operation is limited by the fixed the measured DC output will be 2.540V.
550ns (maximum) minimum off-time one-shot. For best
dropout performance, use the slowest on-time setting The output inductor value may change with current. This
of 200kHz. When working with low input voltages, the will change the output ripple and thus the DC output
duty-factor limit must be calculated using worst-case voltage. It will not change the frequency. Switching
values for on and off times. The IC duty-factor limitation frequency variation with load can be minimized by
is given by:
choosing MOSFETs with lower RDS(ON). High RDS(ON) MOSFETs
will cause the switching frequency to increase as the load
current increases. This will reduce the ripple and thus
the DC output voltage.
t
ON(MIN)
DUTY =
t
+
t
OFF(MAX)
ON(MIN)
SC486 System DC Accuracy (VTT Sink/Source LDO)
The VTT LDO is designed to track the voltage at REF, with
a guaranteed DC accuracy of REF +/-20mV for -2A to
+2A. Thus the DDR/DDR2 absolute requirement of
+/-40mV including transients is an easy goal to achieve
provided that careful attention is paid during board layout
to reduce parasitic ESR/ESL.
Be sure to include inductor resistance and MOSFET on-
state voltage drops when performing worst-case dropout
duty-factor calculations.
VTT: the minimum input voltage allowed to be applied to
VTTIN (if a supply other than VDDQ is being used) should
be determined using the required maximum output
current and the maximum VTT pull-up resistance, 0.45Ω.
The minimum VTTIN for a given VTT and ITT can be
calculated as follows:
DDR Supply Selection
The SC486 can be configured so that the VTT supply can
be generated from the VDDQ supply, or from an alternate
supply (usually lower to minimize power dissipation). If
the VTT LDO is going to be powered from the VDDQ output,
the electrical design of the VDDQ output needs to be for
IDDQ(MAX) + ITT(MAX).
VTTIN(MIN) = VTT +ITT • RPULLUP(MAX)
For example: for VTT = 0.9V out and ITT = 1.25A, VTTIN
can go as low as 1.463V.
SC486 System DC Accuracy (VDDQ Controller)
Two IC parameters affect system DC accuracy, the error
comparator threshold voltage variation and the switching
frequency variation with line and load.
The error comparator threshold does not drift significantly
with supply and temperature. Thus, the error comparator
contributes 1% or less to DC system inaccuracy. Board
components and layout also influence DC accuracy. The
use of 1% feedback resistors contribute 1%. If tighter
DC accuracy is required use 0.1% feedback resistors.
The on-pulse in the SC486 is calculated to give a pseudo
fixed frequency. Nevertheless, some frequency variation
with line and load can be expected. This variation changes
the output ripple voltage. Because constant on-time
regulators regulate to the valley of the output ripple, ½
of the output ripple appears as a DC regulation error.
For example, if the feedback resistors are chosen to
divide down the output by a factor of five, the valley of
the output ripple will be 2.5V. If the ripple is 50mV with
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SC486
POWER MANAGEMENT
Design Procedure - VDDQ Controller
and
Prior to designing an output and making component
selections, it is necessary to determine the input voltage
range and the output voltage specifications. For purposes
of demonstrating the procedure an 8A VDDQ output
being used to power VTT at +/-2A for a total IDDQ of
10A will be designed.
VOUT
BAT(MAX) • tON_ VBAT(MAX)
fSW _ VBAT(MAX)
=
Hz
(
V
)
tON is generated by a one-shot comparator that samples
VBAT via RtON, converting this to a current. This current is
used to charge an internal 3.3pF capacitor to VOUT. The
equations above reflect this along with any internal
components or delays that influence tON. For our DDR2
VDDQ example we select RtON = 715kΩ:
The maximum input voltage (VBAT(MAX)) is determined by
the highest AC adaptor voltage. The minimum input
voltage (VBAT(MIN)) is determined by the lowest battery
voltage after accounting for voltage drops due to
connectors, fuses and battery selector switches. For the
purposes of this design example we will use a VBAT range
of 9V to 19.2V.
tON_VBAT(MIN) = 546ns and tON_VBAT(MAX) = 283ns
fSW_VBAT(MIN) = 366kHz and fSW_VBAT(MAX) = 332kHz
Four parameters are needed for the output:
1) nominal output voltage, VOUT (for DDR2 this is 1.8V)
2) static (or DC) tolerance, TOLST (we will use +/-4% for
this design )
3) transient tolerance, TOLTR and size of transient (we will
use +/-100mV for this design).
Now that we know tON we can calculate suitable values
for the inductor. To do this we select an acceptable
inductor ripple current. The calculations below assume
50% of IOUT which will give us a starting place.
t
LVBAT(MIN)
=
(VBAT(MIN) − VOUT
)
•
ON_ VBAT(MIN) H
4) maximum output current, IOUT (we are designing for
10A)
(0.5 • IOUT
)
and
Switching frequency determines the trade-off between
size and efficiency. Increased frequency increases the
switching losses in the MOSFETs, since losses are a
function of VIN2. Knowing the maximum input voltage and
budget for MOSFET switches usually dictates where the
design ends up. The default RtON value of 715kΩ is
suggested as a starting point, but it is not set in stone.
The first thing to do is to calculate the on-time, tON, at
VBAT(MIN) and VBAT(MAX), since this depends only upon VBAT,
VOUT and RtON.
t
(
LVBAT(MAX)
=
(VBAT(MAX) − VOUT
)
•
ON_ VBAT(MAX) H
0.5 • IOUT )
For our DDR2 VDDQ example:
LVBAT(MIN) = 0.8µH and LVBAT(MAX) = 1.0µH
We will select an inductor value of 1.5µH to reduce the
ripple current, which can be calculated as follows:
VOUT
VBAT(MIN)
−12
−9
tON_ VBAT(MIN) = 3.3 • 10
•
(
RtON + 37 • 103
)
•
+ 50 • 10 s
tON_ VBAT(MIN)
IRIPPLE_ VBAT(MIN)
=
(VBAT(MIN) − VOUT
)
•
AP−P
L
and
and
VOUT
VBAT(MAX)
−12
−9
tON_ VBAT(MAX) = 3.3 • 10
•
(
RtON + 37 • 103
)
•
+ 50 • 10 s
tON_ VBAT(MAX)
IRIPPLE_ VBAT(MAX)
=
(VBAT(MAX) − VOUT
)
•
AP−P
L
From these values of tON we can calculate the nominal
switching frequency as follows:
VOUT
fSW _ VBAT(MIN)
=
Hz
VBAT(MIN) • tON_ VBAT(MIN)
( )
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SC486
POWER MANAGEMENT
Design Procedure (Cont.)
RESR_TR(MAX) = 5.5mΩ for a full 10A load transient
For our DDR2 VDDQ example:
We will select a value of 7.5mΩ maximum for our
design, which would be achieved by using two 15mΩ
output capacitors in parallel.
IRIPPLE_VBAT(MIN) = 2.62AP-P and IRIPPLE_VBAT(MAX) = 3.28AP-P
From this we can calculate the minimum inductor
current rating for normal operation:
Note that for constant-on converters there is a minimum
ESR requirement for stability which can be calculated as
follows:
IRIPPLE _ VBAT(MAX)
IINDUCTOR(MIN) = IOUT(MAX)
+
A(MIN)
2
3
RESR(MIN)
=
For our DDR2 VDDQ example:
IINDUCTOR(MIN) = 11.6A(MIN)
2 • π • COUT • fSW
This criteria should be checked once the output
capacitance has been determined.
Next we will calculate the maximum output capacitor
equivalent series resistance (ESR). This is determined by
calculating the remaining static and transient tolerance
allowances. Then the maximum ESR is the smaller of the
calculated static ESR (RESR_ST(MAX)) and transient ESR
(RESR_TR(MAX)):
Now that we know the output ESR we can calculate the
output ripple voltage:
VRIPPLE_ VBAT(MAX) = RESR • IRIPPLE_ VBAT(MAX)VP−P
and
(
ERRST − ERRDC )• 2
RESR _ST(MAX)
=
Ohms
VRIPPLE_ VBAT(MIN) = RESR • IRIPPLE_ VBAT(MIN)VP−P
IRIPPLE _ VBAT(MAX)
For our DDR2 VDDQ example:
Where ERRST is the static output tolerance and ERRDC is
the DC error. The DC error will be 1% plus the tolerance
of the feedback resistors, thus 2% total for 1%
feedback resistors.
VRIPPLE_VBAT(MAX) = 25mVP-P and VRIPPLE_VBAT(MIN) = 20mVP-P
Note that in order for the device to regulate in a
controlled manner, the ripple content at the feedback
pin, VFB, should be approximately 15mVP-P at minimum
VBAT, and worst case no smaller than 10mVP-P. If
VRIPPLE_VBAT(MIN) is less than 15mVP-P the above component
values should be revisited in order to improve this. A small
capacitor, CTOP, may be required in parallel with the top
feedback resistor, RTOP, in order to ensure that VFB is large
enough. CTOP should not be greater than 100pF. The value
of CTOP can be calculated as follows, where RBOT is the
bottom feedback resistor. Firstly calculating the value of
ZTOP required:
For our DDR2 VDDQ example:
ERRST = 72mV and ERRDC = 36mV, therefore
RESR_ST(MAX) = 22mΩ
(
ERRTR − ERRDC
)
RESR _TR(MAX)
=
Ohms
IRIPPLE _ VBAT(MAX)
IOUT
+
2
RBOT
0.015
Where ERRTR is the transient output tolerance. Note that
this calculation assumes that the worst case load
transient is full load. For half of full load, divide the IOUT
term by 2.
ZTOP
=
•
(
VRIPPLE _ VBAT(MIN) − 0.015
)
Ohms
For our DDR2 VDDQ example:
ERRTR = 100mV and ERRDC = 36mV, therefore
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SC486
POWER MANAGEMENT
Design Procedure (Cont.)
calculated by substituting the desired current for the IOUT
Secondly calculating the value of CTOP required to achieve term.
this:
For our DDR2 VDDQ example:
COUT(MIN) = 839µF.
1
1
−
ZTOP RTOP
CTOP
=
F
We will select 440µF, using two 220µF, 15mΩ
capacitors in parallel, which will be good for load release
steps of up to 6.7A.
2 • π • fSW _ VBAT(MIN)
For our DDR2 VDDQ example we will use RTOP = 4.64kΩ
and RBOT = 23.2kΩ, therefore
Next we calculate the RMS input ripple current, which is
largest at the minimum battery voltage:
VFB_VBAT(MIN) = 16.7mVP-P - good
IOUT
VBAT _MIN
No additional capacitance is required, however a no-pop
space is recommended to allow for adjustment once the
design is complete, laid out and built.
IIN(RMS) = VOUT
•
(VBAT(MIN) − VOUT
)
•
ARMS
For our DDR2 VDDQ example:
IIN(RMS) = 4ARMS
Next we need to calculate the minimum output
capacitance required to ensure that the output voltage
does not exceed the transient maximum limit, POSLIMTR,
starting from the actual static maximum, VOUT_ST_POS, when
a load release occurs:
Input capacitors should be selected with sufficient ripple
current rating for this RMS current, for example a 10µF,
1210 size, 25V ceramic capacitor can handle
approximately 3ARMS. Refer to manufacturer’s data
sheets.
VOUT_ST _POS = VOUT + ERRDC
V
For our DDR2 VDDQ example:
VOUT_ST_POS = 1.836V
Finally, we calculate the current limit resistor value. As
described in the current limit section, the current limit
looks at the “valley current”, which is the average output
current minus half the ripple current. We use the
maximum room temperature specification for MOSFET
RDS(ON) at VGS = 4.5V for purposes of this calculation:
POSLIMTR = VOUT • TOLTR
V
Where TOLTR is the transient tolerance. For our DDR2
VDDQ example:
IRIPPLE _ VBAT(MIN)
IVALLEY = IOUT
−
A
2
POSLIMTR = 1.900V
The ripple at low battery voltage is used because we want
to make sure that current limit does not occur under
normal operating conditions.
The minimum output capacitance is calculated as
follows:
2
R
DS(ON) • 1.4
IRIPPLE _ VBAT(MAX)
RILIM
=
(IVALLEY • 1.2
)
•
Ohms
IOUT
+
−6
10 • 10
2
COUT(MIN) = L •
F
2
2
(
POSLIMTR − VOUT _ST _POS
)
For our DDR2 VDDQ example RDS(ON) = 9mΩ:
IVALLEY = 8.69A and RILIM = 13.1kΩ
This calculation assumes the absolute worst case
condition of a full-load to no load step transient occurring
when the inductor current is at its highest. The
capacitance required for smaller transient steps my be
We select the next lowest 1% resistor value: 13.0kΩ
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SC486
POWER MANAGEMENT
Thermal Considerations
Inserting the following values for VBAT(MIN) condition (since
The junction temperature of the device may be calculated this is the worst case condition for power dissipation in
as follows:
the controller) as an example):
TA = 85°C
θJA = 29°C/W
TJ = TA + PD • θJA °C
VCCA = VDDP = 5V
IVCCA = 2500µA (data sheet maximum)
IVDDP = 150µA (data sheet maximum)
Vg = 5V
Qg = 60nC
f = 366kHz
Where:
TA = ambient temperature (°C)
PD = power dissipation in (W)
θJA = thermal impedance junction to ambient from
absolute maximum ratings (°C/W)
VBAT(MIN) = 8V
The power dissipation may be calculated as follows,
assuming that VTT spends 50% of its time sourcing
current and 50% sinking:
VBST(MIN) = VBAT(MIN)+VDDP = 13V
D1(MIN) = 1.8/8 = 0.225
VDDQ = VTTIN = 1.8V
VTT = 0.9V
PD = VCCA • IVCCA + VDDP • IVDDP
+ Vg • Qg • f + VBST • 1mA • D
ITT = 1.2A
gives us:
+
(
VTTIN − VTT
)
• ITT
W
−6
−6
PD = 5 • 2500e + 5 • 150e
−9
+ 5 • 60e • 366e3 +13 • 1mA • 0.225
Where:
VCCA = chip supply voltage (V)
IVCCA = operating current (A)
+
(1.8 − 0.9
)
• 1.2 = 1.206
W
VDDP = gate drive supply voltage (V)
IVDDP = gate drive operating current (A)
Vg = gate drive voltage, typically 5V (V)
Qg = FET gate charge, from the FET datasheet (C)
f = switching frequency (Hz)
VBST = boost pin voltage during tON (V)
D = duty cycle
VTTIN = input voltage for VTT LDO (V)
ITT = maximum VTT current (A)
and therefore:
TJ = 85 +1.206 • 29 = 120°C
As can be seen, the heating effects due to internal power
dissipation are dominated by the VTT LDO, but they can
be managed comfortably by the MLPQ-24 package which
is heatsunk to the ground plane using 4 vias from its
thermal pad.
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SC486
POWER MANAGEMENT
Layout Guidelines
One (or more) ground planes is/are recommended to minimize the effect of switching noise and copper losses, and
maximize heat dissipation. The IC ground reference, VSSA, should be connected to PGND1 and PGND2 as a star
connection at the thermal pad, which in turn is connected using 4 vias to the ground plane. All components that are
referenced to VSSA should connect to it directly on the chip side, and not through the ground plane.
VDDQ: the feedback trace must be kept far away from noise sources such as switching nodes, inductors and gate
drives. Route the feedback trace in a quiet layer if possible from the output capacitor back to the chip.
Chip supply decoupling capacitors (VCCA, VDDP) should be located next to the pins (VCCA and VSSA, VDDP and
PGND1) and connected directly to them on the same side.
VTT: output capacitors should be located right across the VTT output pins (VTT and PGND2) as close as possible to
the part to minimize parasitics.
The switcher power section should connect directly to the ground plane(s) using multiple vias as required for current
handling (including the chip power ground connections). Power components should be placed to minimize loops and
reduce losses. Make all the connections on one side of the PCB using wide copper filled areas if possible. Do not
use “minimum” land patterns for power components. Minimize trace lengths between the gate drivers and the
gates of the MOSFETs to reduce parasitic impedances (and MOSFET switching losses), the low-side MOSFET is most
critical. Maintain a length to width ratio of <20:1 for gate drive signals. Use multiple vias as required by current
handling requirement (and to reduce parasitics) if routed on more than one layer. Current sense connections must
always be made using Kelvin connections to ensure an accurate signal.
We will examine the SC486 DDR2 reference design used in the Design Procedure section while explaining the layout
guidelines in more detail.
VBAT 5VSUS 5VRUN
5VSUS
VBAT
R3 470k
R1
R2
U1
SC486
PGD
715k
10R
11
3
7
1
PGOOD
VTTEN
R4 10R
VDDQ
VDDQS
TON
C2
1u
D1
EN/PSV
C1
2
R5 4k64
no-pop
6
FB
8
REF
REF
R7 10R
C5
2n2/50V
C6
C7
10u/25V
C8
9
24
COMP
BST
R6
C3
C4
0u1/25V
10u/25V
Q1
10R
no-pop
R9 0R
10
5
0.1uF
VTTS
23
21
22
IRF7811AV
DH
ILIM
LX
R8
R10 13k0
VCCA
C9
1u
C10
C11
1n
C12
1u
23k2
L1 1u5
no-pop
4
VDDQ
VSSA
14
15
Q2
VTT
VTT
+
C13
220u/15m
+
C14
220u/15m
VTT
19
20
FDS6676S
DL
12
13
VDDQ
VTTIN
VTTIN
VDDP
C15
10u
C16
10u
C17
1u
C18
1u
16
17
PGND2
PGND2
18
PGND1
Figure 4: DDR2 Reference Design and Layout Example
Sample DDR2 Design Using SC486
VBAT = 9V to 19.2V
VDDQ = 1.8V @ (8+2)A
VTT = 0.9V @ 2A
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SC486
POWER MANAGEMENT
Layout Guidelines (Cont.)
The layout can be considered in three parts, the control section referenced to VSSA, the VTT output, and the
switcher power section. Looking at the control section first, locate all components referenced to VSSA1 on the
schematic and place these components at the chip. Connect VSSA using a wide (>0.020”) trace. Very little current
flows in the chip ground therefore large areas of copper are not needed. Connect the VSSA pin directly to the
thermal pad under the device as the only connection to PGND from VSSA.
5VRUN
U1
SC486
PGD
11
3
7
1
VTTEN
R4 10R
VDDQ
VDDQS
TON
C2
1u
EN/PSV
C1
2
R5 4k64
no-pop
6
FB
8
REF
REF
R7 10R
9
24
COMP
BST
R6
C3
10R
no-pop
10
5
VTTS
VCCA
23
21
22
DH
ILIM
LX
R8
C9
1u
C10
C11
1n
C12
1u
23k2
no-pop
4
VSSA
14
15
VTT
VTT
19
20
DL
12
13
VTTIN
VTTIN
VDDP
C18
1u
16
17
PGND2
PGND2
18
PAD
PGND1
Figure 7: Components Connected to VSSA
Figure 8: Example VSSA 0.020” Trace
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SC486
POWER MANAGEMENT
Layout Guidelines (Cont.)
In Figure 8, all components referenced to VSSA have been placed and have been connected using a 0.020” trace.
Decoupling capacitor C12 is as close as possible to VCCA and VSSA and the VDDP decoupling capacitor C18 is as
close as possible to VDDP and PGND1. The feedback components R5, R8 and C1 along with the VDDQ sense
components, R4 and C2 are also located at the chip and the feedback trace from the VDDQ output should route
from the top of the output capacitors (C13 and C14) in a quiet layer back to these components. In Figure 8, the
VDDQ feedback trace would connect to the red trace.
U1
SC486
PGD
11
3
7
1
VTTEN
R4 10R
VDDQS
TON
C2
1u
EN/PSV
C1
2
R5 4k64
no-pop
6
FB
8
REF
9
24
COMP
BST
10
5
VTTS
VCCA
23
21
22
DH
ILIM
LX
R8
23k2
4
VDDQ
VSSA
14
15
VTT
VTT
+
+
C13
C14
220u/15m
220u/15m
19
20
DL
12
13
VTTIN
VTTIN
VDDP
16
17
PGND2
PGND2
18
PAD PGND1
VDDQ FEEDBACK
Figure 9: VDDQ Feedback and Sense Components and Feedback Trace
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SC486
POWER MANAGEMENT
Layout Guidelines (Cont.)
Next, looking at the switcher power section, the schematic in Figure 10 below shows the power section for VDDQ:
VBAT
Q1 IRF7811AV
1
2
3
4
8
7
6
5
S
S
S
G
D
D
D
D
C5
C6
C7
C8
2n2/50V
0u1/25V
10u/25V
10u/25V
L1 1u5
VDDQ
FDS6676S Q2
8
7
6
5
1
2
3
4
+
C13
220u/15m
+
C14
220u/15m
D
D
D
D
S
S
S
G
Figure 10: VDDQ Power Section and Input Loop
The highest di/dts occur in the input loop (highlighted in red) and thus this should be kept as small as possible. The
input capacitors should be placed with the highest frequency capacitors closest to the loop to reduce EMI. Use large
copper pours to minimize losses and parasitics. See Figure 11 below for an example.
Figure 11: Example VDDQ Power Section Layout
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SC486
POWER MANAGEMENT
Layout Guidelines (Cont.)
Key points for the switcher power section:
1) there should be a very small input loop, well decoupled.
2) the phase node should be a large copper pour, but compact since this is the noisiest node.
3) input power ground and output power ground should not connect directly, but through the ground planes instead.
Connecting the control and switcher power sections should be accomplished as follows (see Figure 12 below):
1) Route VDDQ feedback trace in a “quiet” layer away from noise sources.
2) Route DL, DH and LX (low side FET gate drive, high side FET gate drive and phase node) to chip using wide traces
with multiple vias if using more than one layer. These connections are to be as short as possible for loop minimization,
with a length to width ratio less than 20:1 to minimize impedance. DL is the most critical gate drive, with power
ground as its return path. LX is the noisiest node in the circuit, switching between VBAT and ground at high frequencies,
thus should be kept as short as practical. DH has LX as its return path.
3) BST is also a noisy node and should be kept as short as possible.
4) Connect PGND pins on the chip directly to the VDDP decoupling capacitor and then drop vias directly to the
ground plane.
U1
SC486
PGD
11
3
7
1
VTTEN
VDDQS
TON
EN/PSV
2
6
FB
8
REF
9
24
COMP
BST
Q1
10
5
VTTS
VCCA
23
21
22
IRF7811AV
DH
ILIM
LX
R10 13k0
L1 1u5
4
VSSA
14
15
Q2
VTT
VTT
19
20
FDS6676S
DL
12
13
VTTIN
VTTIN
VDDP
16
17
PGND2
PGND2
18
PGND1
PAD
Figure 12: Connecting Control and Switcher Power Sections
Phase nodes (black) to be copper islands (preferred) or wide copper traces. Gate drive traces (red) and phase node
traces (blue) to be wide copper traces (L:W < 20:1) and as short as possible, with DL the most critical. Use multiple
vias when switching between layers. Locate the current limit resistor (R10) at the chip with a kelvin connection to
the phase node.
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SC486
POWER MANAGEMENT
Layout Guidelines (Cont.)
Next looking at the VTT output:
U1
SC486
PGD
11
3
7
1
VTTEN
VDDQS
TON
EN/PSV
2
6
FB
8
REF
9
24
COMP
BST
10
5
VTTS
23
21
22
DH
ILIM
LX
VCCA
4
VSSA
14
15
VTT
VTT
VTT
19
20
DL
12
13
VDDQ
VTTIN
VTTIN
VDDP
C15
10u
C16
10u
C17
1u
16
17
PGND2
PGND2
18
PGND1
Figure 13: VTT Output
The output capacitors should be connected right at the chip, on the same side as the chip and right across the pins.
The input capacitor may be placed on the opposite side, if desired. See Figure 14 below:
Figure 14: Example VTT Output Component Placement and Starred Ground
Output capacitors C15 and C16 are placed across the device pins, and connect to the ground plane using multiple
vias. Input capacitor C17 connects directly to the device pins and connects to the ground plane using two vias. Note
that PGND1, PGND2 and VSSA all connect to the pad under the device, which should also connect to the ground
plane using multiple vias.
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SC486
POWER MANAGEMENT
Outline Drawing - MLPQ-24 (4 x 4mm)
A
D
B
E
DIMENSIONS
INCHES MILLIMETERS
DIM
A
MIN NOM MAX MIN NOM MAX
.031
.039
0.90 1.00
.035
.001
0.80
0.02
(0.20)
0.25
A1 .000
.002 0.00
0.05
-
-
-
-
(.008)
A2
PIN 1
b
D
.007
0.30
.010 .012 0.18
INDICATOR
3.85 4.00 4.15
2.70
.152 .157 .163
(LASER MARK)
D1
E
.100 .106 .110 2.55
2.80
3.85 4.00 4.15
.152 .157 .163
E1
e
2.70
.100
2.80
.106 .110 2.55
.020 BSC
0.50 BSC
L
N
.012 .016 .020 0.30 0.40 0.50
24
24
aaa
.004
.004
0.10
0.10
A2
bbb
A
SEATING
PLANE
aaa C
A1
C
D1
LxN
E/2
E1
2
1
N
bxN
bbb
C A B
e
D/2
NOTES:
1. CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES).
COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS.
2.
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SC486
POWER MANAGEMENT
Land Pattern - MLPQ-24 (4 x 4mm)
K
DIMENSIONS
DIM
INCHES
MILLIMETERS
(.156)
.122
.106
.106
.020
.010
.033
.189
(3.95)
3.10
2.70
2.70
0.50
0.25
0.85
4.80
C
G
H
K
P
X
Y
Z
G
Z
(C)
H
X
P
NOTES:
1.
THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY.
CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR
COMPANY'S MANUFACTURING GUIDELINES ARE MET.
2.
THERMAL VIAS IN THE LAND PATTERN OF THE EXPOSED PAD
SHALL BE CONNECTED TO A SYSTEM GROUND PLANE.
FAILURE TO DO SO MAY COMPROMISE THE THERMAL AND/OR
FUNCTIONAL PERFORMANCE OF THE DEVICE.
Contact Information
Semtech Corporation
Power Management Products Division
200 Flynn Road, Camarillo, CA 93012
Phone: (805)498-2111 FAX (805)498-3804
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