SC488 [SEMTECH]
Complete DDR1/2/3 Memory Power Supply; 完整的DDR1 / 2/3存储器电源
| 型号： | SC488 |
| 厂家： | 
SEMTECH CORPORATION |
| 描述： | Complete DDR1/2/3 Memory Power Supply |
| 文件： | 总24页 (文件大小：806K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SC488
Complete DDR1/2/3
Memory Power Supply
POWER MANAGEMENT
Description
Features
The SC488 is a combination switching regulator and lin-
ear source/sink regulator intended for DDR1/2 memory
systems. The purpose of the switching regulator is to gen-
erate the supply voltage, VDDQ, for the memory system.
It is a pseudo-fixed frequency constant on-time controller
designed for high efficiency, superior DC accuracy, and fast
transient response. The purpose of the linear source/sink
regulator is to generate the memory termination voltage,
VTT, with the ability to source and sink 2.8A peak cur-
rents.
ꢀ Constant On-Time Controller for Fast Dynamic
Response on VDDQ
ꢀ DDR1/DDR2/DDR3 Compatible
ꢀ VDDQ = Fixed 1.8V or 2.5V, or Adjustable From
1.5V to 3.0V
ꢀ 1.5% Internal Reference (2.5% System Accuracy)
ꢀ Resistor Programmable On-Time for VDDQ
ꢀ VCCA/VDDP Range = 4.5V to 5.5V
ꢀ VIN Range = 2.5V to 25V
ꢀ VDDQ DC Current Sense Using Low-Side RDS(ON)
Sensing
For the VDDQ regulator, the switching frequency is constant
until a step in load or line voltage occurs at which time the
pulse density, i.e., frequency, will increase or decrease to
counter the transient change in output or input voltage.
After the transient, the frequency will return to steady-state
operation. At lighter loads, the selectable Power-Save
Mode enables the PWM converter to reduce its switching
frequency and improve efficiency. The integrated gate
drivers feature adaptive shoot-through protection and soft-
switching. Additional features include cycle-by-cycle current
limiting, digital soft-start, over-voltage and under-voltage
protection and a power good flag.
ꢀ External RSENSE in Series with Low-Side FET
ꢀ Cycle-by-Cycle Current Limit for VDDQ
ꢀ Digital Soft-Start for VDDQ
ꢀ Analog Soft-Start for VTT/REF
ꢀ Smart Over-Voltage VDDQ Protection
ꢀ Combined EN and PSAVE Pin for VDDQ
ꢀ Over-Voltage/Under-Voltage Fault Protection
ꢀ Power Good Output
ꢀ Separate VCCA and VDDP Supplies
ꢀ VTT/REF Range = 0.75V – 1.5V
ꢀ VTT Source/Sink 2.8A Peak
ꢀ Internal Resistor Divider for VTT/REF
ꢀ VTT is High Impedance in S3
For the VTT regulator, the output voltage tracks REF, which
is ½ VDDQ to provide an accurate termination voltage.
The VTT output is generated from a 1.2V to VDDQ input by
a linear source/sink regulator which is designed for high
DC accuracy, fast transient response, and low external
component count. All three outputs (VDDQ, VTT and REF)
are actively discharged when VDDQ is disabled, reducing
external component count and cost. The SC488 is avail-
able in a 24-pin MLPQ (4x4 mm) package.
ꢀ VDDQ, VTT, REF are Actively Discharged in S4/S5
ꢀ 24 Lead MLPQ (4x4 mm) Lead-Free Package
ꢀ Product Is Fully WEEE and RoHS Compliant
Applications
ꢀ Notebook Computers
ꢀ CPU I/O Supplies
ꢀ Handheld Terminals and PDAs
ꢀ LCD Monitors
ꢀ Network Power Supplies
Typical Application Circuit
5V
VBAT
D1
C2
0.1uF
C3
2x10uF
VDDQ
Q1
VTT
VBAT
VDDQ
L1
C1
1uF
C4
10uF
C5
10uF
+
Q2
C6
1
2
3
4
5
6
18
PGND2
VTTS
VSSA
TON
PGND1
PGND1
ILIM
R1
1Meg
U1
17
RILIM
16
VTTSNS
8
15
VDDP
VDDP
14
C7
1nF
REF
13
PGOOD
VCCA
PGD
PAD
R6
10R
C10
1uF
PAD
R4
REF
C9
1uF
R7
10R
5V
C8
0.1uF
C11
1uF
EN/PSV
VTT_EN
VDDQ
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SC488
POWER MANAGEMENT
Absolute Maximum Ratings
Exceeding the specifications below may result in permanent damage to the device or device malfunction. Operation outside of the parameters specified in the
Electrical Characteristics section is not implied. Exposure to absolute maximum rated conditions for extended periods of time may affect device reliability.
Parameter
Symbol
Maximum
Units
TON to VSSA
-0.3 to +25.0
-0.3 to +31.0
-0.3 to +6.0
-2.0 to +25.0
-0.3 to +6.0
-0.3 to +6.0
-0.3 to +6.0
-0.3 to +6.0
-0.3 to +6.0
-0.3 to +0.3
29
V
V
DH, BST to PGND1
BST, DH to LX
V
LX to PGND1
V
DL, ILIM, VDDP to PGND1
V
VDDP to DL
V
VTTIN to PGND2; VTT to PGND2; VTTIN to VTT
EN/PSV, FB, PGD, REF, VCCA, VDDQS, VTTEN, VTTS to VSSA
VCCA to EN/PSV, FB, REF, VDDQS, VTT, VTTEN, VTTIN, VTTS
PGND1 to PGND2; PGND1 to VSSA; PGND2 to VSSA
Thermal Resistance Junction to Ambient(1)
Operating Junction Temperature Range
Storage Temperature Range
V
V
V
V
θJA
TJ
°C/W
°C
°C
°C
kV
-40 to +150
-65 to +150
260
TSTG
TPKG
VESD
Peak IR Reflow Temperature, 10s - 40s
ESD Protection Level(2)
2
Notes:
1) Calculated from package in still air, mounted to 3” x 4.5”, 4 layer FR4 PCB with thermal vias under the exposed pad per JESD51 standards.
2) Tested according to JEDEC standard JESD22-A114-B.
Electrical Characteristics
Test Conditions: VIN = 15V, VCCA = VDDP = VTTEN = EN/PSV = 5V, VDDQ = VTTIN = 1.8V, RTON = 1MΩ. TAMB = -40 TO +85C.
25°C
Typ
-40°C to 85°C
Parameter
Conditions
Units
Min
Max
Min
Max
Input Supplies
S0 State (VTT on); EN/PSV = VCCA;
FB > Regulation Point, IVDDQ = 0A
VCCA Operating Current
1500
800
2500
1400
μA
μA
S3 State (VTT off); EN/PSV = VCCA;
FB > Regulation Point, IVDDQ = 0A
VCCA Operating Current
VCCA Operating Voltage
VDDP Operating Current
TON Operating Current
VTTIN Operating Current
5
70
15
1
4.5
5.5
V
FB > Regulation Point, IVDDQ = 0A
RTON = 1MΩ
150
μA
μA
μA
IVTT = 0A
5
VCCA + VDDP + TON
Shutdown Current
EN/PSV = VTTEN = 0V
EN/PSV = VTTEN = 0V
5
1
22
μA
μA
VTTIN Shutdown Current
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SC488
POWER MANAGEMENT
Electrical Characteristics (Cont.)
25°C
Typ
-40°C to 85°C
Min Max
Parameter
Conditions
Units
Min
Max
VDDQ Controller
FB Error Comparator
With Adjustable Resistor Divider
1.500
1.4775 1.5225
2.4625 2.5375
V
Threshold(1)
FB = AGND
FB = VCCA
2.5
1.8
460
265
400
80
V
V
VDDQS Regulation Threshold
1.773
368
1.827
552
RTON = 1MΩ, VDDQ = 1.8V
RTON = 500kΩ, VDDQ = 1.8V
On-Time
ns
ns
212
318
Minimum Off-Time
VDDQS Input Resistance
550
FB < 0.3V
FB > 0.3V
kΩ
91
VDDQS Shutdown
Discharge Resistance
EN/PSV = GND
16
8
Ω
μA
%
FB Leakage Current
-1.0
1.0
VDDQ Smart
Psave Threshold
VTT Controller
REF Source Current
REF Sink Resistance
REF Output Accuracy
10
mA
kΩ
50
900
0.32
8
IREF = 0 to 10mA
882
918
mV
VTT
REF
Shutdown Discharge
Resistance (EN/PSV = GND)
Ω
VTT Output Accuracy
(with respect to REF)
-2A < IVTT < 2A(9)
0
-40
+40
1.0
mV
VTTS Leakage Current
Current Sensing
-1.0
μA
ILIM Current
DL High
10
5
9
11
10
μA
mV
mV
Current Comparator Offset
Zero-Crossing Threshold
VDDQ Fault Protection
PGND1 - ILIM
-10
PGND1 - LX, EN/PSV = 5V
PGND1 - LX, RLIM = 5kΩ
PGND1 - LX, RLIM = 10kΩ
PGND1 - LX, RLIM = 20kΩ
PGND1 - LX
50
100
200
-125
-30
35
80
65
120
230
-90
-25
Current Limit (Positive)(2)
mV
170
-160
-35
Current Limit (Negative)
mV
%
Output Under-Voltage Fault
With Respect to FB Regulation Point
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SC488
POWER MANAGEMENT
Electrical Characteristics (Cont.)
25°C
Typ
-40°C to 85°C
Parameter
Conditions
Units
Min
Max
Min
Max
VDDQ Fault Protection (continued)
Under-Voltage Fault Delay
Under-Voltage Blank Time
Output Over-Voltage Fault
Over-Voltage Fault Delay
PGD Low Output Voltage
PGD Leakage Current
PGD UV Threshold
FB Forced Below UV VTH
From EN High
8
clks(3)
clks(3)
%
440
+16
5
With Respect to FB Regulation Point
FB Above Over-VoltageThreshold
Sink 1mA
+12
+20
μs
0.1
1
V
FB in Regulation, PGD = 5V
With Respect to FB Regulation Point
FB Forced Outside PGD Window
Falling Edge (Hysteresis 100 mV)
μA
%
-10
5
-12
-8
PGD Fault Delay
μs
VCCA Under-Voltage (UVLO)
VTT Fault Protection
UV Lower Threshold
4
3.70
4.35
V
VTT w/rt REF
VTT w/rt REF
-12
+12
50
-16
+8
-8
%
%
OV Upper Threshold
+16
Fault Shutdown Delay
Thermal Shutdown(4)(5)
Inputs/Outputs
VTT Outside OV/UV Window
μs
°C
160
150
170
EN/PSV Low/Low (Disabled)
VTTEN Low (VTT Disabled)
1.2
0.6
Logic Input Low Voltage
Logic Input High Voltage
V
EN/PSV Low/High
(Enabled, Psave Disabled)
1.2
2.4
V
V
VTTEN High (VTT Enabled)
2.4
3.1
EN/PSV High/High
(Enabled, Psave Enabled)
Logic Input High Voltage
EN/PSV Input Resistance
Sourcing
Sinking
1.5
1.0
MΩ
μA
VTTEN Leakage Current
Soft-Start
-1
+1
VDDQ Soft-Start Ramp Time
VTT Soft-Start Ramp Rate(6)
FB Input Thresholds
FB Logic Input Low
EN/PSV High to PGD High
440
5.5
clks(3)
mV/μs
VDDQ Set for 2.5V (DDR1)
VDDQ Set for 1.8V (DDR2)
0.3
V
V
VCCA
- 0.7
FB Logic Input High
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SC488
POWER MANAGEMENT
Electrical Characteristics (Cont.)
25°C
Typ
-40°C to 85°C
Min Max
Parameter
Conditions
Units
Min
Max
Gate Drives
Shoot-Thru Protection
Delay(4)(7)
DH or DL Rising
30
ns
DL Pull-Down Resistance
DL Sink Current
DL Low
VDL = 2.5V
0.8
3.1
2
Ω
A
DL Pull-Up Resistance
DL Source Current
DL High
Ω
A
VDL = 2.5V
1.3
2
DH Pull-Down Resistance
DH Pull-Up Resistance(8)
DH Sink/Source Current
VTT Pull-Up Resistance
VTT Pull-Down Resistance
DH Low, BST - LX = 5V
DH High, BST - LX = 5V
VDH = 2.5V
Ω
Ω
A
2
1.3
0.25
0.32
VTTS < REF
Ω
Ω
VTTS > REF
VTT Peak Sink/Source
Current(9)
2.8
A
Notes:
1) The VDDQ DC regulation level is higher than the FB error comparator threshold by 50% of the ripple voltage.
2) Using a current sense resistor, this measurement relates to PGND1 minus the source of the low-side MOSFET.
3) clks = switching cycles, consisting of one high side and one low side gate pulse.
4) Guaranteed by design.
5) Thermal shutdown latches both outputs (VTT and VDDQ) off, requiring VCCA or EN/PSV cycling to reset.
6) VTT soft-start ramp rate is limited to 5.5mV/μs typical. If the VDDQ/2 ramp rate is slower than 5.5mV/μsec, the VTT soft-start ramp will follow the VDDQ/2
ramp.
7) See Shoot-Through Delay Timing Diagram below.
8) Semtech’s SmartDriver™ FET drive first pulls DH high with a pull-up resistance of 10Ω (typ.) until LX = 1.5V (typ.). At this point, an additional pull-up device
is activated, reducing the resistance to 2Ω (typical). This creates a softer turn-on with minimal power loss, eliminating the need for an external gate or boost
resistor.
9) Provided operation below TJ(MAX) is maintained. VTT output current is also limited by internal MOSFET resistance which is typically 0.32Ω at 25°C and which
increases with temperature, and by available source voltage (typically VDDQ/2).
Shoot-Through Delay Timing Diagram
LX
DH
DL
DL
tplhDL
tplhDH
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SC488
POWER MANAGEMENT
Pin Configuration
Ordering Information
Device(2)
Package(1)
MLPQ-24
SC488
MLP24 Pin Out
SC488MLTRT
Notes:
1) Only available in tape and reel packaging. A reel contains 3000 devices.
2) This product is fully WEEE and RoHS compliant.
1
2
3
4
5
6
PGND2
VTTS
VSSA
TON
PGND1
PGND1
ILIM
18
17
16
T
15
14
VDDP
VDDP
PGD
REF
13
VCCA
Pin Description
Pin #
Pin Name Pin Function
1
2
3
PGND2
VTTS
Power ground for VTT output. Connect to thermal pad and ground plane.
Sense pin for VTT. Connect to VTT at the load.
VSSA
Ground reference for analog circuitry. Connect to thermal pad.
This pin is used to sense VBAT through a pull-up resistor, RTON, which sets the top MOSFET
on-time. Bypass this pin with a 1nF capacitor to VSSA.
4
5
TON
REF
Reference output. An internal resistor divider from VDDQS sets this voltage to 50% VDDQ (nomi-
nal). Bypass this pin with a series 10Ω/1μF to VSSA.
6
7
8
9
VCCA
NC
Analog supply voltage input. Use a 10Ω/1μF RC filter from +5V to VSSA.
No connect.
VDDQS
FB
Sense input for VDDQ. Used to set the on-time for the top MOSFET and also to set REF/VTT.
Feedback select input for VDDQ. See FB Configuration Table.
Enable pin for VTT. Pull this pin low to disable VTT (REF remains present as long as VDDQ is
present).
10
11
VTTEN
Enable/Power Save input pin. Tie to ground to disable VDDQ. Tie to +5V to enable VDDQ and
activate PSAVE mode. Float to enable VDDQ and activate continous conduction mode. If floated,
bypass to VSSA with a 10nF capacitor.
EN/PSV
12
13
NC
No connect.
Power good output for VDDQ. PGD is low if VDDQ is outside the power good thresholds. This
pin is an open drain NMOS output and requires an external pull-up resistor.
PGD
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SC488
POWER MANAGEMENT
Pin Description (Cont.)
14,15
16
VDDP
ILIM
+5V supply voltage input for the VDDQ gate drivers.
Current limit input pin. Connect to drain of low-side MOSFET for RDS(on) sensing or the source
for resistor sensing through a threshold sensing resistor.
17,18
19
PGND1
DL
Power ground for VDDQ switching circuits. Connect to thermal pad and ground plane.
Gate drive output for the low side MOSFET switch.
20
LX
Phase node - the junction between the top and bottom FETs and the output inductor.
Gate drive output for the high side MOSFET switch.
21
DH
22
BST
Boost capacitor connection for the high side gate drive.
Input supply for the high side switch for VTT regulator. Decouple with a 1μF capacitor to
PGND2.
23
24
T
VTTIN
VTT
Output of the linear regulator. Decouple with two (minimum) 10μF ceramic capacitors to
PGND2, locating them directly across pins 24 and 1.
THERMAL
PAD
Pad for heatsinking purposes. Connect to ground plane using multiple vias. Not connected
internally.
Enable Control Logic
Enable Pin Status
Output Status
EN/PSV(1)
VTTEN
VDDQ(3)
VTT(2)
REF(2)
OFF, Discharged (2)
OFF, Discharged (2)
3(
)
OFF, Discharged2(
OFF, Discharged2(
)
OFF, Discharged (2)
0
0
1
1
0
1
0
1
3(
)
)
OFF, Discharged2(
)
ON
ON
OFF, High Impedance
ON
ON
ON
Notes:
1) EN/PSV = 1 = EN/PSV high or floating.
2) Typical discharge resistances: VTT = 0.32Ω. REF = 8Ω.
3) VDDQ is discharged via external series resistance which must be added to SC488 internal discharge resistance to calculate discharge times.
This is separate from any external load on VDDQ.
FB Configuration Table
The FB pin can be configured for fixed or adjustable output voltage as shown.
FB
GND
VDDQ(V)
2.5
VREF & VTT (V)
VDDQS/2
Note
DDR1
VCCA
1.8
VDDQS/2
DDR2
FB Resistors
Adjustable
VDDQS/2
1.5V < VDDQ < 3.0V
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SC488
POWER MANAGEMENT
Block Diagram
VTTEN
VTTIN
VCCA
OTSD
DRVH
VDDQS
+12%
POR/SS
VTT
NOVLP
DRVL
-12%
PGND2
REF
DSCHG
DRVH
DRVL
+12%
FEDLY
VCCA
VTTS
VTTRUN
VTTPGD
EN/PSV
OTSD
TON/ TOFF
TON
DSCHG
POR/SS
-12%
VDDQS
DSCHG
VDDQS
BST
DH
HI
1.5V
REF
-10%
+16%
-30%
VMON
CONTROL
LX
SHOOT
THRU
VDDP
LX
DL
OV
SD
LO
DL
1.5V
PGND1
FB
PWM
SENSE
-10%
UV
OV
-30%
ILIM
SD
PGD
+16%
FAULTMON
VSSA
Figure 1
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SC488
POWER MANAGEMENT
Application Information
+5V Bias Supplies
The SC488 requires an external +5V bias supply in addi-
tion to the battery. If stand-alone capability is required,
the +5V supply can be generated with an external linear
regulator. To minimize crosstalk, the controller has seven
supply pins: VDDP (2 pins), PGND1 (2 pins), PGND2, VCCA
and AGND.
§ V
OUT
·
ꢁ12
3
¨
¸
¸
¹
T
3.3x10
x (RTONꢀ 37x10 ) x
ꢀ 50ns
ON
¨
V
IN
©
RTON is a resistor connected between the input supply and
the TONpin.
VDDQ/VTT Enable & Power-Save
The EN/PSV pin controls the VDDQ supply and the REF
output (1/2 of VDDQ). VTTEN enables the VTT supply. The
VTT and VDDQ supplies may be enabled independently.
When EN/PSV is tied to VCCA the VDDQ controller is en-
abled in power-save mode. When the EN/PSV pin is floated,
an internal resistor divider activates the VDDQ controller
with power-save disabled. If PSAVE is enabled, the SC488
PSAVE comparator looks for inductor current to cross zero
on eight consecutive cycles. Once observed, the controller
enters power-save and turns off the low-side MOSFET when
the current crosses zero. To improve the efficiency and
add hysteresis, the on-time is increased by 20% in power-
save. The efficiency improvement at light loads more than
offsets the disadvantage of slightly higher output ripple. If
the inductor current does not cross zero on any switching
cycle, the controller immediately exits power-save. Since
the controller counts zero crossings, the converter can
sink current as long as the current does not cross zero on
eight consecutive cycles. This allows the output voltage
to recover quickly in response to negative load steps even
when power-save is enabled.
The controller requires its own AGND plane which should
be tied by a single trace to the negative terminal of the
output capacitor. All external components referenced to
AGND in the schematic should then be connected to the
AGND plane. The supply decoupling capacitor should be
tied between VCCA and AGND. A single 10Ω resistor should
be used to decouple the VCCA supply from the main VDDP
supply. PGND can then be a separate plane which is not
used for routing analog traces. All PGND connections
should connect directly to this plane with special attention
given to avoiding indirect connections between AGND and
PGND which will create ground loops. As mentioned above,
the AGND plane must be connected to the PGND plane at
the negative terminal of the output capacitor. The VDDP
input provides power to the upper and lower gate drivers.
A decoupling capacitor for the VDDP supply and PGND is
recommended. No series resistor between VDDP and the
5 volt bias is required.
Pseudo-Fixed Frequency Constant On-Time
PWM Controller
The PWM control method is a constant-on-time, pseudo-
fixed frequency PWM controller, see Figure 1. The ripple
voltage seen across the output capacitor’s ESR provides
the PWM ramp signal, eliminating the need for a current
sense resistor. The on-time is determined by a one-shot
whose period is proportional to output voltage, and in-
versely proportional to input voltage. A separate one-shot
sets the minimum off-time (typically 425ns).
VDDQ Voltage Selection
VDDQ voltage is set using the FB pin. Grounding FB sets
VDDQ to fixed 2.5V. Connecting FB to +5V sets VDDQ to
fixed 1.8V. VDDQ can also be adjusted from 1.5 to 3.0V
using external resistors, see Figure 2. The voltage at FB is
then compared to the internal 1.5V reference.
To VDDQ output capacitor
On-Time One-Shot (TON)
The on-time one-shot comparator has two inputs. One
input looks at the output voltage, while the other input
samples the input voltage and converts it to a proportional
current. This current charges an internal on-time capaci-
tor. The TON time is the time required for this capacitor
to charge from zero volts to VOUT, thereby making the
on-time of the high-side switch directly proportional to
output voltage and inversely proportional to input volt-
age. This implementation results in a nearly constant
switching frequency without the need of a clock generator.
C
R2
To SC488 FB (pin 9)
R3
Figure 2
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SC488
POWER MANAGEMENT
Application Information
Referencing Figure 2, the equation for setting the output The schematic of RDSON sensing circuit is shown in Figure
voltage is: 4 with RILIM = R1 and RDSON of Q2.
+5V
+VIN
R2
R3
⎛
⎝
⎞
⎟
⎠
1
V
+
1.5
⋅
⎜
out
+
D1
C2
C1
Q1
Current Limit Circuit
BST
DH
L1
Current limiting of the SC488 can be accomplished in two
ways. The on-state resistance of the low-side MOSFETs
can be used as the current sensing element, or a sense
resistor in the low-side source can be used if greater ac-
curacy is desired. RDSON sensing is more efficient and
less expensive. In both cases, the RILIM resistor between
the ILIM pin and LX sets the over-current threshold. This
resistor RILIM is connected to a 10μA current source within
the SC488 which is turned on when the low-side MOSFET
turns on. When the voltage drop across the sense resistor
or low-side MOSFET equals the voltage across the RILIMresis-
tor, current limit will activate. The high-side MOSFET will
not be allowed to turn on until the voltage drop across the
sense element (resistor or MOSFET) falls below the voltage
across the RILIM resistor.
LX
Vout
ILIM
VDDP
DL
R1
PGND
D2
+
C3
Q2
SC488
Figure 4
Similarly, for resistor sensing, the current through the lower
MOSFET and the source sense resistor develops a voltage
that opposes the voltage developed across RILIM. When the
voltage developed across the RSENSE resistor reaches voltage
drop across RILIM, an over-current exists and the high-side
MOSFET will not be allowed to turn on. The over-current
equation when using an external sense resistor is:
The current sensing circuit actually regulates the inductor
valley current, see Figure 3. This means that if the current
limit is set to 10A, the peak current through the inductor
would be 10A plus the peak ripple current, and the average
current through the inductor would be 10A plus 1/2 the
peak-to-peak ripple current.
R
ILIM
IL
Valley 10ƫA x
ꢂ ꢃ
OC
R
SENSE
Schematic of resistor sensing circuit is shown in Figure 5
with RILIM = R1 and RSENSE = R4.
+5V
+VIN
IPEAK
+
D1
C2
C1
ILOAD
Q1
BST
DH
LX
ILIM
VDDP
DL
L1
I LIMIT
Vout
PGND
D2
+
C3
Q2
SC488
TIME
R4
R1
Valley Current - Limit Threshold Point
Figure 5
Figure 3
© 2006 Semtech Corp.
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SC488
POWER MANAGEMENT
Application Information (Cont.)
Power Good Output
POR, UVLO and Soft-Start
The VDDQ controller has a power good (PGD) output. Power An internal power-on reset (POR) occurs when VCCA
good is an open-drain output and requires a pull-up resistor. exceeds 3V, resetting the fault latch and soft-start counter,
When the output voltage is +16%/-10% from its nominal and preparing the PWM for switching. VCCA under-voltage
voltage, PGD gets pulled low. It is held low until the output lockout (UVLO), circuitry inhibits switching and tristates
voltage returns to within +16%/-10% of nominal. PGD is the drivers until VCCA rises above 4.2V. At this time the
also held low during start-up and will not be allowed to circuit will come out of UVLO and begin switching and the
transition high until soft-start is over and the output reaches softstart circuit will progressively limit the output current
90% of its set voltage. There is a 5μs delay built into the over a pre-determined time period. The ramp occurs in
PGD circuit to prevent false transitions.
four steps: 25%, 50%, 75% and 100%, thereby limiting
the slew rate of the output voltage. There is 100mV of
hysteresis built into the UVLO circuit and when VCCA falls
to 4.1V the output drivers are shutdown and tristated.
Output Over-Voltage Protection
When the VDDQ output exceeds 16% of its set voltage, the
low-side MOSFET is latched on. It stays latched and the
SMPS stays off until the EN/PSV input is toggled or VCCA
is recycled. There is a 5μs delay built into the OV protec-
tion circuit to prevent false transitions. During a VDDQ OV
shutdown, VTT is alive until VDDQ falls to typically 0.4V, at
which point VTT is tri-stated.
MOSFET Gate Drivers
The DH and DL drivers are optimized for moderate,
highside, and larger low-side power MOSFETs. An adaptive
dead-time circuit monitors the DL output and prevents the
high-side MOSFET from turning on until DL is fully off, and
conversely, monitors the DH output and prevents the low
side MOSFET from turning on until DH is fully off.
When VTT exceeds 12% above its set voltage, the VTT
regulator will tristate. There is a 50μs delay to prevent false
OV trips due to transients or noise. The VDDQ regulator
continues to operate after VTT OV shutdown. The VTT OV
condition is removed by toggling VTTEN or EN/PSV, or by
recycling VCCA.
(Note: be sure there is low resistance and low inductance
between the DH and DL outputs to the gate of each MOSFET.)
Design Procedure
Prior to designing a switch mode supply for a notebook
computer, the input voltage, load current, switching
frequency and inductor ripple current must be specified.
Smart Over-Voltage Protection
In some applications, the active loads on VDDQ can actu-
ally leak current into VDDQ. If PSAVE mode is enabled at
very light loading, this leak can cause VDDQ to slowly rise
and reach the OV threshold, causing a hard shutdown. To
prevent this, the SC488 uses Smart OVP to prevent this.
When VDDQ exceeds 8% above nominal, DL drives high to
turn on the low-side MOSFET, which starts to draw current
from VDDQ via the inductor. When VDDQ drops to the FB
trip point, a normal TON switching cycle begins. This pre-
vents a hard OV shutdown.
Input Voltage Range
The maximum input voltage (VINMAX) is determined by the
highest AC adaptor voltage. The minimum input voltage
(VINMIN) is determined by the lowest battery voltage after
accounting for voltage drops due to connectors, fuses and
battery selector switches.
Maximum Load Current
There are two values of load current to consider:
continuous load current and peak load current.
Continuous load current has more to do with thermal
stresses and therefore drives the selection of input
capacitors, MOSFETs and commutation diodes. Peak load
current determines instantaneous component stresses
and filtering requirements such as, inductor saturation,
output capacitors and design of the current limit circuit.
Output Under-Voltage Protection
When VDDQ falls 30% below its set point for eight clock
cycles, the VDDQ output is shut off; the DL/DH drives are
pulled low to tristate the MOSFETS, and the SMPS stays
off until the Enable input is toggled or VCCA is recycled.
When VTT is 12% below its set voltage the VTT output is
tristated. There is a 50μs delay for VTT built into the UV
protection circuits to prevent false transitions.
© 2006 Semtech Corp.
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SC488
POWER MANAGEMENT
Application Information (Cont.)
Switching Frequency
+5V
+VIN
Switching frequency determines the trade-off between
size and effi ciency. Higher frequency increases switch-
ing losses in the MOSFETs, since losses are a function of
F*VIN2. Knowing the maximum input voltage and budget
for MOSFET switches usually dictates the final design.
+
D1
C2
C1
Q1
14
13
12
11
10
9
BST
DH
LX
ILIM
VDDP
DL
L1
0.5V - 5.5V
Inductor Ripple Current
8
R1
R2
R3
C4
PGND
10pF
D2
+
Low inductor values result in smaller size, but create high-
er ripple current and are less efficient because of the high
AC current flowing in the inductor. Higher inductor values
do reduce the ripple current and are more efficient, but
are larger and more costly. The selection of the ripple cur-
rent is based on the maximum output current and tends
to be between 20% to 50% of the maximum load current.
Again, cost, size and efficiency all play a part in the selec-
tion process.
C3
SC488
Q2
FBK
Figure 6
The best way for checking stability is to apply a zero to
full load transient and observe the output voltage ripple
envelope for overshoot and ringing. Over one cycle of ring-
ing after the initial step is a sign that the ESR should be
increased.
Stability Considerations
Unstable operation shows up in two related but distinctly
different ways: double pulsing and fast-feedback loop in-
stability. Double-pulsing occurs due to noise on the output
or because the ESR is too low, causing insufficient voltage
ramp in the output signal. This causes the error amplifier to
trigger prematurely after the 400ns minimum off-time has
expired. Double-pulsing will result in higher ripple voltage at
the output, but in most cases is harmless. In some cases,
however, double-pulsing can indicate the presence of loop
instability, which is caused by insufficient ESR. One simple
way to solve this problem is to add some trace resistance
in the high current output path. A side effect of doing this
is output voltage droop with load. Another way to eliminate
doubling-pulsing is to add a 10pF capacitor across the
upper feedback resistor divider network. This is shown in
Figure 6, by capacitor C4 in the schematic. This capacitance
should be left out until confirmation that double-pulsing ex-
ists. Adding this capacitance will add a zero in the transfer
function and should eliminate the problem. It is best to
leave a spot on the PCB in case it is needed.
SC488 ESR Requirements
The constant on-time control used in the SC488 regulates
the ripple voltage at the output capacitor. This signal
consists of a term generated by the output ESR of the
capacitor and a term based on the increase in voltage
across the capacitor due to charging and discharging
during the switching cycle. The minimum ESR is set to
generate the required ripple voltage for regulation. For most
applications the minimum ESR ripple voltage is dominated
by PCB layout and the properties of SP or POSCAP type
output capacitors. For applications using ceramic output
capacitors, the absolute minimum ESR must be considered.
If the ESR is low enough the ripple voltage is dominated
by the charging of the output capacitor. This ripple voltage
lags the on-time due to the LC poles and can cause double
pulsing if the phase delay exceeds the off-time of the
converter. Referring to Figure 5 on Page 10, the equation
for the minimum ESR as a function of output capacitance
and switching frequency and duty cycle is:
Loop instability can cause oscillations at the output as a
response to line or load transients. These oscillations can
trip the over-voltage protection latch or cause the output
voltage to fall below the tolerance limit.
Fs - 200000
Fs
§
¨
·
¸
§
¨
©
·
¸
¹
1 ꢀ 3 x
VOUT
1.5V
§
¨
©
·
¸
¹
¨
¨
¸
¸
ESR !
x
2
2 x Ư x Cout xFs x 1 ꢁ D
ꢂ ꢃ
¨
©
¸
¹
© 2006 Semtech Corp.
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SC488
POWER MANAGEMENT
Application Information (Cont.)
of trace resistance between the inductor and output ca-
pacitor. This trace resistance should be optimized so that
at full load the output droops to near the lower regulation
limit. Passive droop minimizes the required output capaci-
tance because the voltage excursions due to load steps
are reduced.
Dropout Performance
The output voltage adjust range for continuous-conduction
operation is limited by the fi xed 400nS (typical) Minimum
Off-time One-shot. For best dropout performance, use
the slowest on-time setting of 200KHz. When working
with low input voltages, the duty-factor limit must be
calculated using worst-case values for on and off times.
The IC dutyfactorlimitation is given by:
Board components and layout also influence DC accuracy.
The use of 1% feedback resistors contributes additional
error. If tighter DC accuracy is required use 0.1% feedback
resistor.
TON(MIN)
DUTY
TON(MIN) ꢀ TOFF(MAX)
The output inductor value may change with current. This
will change the output ripple and thus the DC output volt-
age (it will not change the frequency).
Be sure to include inductor resistance and MOSFET on-
state voltage drops when performing worst-case dropout
duty-factor calculations.
Switching frequency variation with load can be minimized
by choosing lower RDSON MOSFETs. High RDSON MOSFETS
will cause the switching frequency to increase as the load
current increases. This will reduce the ripple and thus
the DC output voltage. This inherent droop should be
considered when deciding if passive droop is required, or
if passive droop is desired in order to further reduce the
output capacitance.
SC488 System DC Accuracy (VDDQ Controller)
Three IC parameters affect VDDQ accuracy: the internal
1.5V reference, the error comparator offset voltage, and
the switching frequency variation with line and load.
The internal 1.5%, 1.5V reference contains two error
components, a 0.5% DC error and a 0.5% supply and tem-
perature error. The error comparator offset is trimmed so
that it trips when the feedback pin is nominally 1.5 volts
+/-1.5% at room temperature. The comparator offset trim
compensates for any DC error in the reference. Thus, the
percentage error is the sum of the reference variation
over supply and temperature and the offset in the error
comparator, or 2.0% total.
Output DC Accuracy (VTT Output)
The VTT accuracy compared to VDDQ is determined by two
parameters: the REF output accuracy, and the VTT output
accuracy with respect to REF. The REF output is generated
internally from the VDDQS (sense input), and tracks VDDQS
with 2% accuracy. This REF output becomes the reference
for the VTT regulator. The VTT regulator then tracks REF
within +/-40mV (typically zero). The total VTT/VDDQ track-
ing accuracy is then:
The on-time pulse in the SC488 is calculated to give a
pseudo-fixed frequency. Nevertheless, some frequency
variation with line and load can be expected. This varia-
tion changes the output ripple voltage. Because constant
on-time converters regulate to the valley of the output
ripple, ½ of the output ripple appears as a DC regulation
error. For example, If the output ripple is 50mV with VIN =
6 volts, then the measured DC output will be 25mV above
the comparator trip point. If the ripple increases to 80mV
with VIN = 25 volts, then the measured DC output will be
40mV above the comparator trip. The best way to minimize
this effect is to minimize the output ripple.
VDDQS
VTT error
x r 0.02 r 40mV
2
DDR Reference Buffer
The reference buffer is capable of sourcing 10mA. The
reference buffer has a class A output stage and therefore
will not sink significant current; there is an internal 50 kΩ
(typical) pulldown to ground. If higher current sinking is
required, an external pulldown resistor should be added.
To compensate for valley regulation it is often desirable
to use passive droop. Take the feedback directly from the Make sure that the ground side of this pulldown is tied to
output side of the inductor, incorporating a small amount
the VTT ground plane near the PGND2 pin.
© 2006 Semtech Corp.
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SC488
POWER MANAGEMENT
Application Information (Cont.)
For stability, place a 10Ω/1μF series combination from REF
to VSSA. If REF load capacitance exceeds 1μF, place at
least 10Ω’s in series with the load capacitance to prevent
instability. It is possible to use only one 10Ω resistor, by
connecting the load capacitors in parallel with the 1μF,
and connecting the load REF to the capacitor side of the
10Ω resistor. (See the Typical Application Circuit on Page
1.) Note that this resistor creates an error term when REF
has a DC load. In most applications this is not a concern
since the DC load on REF is negligible.
ª
«
º
V
ꢁ12
ꢁ12
3
3
OUT
ꢁ 9
s
»
t
3.3 x 10
x
x
ꢂ
R
ꢀ 37 x 10
tON
ꢃ
ꢃ
x
x
ꢀ 50 x 10
ON_VBAT(MIN)
V
«
¬
»
BAT(MIN)
¼
and,
ª
º
V
OUT
ꢁ 9
s
«
»
t
3.3 x 10
ꢂ
R
ꢀ 37 x 10
tON
ꢀ 50 x 10
ON_VBAT(MAX)
V
«
¬
»
¼
BAT(MAX)
From these values of tON we can calculate the nominal
switching frequency as follows:
V
OUT
f
Hz
Design Procedure
SW_VBAT(MIN)
§
¨
·
¸
V
x t
BAT(MIN) ON_VBAT(MIN)
Prior to designing a switching output and making com-
ponent selections, it is necessary to determine the input
voltage range and output voltage specifications. To dem-
onstrate the procedure, the output for the schematic in
Figure 7 on page 19 will be designed.
©
¹
and,
V
OUT
f
Hz
SW_VBAT(MAX)
§
·
¸
V
x t
ON_VBAT(MAX)
¨
BAT(MAX)
©
¹
The maximum input voltage (VBAT(MAX)) is determined by the
highest AC adaptor voltage. The minimum input voltage
(VBAT(MIN)) is determined by the lowest battery voltage af-
ter accounting for voltage drops due to connectors, fuses
and battery selector switches. For the purposes of this
design example we will use a VBAT range of 8V to 20V to
design VDDQ.
tON is generated by a one-shot comparator that samples
VBAT via RtON, converting this to a current. This current is
used to charge an internal 3.3pF capacitor to VOUT. The
equations above reflect this along with any internal com-
ponents or delays that influence tON. For our example we
select RtON = 1MΩ:
Four parameters are needed for the design:
tON_VBAT(MIN) = 820ns and, tON_VBAT(MAX) = 358ns
fSW_VBAT(MIN) = 274kHz and fSW_VBAT(MAX) = 251kHz
1. Nominal output voltage, VOUT. We will use 1.8V with
internal feedback resistors (FB pin tied to VCCA).
2. Static (or DC) tolerance, TOLST (we will use +/-2%).
3. Transient tolerance, TOLTR and size of transient (we
will use +/-8% for a 10A to 5A load release for this
demonstration).
Now that we know tON we can calculate suitable values for
the inductor. To do this we select an acceptable inductor
ripple current. The calculations below assume 50% of IOUT
which will give us a starting place.
4. Maximum output current, IOUT (we will design for 10A).
Switching frequency determines the trade-off between
size and efficiency. Increased frequency increases the
switching losses in the MOSFETs, and losses are a func-
tion of VBAT2. Knowing the maximum input voltage and
budget for MOSFET switches usually dictates where the
design ends up. The default RtON values of 1MΩ and
715kΩ are suggested only as a starting point.
t
ON_VBAT(MIN)
L
ꢂ
V
ꢁ V
ꢃ
x
H
VBAT(MIN)
BAT(MIN) OUT
§
¨
·
¸
0.5 xI
OUT
©
¹
and,
t
ON_VBAT(MAX)
L
ꢂ
V
ꢁ V
OUT
ꢃ
x
H
VBAT (MAX)
BAT(MAX)
§
¨
·
¸
0.5 xI
OUT
©
¹
The first thing to do is to calculate the on-time, tON, at
VBAT(MIN) and VBAT(MAX), since this depends only upon VBAT, VOUT
and RtON.
For our example,
LVBAT(MIN) = 1.02μH and LVBAT(MAX) = 1.30μH,
© 2006 Semtech Corp.
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SC488
POWER MANAGEMENT
Application Information (Cont.)
We will select an inductor value of 1.5μH to reduce the
RESR_ST(MAX) = 8.3mΩ
ripple current, which can be calculated as follows:
§
¨
·
¸
ERR ꢁ ERR
TR
DC
©
¹
R
ESR_ TR (MAX)
Ohms
t
ON_ VBAT ( MIN )
I
§
¨
·
¸
§
¨
·
¸
RIPPLE_VBAT( MAX)
2
I
V
ꢁ V
x
A
RIPPLE_VBAT(MIN)
BAT (MIN)
OUT
PꢁP
©
¹
I
ꢀ
TRANS
L
¨
©
¸
¹
and,
where ERRTR is the transient output tolerance. For this
case, ITRANS is the load transient of 5A (10A - 5A).
t
ON_ VBAT ( MAX )
PꢁP
L
§
·
x
¸
I
V
ꢁ V
A
¨
RIPPLE_VBAT(MAX)
BAT (MAX)
OUT
©
¹
For our example:
For our example:
RIPPLE_VBAT(MIN) = 3.39AP-P and IRIPPLE_VBAT(MAX) = 4.34AP-P
ERRTR = 144mV and ERRDC = 18mV, therefore,
RESR_TR(MAX) = 17.6mΩ for a full 5A load transient.
I
We will select a value of 6mΩ maximum for our design,
which would be achieved by using two 12mΩ output ca-
pacitors in parallel. Now that we know the output ESR we
can calculate the output ripple voltage:
From this we can calculate the minimum inductor current
rating for normal operation:
I
RIPPLE_VBAT( MAX )
I
I
ꢀ
A
(MIN)
INDUCTOR ( MIN )
OUT (MAX)
2
V
R
x I
V
RIPPLE_VBAT(MIN)
RIPPLE_VBAT(MIN) PꢁP
ESR
For our example:
INDUCTOR(MIN) = 12.2A(MIN)
and,
I
V
R
x I
V
RIPPLE_VBAT(MAX)
ESR
RIPPLE_VBAT(MAX) PꢁP
Next we will calculate the maximum output capacitor
equivalent series resistance (ESR). This is determined by
calculating the remaining static and transient tolerance
allowances. Then the maximum ESR is the smaller of the
calculated static ESR (RESR_ST(MAX)) and transient ESR
(RESR_TR(MAX)):
For our example:
VRIPPLE_VBAT(MAX) = 20mVP-P and VRIPPLE_VBAT(MIN) = 26mVP-P
Note that in order for the device to regulate in a controlled
manner, the ripple content at the feedback pin, VFB, should
be approximately 15mVP-P at minimum VBAT, and worst case
no smaller than 10mVP-P. Note that the voltage ripple at
FB is smaller than the voltage ripple at the output capaci-
tor, due to the resistor divider. Also, when using internal
feedback (FB pin tied to 5V or GND), the FB resistor di-
vider is actually inside the IC. If VRIPPLE_VBAT(MIN) as seen at
the FB point is less than 15mVP-P - whether internal or ex-
ternal FB is used - the above component values should be
revisited in order to improve this. For our example, since
the internal divider reduces the ripple signal by a factor of
(1.5V/1.8V), the internal FB ripple values are then 17mV
and 22mV, which is above the 15mV minimum.
ERR ꢁ ERR
ST
x 2
DC
RIPPLE _ VBAT(MAX)
R
Ohms
ESR_ ST(MAX)
I
Where ERRST is the static output tolerance and ERRDC is
the DC error. The DC error will be 1% plus the tolerance
of the internal feedback. (Use 2% for external feedback
which is 1% plus another 1% for the external resistors.)
For our example:
ERRST = 36mV and, ERRDC = 18mV, therefore,
© 2006 Semtech Corp.
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SC488
POWER MANAGEMENT
Application Information (Cont.)
When using external feedback, and with VDDQ greater
than 1.5V, a small capacitor, CTOP, can be used in parallel
with the top feedback resistor, RTOP, in order to ensure that
ripple at VFB is large enough. CTOP should not be greater
than 100pF. The value of CTOP can be calculated as fol-
lows, where RBOT is the bottom feedback resistor. Firstly
calculating the value of ZTOP required:
The minimum output capacitance is calculated as fol-
lows:
I
RIPPLE_VBAT(MAX)
I
I
ꢀ
A
init
OUT(MAX)
2
and,
R
BOT
Z
x
ꢂ
V
ꢁ 0.015
RIPPLE_VBAT (MIN)
ꢃ
Ohms
2
2
TOP
ꢂ
Iinit
ꢃ
ꢁ
ꢂ
Ifinal
ꢃ
0.015
C
L x
F
OUT(MIN)
2
2
ꢂ
POSLIM
ꢁ V
ꢃ
TR
OUT_ST_POS
Secondly calculating the value of CTOP required to achieve
this:
This calculation assumes the condition of a full-load to no-
load step transient occurring when the inductor current is
at its highest. The capacitance required for smaller tran-
sient steps my be calculated by substituting the desired
current for the Ifinal term. In this case Ifinal is set for 5A.
§
¨
¨
©
·
¸
¸
¹
1
1
ꢁ
Z
R
TOP
TOP
C
F
TOP
2 x Ư x f
SW_VBAT(MIN)
Since our example uses internal feedback ,this method
cannot be used, however the voltage seen at the internal
FB point is already greater than 15mV.
For our example:
COUT(MIN) = 392μF.
Next we need to calculate the minimum output capaci-
tance required to ensure that the output voltage does not
exceed the transient maximum limit, POSLIMTR, starting
from the actual static maximum, VOUT_ST_POS, when a load
release occurs:
We will select 440μF, using two 220μF, 12mΩ capacitors
in parallel.
Next we calculate the RMS input ripple current, which is
largest at the minimum battery voltage:
V
V
ꢀ ERR
DC
V
OUT_ST_POS
OUT
I
OUT
I
V
x
ꢂ
V
ꢁ V
ꢃ
x
A
RMS
IN (RMS)
OUT
BAT (MIN)
OUT
For our example:
VOUT_ST_POS = 1.818V,
POSLIM V
V
BAT _MIN
For our example:
x TOL
V
IIN(RMS) = 4.17ARMS
TR
TR
OUT
Input capacitors should be selected with sufficient ripple
current rating for this RMS current, for example a 10μF,
1210 size, 25V ceramic capacitor can handle approxi-
mately 3ARMS. Refer to manufacturer’s data sheets and
derate appropriately.
Where TOLTR is the transient tolerance. For our example:
POSLIMTR = 1.944V,
© 2006 Semtech Corp.
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SC488
POWER MANAGEMENT
Application Information (Cont.)
Finally, we calculate the current limit resistor value. As de-
scribed in the current limit section, the current limit looks
at the “valley current”, which is the average output cur-
rent minus half the ripple current.
is always VDDQ2, regardless of whether the regulator is
sinking or sourcing current. In either case the power lost in
the VTT regulator is VTT * |ITT|. The average or long-term
value for ITT should be used. The thermal resistance of the
MLPQ package is affected by PCB layout and the available
ground planes and vias which conduct heat away. A typical
value is 29°C/watt.
I
RIPPLE_VBAT(MIN)
I
I
ꢁ
A
VALLEY
OUT
2
The ripple at low battery voltage is used because we want
to make sure that current limit does not occur under nor-
mal operating conditions.
Example:
ICCA = 1.5mA
VCCA = VDDP = 5V
VTT = 1.25V
IDDP = 25mA
ITT = 0.75A (average)
R
x 1.4
ꢁ6
Ambient = 45 degrees C
Thermal resistance = 29
DS (ON)
R
ꢂ
I
x 1.2
VALLEY
ꢃ
x
Ohms
ILIM
10 x10
PD = 5V • 0.0015 A + 5V • 0.025A + 0.9V • |0.75|A
PD = 0.808W
For our example:
IVALLEY = 8.31A, RDS(ON) = 4mΩ, giving RILIM = 5.62kΩ
TJ = TAMB + PD • TJA = 45 + 0.808W • 29°C/W = 68.4°C
Layout Guidelines
Thermal Considerations
One (or more) ground planes are recommended to
minimize the effect of switching noise and copper losses,
and maximize heat dissipation. The IC ground reference,
VSSA, should be connected to PGND1 and PGND2 as a
star connection at the thermal pad, which in connects
using 4 vias to the ground plane. All components that are
referenced to VSSA should connect to it directly on the chip
side, and not through the ground plane.
The junction temperature of the device may be calculated
as follows:
TJ = TAMB + θJA
where TJ is the junction temperature, TAMB is the ambient
temperature, PD is the total SC488 device dissipation. The
SC488 device dissipation can be determined using:
VDDQ: The feedback trace must be kept far away from
noise sources such as switching nodes, inductors and
gate drives. Route the feedback trace in a quiet layer if
possible, from the output capacitor back to the chip. Chip
supply decoupling capacitors (VCCA, VDDP) should be
located next to the pins (VCCA/VSSA, VDDP/PGND1) and
connected directly to them on the same side.
PD = VCCA • ICCA + VDDP • IDDP + VTT • |ITT|
The fi rst two terms are losses for the analog and gate drive
circuits and generally do not present a thermal problem.
Typical ICCA (VCCA operating current) is roughly 1.5mA,
which creates 7.5mW loss from the 5V VCCA supply. The
VDDP supply current is used to drive the MOSFETs and
can be much higher, on the order of 30mA, which can
create up to 150mW of dissipation.
VTT: Because of the high bandwidth of the VTT regulator,
proper component placement and routing is essential to
prevent unwanted high-frequency oscillations which can
be caused by parasitic inductance and noise. The input
capacitors should be located at the VTT input pins (VTTIN
and PGND2), as close as possible to the chip to minimize
parasitics. Output capacitors should be directly located at
the VTT output pins (VTT and PGND2). The routing of the
The last term, VTT * |ITT|, is the most signifi cant term
from a thermal standpoint. The VTT regulator is a linear
device and will dissipate power proportional to the VTT
current and the voltage drop across the regulator. If VTT
= VDDQ/2, then the voltage drop across the regulator
© 2006 Semtech Corp.
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SC488
POWER MANAGEMENT
Application Information (Cont.)
feedback signal VTTS is critical. The trace from VTTS (pin 3. Input power ground and output power ground should
2) should be connected directly to the output capacitor that
is farthest from VTT (pin24); route this signal away from
noise sources such as the VDDQ power train or highspeed
digital signals.
not connect directly, but through the ground planes
instead.
Finally, connecting the control and switcher power sections
should be accomplished as follows:
The switcher power section should connect directly to the
ground plane(s) using multiple vias as required for current 1. Route VDDQ feedback trace in a “quiet” layer, away
handling (including the chip power ground connections). from noise sources.
Power components should be placed to minimize loops 2. Route DL, DH and LX (low side FET gate drive, high
and reduce losses. Make all the connections on one side
of the PCB using wide copper fi lled areas if possible. Do
not use “minimum” land patterns for power components.
Minimize trace lengths between the gate drivers and the
gates of the MOSFETs to reduce parasitic impedances
(and MOSFET switching losses); the low-side MOSFET is
most critical. Maintain a length to width ratio of <20:1 for
gate drive signals. Use multiple vias as required by current
handling requirement (and to reduce parasitics) if routed
on more than one layer. Current sense connections must
side FET gate drive and phase node) to the chip using
wide traces with multiple vias if using more than one
layer. These connections are to be as short as possible
for loop minimization, with a length to width ratio less
than 20:1 to minimize impedance. DL is the most
critical gate drive, with power ground as its return
path. LX is the noisiest node in the circuit, switching
between VBAT and ground at high frequencies, thus
should be kept as short as practical. DH has LX as its
return path.
always be made using Kelvin connections to ensure an 3. BST is also a noisy node and should be kept as short
accurate signal. The layout can be generally considered as possible.
in three parts; the control section referenced to VSSA, the 4. Connect PGND1 pins on the chip directly to the VDDP
VTT output, and the switcher power section.
decoupling capacitor and then drop vias directly to
the ground plane. Locate the current limit resistor
(if used) at the chip with a kelvin connection to the
phase node.
Looking at the control section first, locate all components
referenced to VSSA on the schematic and place these
components at the chip. Connect VSSA using a wide
(>0.020”) trace. Very little current fl ows in the chip ground
therefore large areas of copper are not needed. Connect the
VSSA pin directly to the thermal pad under the device as
the only connection from PGND1 and PGND2 from VSSA.
Decoupling capacitors for VCCA/VSSA and VDDP/PGND1
should be placed is as close as possible to the chip. The
feedback components connected to FB, along with the
VDDQ sense components, should also be located at the
chip. The feedback trace from the VDDQ output should
route from the top of the output capacitors, in a quiet layer
back to the FB components.
Next, looking at the switcher power section, there are a few
key guidelines to follow:
1. There should be a very small input loop, well
decoupled.
2. The phase node should be a large copper pour, but
still compact since this is the noisiest node.
© 2006 Semtech Corp.
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SC488
POWER MANAGEMENT
Application Information (Cont.)
D1
MBR0530
C1 0.1uF
5V
VBAT
Q1
IRF7811
C2
10uF/25V
1210
C3
10uF/25V
1210
L1
1.5uH
VDDQ
C4
1uF
Vishay IHLP-5050
Q2
VDDQ
IRF7832
VTT
C8
0.1uF
R1
C5
10uF
0805
C6
10uF
0805
C7
10uF
0805
5.62K
+
+
C10*
C9*
C11
0.1uF
1
2
3
4
5
6
18
PGND2
VTTS
VSSA
TON
PGND1
PGND1
ILIM
220uF/12m 220uF/12m
U1
17
*Sany o 4TPL220MC
S
C
4
8
8
16
R2 1MEG
15
VBAT
5V
VDDP
VDDP
R3
10R
C12
1uF
14
REF
5V
REF
R4
R5
10R
13
10K
VCCA
PGD
PAD
PGOOD
PAD
C15
1uF
C13
1nF
C14
1uF
EN/PSV
VTT_EN
C16
0.1uF
VDDQ
1.8V fixed: connect to 5V
2.5V fixed: connect to VSSA
Adjustable 1.5V-3.0V: connect to divider netw ork
Figure 7 - Reference Design
© 2006 Semtech Corp.
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SC488
POWER MANAGEMENT
Typical Characteristics
1.8V Efficiency vs. Output Current
Powersave Mode
1.8V Efficiency vs. Output Current
Continuous Conduction Mode
100%
90%
80%
70%
60%
50%
100%
90%
80%
70%
60%
50%
VBAT = 10
VBAT = 10
VBAT = 20
VBAT = 20
0
2
4
6
8
10
0
2
4
6
8
10
IOUT (A)
IOUT (A)
2.5V Efficiency vs. Output Current
2.5V Efficiency vs. Output Current
Powersave Mode
Continuous Conduction Mode
100%
90%
80%
70%
60%
50%
100%
90%
80%
70%
60%
50%
VBAT = 10
VBAT = 10
VBAT = 20
VBAT = 20
0
2
4
6
8
10
0
2
4
6
8
10
IOUT (A)
IOUT (A)
1.5V Efficiency vs. Output Current
1.5V Efficiency vs. Output Current
Powersave Mode
Continuous Conduction Mode
100%
90%
80%
70%
60%
50%
100%
90%
80%
70%
60%
50%
VBAT = 10
VBAT = 10
VBAT = 20
VBAT = 20
0
2
4
6
8
10
0
2
4
6
8
10
IOUT (A)
IOUT (A)
© 2006 Semtech Corp.
20
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SC488
POWER MANAGEMENT
Typical Characteristics (Cont.)
Load Transient Response, 0 to 5A,
Load Transient Response, 0 to 5A, Psave Mode
Continuous Conduction Mode
Load Transient Response, 5 to 0A,
Continuous Conduction Mode
Load Transient Response, 5 to 0A, Psave Mode
Load Transient Response, 5 to 10A
Load Transient Response, 10 to 5A
© 2006 Semtech Corp.
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SC488
POWER MANAGEMENT
Typical Characteristics (Cont.)
VTT Load Transient Response,
1A Sink/Source, Psave Mode
VTT Load Transient Response, 1A Sink/Source,
Continuous Conduction Mode
Startup (PSV), EN/PSV Going Low, VDDQ = 5A
Startup (PSV), EN/PSV Going High
© 2006 Semtech Corp.
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SC488
POWER MANAGEMENT
Outline Drawing - MLPQ 24 (4x4mm)
A
D
B
E
DIMENSIONS
INCHES MILLIMETERS
MIN NOM MAX MIN NOM MAX
DIM
A
.031
.040
0.90 1.00
.035
.001
0.80
A1 .000
.002 0.00 0.02 0.05
-
-
-
-
(.008)
(0.20)
0.25 0.30
A2
b
D
D1
E
PIN 1
INDICATOR
(LASER MARK)
.007
.010 .012 0.18
.151 .157 .163 3.85 4.00 4.15
2.70
.100 .106 .110 2.55
.151 .157 .163 3.85 4.00 4.15
2.70 2.80
2.80
E1 .100
.106 .110 2.55
e
.020 BSC
0.50 BSC
L
.011 .016 .020 0.30 0.40 0.50
N
24
24
aaa
.004
.004
0.10
0.10
A2
bbb
A
SEATING
PLANE
aaa
C
A1
C
D1
LxN
E/2
E1
2
1
N
bxN
bbb
C A B
e
D/2
NOTES:
1.
CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES).
COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS.
2.
© 2006 Semtech Corp.
23
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SC488
POWER MANAGEMENT
Land Pattern - MLPQ 24 (4x4mm)
K
DIMENSIONS
DIM
INCHES
MILLIMETERS
(.155)
.122
.106
.106
.021
.010
.033
.189
(3.95)
3.10
2.70
2.70
0.50
0.25
0.85
4.80
C
G
H
K
P
X
Y
Z
G
Z
(C)
H
X
P
NOTES:
1.
THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY.
CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR
COMPANY'S MANUFACTURING GUIDELINES ARE MET.
Contact Information
Semtech Corporation
Power Management Products Division
200 Flynn Road, Camarillo, CA 93012
Phone: (805) 498-2111 Fax: (805) 498-3804
www.semtech.com
© 2006 Semtech Corp.
24
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