SK100LVE111PJ [SEMTECH]
Low Skew Clock Driver, 100LVE Series, 9 True Output(s), 0 Inverted Output(s), ECL, PQCC28, PLASTIC, LCC-28;型号: | SK100LVE111PJ |
厂家: | SEMTECH CORPORATION |
描述: | Low Skew Clock Driver, 100LVE Series, 9 True Output(s), 0 Inverted Output(s), ECL, PQCC28, PLASTIC, LCC-28 驱动 逻辑集成电路 |
文件: | 总6页 (文件大小:131K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
SK10/100LVE111
1:9 Differential LVECL/LVPECL
Clock Driver
HIGH-PERFORMANCE PRODUCTS
Description
The SK10/100LVE111 is a low skew 1-to-9 differential
driver designed with clock distribution in mind. The
SK10/100LVE111’s function and performance are
similar to the SK100E111, with the added feature of
low voltage operation and the enable input. It accepts
capability is limited. Whenever used, the VBB pin
should be bypassed to VCC via a 0.01 µF capacitor.
Features
one signal input which can be either differential or • 200 ps Part-to-Part Skew
single-ended if the V output is used. The signal is • 50 ps Output-to-Output Skew
BB
fanned out to 9 identical differential outputs.
BB
The device is specifically designed, modeled, and • Voltage and Temperature Compensated Outputs
• Differential Design
• V Output
produced with low skew as the key goal. Optimal • Low Voltage V Range of –3.0 to –3.8V
EE
design and layout serve to minimize gate-to-gate skew • 75KW Internal Input Pulldown Resistors
within a device, and characterization is used to • Fully Compatible with MC100LVE111
determine process control limits that ensure consistent • Specified Over Industrial Temperature Range:
tpd distributions from lot to lot. The net result is a
dependable, guaranteed low skew device.
–40oC to 85oC
• ESD Protection of >4000V
• Available in 28-pin PLCC Package
To ensure that the tight skew specification is met, it
is necessary that both sides of the differential output
are terminated into 50W, even if only one side is being
used. In most applications, all nine differential pairs
will be used and therefore terminated. In the case
where fewer than nine pairs are used, it is necessary
to terminate at least the output pairs on the same
package side as the pair(s) being used on that side in
order to maintain minimum skew. Failure to do so will
result in small degradations of propagation delay (on
the order of 10–20ps) of the output(s) being used
which, while not being catastrophic to most designs,
will mean a loss of skew margin.
Functional Block Diagram
Q0
Q0*
Q1
Q1*
Q2
Q2*
The SK10/100LVE111, as with most other ECL devices,
can be operated from a positive VCC supply in PECL
mode. This allows the LVE111 to be used for high
performance clock distribution in +3.3V systems.
Designers can take advantage of the LVE111’s
performance to distribute low skew clocks across the
back plane or the board. In a PECL environment, series
or Thevenin line terminations are typically used as
they require no additional power supplies. For systems
incorporating GTL, parallel termination offers the lowest
power by taking advantage of the 1.2V supply as a
terminating voltage.
Q3
Q3*
Q4
Q4*
IN
IN*
Q5
Q5*
Q6
Q6*
Q7
Q7*
Q8
V
BB
Q8*
The SK10/100LVE111 provides VBB output for either
single-ended use or as a DC bias for AC coupling to
the device. The VBB output pin should be used only
as a DC bias for the LVE111 as its current sink/source
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Revision 1/August 27, 2001
1
SK10/100LVE111
HIGH-PERFORMANCE PRODUCTS
PIN Description
Pin Names
Pin
Function
IN, IN*
Differential Input Pair
Q0, Q0* - Q8, Q8* Differential Outputs
VBB
VBB Output
VCC, VCCO
VEE
NC
Positive Supply
Negative Supply
No Connect
Pinout
25
24
23
22
21
20
19
VEE
NC
26
27
28
18
17
16
15
14
13
12
Q3
Q3*
Q4
IN
28 Lead PLCC
VCC
IN*
1
2
3
4
VCC0
Q4*
Q5
(Top View)
VBB
N/C
Q5*
5
6
7
8
9
10
11
Revision 1/August 27, 2001
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2
SK10/100LVE111
HIGH-PERFORMANCE PRODUCTS
Package Information
28 Pin PLCC Package
Y BRK
–N–
S
N
S
S
M
B
0.007 (0.180)
T
L - M
D
U
M
S
N
0.007 (0.180)
+
T
L - M
PIN Descriptions
–L–
– M –
Z
D
W
+
S
0.010 (0.250) T L - M
S
N
S
G1
V
X
28
1
S
S
N
M
0.007(0.180) T L – M
S
N
S
A
R
0.007 (0.180)
M
M
T
L – M
H
Z
S
S
N
0.007 (0.180)
T
L – M
C
K1
View S
E
0.004 (0.100)
–T– SEATING PLANE
G
J
K
G1
VIEW S
S
S
S
N
0.010 (0.250)
T
L – M
S
0.007 (0.180)
M
T L – M
N
S
F
NOTES:
INCHES
MIN
MILLIMETERS
1. Datums -L-, -M-, and -N- determined where top of lead
shoulder exits plastic body at mold parting line.
2. DIM G1, true position to be measured at Datum -T-,
Seating Plane.
3. DIM R and U do not include mold flash. Allowable mold flash
is 0.010 (0.250) per side.
DIM
A
MAX
0.495
0.495
0.180
0.110
0.019
MIN
12.32
12.32
4.20
MAX
12.57
12.57
4.57
0.485
0.485
0.165
0.090
0.013
B
C
E
2.29
2.79
F
0.33
0.48
4. Dimensioning and tolerancing per ANSI Y14.5M, 1982.
5. Controlling Dimension: Inch.
6. The package top may be smaller than the package bottom by
G
0.050 BSC
1.27 BSC
H
0.026
0.020
0.025
0.450
0.450
0.042
0.042
0.042
--
0.032
0.66
0.51
0.64
11.43
11.43
1.07
1.07
1.07
--
0.81
--
J
--
up to 0.012 (0.300). Dimensions R and U are determined at
the outermost extremes of the plastic body exclusive of
mold flash, tie bar burrs, gate burrs and interlead flash,
but including any mismatch between the top and bottom of
the plastic body.
K
--
--
R
0.456
0.456
0.048
0.048
0.056
0.020
10o
11.58
11.58
1.21
1.21
1.42
0.50
10o
U
V
W
X
7. Dimension H does not include Dambar protrusion or
intrusion. The Dambar protrusion(s) shall not cause the H
dimension to be greater than 0.037 (0.940). The Dambar
intrusion(s) shall not cause the H dimension to be smaller
than 0.025 (0.635).
Y
Z
2o
2o
G1
K1
0.410
0.040
0.430
--
10.42
1.02
10.92
--
Revision 1/August 27, 2001
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SK10/100LVE111
HIGH-PERFORMANCE PRODUCTS
DC Characteristics
SK10LVE111 LVPECL DC Electrical Characteristics (Note 1, 9)
(V – V
CC
= 3.0V to 3.8V; VOUT Loaded 50W to V – 2.0V)
EE
CC
o
o
o
o
TA = - 40 C
TA = 0 C
TA = + 25 C
TA = + 85 C
Symbol
Characteristic
Min
Typ
Max
2410
1650
2410
1800
2.00
Min
Typ
Max
2460
1670
2460
1820
2.03
Min
Typ
Max
2490
1670
2490
1820
2.05
Min
Typ
Max
2580
1705
2580
1855
2.11
Unit
mV
mV
mV
mV
V
3
V
V
V
V
V
Output HIGH Voltage
2220
1350
2070
1350
2280
1350
2130
1350
2320
1350
2170
1350
2390
1350
2240
1350
OH
OL
IH
IL
3
Output LOW Voltage
3
Input HIGH Voltage
3
Input LOW Voltage
3
Output Reference Voltage
1.87
-150
1.92
-150
1.95
-150
1.99
-150
BB
Input Current (Diff)
(SE)
150
150
150
150
150
150
150
150
µA
µA
I
IN
I
Power Supply Current
49
66
49
66
49
66
49
66
mA
EE
SK100LVE111 LVPECL DC Electrical Characteristics (Note 2)
(V – V
CC
= 3.0V to 3.8V; VOUT Loaded 50W to V – 2.0V)
CC
EE
o
o
o
o
TA = - 40 C
TA = 0 C
TA = 25 C
TA = 85 C
Symbol
Characteristic
Min
Typ
Max
2420
1605
2420
1825
2.04
3.8
Min
Typ
Max
2420
1680
2420
1825
2.04
3.8
Min
Typ
Max
Min
Typ
Max
Unit
mV
mV
mV
mV
V
3
V
V
V
V
V
V
Output HIGH Voltage
2215
1470
2135
1490
1.92
2345
1595
2275
1490
2135
1490
1.92
2345
1595
2275
1490
2135
1490
1.92
2345
1595
2420
1680
2420
1825
2.04
3.8
2275
1490
2135
1490
1.92
2345
1595
2420
1680
2420
1825
2.04
3.8
OH
OL
IH
3
Output LOW Voltage
3
Input HIGH Voltage
3
Input LOW Voltage
IL
3
Output Reference Voltage
Power Supply Voltage
BB
CC
3.0
3.0
3.0
3.0
V
Input Current (Diff)
(SE)
-150
150
150
-150
150
150
-150
150
150
-150
150
150
µA
µA
I
IN
I
Power Supply Current
57
78
57
78
57
78
57
78
mA
EE
Revision 1/August 27, 2001
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4
SK10/100LVE111
HIGH-PERFORMANCE PRODUCTS
AC Characteristics
SK10/100LVE111 AC Electrical Characteristics
(V – V
CC
= 3.0V to 3.8V; VOUT Loaded 50W to V – 2.0V)
EE
CC
o
o
o
o
TA = - 40 C
TA = 0 C
TA = + 25 C
TA = + 85 C
Symbol
Characteristic
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
4,
Propagation Delay to Output
5
t
PLH
t
PHL
IN (Differential)
IN (Single-Ended)
455
490
530
560
640
680
465
510
550
600
665
685
490
520
560
610
665
690
520
540
590
630
660
720
ps
ps
t
Within-Device Skew
Part-to-Part Skew (Diff)
50
200
50
200
50
200
50
200
ps
ps
skew
6
7
V
V
Minimum Input Swing
500
1000
500
1000
500
1000
500
1000
mV
V
PP
VEE +
1.5
VCC – VEE +
0.4
VCC – VEE +
0.4
VCC – VEE +
0.4
VCC –
0.4
8
Common Mode Range
CMR
1.5
1.5
1.5
Rise/Fall Time
20% to 80%
t , t
180
270
590
200
300
595
210
310
560
220
330
470
ps
r
f
1. 10LVE111 circuits are designed to meet the DC specifications shown in the table after thermal
equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and
transverse airflow greater than 500 lfpm is maintained.
2. 100LVE111 circuits are designed to meet the DC specifications shown in the table where transverse
airflow greater than 500 lfpm is maintained.
3. These values are for VCC = 3.3V. Level Specifications will vary 1:1 with VCC.
4. The differential propagation delay is defined as the delay from the crossing points of the differential input
signals to the crossing point of the differential output signals.
5. The single-ended propagation delay is defined as the delay from the 50% point of the input signal to the
50% point of the output signal.
6. The within-device skew is defined as the worst case difference between any two similar delay paths within a
single device.
7. V (min) is defined as the minimum input differential voltage which will cause no increase in the
PP
propagation delay. The V (min) is AC limited for the LVE111 as a differential input as low as 500 mV
PP
will still produce full ECL levels at the output.
8. CMR range is referenced to the most positive side of the differential input signal. Normal operation is
obtained if the high level falls within the specified range and the peak-to-peak voltage lies between
VPP
and 1V. The lower end of the CMR range varies 1:1 with VEE and is equal to VEE + 1.5V.
(min)
9. For part ordering description, see HPP Part Ordering Information Data Sheet.
Revision 1/August 27, 2001
5
www.semtech.com
SK10/100LVE111
HIGH-PERFORMANCE PRODUCTS
Ordering Information
Ordering Code
SK10LVE111PJ
SK10LVE111PJT
SK100LVE111PJ
SK100LVE111PJT
Package ID
28-PLCC
28-PLCC
28-PLCC
28-PLCC
Temperature Range
Industrial
Industrial
Industrial
Industrial
Contact Information
Semtech Corporation
High-Performance Products Division
Division Headquarters
10021 Willow Creek Road
San Diego, CA 92131
Phone: (858) 695-1808
Marketing Group
1111 Comstock Street
Santa Clara, CA 95054
Phone: (408) 566-8776
FAX:
(858) 695-2633
FAX: (408) 727-8994
Revision 1/August 27, 2001
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6
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