SK10E142 [SEMTECH]

9-Bit Shift Register; 9位移位寄存器
SK10E142
型号: SK10E142
厂家: SEMTECH CORPORATION    SEMTECH CORPORATION
描述:

9-Bit Shift Register
9位移位寄存器

移位寄存器
文件: 总4页 (文件大小:114K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
SK10/100E142  
9-Bit Shift Register  
HIGH-PERꢀORMANCE PRODUCTS  
ꢀeatures  
Description  
• 700 MHz Minimum Shift Frequency  
• 9-Bit for Byte-Parity Applications  
• Asynchronous Master Reset  
• Dual Clocks  
The SK10E/100E142 is a 9-bit shift register, designed  
with byte-parity applications in mind. The E142 performs  
serial/parallel in and serial/parallel out, shifting in one  
direction. The nine inputs D0 – D8 accept parallel input  
data, while S-IN accepts serial input data. The Qn outputs  
do not need to be terminated for the shift operation to  
function. To minimize noise and power, any Q output not  
used should be left unterminated.  
• Extended 100E V Range of –4.2 to –5.5V  
EE  
• 75KInternal Input Pulldown Resistors  
• Fully Compatible with MC10E142 and  
MC100E142  
• Specified over Industrial Temperature Range:  
–40oC to 85oC  
• ESD Protection of >4000V  
• Available in 28-pin PLCC Package  
The SEL (Select) input pin is used to switch between the  
two modes of operation – SHIFT and LOAD. The shift  
direction is from bit 0 to bit 8. Input data is accepted by  
the registers at set-up time before the posiitive going  
edge of CLK1 or CLK2. Shifting is also accomplished  
on the positive clock edge. A HIGH on the Master Reset  
pin (MR) asynchronously resets all the registers to zero.  
PIN Description  
Pin Names  
Pin  
ꢀunction  
ꢀunctional Block Diagram  
D0 - D8  
S-IN  
SEL  
Parallel Data Inputs  
Serial Data Input  
Mode Select Input  
Clock Inputs  
CLK1, CLK2  
MR  
Q0 - Q8  
Master Reset  
Data Outputs  
S-IN  
Q
1
0
Q
Q
Q
Q
0
D
D
D
D
D
0
Pinout  
Q
Q
Q
1
0
1
2
3
D
D
D
1
2
3
25  
24  
23  
22  
21  
20  
19  
1
0
MR  
CLK1  
CLK2  
26  
27  
28  
18  
17  
16  
15  
14  
13  
12  
Q
7
Q
6
V
CC  
1
0
28 Lead PLCC  
V
1
2
3
4
Q5  
V
EE  
(Top View)  
S-IN  
CC0  
D
0
Q
4
D
1
Q
3
5
6
7
8
9
10  
11  
1
0
Q
Q
8
D
D
8
SEL  
ꢀunctions  
CLK1  
CLK2  
SEL  
Mode  
MR  
L
Load  
Shift  
H
www.semtech.com  
Revision 1/ꢀebruary 14, 2001  
1
SK10/100E142  
HIGH-PERꢀORMANCE PRODUCTS  
Package Information  
Y BRK  
S
S
N
M
M
A
R
0.007 (0.180)  
T
L – M  
N–  
Z
S
S
N
0.007 (0.180)  
T
L M  
D
–L–  
PIN Descriptions  
M –  
C
E
0.004 (0.100)  
TSEATING PLANE  
G
J
D
W
G1  
VIEW S  
V
S
S
S
N
0.010 (0.250)  
T
L M  
28  
1
0.007(0.180)  
M
T
L M  
S
N
S
S
S
S
B
M
0.007 (0.180)  
T
L - M  
N
H
U
M
S
N
0.007 (0.180)  
+
T
L - M  
Z
K1  
K
+
S
S
0.007 (0.180)  
M
T L M  
N
F
G1  
0.010 (0.250)S T L - M  
S
N
S
X
View S  
NOTES:  
1. Datums -L-, -M-, and -N- determined where top of lead  
shoulder exits plastic body at mold parting line.  
2. DIM G1, true position to be measured at Datum -T-,  
Seating Plane.  
3. DIM R and U do not include mold flash. Allowable  
mold flash is 0.010 (0.250) per side.  
4. Dimensioning and tolerancing per ANSI Y14.5M,  
1982.  
5. Controlling Dimension: Inch.  
6. The package top may be smaller than the package  
bottom by up to 0.012 (0.300). Dimensions R and U  
are determined at the outermost extremes of the  
plastic body exclusive of mold flash, tie bar burrs,  
gate burrs and interlead flash, but including any  
mismatch between the top and bottom of the plastic  
body.  
7. Dimension H does not include Dambar protrusion or  
intrusion. The Dambar protrusion(s) shall not cause  
the H dimension to be greater than 0.037 (0.940).  
The Dambar intrusion(s) shall not cause the H  
dimension to be smaller than 0.025 (0.635).  
INCHES  
MILLIMETERS  
DIM  
A
MIN  
MAX  
0.495  
0.495  
0.180  
0.110  
0.019  
MIN  
12.32  
12.32  
4.20  
MAX  
12.57  
12.57  
4.57  
0.485  
0.485  
0.165  
0.090  
0.013  
B
C
E
2.29  
2.79  
0.33  
0.48  
G
H
J
0.050 BSC  
0.032  
1.27 BSC  
0.026  
0.020  
0.025  
0.450  
0.450  
0.042  
0.042  
0.042  
--  
0.66  
0.51  
0.64  
11.43  
11.43  
1.07  
1.07  
1.07  
--  
0.81  
--  
--  
K
--  
--  
R
0.456  
0.456  
0.048  
0.048  
0.056  
0.020  
10o  
11.58  
11.58  
1.21  
1.21  
1.42  
0.50  
10o  
U
V
W
X
Y
Z
2o  
2o  
G1  
K1  
0.410  
0.040  
0.430  
--  
10.42  
1.02  
10.92  
--  
Revision 1/ꢀebruary 14, 2001  
2
www.semtech.com  
SK10/100E142  
HIGH-PERꢀORMANCE PRODUCTS  
DC Characteristics  
SK10/100E142 DC Electrical Characteristics (Notes 1, 2)  
V
CC  
– V = 4.2V to 5.5V; V  
EE  
Loaded 50to VCC – 2.0V)  
OUT  
TA = –40oC  
TA = 0oC  
TA = +85oC  
TA = +25oC  
Symbol  
Characteristic  
Min  
Max  
Min  
Max  
Min  
Max  
Min  
Max  
Unit  
I
IH  
Input HIGH Current  
150  
150  
150  
150  
µA  
Power Supply Current  
I
EE  
10E  
67  
69  
108  
112  
70  
74  
112  
120  
71  
78  
114  
125  
74  
86  
119  
138  
mA  
mA  
100E  
AC Characteristics  
SK10/100E142 AC Electrical Characteristics  
V
– V = 4.2V to 5.5V; V  
Loaded 50to VCC – 2.0V)  
CC  
EE  
OUT  
TA = –40oC  
TA = 0oC  
TA = +25oC  
TA = +85oC  
Symbol  
Characteristic  
Min  
Typ  
Max  
Min  
Typ  
Max  
Min  
700  
Typ  
Max  
Min  
Typ  
Max  
Unit  
f
Max. Shift ꢀrequency  
700  
900  
700  
900  
900  
700  
900  
MHz  
SHIꢀT  
Propagation Delay to  
Output  
CLK  
MR  
t
t
788  
831  
1053  
989  
795  
836  
1043  
994  
800  
840  
1037  
987  
813  
851  
1023  
976  
ps  
ps  
PLH  
PHL  
t
Setup Time  
s
D
SEL  
50  
300  
50  
300  
50  
300  
50  
300  
ps  
Hold Time  
t
D
SEL  
300  
75  
300  
75  
300  
75  
300  
75  
ps  
ps  
H
t
t
Reset Recovery Time  
900  
400  
900  
400  
900  
400  
900  
400  
RR  
Minimum Pulse Width  
CLK, MR  
PW  
ps  
ps  
3
t
Within Device Skew  
50  
50  
50  
50  
SKEW  
t
t
Rise/ꢀall Times  
(20% - 80%)  
r
f
255  
574  
266  
566  
270  
525  
282  
428  
ps  
Revision 1/ꢀebruary 14, 2001  
3
www.semtech.com  
SK10/100E142  
HIGH-PERꢀORMANCE PRODUCTS  
AC Characteristics (continued)  
Notes:  
1. 10E circuits are designed to meet the DC specifications shown in the table after thermal equilibrium  
has been established. The circuit is in a test socket or mounted on a printed circuit board and  
transverseairflow greater than 500 lfpm is maintained. Outputs are terminated through a 50Ω  
resistor to VCC–2.0V.  
2. 100K circuits are designed to meet the DC specification shown in the table where transverse airflow  
greater than 500 lfpm is maintained.  
3. Within device skew is defined as identical transitions on similar paths through a device.  
4. For standard ECL DC specifications, refer to the ECL Logic Family Standard DC Specifications Data  
Sheet.  
5. For part oredering description, see HPP Part Ordering Information Data Sheet.  
Ordering Information  
Ordering Code  
SK10E142PJ  
Package ID  
28-PLCC  
28-PLCC  
28-PLCC  
28-PLCC  
Temperature Range  
Industrial  
SK10E142PJT  
SK100E142PJ  
SK100E142PJT  
Industrial  
Industrial  
Industrial  
Contact Information  
Semtech Corporation  
High-Performance Products Division  
Division Headquarters  
10021 Willow Creek Road  
San Diego, CA 92131  
Phone: (858) 695-1808  
Marketing Group  
1111 Comstock Street  
Santa Clara, CA 95054  
Phone: (408) 566-8776  
FAX:  
(858) 695-2633  
FAX: (408) 727-8994  
Revision 1/ꢀebruary 14, 2001  
www.semtech.com  
4

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