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PDF下载SX1511B/SX1512B
World’s Lowest Voltage Level Shifting GPIO
with LED Driver and Keypad Engine
ADVANCED COMMUNICATIONS & SENSING
SX1511B/SX1512B
World’s Lowest Voltage Level Shifting GPIO with LED Driver and Keypad Engine
KEY PRODUCT FEATURES
G
ENERAL DESCRIPTION
The SX1511B and SX1512B are complete ultra low
voltage General Purpose parallel Input/Output (GPIO)
expanders ideal for low power handheld battery
powered equipment. This family of GPIOs comes in
8-, 16-channel configuration and allows easy serial
expansion of I/O through a standard SPI interface.
GPIO devices can provide additional control and
monitoring when the microcontroller or chipset has
insufficient I/O ports, or in systems where serial
communication and control from a remote location is
advantageous.
•
1.2V to 3.6V Low Operating Voltage with Dual
Independent I/O Rails (VCC1, VCC2)
ꢀ
Enable Direct Level Shifting Between I/O
Banks and Host Controller
•
•
5.5V Tolerant I/Os, Up to 15mA Output Sink on
all I/Os (No Total Sink Current Limit)
Integrated LED Driver for Enhanced Lighting
ꢀ
ꢀ
ꢀ
Intensity Control (256-step PWM)
Blink Control (224 On/Off values)
Breathing Control (224 Fade In/Out values)
These devices can also act as a level shifter to
connect a microcontroller running at one voltage level
to a component running at a different voltage level,
thus eliminating the need for extra level translating
circuits. The core is operating as low as 1.425V while
the dual I/O banks can operate between 1.2V and
3.6V independent of the core voltage and each other
(5.5V tolerant).
•
•
On-Chip Keypad Scanning Engine
ꢀ
ꢀ
Support Up to 8x8 Matrix (64 Keys)
Configurable Input Debouncer
8/16 Channels of True Bi-directional Style I/O
ꢀ
ꢀ
ꢀ
Programmable Pull-up/Pull-down
Push/Pull or Open-drain outputs
Programmable Polarity
The SX1511B and SX1512B feature
a
fully
•
•
Open Drain Active Low Interrupt Output (NINT)
programmable LED Driver with internal oscillator for
enhanced lighting control such as intensity (via 256-
step PWM), blinking and breathing (fade in/out) make
them highly versatile for a wide range of LED
applications.
ꢀ
ꢀ
Bit Maskable
Programmable Edge Sensitivity
Built-in Clock Management (Internal 2MHz
Oscillator/External Clock Input, 7 clock values)
ꢀ
OSCIO can be Configured as GPO
In addition, keypad applications are also supported
with an on-chip scanning engine that enables
continuous keypad monitoring up to 64 keys without
any additional host interaction reducing the bus
activity.
•
•
•
•
•
•
•
SPI Compatible Slave Interface (up to 20MHz)
Power-On Reset and Reset Input (NRESET)
Ultra Low Current Consumption: 1uA Typ
-40°C to +85°C Operating Temperature Range
Up to 2kV HBM ESD Protection
The SX1511B and SX1512B have the ability to
generate mask-programmable interrupts based on a
falling/rising edge of any of its GPIO lines. A
dedicated pin (NINT) indicates to a host controller
that a state change occurred on one or more of the
lines. Each GPIO is programmable via a bank of 8-bit
configuration registers that include data, direction,
pull-up/pull-down, interrupt mask and interrupt
registers. These I/O expanders feature small footprint
packages and are rated from -40°C to +85°C
temperature range.
Small Footprint Packages
Pb & Halogen Free, RoHS/WEEE compliant
T
YPICAL APPLICATIONS
•
•
•
Cell phones, PDAs, MP3 players
Digital camera, Notebooks, GPS Units
Any battery powered equipment
O
RDERING
INFORMATION
LEVEL SHIFTING
VCC1
1.2 - 3.6V
Part Number
I/Os
8
16
16
Package
QFN-UT-20
QFN-UT-28
Evaluation Kit
Marking
JKA5
KA25
-
IO0
IO1
IO2
IO3
SX1511BIULTRT
SX1512BIULTRT
SX1512BEVK
VDDM
1.425 - 3.6V
Host
Controller
FULL LED DRIVE
KEYPAD SCANNING
BUTTON CONTROL
SPI
SX1511B
VCC2
1.2 - 3.6V
NINT
NRESET
IO4
IO5
IO6
IO7
Rev 4 – 26th April 2011
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SX1511B/SX1512B
World’s Lowest Voltage Level Shifting GPIO
with LED Driver and Keypad Engine
ADVANCED COMMUNICATIONS & SENSING
Table of Contents
G
ENERAL
RDERING
EY
YPICAL
D
ESCRIPTION..................................................................................................................... 1
O
I
NFORMATION................................................................................................................... 1
RODUCT EATURES.................................................................................................................. 1
PPLICATIONS ..................................................................................................................... 1
IN DESCRIPTION ...................................................................................................................... 4
K
P
F
T
1
A
P
1.1
1.2
1.3
SX1511B 8-channel SPI GPIO with LED Driver and Keypad Engine
SX1512B 16-channel SPI GPIO with LED Driver and Keypad Engine
I/Os Feature Summary
4
5
6
2
ELECTRICAL CHARACTERISTICS............................................................................................... 7
2.1
2.2
Absolute Maximum Ratings
Electrical Specifications
7
7
3
4
T
YPICAL
O
PERATING
C
HARACTERISTICS ............................................................................... 10
B
LOCK
D
ETAILED
DESCRIPTION............................................................................................. 12
4.1
4.2
4.3
SX1511B 8-channel SPI GPIO with LED Driver and Keypad Engine
SX1512B 16-channel SPI GPIO with LED Driver and Keypad Engine
12
12
Reset
13
13
13
4.3.1
4.3.2
Hardware (NRESET)
Software (RegReset)
4.4
4.5
SPI Interface
WRITE
13
14
14
4.4.1
4.4.2
READ
I/O Banks
14
14
14
15
16
4.5.1
4.5.2
4.5.3
4.5.4
Input Debouncer
Keypad Scanning Engine
Level Shifter
Polarity Inverter
4.6
4.7
4.8
Interrupt (NINT)
16
17
Clock Management
LED Driver
17
17
18
18
19
19
20
20
4.8.1
4.8.2
4.8.3
4.8.4
4.8.5
4.8.6
4.8.7
Overview
Static Mode
Single Shot Mode
Blink Mode
LED Driver Modes
Synchronization of LED Drivers across several ICs
Tutorial
5
6
7
C
ONFIGURATION
R
EGISTERS.................................................................................................. 22
5.1
5.1
SX1511B 8-channel GPIO with LED Driver and Keypad Engine
SX1512B 16-channel GPIO with LED Driver and Keypad Engine
22
26
APPLICATION
I
NFORMATION ................................................................................................... 32
6.1
6.2
Typical Application Circuit
Typical LED Connection
32
32
PACKAGING INFORMATION ..................................................................................................... 33
7.1
7.2
QFN-UT 20-pin Outline Drawing
QFN-UT 20-pin Land Pattern
33
33
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SX1511B/SX1512B
World’s Lowest Voltage Level Shifting GPIO
with LED Driver and Keypad Engine
ADVANCED COMMUNICATIONS & SENSING
7.3
7.4
QFN-UT 28-pin Outline Drawing
QFN-UT 28-pin Land Pattern
34
34
8
9
S
OLDERING
P
ROFILE .............................................................................................................. 35
M
ARKING
INFORMATION ......................................................................................................... 36
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SX1511B/SX1512B
World’s Lowest Voltage Level Shifting GPIO
with LED Driver and Keypad Engine
ADVANCED COMMUNICATIONS & SENSING
1
PIN DESCRIPTION
1.1
SX1511B 8-channel SPI GPIO with LED Driver and Keypad Engine
Pin Symbol
Type
DI
DO
DI
Description
1
2
3
4
NRESET
SO
SCK
SI
Active low reset input
SPI data output (HZ when not used)
SPI clock input
SPI data input
DI
I/O[0], at power-on configured as an input
LED driver : Intensity control (PWM)
I/O[1], at power-on configured as an input
LED driver : Intensity control (PWM)
Supply voltage for Bank A I/O[3-0]
Ground Pin
5
6
I/O[0]
I/O[1]
DIO (*1)
DIO (*1)
7
8
VCC1
GND
P
P
I/O[2], at power-on configured as an input
LED driver : Intensity control (PWM), Blinking
I/O[3], at power-on configured as an input
LED driver : Intensity control (PWM), Blinking, Breathing (Fade In/Out)
Active low interrupt output
9
I/O[2]
I/O[3]
DIO (*1)
10
DIO (*1)
11
12
13
14
NINT
NSS
OSCIO
VDDM
DO
DI
SPI slave select input (active low)
DIO (*1) Oscillator input/output, can also be used as GPO
P
Main supply voltage
I/O[4], at power-on configured as an input
LED driver : Intensity control (PWM)
I/O[5], at power-on configured as an input
LED driver : Intensity control (PWM)
Supply voltage for Bank B I/O[7-4]
15
16
I/O[4]
I/O[5]
DIO (*1)
DIO (*1)
17
18
VCC2
GND
P
P
Ground Pin
I/O[6], at power-on configured as an input
LED driver : Intensity control (PWM), Blinking
I/O[7], at power-on configured as an input
LED driver : Intensity control (PWM), Blinking, Breathing (Fade In/Out)
19
20
I/O[6]
I/O[7]
DIO (*1)
DIO (*1)
D/I/O/P: Digital/Input/Output/Power
(*1) This pin is programmable through the SPI interface
Table 1 – SX1511B Pin Description
NRESET
SO
I/O[4]
VDDM
OSCIO
NSS
SCK
SI
GND
(PAD)
I/O[0]
NINT
Figure 1 – SX1511B QFN-UT-20 Pinout
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SX1511B/SX1512B
World’s Lowest Voltage Level Shifting GPIO
with LED Driver and Keypad Engine
ADVANCED COMMUNICATIONS & SENSING
1.2
SX1512B 16-channel SPI GPIO with LED Driver and Keypad Engine
Pin Symbol
Type
DIO (*1)
Description
I/O[2], at power-on configured as an input
LED driver : Intensity control (PWM), Blinking
I/O[3], at power-on configured as an input
LED driver : Intensity control (PWM), Blinking
Ground Pin
1
I/O[2]
2
I/O[3]
DIO (*1)
3
4
GND
VCC1
P
P
Supply voltage for Bank A I/O[7-0]
I/O[4], at power-on configured as an input
LED driver : Intensity control (PWM), Blinking, Breathing (Fade In/Out)
I/O[5], at power-on configured as an input
LED driver : Intensity control (PWM), Blinking, Breathing (Fade In/Out)
I/O[6], at power-on configured as an input
LED driver : Intensity control (PWM), Blinking, Breathing (Fade In/Out)
I/O[7], at power-on configured as an input
LED driver : Intensity control (PWM), Blinking, Breathing (Fade In/Out)
Active low interrupt output
5
6
7
8
I/O[4]
I/O[5]
I/O[6]
I/O[7]
DIO (*1)
DIO (*1)
DIO (*1)
DIO (*1)
9
NINT
NSS
OSCIO
VDDM
DO
DI
10
11
12
SPI slave select input (active low)
DIO (*1) Oscillator input/output, can also be used as GPO
P
Main supply voltage
I/O[8], at power-on configured as an input
LED driver : Intensity control (PWM), Blinking
I/O[9], at power-on configured as an input
LED driver : Intensity control (PWM), Blinking
I/O[10], at power-on configured as an input
LED driver : Intensity control (PWM), Blinking
I/O[11], at power-on configured as an input
LED driver : Intensity control (PWM), Blinking
Ground Pin
13
14
15
16
I/O[8]
I/O[9]
DIO (*1)
DIO (*1)
DIO (*1)
DIO (*1)
I/O[10]
I/O[11]
17
18
GND
VCC2
P
P
Supply voltage for Bank B I/O[15-8]
I/O[12], at power-on configured as an input
LED driver : Intensity control (PWM), Blinking, Breathing (Fade In/Out)
I/O[13], at power-on configured as an input
LED driver : Intensity control (PWM), Blinking, Breathing (Fade In/Out)
I/O[14], at power-on configured as an input
LED driver : Intensity control (PWM), Blinking, Breathing (Fade In/Out)
I/O[15], at power-on configured as an input
LED driver : Intensity control (PWM), Blinking, Breathing (Fade In/Out)
Active low reset input
19
20
21
22
I/O[12]
I/O[13]
I/O[14]
I/O[15]
DIO (*1)
DIO (*1)
DIO (*1)
DIO (*1)
23
24
25
26
NRESET
SO
SCK
SI
DI
DO
DI
SPI data output (HZ when not used)
SPI clock input
SPI data input
DI
I/O[0], at power-on configured as an input
LED driver : Intensity control (PWM), Blinking
I/O[1], at power-on configured as an input
LED driver : Intensity control (PWM), Blinking
27
28
I/O[0]
I/O[1]
DIO (*1)
DIO (*1)
D/I/O/P: Digital/Input/Output/Power
(*1) This pin is programmable through the SPI interface
Table 2 – SX1512B Pin Description
I/O[14]
I/O[13]
I/O[12]
VCC2
GND
21
20
19
18
17
16
15
1
2
3
4
5
6
7
I/O[2]
I/O[3]
GND
TOP VIEW
GND
(PAD)
VCC1
I/O[4]
I/O[5]
I/O[6]
I/O[11]
I/O[10]
Figure 2 – SX1512B QFN-UT-28 Pinout
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SX1511B/SX1512B
World’s Lowest Voltage Level Shifting GPIO
with LED Driver and Keypad Engine
ADVANCED COMMUNICATIONS & SENSING
1.3
I/Os Feature Summary
SX1511B
SX1512B
I/O
LED Driver
Keypad
LED Driver
Keypad
PWM
Blink
Breathe
Row
Col.
PWM
Blink
Breathe
Row
Col.
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
0
1
2
3
4
5
6
7
8
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
9
10
11
12
13
14
15
√
√
√
√
Table 3 – I/Os Feature Summary
Please note that in addition to table above, all I/Os feature bank-to-bank and bank-to-host level shifting.
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SX1511B/SX1512B
World’s Lowest Voltage Level Shifting GPIO
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ADVANCED COMMUNICATIONS & SENSING
2
ELECTRICAL
CHARACTERISTICS
2.1
Absolute Maximum Ratings
Stress above the limits listed in the following table may cause permanent failure. Exposure to absolute ratings for
extended time periods may affect device reliability. The limiting values are in accordance with the Absolute
Maximum Rating System (IEC 134). All voltages are referenced to ground (GND).
Symbol
Vmax_VDDM
Vmax_VCC1-2
Description
Min
- 0.4
- 0.4
-
Max
3.7
3.7
Unit
V
V
Main supply voltage
Digital I/O pin supply voltage (SX1511/12B)
Electrostatic handling HBM model(1) (SX1511B)
Electrostatic handling HBM model(1) (SX1512B)
Electrostatic handling CDM model
Electrostatic handling MM model (SX1511B)
Electrostatic handling MM model (SX1512B)
Operating ambient temperature range
Junction temperature range
2000
VES_HBM
VES_CDM
VES_MM
V
V
V
-
1500
1000
200
150
+85
+125
+150
-
-
-
-
TA
TC
-40
-40
-55
+/-100
°C
°C
TSTG
Ilat
Storage temperature range
Latchup-free input pin current(2)
°C
mA
(1) Tested according to JESD22-A114A
(2) Static latch-up values are valid at maximum temperature according to JEDEC 78 specification
Table 4 - Absolute Maximum Ratings
2.2
Electrical Specifications
Table below assumes default registers values, unless otherwise specified. Typical values are given for TA =
+25°C, VDDM=VCC1=VCC2=3.3V.
Symbol Description
Conditions
Min
Typ
Max
Unit
Supply
VDDM Main supply voltage
VCC1,2 I/O banks supply voltage
1.425
1.2
-
-
1
175
10
1
365
10
1
3.6
3.6
5
235
-
5
460
-
V
V
Oscillator OFF
Internal osc. (2MHz)
External osc. (32kHz)
Oscillator OFF
Internal osc. (2MHz)
External osc. (32kHz)
-
-
-
-
-
-
-
Main supply current
(SX1511B, SPI inactive)
IDDM
Main supply current
(SX1512B, SPI inactive)
ICC1,2 I/O banks supply current(1)
µA
µA
µA
2
I/Os set as Input
0.7*
VCC1,2
0.8*
VCC1,2 >= 2V
VCC1,2 < 2V
VCC1,2 >= 2V
VCC1,2 < 2V
-
-
-
-
5.5(3)
5.5(3)
VIH
VIL
High level input voltage
Low level input voltage
V
V
VCC1,2
0.3*
VCC1,2
0.2*
-0.4
-0.4
VCC1,2
Assuming no active
ILEAK
CI
Input leakage current
Input capacitance
-1
-
-
-
1
µA
pF
pull-up/down
-
10
I/Os set as Output
VCC1,2
– 0.3
-0.4
-
-
VOH
VOL
IOH
High level output voltage
-
-
VCC1,2
V
Low level output voltage
-
-
-
-
0.3
8(2)
2(2)
V
VCC1,2 >= 2V
VCC1,2 < 2V
High level output source current
mA
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SX1511B/SX1512B
World’s Lowest Voltage Level Shifting GPIO
with LED Driver and Keypad Engine
ADVANCED COMMUNICATIONS & SENSING
Symbol Description
Conditions
Min
-
-
Typ
-
-
Max
15(2)
8(2)
Unit
VCC1,2 >= 2V
VCC1,2 < 2V
After 8th SCK falling
edge
IOL
tPV
Low level output sink current
Output data valid timing
mA
-
-
200
ns
NINT (Output)
VOL
IOLM
tIV
Low level output voltage
-
-0.4
-
-
-
-
0.3
8
4
V
mA
ꢀs
VDDM >= 2V
VDDM < 2V
From input data change
From RegInterruptSource
clearing
-
-
-
Low level output sink current
Interrupt valid timing
4
tIR
Interrupt reset timing
-
-
4
ꢀs
NRESET (Input)
VDDM >= 2V
VDDM < 2V
VDDM >= 2V
VDDM < 2V
-
0.7*VDDM
0.8*VDDM
-
-
-
-
-
-
VDDMmax
VDDMmax
0.3*VDDM
0.2*VDDM
VIHMR High level input voltage
V
V
-0.4
-0.4
-1
-
-
-
VILM
Low level input voltage
ILEAK Input leakage current
CI Input capacitance
VPOR Power-On-Reset voltage
VDROPH High brown-out voltage
VDROPL Low brown-out voltage
1
10
-
-
-
µA
pF
V
V
V
-
Cf. Figure 6
Cf. Figure 6
Cf. Figure 6
Cf. Figure 6
Cf. Figure 6
0.8
VDDM-1
-
0.2
-
-
tRESET
tPULSE
Reset time
Reset pulse from host uC
0.6
200
2.5
-
ms
ns
OSCIO (Input/Output)
VDDM >= 2V
1.425V =< VDDM < 2V 0.8*VDDM
VDDM < 1.425V
VDDM >= 2V
1.425V =< VDDM < 2V
0.7*VDDM
-
-
-
-
-
-
-
-
-
-
-
-
-
-
VDDM+0.3
VDDM+0.3
VDDM+0.3
0.3*VDDM
0.2*VDDM
0.1*VDDM
VIHMO High level input voltage
V
V
0.9*VDDM
-0.4
-0.4
-0.4
-1
VILMO Low level input voltage
ILEAK Input leakage current
VDDM < 1.425V
-
-
-
-
1
10
VDDM
0.3
8
µA
pF
V
CI
Input capacitance
-
VOHM High level output voltage
VDDM-0.3
VOL
Low level output voltage
-0.4
V
VDDM >= 2V
VDDM < 2V
VDDM >= 2V
VDDM < 2V
-
-
-
-
IOHM
High level output source current
mA
2
8
4
IOLM
Low level output sink current
mA
SPI Interface : NSS(Input), SCK(Input), SI(Input), SO(Output)
0.7*
VDDM
0.8*
VDDM
+0.3
VDDM
+0.3
0.3*
VDDM
0.2*
VDDM
1
10
VDDM >= 2V
-
-
-
-
VIHMA
VILM
High level input voltage
Low level input voltage
V
V
VDDM < 2V
VDDM >= 2V
VDDM < 2V
VDDM
-0.4
-0.4
ILEAK
CI
Input leakage current
Input capacitance
-
-
-1
-
-
-
µA
pF
VDDM –
VOHM
VOL
High level output voltage
Low level output voltage
-
-
VDDM
V
0.3
-0.4
-
-
-
-
-
-
0.3
8
2
V
VDDM >= 2V
VDDM < 2V
IOHM
High level output source current
mA
VDDM >= 2V
VDDM < 2V
-
-
-
45
45
9
9
-
8
4
-
55
55
-
IOLM
Low level output sink current
mA
-
fSCK
SCK max clock frequency
SCK low time (% of SCK cycle)
SCK high time (% of SCK cycle)
SI setup time
-
-
-
-
-
20(4)
MHz
%
%
ns
ns
tSCK,LOW
tSCK,HIGH
tSI,SETUP
tSI,HOLD
-
-
-
-
SI hold time
-
Rev 4 – 26th April 2011
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SX1511B/SX1512B
World’s Lowest Voltage Level Shifting GPIO
with LED Driver and Keypad Engine
ADVANCED COMMUNICATIONS & SENSING
Symbol Description
Conditions
After SCK falling edge
Min
-
25
25
25
Typ
Max
Unit
%
ns
ns
ns
tSO,VALID
tNSS,SCK
tSCK,NSS
tNSS,HIGH
SO valid time (% of SCK cycle)
-
-
-
-
33(4)
NSS low to SCK rising edge
SCK falling edge to NSS high
NSS rising to falling edge
-
-
-
-
-
-
Miscellaneous
Programmable pull-up/down
resistors for IO[0-7]
RPULL
-
-
1.3
-
42
2
-
kꢁ
Internal
External from OSCIN
(40-60% duty cycle)
2.6
2.6
fOSC
Oscillator frequency
MHz
-
(1) Assuming no load connected to outputs and inputs fixed to VCC1,2 or GND.
(2) Can be increased by tying together and driving simultaneously several I/Os.
(3) With RegHighInput bit enabled (VCCx min =1.65V), else 3.6V (VCCx min = 1.2V)
(4) fSCK is calculated assuming a tSO,VALID of maximum 1/3 of SCK cycle. This gives 1/6 of SCK cycle as setup time to the host controller.
For systems where the setup time can be relaxed, tSO,VALID is also shown in §3 to allow the user to calculate the maximum SPI frequency
for individual systems.
Table 5 – Electrical Specifications
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3
TYPICAL OPERATING CHARACTERISTICS
SX1512B IDDM vs.VDDM (Oscillator Enabled)
SX1512B IDDM vs.VDDM (Oscillator Enabled)
360
360
340
320
300
280
260
240
220
340
320
300
280
260
240
220
200
180
200
180
160
140
120
100
160
140
120
100
1.3
1.5
1.7
1.9
2.1
2.3
2.5
2.7
2.9
3.1
3.3
3.5
1.3
1.5
1.7
1.9
2.1
2.3
2.5
2.7
2.9
3.1
3.3
3.5
VDDM (V)
VDDM (V)
Fosc vs. VDDM
Fosc vs.Temperature (VDDM
=
3.6V)
2.5
2.3
2.1
1.9
1.7
2.5
2.3
2.1
1.9
1.7
1.5
1.3
1.5
1.3
1.3
1.5
1.7
1.9
2.1
2.3
2.5
2.7
2.9
3.1
3.3
3.5
-50
-30
-10
10
30
50
70
90
VDDM (V)
Temp
(
oC)
VOL vs.Temperature (VCCx
=
3.6V, IOL = 15mA)
VOL vs. IOL (VCCx
= 3.6V, Temp 25C)
0.3
0.3
0.25
0.25
0.2
0.15
0.1
0.05
0
0.2
0.15
0.1
0.05
0
0
2
4
6
8
IOL (mA)
10
12
14
-50
-30
-10
10
30
50
70
90
Temp
(
oC)
VOH vs. IOH (VDDM
= 3.6V, Temp 25C)
VOH vs. Temperature (VCCx
=
3.6V, IOH
=
8mA)
3.6
3.55
3.5
3.6
3.55
3.5
3.45
3.4
3.45
3.4
3.35
3.3
3.35
3.3
3.25
3.2
3.25
3.2
-50
-30
-10
10
30
50
70
90
-8
-7
-6
-5
-4
IOH (mA)
-3
-2
-1
0
Temp
(
oC)
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SCK
t
SO,VALID
vs. VDDM
f
vs. VDDM
90
80
70
60
50
40
30
20
10
30
25
20
15
10
5
0
1.3
1.5
1.7
1.9
2.1
2.3
2.5
2.7
2.9
3.1
3.3
3.5
3.7
1.3
1.5
1.7
1.9
2.1
2.3
2.5
2.7
2.9
3.1
3.3
3.5
3.7
VDDM (V)
VDDM (V)
Worst Case
Typical
Worst Case
Typical
Figure 3 – Typical Operating Characteristics
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4
BLOCK DETAILED DESCRIPTION
4.1
SX1511B 8-channel SPI GPIO with LED Driver and Keypad Engine
OSCIO
Keypad
Engine
Clock Mgmt
External
Clock
LED Driver
Intensity (PWM)
Blink (Timer)
16 Keys Max
Internal
Oscillator
Breath (Ramp)
VCC1
I/O[0]
I/O[1]
I/O[2]
I/O[3]
VDDM
I/O Bank A
Reset
NRESET
8-Bit
R/W
SPI Bus
Control
NSS
SCK
SI
VCC2
I/O[4]
I/O[5]
I/O[6]
I/O[7]
I/O Bank B
Interrupt
SO
SX1511B
NINT
GND
Figure 4 – 8-channel Low Voltage GPIO with LED Driver and Keypad Engine
4.2
SX1512B 16-channel SPI GPIO with LED Driver and Keypad Engine
OSCIO
Keypad
Engine
Clock Mgmt
External
Clock
LED Driver
Intensity (PWM)
64 Keys Max
Blink (Timer)
Internal
Oscillator
Auto
Sleep/Wakeup
Breath (Ramp)
VCC1
I/O[0]
I/O[1]
I/O[2]
I/O[3]
I/O[4]
I/O[5]
I/O[6]
I/O[7]
I/O Bank A
VDDM
8-Bit
R/W
Reset
NRESET
SPI Bus
Control
NSS
SCK
SI
VCC2
I/O[8]
I/O[9]
I/O[10]
I/O[11]
I/O[12]
I/O[13]
I/O[14]
I/O[15]
8-Bit
R/W
SO
I/O Bank B
NINT
Interrupt
GND
Figure 5 – 16-channel Low Voltage GPIO with LED Driver and Keypad Engine
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4.3
Reset
4.3.1 Hardware (NRESET)
The SX1511B and SX1512B generate their own power on reset signal after a power supply is connected to the
VDDM pin. NRESET input pin can be used to reset the chip anytime, it must be connected to VDDM (or greater)
either directly (if not used), or via a resistor.
2
1
2
3
4
5
6
1
VDROPH
VDDM
VPOR
VDROPL
Reset
Signal
Undefined
Undefined
Undefined
tRESET
tPULSE
tRESET
Figure 6 – Power-On / Brown-out Reset Conditions
1. Device behavior is undefined until VDDM rises above VPOR, at which point internal reset procedure is
started.
2. After tRESET, the reset procedure is completed.
3. In operation, the SX1511B and SX1512B may be reset (POR like or LED driver counters only depending
on RegMisc setting) at anytime by an external device driving NRESET low for tPULSE or longer Chip can
be accessed normally again after NRESET rising edge.
4. During a brown-out event, if VDDM drops above VDROPH a reset will not occur.
5. During a brown-out event, if VDDM drops between VDROPH and VDROPL a reset may occur.
6. During a brown-out event, if VDDM drops below VDROPL a reset will occur next time VPOR is crossed.
Please note that a brown-out event is defined as a transient event on VDDM. If VDDM is attached to a battery,
then the gradual decay of the battery voltage will not be interpreted as a brown-out event.
Please also note that a sharp rise in VDDM (> 1V/us) may induce a circuit reset.
4.3.2 Software (RegReset)
Writing consecutively 0x12 and 0x34 to RegReset register will reset all registers to their default values.
4.4
SPI Interface
The SX1511B and SX1512B SPI interface operates only in slave mode. 4 lines are used to exchange data
between an external master host and the slave device:
•
•
•
•
NSS : Slave select input (active low)
SCK : Clock input
SI : Data input
SO : Data output
The SX1511B and SX1512B have a few user-accessible internal 8-bits registers to set the various parameters of
operation (Cf. §5 for detailed configuration registers description). The SPI interface has been designed for
program flexibility, in that any register can be written or read independently of each other.
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4.4.1 WRITE
To write a value into a configuration register the timing diagram below should be carefully followed by the uC.
NSS
SCK
SI
SO
Figure 7 - SPI Write Operation
Successive register data can be written by the master without repeating the address byte, the register address
can be automatically incremented or kept fixed depending on the setting programmed in RegMisc.
4.4.2
READ
To read a value from a configuration register the timing diagram below should be carefully followed by the uC.
NSS
SCK
SI
SO
Figure 8 – SPI Read Operation
Successive register data can be read by the master without repeating the address byte, the register address will
be automatically incremented or kept fixed depending on the setting programmed in RegMisc.
4.5
I/O Banks
4.5.1 Input Debouncer
Each input can be individually debounced by setting corresponding bits in RegDebounce register. At power up
the debounce function is disabled. After enabling the debouncer, the change of the input value is accepted only if
the input value is identical at two consecutive sampling times.
The debounce time common to all IOs can be set in RegDebounceConfig register from 0.5 to 64ms.(fOSC =
2MHz)
4.5.2 Keypad Scanning Engine
SX1511B, and SX1512B integrate a fully programmable keypad scanning engine to implement keypad
applications up to 8x8 matrix (i.e. 64 keys).
Please note that SX1512B also implements an Auto Sleep/Wakeup feature to save power consumption when no
key has been pressed for a programmed time.
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Y
SX1511B
IO3
IO2
IO1
IO0
IO4
IO5
IO6
IO7
X
RegKeyData =
- IO[3-0] as outputs (scanning)
- IO[7-4] as inputs
X
Y
Figure 9 – 4x4 Keypad Connection to SX1511B
Following procedure should be implemented on the host controller for a 4x4 keypad:
1. Set RegDir to 0xF0 (IO[3-0] as outputs, IO[7-4] as inputs) , set RegOpenDrain to 0x0F (IO[3-0] as open-drain
outputs), set RegPullup to 0xF0 (pull-ups enabled on inputs IO[7-4]).
2. Enable and configure debouncing on IO[7-4] (RegDebounceEnable = 0xF0, Ex : RegDebounceConfig = 0x05)
3. Enable and configure keypad scanning engine (Ex : RegKeyConfig = 0x7D) This will start an infinite loop with
the following sequence to IO[3:0]: ZZZ0, ZZ0Z, Z0ZZ, 0ZZZ. Make sure that scan interval is set to higher value
than the debounce time.
4. When a key is pressed, NINT goes low, key scan is halted and the key coordinates are stored in RegKeyData:
•
•
•
The column data will be stored in RegKeyData[7:4] (Note: column indication is active low)
The row data will be stored in RegKeyData[3:0] (Note: row indication is active low)
When RegKeyData is read, this data along with the interrupt is automatically cleared (same behavior
as reading RegData) and the key scan continues to the next row.
5. Restart from point 4.
This implementation allows the host to handle both single and multi-touches easily (fast AAAAAA sequence is a
long press of key A, fast ABABABAB sequence is key A and key B pressed together, etc)
4.5.3 Level Shifter
Because of their 5.5V tolerant I/O banks with independent supply voltages between 1.2V and 3.6V, the SX1511B
and SX1512B can perform level shifting of signals from one I/O bank to another without uC activity by
programming the corresponding configuration register bits accordingly in RegLevelShifter (and RegDir).
This can save significant BOM cost in a final application where only a few signals need to be level-shifted (no
need for an additional external level shifter IC).
1.2-3.6V
VCC1
1.2-5.5V
IO0
SX1510/11B
1.2-3.6V
1.2-3.6V
VCC2
IO4
Figure 10 – Level Shifting Example
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The minimum pulse width tLevelShiftMin which can be level shifted properly depends on VCCx and VDDM:
tLevelShiftMin = Input Delay + Core Delay + Output Delay
Input/Core/Output delays vs VCCx/VDDM are given in figures below.
IO Input Delay vs. Supply Voltage
10.000
9.000
8.000
7.000
6.000
5.000
4.000
3.000
2.000
1.000
0.000
1.000
1.500
2.000
2.500
VCCx (V)
3.000
3.500
Typical
Worst Case
SX1512B Digital Core Delay vs. Supply Voltage
SX1511B Digital Core Delay vs. Supply Voltage
28
26
24
22
20
18
16
14
28
26
24
22
20
18
16
14
1
1.5
2
2.5
3
3.5
1
1.5
2
2.5
3
3.5
VDDM (V)
VDDM (V)
Typical
Worst Case
Typical
Worst Case
IO Output Delay vs. Supply Voltage ( LowDriveEn=0, 20pF Load)
IO Output Delay vs. Supply Voltage (LowDriveEn=1, 20pF Load)
140.000
120.000
100.000
80.000
60.000
40.000
20.000
0.000
140.000
120.000
100.000
80.000
60.000
40.000
20.000
0.000
1.000
1.500
2.000
2.500
VCCx (V)
3.000
3.500
1.000
1.500
2.000
2.500
3.000
3.500
VCCx (V)
Typical
Worst Case
Typical
Worst Case
Figure 11 – Level Shifter Max Frequency Calculation Data
4.5.4 Polarity Inverter
Each IO’s polarity can be individually inverted by setting corresponding bit in RegPolarity register. Please note
that polarity inversion can also be combined with level shifting feature.
4.6
Interrupt (NINT)
At start-up, the transition detection logic is reset, and NINT is released to a high-impedance state. The interrupt
mask register is set to 0xFF, disabling the interrupt output for transitions on all I/O ports. The transition flags are
cleared to indicate no data changes.
An interrupt NINT can be generated on any programmed combination of I/Os rising and/or falling edges through
the RegInterruptMask and RegSense registers.
If needed, the I/Os which triggered the interrupt can then be identified by reading RegInterruptSource register.
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When NINT is low (i.e. interrupt occurred), it can be reset back high (i.e. cleared) by writing 0xFF in
RegInterruptSource (this will also clear corresponding bits in RegEventStatus register).
The interrupt can also be cleared automatically when reading RegData register (Cf. RegMisc)
Example: We want to detect rising edge of I/O[1] on SX1511B (NINT will go low).
1. We enable interrupt on I/O[1] in RegInterruptMask
ꢁ RegInterruptMask =“XXXXXX0X”
2. We set edge sense for I/O[1] in RegSense
ꢁ RegSenseLow =“XXXX01XX”
Please note that independently from the “user defined” process described above the keypad engine, when
enabled, also uses NINT to indicate a key press.
Hence we have NINT = “user defined condition occurred” OR “keypad engine condition occurred”
4.7
Clock Management
A main oscillator clock fOSC is needed by the LED driver, keypad engine and debounce features.
Clock management block is illustrated in figure below.
OSCIO
Clock
Mgmt
External
Clock
Div
fOSC
Internal
Oscillator
Figure 12 – Clock Management Overview
The block is configured in register RegClock (Cf §5 for more detailed information):
ꢂ
ꢂ
ꢂ
Selection of internal clock source: none (OFF) or internal oscillator or external clock input from OSCIN.
Definition of OSCIO pin function (OSCIN or OSCOUT)
OSCOUT frequency setting (sub-multiple of fOSC)
Please note that if needed the OSCOUT feature can be used as an additional GPO (Cf. RegClock)
4.8
LED Driver
4.8.1 Overview
Every IO has its own independent LED driver (Cf §6.2 for typical LED connection) , all IOs can perform intensity
control (PWM) while some of them additionally include blinking and breathing features (Cf pin description §1.3)
The LED drivers of all I/Os share the same clock ClkX configurable in RegMisc[6:4]. Please note that for power
consumption reasons ClkX is OFF by default.
Assuming ClkX is not OFF, LED driver for IO[X] is enabled when RegLEDDriverEnable[X] = 1 in which case it
can operate in one of the three modes below:
•
•
•
Static mode (all I/Os, with or without fade in/out)
Single shot mode (blinking capable I/Os only, with or without fade in/out)
Blink mode (blinking capable I/Os only, with or without fade in/out)
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RegData[X]
1
0
t
IO[X] Intensity (PWM value)
100%
ON
IOnX
Fade In
Fade Out
OFF
IOffX
0
t
TRiseX
TOnX
TFallX
TOffX
Figure 13 – LED Driver Overview
Each IO[X] has its own set of programmable registers (Cf §5 for more detailed information):
ꢂ
ꢂ
ꢂ
ꢂ
ꢂ
RegTOnX (blinking capable I/Os only): TOnX, ON time of IO[X]
RegIOnX (all I/Os): IOnX, ON intensity of IO[X]
RegOffX (blinking capable I/Os only): TOffX and IOffX, OFF time and intensity of IO[X]
RegTRiseX(breathing capable I/Os only): TRiseX, fade in time of IO[X]
RegTFallX(breathing capable I/Os only): TFallX, fade out time of IO[X]
Please note that the LED Driver mode is selectable for each IO bank between linear and logarithmic. (Cf 4.8.5)
All the figures assume normal IO polarity, for inverse polarity RegData control must be inverted (does not invert
the polarity of the IO signal itself).
4.8.2 Static Mode
Only mode available for non blinking capable IOs (with Off intensity = 0), else invoked when TOnX = 0.
If the I/O doesn’t support fading the LED intensity will step directly to the IOnX/IOffX value.
RegData(X)
On intensity(max) determined by
register RegIOnX
IOLED(X) level
Off intensity(min) determined by
register RegIOffX
Fade in rate determined by
register RegTRiseX
Fade out rate determined
by register RegTFallX
Figure 14 – LED Driver Static Mode
4.8.3 Single Shot Mode
Invoked when TOnX != 0 and TOffX = 0.
If the I/O doesn’t support fading the LED intensity will step directly to the IOnX/IOffX value.
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RegData(X)
On intensity(max)
IOLED(X) level
Off intensity(min)
Fade in rate determined by
register RegTRiseX
Minimum intensity duration
determined by register
RegData(x)
Fade out rate determined
by register RegTFallX
Figure 15 – LED Driver Single Shot Mode
4.8.4 Blink Mode
Invoked when TOnX != 0 and TOffX != 0.
If the I/O doesn’t support fading the LED intensity will step directly to the IOnX/IOffX value.
When RegData(X) is cleared, the LED
will complete any current ramp, and then
stay at minimum intensity
RegData(X)
On intensity(max)
IOLED(X) level
Off intensity(min)
Fade in rate determined by
register RegTRiseX
Maximum intensity
duration determined by
register RegTOnX
Minimum intensity duration
determined by register
RegTOffX
Fade out rate determined
by register RegTFallX
Figure 16 – LED Driver Blink Mode
4.8.5 LED Driver Modes
For each IO bank, the LED driver mode of fading capable IOs can be selected between linear or logarithmic in
RegMisc.
Lin. Log. Lin. Log. Lin. Log. Lin. Log. Lin. Log. Lin. Log. Lin. Log. Lin. Log.
0
1
2
3
4
5
6
7
8
0
0
0
0
0
0
0
0
1
1
1
1
1
1
32
33
34
35
36
37
38
39
40
41
42
43
44
45
4
4
4
4
5
5
5
5
6
6
6
6
7
7
64
65
66
67
68
69
70
71
72
73
74
75
76
77
13
13
13
13
14
14
14
14
16
16
17
17
18
18
96
97
98
99
28
28
30
30
31
31
32
32
34
34
35
35
36
36
128
129
130
131
132
133
134
135
136
137
138
139
140
141
53
53
53
53
56
56
56
56
60
60
60
60
65
65
160
161
162
163
164
165
166
167
168
169
170
171
172
173
88
88
88
88
93
93
93
93
98
98
98
98
104
104
192
193
194
195
196
197
198
199
200
201
202
203
204
205
135
135
135
135
142
142
142
142
150
150
150
150
157
157
224
225
226
227
228
229
230
231
232
233
234
235
236
237
198
198
198
198
207
207
207
207
216
216
216
216
225
225
100
101
102
103
104
105
106
107
108
109
9
10
11
12
13
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14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
1
1
2
2
2
2
2
2
2
2
3
3
3
3
3
3
3
3
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
7
7
8
8
8
8
9
9
9
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
19
19
20
20
21
21
22
22
23
23
24
24
25
25
26
26
27
27
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
38
38
39
39
41
41
42
42
44
44
46
46
46
46
49
49
49
49
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
65
65
69
69
69
69
73
73
73
73
78
78
78
78
83
83
83
83
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
104
104
110
110
110
110
116
116
116
116
122
122
122
122
129
129
129
129
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
157
157
165
165
165
165
172
172
172
172
181
181
181
181
189
189
189
189
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
225
225
235
235
235
235
245
245
245
245
255
255
255
255
255
255
255
255
9
10
10
10
10
11
11
12
12
Table 6 – LED Driver Linear vs Logarithmic Function (I)
300
250
200
150
100
50
Linear mode
Log mode
0
1
10 19 28 37 46 55 64 73 82 91 100 109 118 127 136 145 154 163 172 181 190 199 208 217 226 235 244 253
RegIOn (4xRegOff[2:0])
Figure 17 – LED Driver Linear vs Logarithmic Function (II)
4.8.6 Synchronization of LED Drivers across several ICs
When several GPIO expanders are used in the same application it may be useful that their LEDs drivers are
synchronous for coherent global operation.
In this case all ICs should share their fOSC through their OSCIO pins and have their reset connected together.
When RegMisc of each IC is set accordingly, NRESET signal can then be used to reset all devices’ internal
counters (but not the register settings) and allow synchronous LED operation (blinking, fading) across multiple
devices.
4.8.7 Tutorial
Below are the steps required to use the LED driver with the typical LED connection described §6.2:
-
-
-
Disable input buffer (RegInputDisable)
Disable pull-up (RegPullUp)
Enable open drain (RegOpenDrain)
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-
-
-
-
-
-
Set direction to output (RegDir) – by default RegData is set high => LED OFF
Enable oscillator (RegClock)
Configure LED driver clock and mode if relevant (RegMisc)
Enable LED driver operation (RegLEDDriverEnable)
Configure LED driver parameters (RegTOn, RegIOn, RegOff, RegTRise, RegTFall)
Set RegData bit low => LED driver started
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5
CONFIGURATION REGISTERS
5.1
SX1511B 8-channel GPIO with LED Driver and Keypad Engine
Address Name
Description
Default
Device and IO Banks
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
0x11
RegInputDisable
Input buffer disable register
Output buffer long slew register
Output buffer low drive register
Pull-up register
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
1111 1111
1111 1111*
1111 1111
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
RegLongSlew
RegLowDrive
RegPullUp
RegPullDown
RegOpenDrain
RegPolarity
Pull-down register
Open drain register
Polarity register
RegDir
Direction register
RegData
Data register
RegInterruptMask
RegSenseHigh
RegSenseLow
RegInterruptSource
RegEventStatus
RegLevelShifter
RegClock
Interrupt mask register
Sense register for I/O[7:4]
Sense register for I/O[3:0]
Interrupt source register
Event status register
Level shifter register
Clock management register
Miscellaneous device settings register
LED driver enable register
RegMisc
RegLEDDriverEnable
Debounce and Keypad Engine
0x12
0x13
0x14
0x15
RegDebounceConfig
RegDebounceEnable
RegKeyConfig
Debounce configuration register
Debounce enable register
Key scan configuration register
Key value
0000 0000
0000 0000
0000 0000
1111 1111
RegKeyData
LED Driver (PWM, blinking, breathing)
0x16
0x17
RegIOn0
RegIOn1
RegTOn2
RegIOn2
RegOff2
ON intensity register for I/O[0]
ON intensity register for I/O[1]
ON time register for I/O[2]
1111 1111
1111 1111
0000 0000
1111 1111
0000 0000
0000 0000
1111 1111
0000 0000
0000 0000
0000 0000
1111 1111
1111 1111
0000 0000
1111 1111
0000 0000
0000 0000
1111 1111
0000 0000
0000 0000
0000 0000
0x18
0x19
ON intensity register for I/O[2]
OFF time/intensity register for I/O[2]
ON time register for I/O[3]
0x1A
0x1B
RegTOn3
RegIOn3
RegOff3
0x1C
ON intensity register for I/O[3]
OFF time/intensity register for I/O[3]
Fade in register for I/O[3]
0x1D
0x1E
RegTRise3
RegTFall3
RegIOn4
RegIOn5
RegTOn6
RegIOn6
RegOff6
0x1F
Fade out register for I/O[3]
0x20
ON intensity register for I/O[4]
ON intensity register for I/O[5]
ON time register for I/O[6]
0x21
0x22
0x23
ON intensity register for I/O[6]
OFF time/intensity register for I/O[6]
ON time register for I/O[7]
0x24
0x25
RegTOn7
RegIOn7
RegOff7
0x26
ON intensity register for I/O[7]
OFF time/intensity register for I/O[7]
Fade in register for I/O[7]
0x27
0x28
RegTRise7
RegTFall7
0x29
Fade out register for I/O[7]
Miscellaneous
0x2A
RegHighInput
RegReset
High input enable register
Software reset register
0000 0000
0000 0000
Software Reset
0x7D
Test (not to be written)
0x7E
0x7F
RegTest1
RegTest2
Test register
Test register
0000 0000
0000 0000
*Bits set as output take “1” as default value.
Table 7 – SX1511B Configuration Registers Overview
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Addr Name
Default Bits Description
Disables the input buffer of each [input-configured] IO
0x00
0x01
0x02
0x03
0x04
0x05
0x06
RegInputDisable
0x00
0x00
0x00
0x00
0x00
0x00
0x00
7:0
7:0
7:0
7:0
7:0
7:0
7:0
0 : Input buffer is enabled (input actually being used)
1 : Input buffer is disabled (input actually not being used or LED connection)
Enables increased slew rate of the output buffer of each [output-configured] IO
0 : Increased slew rate is disabled
1 : Increased slew rate is enabled
Enables reduced drive of the output buffer of each [output-configured] IO
0 : Reduced drive is disabled
1 : Reduced drive is enabled, IOL specifications are divided by 2.
Enables the pull-up for each IO
0 : Pull-up is disabled
1 : Pull-up is enabled
Enables the pull-down for each IO
0 : Pull-down is disabled
1 : Pull-down is enabled
Enables open drain operation for each [output-configured] IO
0 : Regular push-pull operation
1 : Open drain operation
RegLongSlew
RegLowDrive
RegPullUp
RegPullDown
RegOpenDrain
RegPolarity
Enables polarity inversion for each IO
0 : Normal polarity : RegData[x] = IO[x]
1 : Inverted polarity : RegData[x] = !IO[x] (for both input and output configured IOs)
Configures direction for each IO.
0 : IO is configured as an output
1 : IO is configured as an input
Write: Data to be output to the output-configured IOs
Read: Data seen at the IOs, independent of the direction configured.
0x07
0x08
0x09
RegDir
0xFF
0xFF
0xFF
7:0
7:0
7:0
RegData
Configures which [input-configured] IO will trigger an interrupt on NINT pin
0 : An event on this IO will trigger an interrupt
RegInterruptMask
1 : An event on this IO will NOT trigger an interrupt
7:6
5:4
3:2
1:0
7:6
5:4
3:2
1:0
Edge sensitivity of RegData[7]
Edge sensitivity of RegData[6]
Edge sensitivity of RegData[5]
Edge sensitivity of RegData[4]
Edge sensitivity of RegData[3]
Edge sensitivity of RegData[2]
Edge sensitivity of RegData[1]
Edge sensitivity of RegData[0]
00 : None
01 : Rising
10 : Falling
11 : Both
0x0A
0x0B
RegSenseHigh
RegSenseLow
0x00
0x00
00 : None
01 : Rising
10 : Falling
11 : Both
Interrupt source (from IOs set in RegInterruptMask)
0 : No interrupt has been triggered by this IO
1 : An interrupt has been triggered by this IO (an event as configured in relevant
RegSense register occured).
0x0C
RegInterruptSource
0x00
7:0
7:0
Writing '1' clears the bit in RegInterruptSource and in RegEventStatus
When all bits are cleared, NINT signal goes back high.
Event status of all IOs.
0 : No event has occured on this IO
1 : An event has occured on this IO (an edge as configured in relevant RegSense
register occured).
0x0D
0x0E
RegEventStatus
RegLevelShifter
0x00
0x00
Writing '1' clears the bit in RegEventStatus and in RegInterruptSource if relevant.
If the edge sensitivity of the IO is changed, the bit(s) will be cleared automatically
7:6
5:4
3:2
1:0
7
Level shifter mode for IO[3] (Bank A) and IO[7] (Bank B)
Level shifter mode for IO[2] (Bank A) and IO[6] (Bank B)
Level shifter mode for IO[1] (Bank A) and IO[5] (Bank B)
Level shifter mode for IO[0] (Bank A) and IO[4] (Bank B)
Unused
00 : OFF
01 : A->B
10 : B->A
11 : Reserved
Oscillator frequency (fOSC) source
00 : OFF. LED driver, keypad engine and debounce features are disabled.
01 : External clock input (OSCIN)
6:5
10 : Internal 2MHz oscillator
11 : Reserved
OSCIO pin function (Cf. §4.7)
0x0F
RegClock
0x00
4
0 : OSCIO is an input (OSCIN)
1 : OSCIO is an output (OSCOUT)
Frequency of the signal output on OSCOUT pin:
0x0 : 0Hz, permanent "0" logical level (GPO)
0xF : 0Hz, permanent "1" logical level (GPO)
Else : fOSCOUT = fOSC/(2^(RegClock[3:0]-1))
3:0
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LED Driver mode for Bank B’s fading capable IOs (IO7)
0: Linear
1: Logarithmic
Frequency of the LED Driver clock ClkX of all IOs:
0 : OFF. LED driver functionality is disabled for all IOs.
Else : ClkX = fOSC/(2^(RegMisc[6:4]-1))
LED Driver mode for Bank A’s fading capable IOs (IO3)
0: Linear
7
6:4
3
1: Logarithmic
NRESET pin function when externally forced low (Cf. §4.3.1 and §4.8.5)
0: Equivalent to POR
1: Reset PWM/Blink/Fade counters (not user programmed values)
This bit can only be reset manually or by POR, not by NRESET.
Auto-increment register address (Cf. §4.4)
0: ON. When several consecutive data are read/written, register address is incremented.
1: OFF. When several consecutive data are read/written, register address is kept fixed.
Autoclear NINT on RegData read (Cf. §4.6)
0: ON. RegInterruptSource is also automatically cleared when RegData is read.
1: OFF. RegInterruptSource must be manually cleared, either directly or via
RegEventStatus.
0x10
RegMisc
0x00
2
1
0
Enables LED Driver for each [output-configured] IO
0 : LED Driver is disabled
1 : LED Driver is enabled
0x11
0x12
RegLEDDriverEnable
RegDebounceConfig
0x00
0x00
7:0
7:3
Unused
Debounce time (Cf. §4.5.1)
000: 0.5ms x 2MHz/fOSC
001: 1ms x 2MHz/fOSC
010: 2ms x 2MHz/fOSC
011: 4ms x 2MHz/fOSC
100: 8ms x 2MHz/fOSC
101: 16ms x 2MHz/fOSC
110: 32ms x 2MHz/fOSC
111: 64ms x 2MHz/fOSC
2:0
Enables debouncing for each [input-configured] IO
0 : Debouncing is disabled
1 : Debouncing is enabled
0x13
RegDebounceEnable
0x00
7:0
7
Unused
Number of rows (outputs) + key scan enable
00 : Key scan OFF
6:5
4:3
01 : 2 rows – IO[0:1]
10 : 3 rows – IO[0:2]
11 : 4 rows – IO[0:3]
Number of columns (inputs)
00 : 1 column – IO[4]
01 : 2 columns – IO[4:5]
10 : 3 columns – IO[4:6]
11 : 4 columns – IO[4:7]
Scan time per row (must be set above debounce time).
000 : 1ms x 2MHz/fOSC
001 : 2ms x 2MHz/fOSC
010 : 4ms x 2MHz/fOSC
011 : 8ms x 2MHz/fOSC
100 : 16ms x 2MHz/fOSC
101 : 32ms x 2MHz/fOSC
110 : 64ms x 2MHz/fOSC
111 : 128ms x 2MHz/fOSC
0x14
RegKeyConfig
0x00
2:0
Key which generated NINT (active low)
0x15
0xXX
RegKeyData
RegTOnX
0xFF
0x00
7:0
7:5
Ex: RegKeyData=11011110 => key [IO5;IO0] has been pressed and generated NINT
When read it is automatically cleared together with NINT and key scan continues.
Unused
ON Time of IO[X]:
0 : Infinite (Static mode, TOn directly controlled by RegData, Cf §4.8.2)
1 - 15 : TOnX = 64 * RegTOnX * (255/ClkX)
16 - 31 : TOnX = 512 * RegTOnX * (255/ClkX)
ON Intensity of IO[X]
- Linear mode : IOnX = RegIOnX
- Logarithmic mode (fading capable IOs only) : IOnX = f(RegIOnX) , Cf §4.8.5
OFF Time of IO[X]:
0 : Infinite (Single shot mode, TOff directly controlled by RegData, Cf §4.8.3)
1 - 15 : TOffX = 64 * RegOffX[7:3] * (255/ClkX)
16 - 31 : TOffX = 512 * RegOffX[7:3] * (255/ClkX)
OFF Intensity of IO[X]
4:0
7:0
7:3
0xXX
RegIOnX
0xFF
0xXX
0xXX
RegOffX
0x00
0x00
2:0
7:5
- Linear mode : IOffX = 4 x RegOff[2:0]
- Logarithmic mode (fading capable IOs only) : IOffX = f(4 x RegOffX[2:0]) , Cf §4.8.5
Unused
RegTRiseX
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Fade In setting of IO[X]
0 : OFF
4:0
1 - 15 : TRiseX = (RegIOnX-(4xRegOffX[2:0])) * RegTRiseX * (255/ClkX)
16 - 31 : TRiseX = 16 * (RegIOnX-(4xRegOffX[2:0])) * RegTRiseX * (255/ClkX)
7:5
4:0
Unused
Fade Out setting of IO[X]
0 : OFF
1 - 15 : TFallX = (RegIOnX-(4xRegOffX[2:0])) * RegTFallX * (255/ClkX)
16 - 31 : TFallX = 16 * (RegIOnX-(4xRegOffX[2:0])) * RegTFallX * (255/ClkX)
0xXX
RegTFallX
0x00
Enables high input mode for each [input-configured] IO
0 : OFF. VIH max = 3.6V and VCCx min = 1.2V
1 : ON. VIH max = 5.5V and VCCx min = 1.65V
Software reset register
Writing consecutively 0x12 and 0x34 will reset the device (same as POR)
Always reads 0.
0x2A
0x7D
RegHighInput
RegReset
0x00
0x00
7:0
7:0
Table 8 – SX1511B Configuration Registers Description
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5.1
SX1512B 16-channel GPIO with LED Driver and Keypad Engine
Address Name
Description
Default
Device and IO Banks
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x18
0x19
0x1A
0x1B
0x1C
0x1D
0x1E
0x1F
0x20
0x21
RegInputDisableB
Input buffer disable register - I/O[15-8] (Bank B)
Input buffer disable register - I/O[7-0] (Bank A)
Output buffer long slew register - I/O[15-8] (Bank B)
Output buffer long slew register - I/O[7-0] (Bank A)
Output buffer low drive register - I/O[15-8] (Bank B)
Output buffer low drive register - I/O[7-0] (Bank A)
Pull-up register - I/O[15-8] (Bank B)
Pull-up register - I/O[7-0] (Bank A)
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
1111 1111
1111 1111
1111 1111*
1111 1111*
1111 1111
1111 1111
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
RegInputDisableA
RegLongSlewB
RegLongSlewA
RegLowDriveB
RegLowDriveA
RegPullUpB
RegPullUpA
RegPullDownB
RegPullDownA
RegOpenDrainB
RegOpenDrainA
RegPolarityB
Pull-down register - I/O[15-8] (Bank B)
Pull-down register - I/O[7-0] (Bank A)
Open drain register - I/O[15-8] (Bank B)
Open drain register - I/O[7-0] (Bank A)
Polarity register - I/O[15-8] (Bank B)
Polarity register - I/O[7-0] (Bank A)
Direction register - I/O[15-8] (Bank B)
Direction register - I/O[7-0] (Bank A)
Data register - I/O[15-8] (Bank B)
RegPolarityA
RegDirB
RegDirA
RegDataB
RegDataA
Data register - I/O[7-0] (Bank A)
RegInterruptMaskB
RegInterruptMaskA
RegSenseHighB
RegSenseLowB
RegSenseHighA
RegSenseLowA
RegInterruptSourceB
RegInterruptSourceA
RegEventStatusB
RegEventStatusA
RegLevelShifter1
RegLevelShifter2
RegClock
Interrupt mask register - I/O[15-8] (Bank B)
Interrupt mask register - I/O[7-0] (Bank A)
Sense register for I/O[15:12]
Sense register for I/O[11:8]
Sense register for I/O[7:4]
Sense register for I/O[3:0]
Interrupt source register - I/O[15-8] (Bank B)
Interrupt source register - I/O[7-0] (Bank A)
Event status register - I/O[15-8] (Bank B)
Event status register - I/O[7-0] (Bank A)
Level shifter register
Level shifter register
Clock management register
RegMisc
Miscellaneous device settings register
LED driver enable register - I/O[15-8] (Bank B)
LED driver enable register - I/O[7-0] (Bank A)
RegLEDDriverEnableB
RegLEDDriverEnableA
Debounce and Keypad Engine
0x22
0x23
0x24
0x25
0x26
0x27
0x28
RegDebounceConfig
RegDebounceEnableB
RegDebounceEnableA
RegKeyConfig1
Debounce configuration register
Debounce enable register - I/O[15-8] (Bank B)
Debounce enable register - I/O[7-0] (Bank A)
Key scan configuration register
Key scan configuration register
Key value (column)
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
1111 1111
1111 1111
RegKeyConfig2
RegKeyData1
RegKeyData2
Key value (row)
LED Driver (PWM, blinking, breathing)
0x29
0x2A
0x2B
0x2C
0x2D
0x2E
0x2F
0x30
0x31
0x32
0x33
0x34
0x35
0x36
0x37
RegTOn0
RegIOn0
RegOff0
RegTOn1
RegIOn1
RegOff1
RegTOn2
RegIOn2
RegOff2
RegTOn3
RegIOn3
RegOff3
RegTOn4
RegIOn4
RegOff4
ON time register for I/O[0]
0000 0000
1111 1111
0000 0000
0000 0000
1111 1111
0000 0000
0000 0000
1111 1111
0000 0000
0000 0000
1111 1111
0000 0000
0000 0000
1111 1111
0000 0000
ON intensity register for I/O[0]
OFF time/intensity register for I/O[0]
ON time register for I/O[1]
ON intensity register for I/O[1]
OFF time/intensity register for I/O[1]
ON time register for I/O[2]
ON intensity register for I/O[2]
OFF time/intensity register for I/O[2]
ON time register for I/O[3]
ON intensity register for I/O[3]
OFF time/intensity register for I/O[3]
ON time register for I/O[4]
ON intensity register for I/O[4]
OFF time/intensity register for I/O[4]
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Address Name
Description
Default
0000 0000
0000 0000
0000 0000
0x38
RegTRise4
Fade in register for I/O[4]
Fade out register for I/O[4]
ON time register for I/O[5]
0x39
RegTFall4
RegTOn5
RegIOn5
0x3A
0x3B
0x3C
0x3D
0x3E
0x3F
0x40
ON intensity register for I/O[5]
OFF time/intensity register for I/O[5]
Fade in register for I/O[5]
1111 1111
0000 0000
0000 0000
0000 0000
0000 0000
1111 1111
0000 0000
0000 0000
0000 0000
0000 0000
1111 1111
0000 0000
0000 0000
0000 0000
0000 0000
1111 1111
0000 0000
0000 0000
1111 1111
0000 0000
0000 0000
1111 1111
0000 0000
0000 0000
1111 1111
0000 0000
0000 0000
1111 1111
0000 0000
0000 0000
0000 0000
0000 0000
1111 1111
0000 0000
0000 0000
0000 0000
0000 0000
1111 1111
0000 0000
0000 0000
0000 0000
0000 0000
1111 1111
0000 0000
0000 0000
0000 0000
RegOff5
RegTRise5
RegTFall5
RegTOn6
RegIOn6
Fade out register for I/O[5]
ON time register for I/O[6]
ON intensity register for I/O[6]
OFF time/intensity register for I/O[6]
Fade in register for I/O[6]
0x41
RegOff6
0x42
RegTRise6
RegTFall6
RegTOn7
RegIOn7
0x43
Fade out register for I/O[6]
0x44
ON time register for I/O[7]
0x45
ON intensity register for I/O[7]
OFF time/intensity register for I/O[7]
Fade in register for I/O[7]
0x46
RegOff7
0x47
RegTRise7
RegTFall7
RegTOn8
RegIOn8
0x48
Fade out register for I/O[7]
0x49
ON time register for I/O[8]
0x4A
0x4B
0x4C
0x4D
0x4E
0x4F
0x50
ON intensity register for I/O[8]
OFF time/intensity register for I/O[8]
ON time register for I/O[9]
RegOff8
RegTOn9
RegIOn9
ON intensity register for I/O[9]
OFF time/intensity register for I/O[9]
ON time register for I/O[10]
RegOff9
RegTOn10
RegIOn10
RegOff10
RegTOn11
RegIOn11
RegOff11
RegTOn12
RegIOn12
RegOff12
RegTRise12
RegTFall12
RegTOn13
RegIOn13
RegOff13
RegTRise13
RegTFall13
RegTOn14
RegIOn14
RegOff14
RegTRise14
RegTFall14
RegTOn15
RegIOn15
RegOff15
RegTRise15
RegTFall15
ON intensity register for I/O[10]
OFF time/intensity register for I/O[10]
ON time register for I/O[11]
0x51
0x52
0x53
ON intensity register for I/O[11]
OFF time/intensity register for I/O[11]
ON time register for I/O[12]
0x54
0x55
0x56
ON intensity register for I/O[12]
OFF time/intensity register for I/O[12]
Fade in register for I/O[12]
0x57
0x58
0x59
Fade out register for I/O[12]
ON time register for I/O[13]
0x5A
0x5B
0x5C
0x5D
0x5E
0x5F
0x60
ON intensity register for I/O[13]
OFF time/intensity register for I/O[13]
Fade in register for I/O[13]
Fade out register for I/O[13]
ON time register for I/O[14]
ON intensity register for I/O[14]
OFF time/intensity register for I/O[14]
Fade in register for I/O[14]
0x61
0x62
0x63
Fade out register for I/O[14]
ON time register for I/O[15]
0x64
0x65
ON intensity register for I/O[15]
OFF time/intensity register for I/O[15]
Fade in register for I/O[15]
0x66
0x67
0x68
Fade out register for I/O[15]
Miscellaneous
0x69
RegHighInputB
RegHighInputA
High input enable register - I/O[15-8] (Bank B)
High input enable register - I/O[7-0] (Bank A)
0000 0000
0000 0000
0x6A
Software Reset
0x7D
RegReset
Software reset register
0000 0000
Test (not to be written)
0x7E
0x7F
RegTest1
RegTest2
Test register
Test register
0000 0000
0000 0000
*Bits set as output take “1” as default value.
Table 9 – SX1512B Configuration Registers Overview
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ADVANCED COMMUNICATIONS & SENSING
Addr Name
Default Bits Description
Disables the input buffer of each IO
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
RegInputDisableB
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0xFF
0xFF
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
0 : Input buffer is enabled (input actually being used)
1 : Input buffer is disabled (input actually not being used or LED connection)
Disables the input buffer of each IO
0 : Input buffer is enabled (input actually being used)
1 : Input buffer is disabled (input actually not being used, LED connection)
Enables increased slew rate of the output buffer of each [output-configured] IO
0 : Increased slew rate is disabled
1 : Increased slew rate is enabled
Enables increased slew rate of the output buffer of each [output-configured] IO
0 : Increased slew rate is disabled
1 : Increased slew rate is enabled
Enables reduced drive of the output buffer of each [output-configured] IO
0 : Reduced drive is disabled
1 : Reduced drive is enabled, IOL specifications are divided by 2.
Enables reduced drive of the output buffer of each [output-configured] IO
0 : Reduced drive is disabled
1 : Reduced drive is enabled, IOL specifications are divided by 2.
Enables the pull-up for each IO
0 : Pull-up is disabled
1 : Pull-up is enabled
Enables the pull-up for each IO
0 : Pull-up is disabled
1 : Pull-up is enabled
Enables the pull-down for each IO
0 : Pull-down is disabled
1 : Pull-down is enabled
Enables the pull-down for each IO
0 : Pull-down is disabled
1 : Pull-down is enabled
Enables open drain operation for each [output-configured] IO
0 : Regular push-pull operation
1 : Open drain operation
Enables open drain operation for each [output-configured] IO
0 : Regular push-pull operation
1 : Open drain operation
Enables polarity inversion for each IO
0 : Normal polarity : RegData[x] = IO[x]
1 : Inverted polarity : RegData[x] = !IO[x] (for both input and output configured IOs)
Enables polarity inversion for each IO
0 : Normal polarity : RegData[x] = IO[x]
1 : Inverted polarity : RegData[x] = !IO[x] (for both input and output configured IOs)
RegInputDisableA
RegLongSlewB
RegLongSlewA
RegLowDriveB
RegLowDriveA
RegPullUpB
RegPullUpA
RegPullDownB
RegPullDownA
RegOpenDrainB
RegOpenDrainA
RegPolarityB
RegPolarityA
RegDirB
Configures direction for each IO.
0 : IO is configured as an output
1 : IO is configured as an input
Configures direction for each IO.
0 : IO is configured as an output
1 : IO is configured as an input
RegDirA
Write: Data to be output to the output-configured IOs
Read: Data seen at the IOs, independent of the direction configured.
Write: Data to be output to the output-configured IOs
Read: Data seen at the IOs, independent of the direction configured.
0x10
0x11
RegDataB
RegDataA
0xFF
0xFF
7:0
7:0
Configures which [input-configured] IO will trigger an interrupt on NINT pin
0 : An event on this IO will trigger an interrupt
1 : An event on this IO will NOT trigger an interrupt
Configures which [input-configured] IO will trigger an interrupt on NINT pin
0 : An event on this IO will trigger an interrupt
0x12
0x13
RegInterruptMaskB
RegInterruptMaskA
0xFF
0xFF
7:0
7:0
1 : An event on this IO will NOT trigger an interrupt
7:6
5:4
3:2
1:0
7:6
5:4
3:2
1:0
7:6
5:4
3:2
1:0
7:6
5:4
Edge sensitivity of RegData[15]
Edge sensitivity of RegData[14]
Edge sensitivity of RegData[13]
Edge sensitivity of RegData[12]
Edge sensitivity of RegData[11]
Edge sensitivity of RegData[10]
Edge sensitivity of RegData[9]
Edge sensitivity of RegData[8]
Edge sensitivity of RegData[7]
Edge sensitivity of RegData[6]
Edge sensitivity of RegData[5]
Edge sensitivity of RegData[4]
Edge sensitivity of RegData[3]
Edge sensitivity of RegData[2]
00 : None
01 : Rising
10 : Falling
11 : Both
0x14
0x15
RegSenseHighB
RegSenseLowB
0x00
0x00
00 : None
01 : Rising
10 : Falling
11 : Both
00 : None
01 : Rising
10 : Falling
11 : Both
0x16
0x17
RegSenseHighA
RegSenseLowA
0x00
0x00
00 : None
01 : Rising
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World’s Lowest Voltage Level Shifting GPIO
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3:2
1:0
Edge sensitivity of RegData[1]
Edge sensitivity of RegData[0]
Interrupt source (from IOs set in RegInterruptMask)
0 : No interrupt has been triggered by this IO
1 : An interrupt has been triggered by this IO (an event as configured in relevant
RegSense register occured).
0x18
0x19
0x1A
0x1B
RegInterruptSourceB
RegInterruptSourceA
RegEventStatusB
0x00
0x00
0x00
0x00
7:0
7:0
7:0
7:0
Writing '1' clears the bit in RegInterruptSource and in RegEventStatus
When all bits are cleared, NINT signal goes back high.
Interrupt source (from IOs set in RegInterruptMask)
0 : No interrupt has been triggered by this IO
1 : An interrupt has been triggered by this IO (an event as configured in relevant
RegSense register occured).
Writing '1' clears the bit in RegInterruptSource and in RegEventStatus
When all bits are cleared, NINT signal goes back high.
Event status of all IOs.
0 : No event has occured on this IO
1 : An event has occured on this IO (an edge as configured in relevant RegSense
register occured).
Writing '1' clears the bit in RegEventStatus and in RegInterruptSource if relevant.
If the edge sensitivity of the IO is changed, the bit(s) will be cleared automatically
Event status of all IOs.
0 : No event has occured on this IO
1 : An event has occured on this IO (an edge as configured in relevant RegSense
register occured).
RegEventStatusA
Writing '1' clears the bit in RegEventStatus and in RegInterruptSource if relevant.
If the edge sensitivity of the IO is changed, the bit(s) will be cleared automatically
7:6
5:4
3:2
1:0
7:6
5:4
3:2
1:0
7
Level shifter mode for IO[7] (Bank A) and IO[15] (Bank B)
Level shifter mode for IO[6] (Bank A) and IO[14] (Bank B)
Level shifter mode for IO[5] (Bank A) and IO[13] (Bank B)
Level shifter mode for IO[4] (Bank A) and IO[12] (Bank B)
Level shifter mode for IO[3] (Bank A) and IO[11] (Bank B)
Level shifter mode for IO[2] (Bank A) and IO[10] (Bank B)
Level shifter mode for IO[1] (Bank A) and IO[9] (Bank B)
Level shifter mode for IO[0] (Bank A) and IO[8] (Bank B)
Unused
00 : OFF
01 : A->B
10 : B->A
11 : Reserved
0x1C
0x1D
RegLevelShifter1
RegLevelShifter2
0x00
0x00
00 : OFF
01 : A->B
10 : B->A
11 : Reserved
Oscillator frequency (fOSC) source
00 : OFF. LED driver, keypad engine and debounce features are disabled.
01 : External clock input (OSCIN)
6:5
10 : Internal 2MHz oscillator
11 : Reserved
OSCIO pin function (Cf. §4.7)
0x1E
RegClock
0x00
4
0 : OSCIO is an input (OSCIN)
1 : OSCIO is an output (OSCOUT)
Frequency of the signal output on OSCOUT pin:
0x0 : 0Hz, permanent "0" logical level (GPO)
0xF : 0Hz, permanent "1" logical level (GPO)
Else : fOSCOUT = fOSC/(2^(RegClock[3:0]-1))
3:0
LED Driver mode for Bank B’s fading capable IOs (IO15-12)
0: Linear
1: Logarithmic
Frequency of the LED Driver clock ClkX of all IOs:
0 : OFF. LED driver functionality is disabled for all IOs.
Else : ClkX = fOSC/(2^(RegMisc[6:4]-1))
LED Driver mode for Bank A’s fading capable IOs (IO7-4)
0: Linear
7
6:4
3
1: Logarithmic
NRESET pin function when externally forced low (Cf. §4.3.1 and §4.8.5)
0: Equivalent to POR
1: Reset PWM/Blink/Fade counters (not user programmed values)
This bit is can only be reset manually or by POR, not by NRESET.
Auto-increment register address (Cf. §4.4)
0: ON. When several consecutive data are read/written, register address is incremented.
1: OFF. When several consecutive data are read/written, register address is kept fixed.
Autoclear NINT on RegData read (Cf. §4.6)
0x1F
RegMisc
0x00
2
1
0: ON. RegInterruptSourceA/B is also automatically cleared when RegDataA/B is read.
1: OFF. RegInterruptSourceA/B must be manually cleared, either directly or via
RegEventStatusA/B.
0
Enables LED Driver for each [output-configured] IO
0 : LED Driver is disabled
0x20
RegLEDDriverEnableB
0x00
7:0
1 : LED Driver is enabled
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Enables LED Driver for each [output-configured] IO
0 : LED Driver is disabled
1 : LED Driver is enabled
0x21
RegLEDDriverEnableA
0x00
7:0
7:3
Unused
Debounce time (Cf. §4.5.1)
000: 0.5ms x 2MHz/fOSC
001: 1ms x 2MHz/fOSC
010: 2ms x 2MHz/fOSC
011: 4ms x 2MHz/fOSC
100: 8ms x 2MHz/fOSC
101: 16ms x 2MHz/fOSC
110: 32ms x 2MHz/fOSC
111: 64ms x 2MHz/fOSC
0x22
RegDebounceConfig
0x00
2:0
Enables debouncing for each [input-configured] IO
0 : Debouncing is disabled
1 : Debouncing is enabled
Enables debouncing for each [input-configured] IO
0 : Debouncing is disabled
1 : Debouncing is enabled
0x23
0x24
RegDebounceEnableB
RegDebounceEnableA
0x00
0x00
7:0
7:0
7
Reserved
Auto Sleep time (no key press within this time will set keypad engine to sleep)
000 : OFF
001 : 128ms x 2MHz/fOSC
010 : 256ms x 2MHz/fOSC
6:4
011 : 512ms x 2MHz/fOSC
100 : 1sec x 2MHz/fOSC
101 : 2sec x 2MHz/fOSC
110 : 4sec x 2MHz/fOSC
111 : 8sec x 2MHz/fOSC
Unused
0x25
RegKeyConfig1
0x00
3
Scan time per row (must be set above debounce time).
000 : 1ms x 2MHz/fOSC
001 : 2ms x 2MHz/fOSC
010 : 4ms x 2MHz/fOSC
011 : 8ms x 2MHz/fOSC
100 : 16ms x 2MHz/fOSC
101 : 32ms x 2MHz/fOSC
110 : 64ms x 2MHz/fOSC
111 : 128ms x 2MHz/fOSC
2:0
7:6
5:3
Unused
Number of rows (outputs) + key scan enable
000 : Key scan OFF
001 : 2 rows – IO[0:1]
010 : 3 rows – IO[0:2]
011 : 4 rows – IO[0:3]
100 : 5 rows – IO[0:4]
101 : 6 rows – IO[0:5]
110 : 7 rows – IO[0:6]
111 : 8 rows – IO[0:7]
0x26
RegKeyConfig2
0x00
Number of columns (inputs)
000 : 1 column – IO[8]
001 : 2 columns – IO[8:9]
010 : 3 columns – IO[8:10]
011 : 4 columns – IO[8:11]
100 : 5 columns – IO[8:12]
101 : 6 columns – IO[8:13]
110 : 7 columns – IO[8:14]
111 : 8 columns – IO[8:15]
2:0
7:0
Column which generated NINT (active low)
Ex: RegKeyData1=11011111 => IO13 has generated NINT
The register is automatically cleared when RegKeyData2 is read.
0x27
0x28
RegKeyData1
RegKeyData2
0xFF
0xFF
Row which generated NINT (active low)
Ex: RegKeyData2=11111110 => IO0 has generated NINT
When the register is read both RegKeyData1 & RegKeyData2 are automatically cleared
together with NINT and key scan continues.
Unused
ON Time of IO[X]:
0 : Infinite (Static mode, TOn directly controlled by RegData, Cf §4.8.2)
1 - 15 : TOnX = 64 * RegTOnX * (255/ClkX)
16 - 31 : TOnX = 512 * RegTOnX * (255/ClkX)
ON Intensity of IO[X]
- Linear mode : IOnX = RegIOnX
7:0
7:5
4:0
0xXX
0xXX
RegTOnX
RegIOnX
0x00
0xFF
7:0
- Logarithmic mode (fading capable IOs only) : IOnX = f(RegIOnX) , Cf §4.8.5
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World’s Lowest Voltage Level Shifting GPIO
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ADVANCED COMMUNICATIONS & SENSING
OFF Time of IO[X]:
0 : Infinite (Single shot mode, TOff directly controlled by RegData, Cf §4.8.3)
1 - 15 : TOffX = 64 * RegOffX[7:3] * (255/ClkX)
16 - 31 : TOffX = 512 * RegOffX[7:3] * (255/ClkX)
7:3
0xXX
RegOffX
0x00
OFF Intensity of IO[X]
2:0
7:5
- Linear mode : IOffX = 4 x RegOff[2:0]
- Logarithmic mode (fading capable IOs only) : IOffX = f(4 x RegOffX[2:0]) , Cf §4.8.5
Unused
Fade In setting of IO[X]
0 : OFF
1 - 15 : TRiseX = (RegIOnX-(4xRegOffX[2:0])) * RegTRiseX * (255/ClkX)
16 - 31 : TRiseX = 16 * (RegIOnX-(4xRegOffX[2:0])) * RegTRiseX * (255/ClkX)
Unused
Fade Out setting of IO[X]
0 : OFF
1 - 15 : TFallX = (RegIOnX-(4xRegOffX[2:0])) * RegTFallX * (255/ClkX)
16 - 31 : TFallX = 16 * (RegIOnX-(4xRegOffX[2:0])) * RegTFallX * (255/ClkX)
0xXX
0xXX
RegTRiseX
RegTFallX
0x00
0x00
4:0
7:5
4:0
Enables high input mode for each [input-configured] IO
0 : OFF. VIH max = 3.6V and VCCx min = 1.2V
1 : ON. VIH max = 5.5V and VCCx min = 1.65V
Enables high input mode for each [input-configured] IO
0 : OFF. VIH max = 3.6V and VCCx min = 1.2V
1 : ON. VIH max = 5.5V and VCCx min = 1.65V
Software reset register
Writing consecutively 0x12 and 0x34 will reset the device (same as POR)
Always reads 0.
0x69
0x6A
0x7D
RegHighInputB
RegHighInputA
RegReset
0x00
0x00
0x00
7:0
7:0
7:0
Table 10 – SX1512B Configuration Registers Description
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SX1511B/SX1512B
World’s Lowest Voltage Level Shifting GPIO
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ADVANCED COMMUNICATIONS & SENSING
6
APPLICATION INFORMATION
6.1
Typical Application Circuit
OSCIO
2.5V
3.3V
VCC1
I/O[0]
I/O[1]
I/O[2]
I/O[3]
VDDM
5V 5V
Host
I/O
NRESET
1.2V
SX1511B
VCC2
I/O[4]
I/O[5]
NSS
SCK
SI
NSS
SCK
SI
I/O[6]
I/O[7]
SO
SO
I/O
NINT
GND
Optional (depends
on the application)
Figure 18 - Typical Application Schematic
6.2
Typical LED Connection
Typical LED Connection is described below. The LED is usually connected to a high voltage (VBAT) to take
advantage of the high sink current of the I/O and to accommodate high LED threshold voltages (VLED).
Please note that in this configuration the IO must be programmed as open drain output (RegOpenDrain) with no
pull-up (RegPullUp) and input buffer must be disabled (RegInputBufferDisable).
VCCx can take any value without compromising LED operation.
VBAT
VCCx
VLED*
VCCx
SX1511/12B
IOx
R
IOL
*LED colour/technology dependent
Figure 19 – Typical LED Operation
Serial R must be calculated for IOL not to exceed its max spec (Cf. Table 5) else VOL will increase.
Rev 4 – 26th April 2011
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World’s Lowest Voltage Level Shifting GPIO
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ADVANCED COMMUNICATIONS & SENSING
7
PACKAGING INFORMATION
7.1
QFN-UT 20-pin Outline Drawing
QFN-UT 20-pin, 3 x 3 mm, 0.4 mm pitch
Figure 20 - QFN-UT 20-pin Outline Drawing
7.2
QFN-UT 20-pin Land Pattern
Figure 21 - QFN-UT 20-pin Land Pattern
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World’s Lowest Voltage Level Shifting GPIO
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7.3
QFN-UT 28-pin Outline Drawing
QFN-UT 28-pin, 4 x 4 mm, 0.4 mm pitch
Figure 22 - QFN-UT 28-pin Outline Drawing
7.4
QFN-UT 28-pin Land Pattern
Figure 23 - QFN-UT 28-pin Land Pattern
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SX1511B/SX1512B
World’s Lowest Voltage Level Shifting GPIO
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ADVANCED COMMUNICATIONS & SENSING
8
SOLDERING PROFILE
The soldering reflow profile for the SX1511B and SX1512B is described in the standard IPC/JEDEC J-STD-
020C. For detailed information please go to http://www.jedec.org/download/search/jstd020c.pdf
Figure 24 - Classification Reflow Profile (IPC/JEDEC J-STD-020C)
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SX1511B/SX1512B
World’s Lowest Voltage Level Shifting GPIO
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ADVANCED COMMUNICATIONS & SENSING
9
MARKING INFORMATION
JKA5
yyww
xxxx
yyww =ꢂDateꢂCode
xxxx =ꢂSemtechꢂLotꢂNo.
Figure 25 – SX1511B Marking Information
KA25
yyww
xxxxx
xxxxx
yyww =ꢂDateꢂCode
xxxxx =ꢂSemtechꢂLotꢂNo.
xxxxx
Figure 26 – SX1512B Marking Information
Rev 4 – 26th April 2011
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SX1511B/SX1512B
World’s Lowest Voltage Level Shifting GPIO
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ADVANCED COMMUNICATIONS & SENSING
© Semtech 2011
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SEMTECH PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED OR WARRANTED TO BE
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Contact Information
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Phone: (805) 498-2111 Fax: (805) 498-3804
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