UR8HC007-001 [SEMTECH]
Input Device and Power Management Companion IC for Jupiter Devices; 输入设备和电源管理IC伴侣木星设备型号: | UR8HC007-001 |
厂家: | SEMTECH CORPORATION |
描述: | Input Device and Power Management Companion IC for Jupiter Devices |
文件: | 总18页 (文件大小:150K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
TM
Juno UR8HC007-001
Input Device and Power Management
Companion IC for Jupiter Devices
HID & SYSTEM MANAGEMENT PRODUCTS, H/PC IC FAMILY
DESCRIPTION
FEATURES
TM
Juno 01 is a member of a series of
• Typically consumes less than 1 µA
• Scans a fully programmable 8 X
16 matrix that supports Japanese,
English and European keyboards
• Operates continuously between 3
and 5 Volts
• GPIO pins provide interrupt at
both falling and rising edge of
signals, ideal for lid functions,
power, ring indicators, docking
signals, battery measurement, etc.
• Has additional GPIO available for
LEDs, switches, etc.
• Offers internal control of LCD
brightness/contrast, audio, etc. as
well as four 10-bit A/D channels
for power management monitoring
• Cost-effective, reducing overall
system costs by integrating
features that would typically
require multiple additional
multi-functional companion ICs for
Jupiter and other devices running
®
®
Microsoft Windows CE and
utilizing RISC-based processors.
The IC interfaces the system via
either asynchronous serial or the
Serial Peripheral Interface (SPI) and
provides keyboard scanning,
special general purpose I/O (GPIO)
and unique system power
• Offers unique power management
capabilities that work in harmony
®
with Windows CE’s power modes
• Always runs in “Stop” mode
without data or event loss
TM
management capabilities.
• Provides three Zero-Power PS/2
ports for the hot-plug connection
of external keyboards/mice &
internal mouse, including
MouseWheels
• Uses proprietary circuitry, so
“Stop” mode is entered even when
PS/2 devices are connected and
active
TM
TM
The Zero-Power Juno will power
down even between key presses.
Semtech’s proprietary circuitry
(patent pending) allows the IC to
power down even when PS/2
devices are connected and active.
Typical power consumption is less
than 1 µA, a first for embedded ICs.
components
• Provides programmable features
that allow for maximum design
differentiation without
customization
TM
• Available in 1.7mm high package
to accommodate slim designs
• Other Juno versions offer control
of internal pointing device
TM
The Juno provides continuous
operation between 3 and 5V and
scans a fully programmable 8 X 16
keyboard matrix. The IC is equipped
PIN ASSIGNMENTS
• Jupiter devices/Professional PCs
• H/PCs, Web Phones, & G3
Terminals
TM
with three Zero-Power PS/2 ports
for the hot-plug connection of an
external PS/2 keyboard and mouse
as well as an internal PS/2 mouse,
including those with MouseWheels.
APPLICATIONS
41
60
TM
In addition, the Juno offers special
61
PWM1
PWM0
R7
R6
R5
R4
R3
R2
R1
40
C14
C15
EPX3
general purpose I/O (GPIO), ideal
for use for lid functions, power
switches, ring indicators, docking
signals, battery measurement, LEDs,
etc.
EPX2
GIO14/SW14
GIO15/SW15
GIO00/LED0
GIO01/LED1
GIO02/LED2
GIO03/LED3
VSS
OSCO
OSCI
PS2EN
HSUS
RESET
VSS1
LID
PWROK
MOSI/RXD
R0
VDD
The integration of features, many of
them programmable, on one IC
increases flexibility and reduces
component count and cost.
UR8HC007-001-FQ
AVREF
AVSS
EPX10
EPX9
EPX1
EPX0
GIO33/AD3
GIO32/AD2
GIO31/AD1
80
21
1
20
Juno is a trademark of Semtech Corporation. All
other trademarks belong to their respective
companies.
Copyright @1998-2001 Semtech Corporation
DOC8-007-001-DS-108
www.semtech.com
1
ORDERING CODE
Package options
80-pin, Plastic LQFP
Other materials
Pitch in mm’s
0.5
Type
TA = 0°C to +75°C
UR8HC007-001-XX-FQ
Part number
Technical Reference Manual
Juno Evaluation Kit
Document
Evaluation Kit
DOC8-007-001-TR-XXX
EVK8-007-001-XXX
TM
XX = Optional for customization
XXX = Denotes revision number
FUNCTIONAL DIAGRAM
SCLK / ISEL
MOSI/RxD
MISO/TxD
ROW 0-7
COL 0-15
Dual Mode
Serial
Communications
Port
Keyboard
Matrix
Scanner
SS/RTS
10
Embedded
Pointer
ATN/CTS
PWROK
LID
Configuration
Status and
Control
Power
Management
Unit
Clock
Data
External
PS/2 Port 2
Registers
HSUS
Analog Outputs
14 bit PWM0
14 bit PWM1
8 bit D/A
Clock
Data
External
PS/2 Port 1
3
4
Clock
Data
Internal PS/2
Pointer
Analog Inputs
10 bit A/D
(Shared with GI03)
GPIO
GIO30-33 /
A/D0-3
GIO00-03 /
LED0-3
GIO10-17 /
SW / INT
GIO20-21 /
±INT0-1
4
4
8
2
Copyright ©1998-2001 Semtech Corporation
DOC8-007-001-DS-108
www.semtech.com
2
PIN DEFINITIONS
Pin Numbers
Mnemonic
Power Supply
VDD
AVREF
AVSS
QFP
Type
Name and Function
71
72
73
30
24
PWR
AI
PWR
PWR
PWR
Positive Supply Voltage
Positive analog reference voltage
Ground: analog signal
Ground: negative supply voltage
Auxiliary Ground; must be tied to
pin 30
VSS
VSS1
Reset
_RESET
25
I
Controller hardware reset pin:
when at Low-level, this pin holds the
UR8HC007in a reset state. This pin
must be held at a logic-low until Power
Supply voltage (VDD) reaches the
minimum operating level (2.7V).
Oscillator pins
OSCI
28
29
I
Oscillator input: connect ceramic
resonator with built-in load capacitors
or CMOS clock from external oscillator
4 MHz operating frequency
Oscillator Output: connect ceramic
resonator with built-in load capacitors
or keep open if external oscillator
is used
_OSCO
O
Keyboard /
Event Wake-up
_WKUP
59
I/pD
Wake-up: wakes up the chip if
there is a key press in the scanned
keyboard matrix (Active-Low) or drives
the pin High when running
Scanned
matrix pins
ROW0-ROW7
COL0-COL7
COL8-COL11
COL12-COL13
COL14-COL15
PS/2 ports
PS2EN
62-55
54-47
38-35
27-26
79-78
I
O
Row matrix outputs
Column matrix outputs
27
O
Control output: when Low, disables
PS/2 communications by holding the
PS/2 Clock lines low
IPDAT
IPCLK
9
6
I5V/nD5V
I5V/nD5V
PS/2 Data line for Internal Pointing
Device
PS/2 Clock line for Internal Pointing
Device
EX0DAT
EX0CLK
EX1DAT
EX1CLK
8
5
7
4
I5V/nD5V
I5V/nD5V
I5V/nD5V
I5V/nD5V
PS/2 Data line for External Device 0
PS/2 Clock line for External Device 0
PS/2 Data line for External Device 1
PS/2 Clock line for External Device 1
Copyright ©1998-2001 Semtech Corporation
DOC8-007-001-DS-108
www.semtech.com
3
PIN DEFINITIONS (CON’T)
Pin Numbers
Mnemonic
QFP
Type
Name and Function
General Purpose
Input/Ouput
GIO0
GIO00/LED0-GIO3/LED3
34-31
I/O
General purpose input/output pin,
LED driver
GIO1
GIO10/SW10-GIO15/SW15 17-14
I/O
General purpose input/output pin,
Switch input
36-35
GIO16/SW16-GIO17/SW17 3-2
I5V/nD5V
General purpose input/output pin,
Switch input
Note: In order to have a Negative Edge Interrupt capability for SW10 - SW17, the
corresponding Switch Inputs should also be connected to the extended resistive network
acting on the _WKUP pin. Switch closure must be tied to Ground; the IC will remain in high
power consumption mode until all the switches are released.
GIO2
GIO20/SW0/ INT0
GIO20/SW0/ INT0
13-12
I/O, I Int
General purpose input/output pin,
Switch Input. Capable of Interrupt on
both Positive and Negative edges
GIO3 - analog input
GIO30/AD0
1
I/O/Ai
I/O/Ai
I/O/Ai
I/O/Ai
General purpose input/output pin,
A/D input 0
General purpose input/output pin,
A/D input 1
General purpose input/output pin,
A/D input 2
General purpose input/output pin,
A/D input 3
GIO31/AD1
GIO32/AD2
GIO33/AD3
80
79
78
Analog output
PWM0
PWM1
62
61
11
O
O
Ao
Channel 0 of Pulse Width Modulator
Channel 1 of Pulse Width Modulator
D/A output (Range: AVSS to AVREF)
DA
Reserved for
embedded pointing
device
EPX0
EPX1
EPX2
EPX3
EPX4
EPX5
EPX6
77
76
37
38
55
10
58
57
56
75
74
I/O/Ai
I/O/Ai
I/O
I/O
I/O
I/O/Ao
I/Ipup/O
I/Ipup/O
I/Ipup/O
I/O/Ai
I/O/Ai
Driver, A/D
Driver, A/D
Control, Driver
Control, Driver
Control, Driver
Control, Driver, Analog Adjustment
Left Button
Middle Button
Right Button
Driver, A/D
EPX7
EPX8
EPX9
EPX10
Driver, A/D
System status
monitoring
_LID
23
22
I Int
I Int
Lid closed signal from the lid switch
(Active-Low). Capable of Interrupt on
both Positive and Negative edges
Power OK signal. Capable of Interrupt
on both Positive and Negative edges
PWROK
Copyright ©1998-2001 Semtech Corporation
DOC8-007-001-DS-108
www.semtech.com
4
PIN DEFINITIONS (CON’T)
Pin Numbers
QFP Type
26
Mnemonic
_HSUS
Name and Function
Host_Suspended signal
I
(Active-Low). When Low, indicates
that Host Computer System is in
Power-reduced or Stop mode.
Communication
interface
_SS/_RTS
60
I_Int
Slave_Select (SPI Mode) or
Ready_To_Send (Asynchronous
Serial Mode). Active-Low signal Input.
Low-level indicates that the Host
System has data for the UR8HC007-
001 peripheral device or the Host
System is ready to accept data from
the UR8HC007-001 peripheral device.
Capable of Interrupt on Negative edge.
Pin 60 and pin 18 should both be "Low"
for data exchange to occur.
_ATN/_CTS
18
O
Attention (SPI Mode) or
Clear_To_Send (Asynchronous
Serial Mode ). Active-Low signal
Output. Low-level indicates that the
UR8HC007-001 peripheral device has
data for the Host System or the
UR8HC007 peripheral device is ready
to accept data from the Host System.
Pin 18 and pin 60 should both be "Low"
for data exchange to occur.
MISO/TXD
MOSI/RXD
SCLK/ISEL
20
21
19
I/O / O
Master-In-Slave-Out (SPI Mode) or
Transmit Data (Asynchronous Serial
Mode, Idle = "High" = 1)
Master-Out-Slave-In (SPI Mode) or
Receive Data (Asynchronous
I
I
Serial Mode)
Serial Clock (SPI Mode) or Interface
Select (Asynchronous Serial Mode).
Tie "Low" to select Asynchronous
Serial Mode. In SPI Mode, use the
following Clock sequence: Idle-High /
Negative-Edge (Shift Data) \ Positive-
Edge (Latch Data), Idle-High.
Note 1: An underscore in front of the pin
mnemonic denotes an active low signal.
Copyright ©1998-2001 Semtech Corporation
DOC8-007-001-DS-108
www.semtech.com
5
TM
JUNO FAMILY COMMUNICATIONS INTERFACE
The Juno™ family of controllers
implements two modes of serial
communications: The "Synchronous
Peripheral Interface" (SPI) mode
and the "Asynchronous Serial
Interface" (ASI).
The diagrams below describe the SPI and ASI communications interfaces,
respectively.
SPI Communications Interface
MOSI
MISO
The SPI is a synchronous bi-
directional, multi-slave interface that
supports bit rates up to 500 Kb/s.
Several Hosts and companion chips
implement the SPI protocol in order
to communicate with a wide range
of peripherals such as EEPROMs,
A/D converters, MCUs and other
system components. Alternatively,
the SPI may be implemented
SCLK
Host
(master)
_SS
_ATN
_SS
USAR Juno™
SLAVE 2
through software on the Host side.
(slave)
The Juno™ family implements the
_ATN as an additional hand-shake
signal in order to support low power
operation of the bus.
ASI Communications Interface
The ASI is an asynchronous
interface (UART type) that operates
at a fixed baud rate of 62.5 Kb/s.
Host
UR8HC007
Both interfaces are implemented
through the same set of four pins.
CTS
CTS
RTS
RTS
The IC determines the mode of
communication with the Host during
power-up by reading the value of
the SCLK/ISEL pin. If the pin is tied
low, the ASI mode is enabled. If it
is high, the SPI interface is enabled.
RxD
TxD
RxD
TxD
TM
ISEL
Please refer to the Juno Technical
Reference Manual for a description
of handshake and critical timing
parameters for each interface.
GND
Copyright ©1998-2001 Semtech Corporation
DOC8-007-001-DS-108
www.semtech.com
6
PROTOCOLS, COMMANDS AND REPORTS
Overview
General Message Structure
The Juno™ UR8HC007 implements
and supports four types of
transaction messages.
Communications between the Juno™ UR8HC007 and the Host processor
are implemented using a set of packet protocols and commands. The
general structure of a message is shown in the following diagram:
Protocol Header
Command/Report Identifier
Message Body
1. Commands from the UR8HC007
to the Host system
(if applicable)
2. Commands from the Host system
to the UR8HC007
LRC
3. Human Input Device (HID)
reports to the system
General Message Format
The Protocol Header identifies the type of transaction. The following table
lists the available protocols.
4. Event Alert messages to the
system
Protocol Headers
The protocol is fundamentally
implemented through a set of
general packet commands that
allow handling and reporting of
each individual controller register
and each bit within each register. In
this manner, the system achieves
maximum flexibility in manipulating
the operation of the UR8HC007
controller.
Protocols used in
commands issued by the Host
Protocol
Simple Commands
Write Register bit
Read Register bit
Write Register
Read Register
Write Block
Read Block
Protocols used in responses,
reports and alerts issued
by the controller
Protocol
Header
80H
81H
82H
83H
84H
85H
86H
Header
80H
81H
Simple Commands
Report Register bit & Event Alerts
Report Register
83H
Report Block
85H
Pointing Device Data Report
Keyboard Device Data Report
87H
88H
Copyright ©1998-2001 Semtech Corporation
DOC8-007-001-DS-108
www.semtech.com
7
PROTOCOLS, COMMANDS AND REPORTS, (CON’T)
HID Data Report
General Commands Format
The Pointing Device Data Reports
format covers both absolute (where
applicable) and relative positioning
devices. In addition, it provides
support for MouseWheel-type of
input devices.
For protocols used by either the host or the UR8HC007, a set of simple
commands is implemented. These support the basic communication
protocol and handle reset and errors in transmission.
A simple command would have the following structure:
Header (80H)
Command Code
LRC
Keyboard Data Report
The Keyboard Data Reports return
changes on the keyboard matrix or
the External PS/2 keyboard device.
Keys are uniquely identified
Simple Command Structure
Following is a summary of the simple commands used by both the Host
and the UR8HC007:
according to the Key Number table
TM
listed in Appendix A of the Juno
Simple Commands Summary
Technical Reference Manual. The
Key Up or Key Release numbers
comprise the logic OR of the Key
Number and 80H.
Command
Initialize
Protocol
Simple
Cmd Code
20H
Description
Forces the recipient to enter the
known default power-on state
Issued as a hand-shake response
only to the "Initialize" command.
Issued upon error in the reception
of a package. The recipient will
resend the last transmitted packet
Initialization Complete Simple
21H
25H
LRC (Longitudinal
Redundancy Check)
Resend Request
Simple
The LRC is calculated for the
whole packet, including the
Protocol Header. The LRC is
calculated by first taking the
bitwise exclusive OR of all bytes
from the message. If the most
significant bit (MSB) of the LRC is
set, the LRC is modified by
clearing the MSB and changing the
state of the next most significant
bit. Thus, the Packet Check Byte
will never consist of a valid LRC
with the most significant bit set.
Copyright ©1998-2001 Semtech Corporation
DOC8-007-001-DS-108
www.semtech.com
8
REGISTERS
The Juno™ implements a set of
internal registers that can be used
to control and monitor the
Registers’ Page Organization
Register Offset
operation of the various functional
units of the controller IC. These
registers can be accessed through
the Read/Write Register commands
described in the Commands
chapter of the Juno™ Technical
Reference Manual. The register
architecture of the Juno™ allows
for maximum flexibility and
expandability of the controller
operation. At the same time, by
using the default values for each
register, a system can utilize all the
basic functionality of the IC
00
01
Registers’ Page 0
Control and Status
Registers
0
1
255
Page Number Register
Page Number Register
controller with minimum Host driver
intervention.
Register Offset
00
01
Registers’ Page 1
Scanned Matrix and
Alternate Layout Keys
Registers
255
Page Number Register
Figure 1: Registers’ Page Organization
Copyright ©1998-2001 Semtech Corporation
DOC8-007-001-DS-108
www.semtech.com
9
POWER MANAGEMENT MODES OF OPERATION
POWER MANAGEMENT
The UR8HC007 has three modes of
operation relating to its power
consumption.
The Juno™ UR8HC007 family of controllers implements two power
management methods: system-coordinated power management and Self
Power Management™ (SPM).
The "Stop" mode is the lowest
System-coordinated power management primarily determines the tasks
performed and the type of reports communicated to the Host. The Juno™
monitors the system states through the PWROK (Power OK), _LID (Lid
closed) and _HSUS (Host suspended) lines. In addition to these signal
inputs, the UR8HC007 family provides a set of registers, described in the
power consumption mode. In this
mode, the crystal is stopped and
the IC consumes only 1 µA of
leakage current. This is the default
mode to which the IC will revert any
time an event or a signal condition
does not force it to exit this mode.
TM
"Registers" chapter of the Juno Technical Reference Manual, that can be
used by the host to control the PM-related performance of the controller
through software. According to the status of these lines (or register
settings), the Juno™ will enable or disable specific tasks and reports suited
to the current power and system management state of the Host.
The "Wait" mode is entered each
time it is necessary for a timer to be
running in order to perform a
system function. Such functions
include the LED blinking mode and
the use of one of the PWM
channels. Typical power
consumption in this mode is several
hundred µAs.
Self Power Management™ describes a method implemented by the Juno™
controller that, independently of any system intervention, results in the
lowest power consumption possible within the given parameters of its
operation. Through Self Power Management™, the Juno™ controllers are
capable of typically operating at only 1 µA, independent of the state of the
system. Self Power Management™ primarily determines the actual power
consumption of the controller IC.
The "Run" mode is entered briefly,
only to process an event or while an
interrupt-generating signal condition
persists. The controller IC will
remain in this mode only for as long
a signal prohibits it from reentering
a lower power consumption mode
or for as long as it is necessary to
process a Host-related transaction
(a few milliseconds).
The Juno™ implements the Semtech-patented Self Power Management™
method to achieve the minimum power consumption possible, independent
of the Host power management state.
Even when the Host is in the active state, the IC can still operate most of the
time at only 1 µA, even with external PS/2 devices attached to it.
Critical
Suspend
PWROK=1
AND
PWROK=1
PWROK=0
AND _LID=1
AND _HSUS=1
_LID=0
PWROK=0
PWROK=1
AND _LID=1
AND _HSUS=0
PWROK=0
PWROK=1
Lid
Closed*
AND _LID=1
PWROK=1
AND _LID=0
AND _HSUS=1
PWROK=1
AND _LID=1
AND _HSUS=0
PWROK=1
AND _LID=0
Host
PWROK=1 AND _LID=1 AND _HSUS=1
SPM
Suspend
PWROK=1 AND _LID=1
AND _HSUS=0
TM
Figure 2: USAR Juno State Diagram
Copyright ©1998-2001 Semtech Corporation
DOC8-007-001-DS-108
www.semtech.com
10
TM
ZERO-POWER OPERATION OF PS/2 PORTS
PS/2 PORTS
The Juno™ implements the
Semtech-patented "Message loss-
less wake-up™" method to operate
all three PS/2 ports. This method
enables the controller to interface
with devices attached to its PS/2
ports while still operating in the
"Stop" mode. Typical power
consumption of the PS/2 ports is
therefore 1 µA.
The UR8HC007-001 provides three PS/2 ports for the hot-plug connection of
an external keyboard, an external mouse and an internal mouse.
All of the internal and external devices are active at all times. Data from
both the external and internal keyboards and mice are merged and
seamlessly presented to the system.
5-Volt Tolerant PS/2 ports
The UR8HC007 controller can be powered by a power supply between 3
and 5 Volts (+/- 10%). Even when the USAR controller is powered by a 3-
Volt supply, the three PS/2 ports can directly interface with 5-Volt powered
devices — without the need of any external level-shifting circuitry. The Host
can enable or disable all the external PS/2 ports simultaneously, in sync with
the 5-Volt power plane that powers them. Alternatively, it can select any
PS/2 port selectively, through the "HID enable/disable control" register.
If a PS/2 device reports a data
packet, the controller will exit the
"Stop" mode for as long as it takes
to process the device message and
relay the information, if necessary,
to the Host system. This operation
is done transparently to the Host,
without any message loss or any
response delays from the input
devices.
PS/2 Mouse Handling
TM
The Juno provides a port for the connection of an internal PS/2 mouse.
This port supports MouseWheel functionality.
This unique technology allows
computers to operate at their
An internal mouse connected to a system’s PS/2 port consumes a significant
amount of power as it must always be “on.” A mouse connected to one of
Juno’s™ PS/2 ports consumes minimal power because the Juno™ will
power down even when the internal mouse is connected and active.
minimum power consumption state
even with PS/2 devices attached.
Systems that employ an internal
pointing device, such as a touch
pad or a force stick, can benefit the
most from this feature, since the
pointing device will force the
controller to exit its "Stop" mode only
when there is data to be reported.
Copyright ©1998-2001 Semtech Corporation
DOC8-007-001-DS-108
www.semtech.com
11
HID MANAGER
KEYBOARD ENCODING
The UR8HC007-001 will encode an 8-row by 16-column keyboard matrix.
OEMs may reprogram the matrix by sending commands to the IC from the
system. The Juno supports English, Japanese and European keyboards.
The UR8HC007 Human Input
Device (HID) Manager is
TM
responsible for the configuration
and handling of HID devices that
are embedded or attached to the
controller. The HID Manager has
the following responsibilities:
1. Enabling and disabling
In addition, the IC supports both sticky keys and notebook-style keyboards.
The keyboard below, the Fujitsu FKB7654, is the default keyboard for the
UR8HC007-001.
SL
NL
Pau
Brk
Ins
Prt
Del
Srq
Esc
F1
F2
F3
F4
F5
F6
F7
F8
F9
8
F10
F11
F12
embedded and attached input
devices through the "HID
_
7
9
~
`
!
1
@
2
#
3
$
4
%
5
^
6
&
7
*
8
(
)
0
+
=
bk
sp
-
9
enable/disable control" register
2. Formatting and relaying input
device reports to the Host
3. Controlling the configuration and
operation of both embedded and
attached input devices
4
5
6
{
[
}
]
Q
W
E
R
T
Y
U
I
O
P
enter
shift
tab
+
1
2
3
:
;
|
\
cap
lock
A
S
D
F
G
H
J
K
L
"
'
.
0
/
<
>
?
/
Z
X
C
V
B
N
M
shift
ctrl
,
.
fn
alt
space
alt
ctrl
pgup
pgup
The HID Manager consists of the
four functional blocks: the PS/2 Port
Manager; the Keyboard Manager;
the Pointing Device Manager; and
the Direct Port Manager.
pgup
pgup
Fujitsu FKB7654
GENERAL PURPOSE INPUT OUTPUT
TM
The Juno provides many GPIO pins which enable OEMs to easily
differentiate their products.
The function of each Manager is
explained in full in the Juno
TM
Technical Reference Manual.
Four GPIO ports provide interrupt at both falling and rising edge of signals.
Two of these pins are dedicated for use as a Lid indicator and Digital power
monitor. The other two may be used for a ring indicator, docking signal, soft
power button, etc.
TM
OTHER JUNO SERIES MEMBERS
TM
Other members of the Juno series
of companion ICs offers advanced,
ergonomic control of an internal
pointing device. Enabled pointing
devices include touch pads, touch
screens or force sticks. If the
Three GPIO pins provide A/D input and are ideal for battery measurement.
Three GPIO pins provide two Pulse Width Modulation (PWM) channels and
one D/A channel and may be used for analog control functions such as
LCD brightness/contrast or audio volume control.
application requires an internal
pointing device, using a pointing-
Four GPIO pins with high drive ability are set aside as LED drivers or I/O.
TM
enabled Juno will eliminate the
need for a dedicated mouse
encoder IC.
Eight GPIO pins can be used as system control outputs or inputs, for
example, for switches.
Copyright ©1998-2001 Semtech Corporation
DOC8-007-001-DS-108
www.semtech.com
12
SAMPLE SCHEMATIC FOR THE UR8HC007-001-FQ
R
I N T E R N A L P S / 2 P O I N T E
P S / 2 I / O
T O P P A A G G E E 2 2
9
8
7
6
5
4
3
2
9
C
10
B
11
A
6
INH
3
Z1
5
Z0
4
15
14
1
2
Y1
Y0
Z
Y
X
13
12
X1
X0
31
GIO03
GIO02
GIO01
GIO00
GIO03/LED3
GIO02/LED2
GIO01/LED1
GIO00/LED0
32
33
34
29
28
O S C O
OSCI
2
3
GIO17
GIO16
GIO15
GIO14
GIO13
GIO12
GIO11
GIO10
GIO17/SW17
GIO16/SW16
GIO15/SW15
GIO14/SW14
GIO13/SW13
GIO12/SW12
GIO11/SW11
GIO10/SW10
35
36
14
15
16
17
24
30
73
VSS1
VSS
12
13
AVSS
GIO21
GIO20
GIO21/SW1/ INT1
GIO20/SW0/ INT0
78
79
80
1
GIO33
GIO32
GIO31
GIO30
GIO33/AD3
GIO32/AD2
GIO31/AD1
GIO30/AD0
25
RESET
61
62
11
PWM1
PWM0
DA
P W M 1
P W M 0
DA
72
71
AVREF
VDD
2
3
ASYNCRONOUS
INTERFACE
ONOUS
FACE
SYNCR
INTER
SYNCRONOUS S ERIAL CLOCK
MASTER_OUT / SLAVE_IN or RxD
MASTER_IN / SLAVE_OUT or TxD
_ATTENTION or _CTS
RESERVED FOR
EEMBEDDED
POINTER
ELECT or _RTS
_SLAVE_S
Copyright ©1998-2001 Semtech Corporation
DOC8-007-001-DS-108
www.semtech.com
13
TM
JUNO ELECTRICAL CHARACTERISTICS
Absolute maximum ratings
(VSS = 0V, Ambient Temperature TA is in the range TLOW to THIGH)
Parameter
Symbol
Value
Unit
Supply Voltage
VDD
-0.3 to +7.0
V
Input voltage
All pins except 2-9
Pins 2-9
(PS/2 ports XXXDAT, XXXCLK,
GIO16/SW16, GIO17/SW17)
Output current
Total peak for all pins
VIN
-0.3 to VDD+0.3
-0.3 to +5.8
V
V
VIN
ΣIOH (Peak)
ΣIOL (Peak)
ΣIOH (Avg)
ΣIOL (Avg)
-80
80
-40
40
mA
mA
Total average for all pins
All pins except 31-34
Peak for each pin
IOH (Peak)
IOL (Peak)
IOH (Avg)
IOL (Avg)
-10
10
-5
mA
mA
Average for each pin
5
Pins 31-34
(GIO00/LED0 - GIO03/LED3)
Peak for each pin
IOH (Peak)
IOL (Peak)
IOH (Avg)
IOL (Avg)
-10
20
-5
mA
mA
Average for each pin
15
Temperature range
Operating Temperature
Storage Temperature
TLOW to THIGH
TSTG
-20 to 85
-40 to 125
ºC
ºC
Copyright ©1998-2001 Semtech Corporation
DOC8-007-001-DS-108
www.semtech.com
14
POWER CONSUMPTION WHILE OPERATING THE PWM CHANNELS
Users should consider the built-in PWM channels for generating slowly changing DC control voltages. Since
continuous clocking is necessary for the PWM operations, the only penalty for using the built-in PWM channels is the
requirement for the chip to operate at least in the Reduced Power Mode, with typical Current Consumption of 750 µA.
TM
JUNO ELECTRICAL CHARACTERISTICS, (CON’T)
NOTES FOR ELECTRICALS
Note1:
Recommended Operating Conditions, Digital Section
(VSS = 0V, Ambient Temperature TA is in the range TLOW to THIGH)
Parameter
Symbol
VDD
Min
2.7
Typ
3.0
Max
5.5
Unit
V
Current Consumption values do not
include any loading on the Output
pins or Analog Reference Current
for the built-in A/D or D/A modules.
Supply voltage
Input logic high
voltage
All pins except 2-9
Pins 2-9
(PS/2 ports xxxDAT,
xxxCLK, GIO16/SW16,
GIO17/SW17)
VIH
VIH
0.8VDD
0.8VDD
VDD
5.5
V
V
Note 2:
Since the built-in A/D module
consumes current only during short
periods of time (when A/D
conversion is actually requested),
the Analog Reference Current for
the built-in A/D module is not a
significant contributor to the overall
power consumption.
Input logic low
voltage
All pins except 28
Pin 28 (OSCI)
Input current
VI = VSS, VDD)
Input Pull-up Current
(pins 56-58 / IP6-IP8,
VI = VSS)
Output voltage
IOH = -1.0 mA
VIL
VIL
0
0
0.2VDD
0.16VDD
V
V
IIL / IIL
IPUP
-5.0
0
5.0
-10
0.4
µA
µA
-120
VOH
VOL
VDD-1.0
V
V
Note 3:
IOL = 1.6 mA
Current Consumption
(see note 1 below)
Full Speed Mode
(Fosc=4MHz)
Reduced Power Mode
(Fosc=4MHz)
The Analog Reference Current for
the built-in D/A module correlates
linearly to the Output Voltage. For
D/A output of 0V, the Analog
Reference Current is null. For D/A
outputs approaching Full Scale
(AVREF), the maximum Analog
Reference Current is indicated in
this Table. This current is a
IDD
IDD
3.5
7.0
mA
µA
750
Stop Mode
(Interrupts active, Fosc=0)
1.0 (TA = 25ºC)
10(TA = 85ºC ) µA
IDD
.1
Recommended operating conditions, analog section
(VSS = 0V, Ambient Temperature TA is in the range TLOW to THIGH)
significant contributor to the overall
power consumption.
Parameter
Symbol
AVSS
AVREF
Min
Typ
0
VDD
Max
Unit
V
V
Bits
LSb
Analog Signal Ground
Analog Reference Voltage
A/D Resolution-
A/D Absolute Accuracy
A/D Analog Input
2.7
VDD
10
4
Voltage Range
VIA
IIA
AVSS
AVREF
5.0
V
µA
A/D Analog Input Current
Analog Reference Current
(see note 2)
(A/D is active)
D/A Resolution-
D/A Absolute Accuracy -
D/A Output Impedance
Analog Reference Current
(see note 3)
IAVREF
RO
200
8
2.5
4.0
µA
Bits
%
1
2.5
KOhms
(D/A is active,
Output = Full Scale)
IAVREF
3.2
mA
Note 1: please see left
Note 2: please see left
Note 3: please see left
Copyright ©1998-2001 Semtech Corporation
DOC8-007-001-DS-108
www.semtech.com
15
MECHANICALS FOR THE UR8HC007 LQFP PACKAGE
HD
D
80
61
1
60
20
41
A
21
40
L1
F
e
L
Detail F
b
y
Dimension in Millimeters
Symbol
A
Min
–
Nom
–
Max
1.7
0.2
–
M
D
A
1
0
0.1
A2
–
1.4
b
0.13
0.105
11.9
11.9
–
0.18
0.125
12.0
12.0
0.5
0.28
0.175
12.1
12.1
–
c
D
E
e
H
H
L
D
E
13.8
13.8
0.3
–
–
0˚
–
1.0
–
14.0
14.0
0.5
1.0
–
14.2
14.2
0.7
–
0.1
10˚
–
–
–
–
I
2
Recommended Mount Pad
L1
y
–
b2
0.225
–
12.4
12.4
I2
M
M
D
E
–
Copyright ©1998-2001 Semtech Corporation
DOC8-007-001-DS-108
www.semtech.com
16
BILL OF MATERIALS FOR THE UR8HC007-001-FQ
Quantity
Manufacturer
Generic
Generic
Harris
Generic
CTS
Part#
Description
1
2
1
3
1
1
2
C1296-104-X50
C1206-470-N50
CD74HCT4053M
R1206-103-TF-5
745-101-R103CT-ND
PBRC-4.00BR
ADE-03
.1uF Ceramic Chip Cap, Z5U, SMT, 1206
47 pF Ceramic Chip Cap, NPO orX7R, SMT, Size:1206
SMT Triple 2-ch Ana Mult/Dem
10K Resistor, 5% Thick Film, SMT, 1206
10K, 8 resistors, bussed, 10 pins, SMT
4.00MHz Ceramic Resonator w/Caps, SMT
Switch, 3 Position Dip, THD
AVX
ALCO
Copyright ©1998-2001 Semtech Corporation
DOC8-007-001-DS-108
www.semtech.com
17
For sales information
and product literature,
contact:
HID & System Mgmt Division
Semtech Corporation
568 Broadway
New York, NY 10012
hidinfo@semtech.com
http://www.semtech.com
212 226 2042 Telephone
212 226 3215 Telefax
Semtech Western Regional Sales
805-498-2111 Telephone
805-498-3804 Telefax
Semtech Central Regional Sales
972-437-0380 Telephone
972-437-0381 Telefax
Semtech Eastern Regional Sales
203-964-1766 Telephone
203-964-1755 Telefax
Semtech Asia-Pacific Sales Office
+886-2-2748-3380 Telephone
+886-2-2748-3390 Telefax
Semtech Japan Sales Office
+81-45-948-5925 Telephone
+81-45-948-5930 Telefax
Semtech Korea Sales Sales
+82-2-527-4377 Telephone
+82-2-527-4376 Telefax
Northern European Sales Office
+44 (0)2380-769008 Telephone
+44 (0)2380-768612 Telefax
Southern European Sales Office
+33 (0)1 69-28-22-00 Telephone
+33 (0)1 69-28-12-98 Telefax
Central European Sales Office
+49 (0)8161 140 123 Telephone
+49 (0)8161 140 124 Telefax
Copyright ©1998-2001 Semtech Corporation. All rights reserved.
Juno is a trademark of Semtech Corporation. Semtech is a
registered trademark of Semtech Corporation. All other trademarks
belong to their respective companies.
INTELLECTUAL PROPERTY DISCLAIMER
This specification is provided "as is" with no warranties whatsoever
including any warranty of merchantability, fitness for any particular
purpose, or any warranty otherwise arising out of any proposal,
specification or sample. A license is hereby granted to reproduce
and distribute this specification for internal use only. No other
license, expressed or implied to any other intellectual property
rights is granted or intended hereby. Authors of this specification
disclaim any liability, including liability for infringement of proprietary
rights, relating to the implementation of information in this
specification. Authors of this specification also do not warrant or
represent that such implementation(s) will not infringe such rights.
Copyright ©1998-2001 Semtech Corporation
DOC8-007-001-DS-108
18
www.semtech.com
相关型号:
UR8HC007-0A4-XX-FQ
Microprocessor Circuit, CMOS, PQFP80, 13 X 13 MM, 0.50 MM PITCH, 1.70 MM HEIGHT, PLASTIC, LQFP-80
SEMTECH
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