SGM41542_技术文档

SGM41541/SGM41542

High Input Voltage,

3.78A Single-Cell Battery Charger

with NVDC Power Path Management

● Flexible Autonomous and I²C Operation Modes for

Optimal System Performance

FEATURES

● High Efficiency, 1.5MHz, Synchronous Buck Charger

● Fully Integrated Switches, Current Sense and

Compensation



95% Charge Efficiency at 1A from 5V Input

91.4% Charge Efficiency at 2A from 9V Input

Optimized for USB Voltage Input (5V)

● External Direct Charging Path Enable Output

● 9μA Ship Mode Low Battery Leakage Current

● High Accuracy

Selectable PFM Mode for Light Load Efficiency

● USB On-The-Go (OTG) Support (Boost Mode)



±0.6% Charge Voltage Regulation (8mV/Step)

±5% Charge Current Regulation at 2A

±10% Input Current Regulation at 0.9A



Boost Converter with up to 2A Output

Boost Efficiency of 93.5% at 0.5A and 94.3% at 1A

Accurate Hiccup Mode Over-Current Protection

Soft-Start Capable with up to 500μF Capacitive Load

Output Short Circuit Protection

● Safety



Battery Temperature Sensing (Charge/Boost Modes)

Thermal Regulation and Thermal Shutdown

Input Under-Voltage Lockout (UVLO)

Input Over-Voltage (ACOV) Protection

Selectable PFM Mode for Light Load Operations

● Single Input for USB or High Voltage Adapters



3.9V to 13.5V Operating Input Voltage Range

22V Absolute Maximum Input Voltage Rating

Programmable Input Current Limit and Dynamic

Power Management (IINDPM, 100mA to 3.1A with

100mA Resolution & 3.8A) to Support USB 2.0 and

USB 3.0 Standards and High Voltage Adaptors

Maximum Power Tracking by Programmable Input

Voltage Limit (VINDPM) with Selectable Offset

VINDPM Tracking of Battery Voltage

APPLICATIONS

Smart Phones, EPOS

Portable Internet Devices and Accessory



SIMPLIFIED SCHEMATIC



Input

PMID

LS/SC

3.9V to 13.5V

Auto Detect USB BC1.2, SDP, CDP, DCP and

Non-Standard Adaptors

USB

VBUS

DCEN

OTG

5.15V at 2A

VSYS

SW

● High Battery Discharge Efficiency with 19mΩ Switch

● Narrow Voltage DC (NVDC) Power Path Management

I²C Bus

BTST

SYS

BAT

Host

I_CHG



Instant-On with No or Highly Depleted Battery

Host Control

REGN

Ideal Diode Operation in Battery Supplement Mode

nQON

TS

● Ship Mode, Wake-Up and Full System Reset Capability

SGM41541

SGM41542

by Battery FET Control

Optional

SG Micro Corp

SEPTEMBER2022–REV.B.2

www.sg-micro.com

SGM41541

SGM41542

High Input Voltage, 3.78A Single-Cell Battery Charger

with NVDC Power Path Management

GENERAL DESCRIPTION

The SGM41541/SGM41542 are battery chargers and system

power path management devices with integrated converter

and power switches for using with single-cell Li-Ion or

Li-polymer batteries. This highly integrated 3.78A device is

capable of fast charging and supports a wide input voltage

range suitable for smart phones, tablets and portable systems.

I²C programming makes it a very flexible powering and

charger design solution.

reduction of charge current down to zero, the power path

management provides the deficit from battery by discharging

battery to the system until the system power demand is

fulfilled. This is called supplement mode, which prevents the

input source from overloading.

Starting and termination of a charging cycle can be

accomplished without software control. The sensed battery

voltage is used to decide for starting phase of charging in one

of the three phases of charging cycle: pre-conditioning,

constant current or constant voltage. When the charge

current falls below a preset limit and the battery voltage is

above recharge threshold, the charger function will

automatically terminate and end the charging cycle. If the

voltage of a charged battery falls below the recharge

threshold, the charger starts another charging cycle.

The devices include four main power switches: input reverse

blocking FET (RBFET, Q1), high-side switching FET for Buck

or Boost mode (HSFET, Q2), low-side switching FET for Buck

or Boost mode switching (LSFET, Q3) and battery FET that

controls the interconnection of the system and battery

(BATFET, Q4). The bootstrap diode for the high-side gate

driving is also integrated. The internal power path has a very

low impedance that reduces the charging time and maximizes

the battery discharge efficiency. Moreover, the input voltage

and current regulations provide maximum charging power

delivery to the battery with various types of input sources.

Several safety features are provided in the SGM41541/

SGM41542 such as over-voltage and over-current protections,

battery temperature monitoring, charging safety timing,

thermal shutdown and input UVLO. TS pin is connected to an

NTC thermistor for battery temperature monitoring and

protection in both charge and Boost modes according to

JEITA profile. This device also features thermal regulation in

which the charge current is reduced, if the junction

temperature exceeds 80℃ or 120℃ (selectable).

A wide range of input sources are supported, including

standard USB hosts, charging ports and USB compliant high

voltage adapters. The default input current limit is

automatically selected based on the built-in USB interface.

This limit is determined by the detection circuit in the system

(e.g. USB PHY). The SGM41541/SGM41542 is USB 2.0 and

USB 3.0 power specifications compliant with input current

and voltage regulation. It also meets USB On-The-Go (OTG)

power rating specification and is capable to boost the battery

voltage to supply 5.15V on VBUS with 2A (or 1.2A) current

limit.

Charging status is reported by the STAT output and

fault/status bits. A negative pulse is sent to the nINT output

pin as soon as a fault occurs to notify the host. BATFET reset

control is provided by nQON pin to exit ship mode or for a full

system reset.

The devices supply a DCEN signal to control an external

P-MOSFET or load switch as a direct charging path for low

voltage PMID, or to control a 2:1 switching capacitor divider

for high voltage PMID.

The system voltage is regulated slightly above the battery

voltage by the power path management circuit and is kept

above the programmable minimum system voltage (3.5V by

default). Therefore, system power is maintained even if the

battery is completely depleted or removed. Dynamic power

management (DPM) feature is also included that automatically

reduces the charge current if the input current or voltage limit

is reached. If the system load continues to increase after

The SGM41541/SGM41542 are available in

TQFN-4×4-24L package.

a Green

SG Micro Corp

www.sg-micro.com

SEPTEMBER 2022

2

SGM41541

SGM41542

High Input Voltage, 3.78A Single-Cell Battery Charger

with NVDC Power Path Management

PACKAGE/ORDERING INFORMATION

SPECIFIED

TEMPERATURE

RANGE

PACKAGE

DESCRIPTION

ORDERING

NUMBER

PACKAGE

MARKING

PACKING

OPTION

MODEL

SGM41541

YTQF24

XXXXX

SGM41541

SGM41542

TQFN-4×4-24L

SGM41541YTQF24G/TR

Tape and Reel, 3000

-40℃ to +85℃

SGM41542

YTQF24

XXXXX

SGM41542YTQF24G/TR

MARKING INFORMATION

NOTE: XXXXX = Date Code, Trace Code and Vendor Code.

X X X X X

Vendor Code

Trace Code

Date Code - Year

Green (RoHS & HSF): SG Micro Corp defines "Green" to mean Pb-Free (RoHS compatible) and free of halogen substances. If

you have additional comments or questions, please contact your SGMICRO representative directly.

ABSOLUTE MAXIMUM RATINGS

Voltage Range (with Respect to GND)

RECOMMENDED OPERATING CONDITIONS

Input Voltage Range, V_VBUS..............................3.9V to 13.5V

Input Current (VBUS), I_IN..................................... 3.8A (MAX)

Output DC Current (SW), I_SWOP.............................. 5A (MAX)

Battery Voltage, V_BATOP................................... 4.624V (MAX)

Fast Charging Current, I_CHGOP........................... 3.78A (MAX)

Discharging Current (Continuous), I_BATOP............... 6A (MAX)

Ambient Temperature Range......................... -40℃ to +85℃

Junction Temperature Range....................... -40℃ to +125℃

VAC, VBUS (Converter Not Switching)............-2V to 22V ⁽¹⁾

BTST, PMID (Converter Not Switching)........... -0.3V to 22V

SW ...................................................................... -2V to 16V

SW (Peak for 10ns Duration).............................. -3V to 16V

BTST to SW....................................................... -0.3V to 6V

D+, D- ................................................................ -0.3V to 6V

REGN, TS, nCE, BAT, SYS (Converter Not Switching)

........................................................................... -0.3V to 6V

SDA, SCL, nINT, nQON, STAT, DCEN ............. -0.3V to 6V

Package Thermal Resistance

OVERSTRESS CAUTION

Stresses beyond those listed in Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to

absolute maximum rating conditions for extended periods

may affect reliability. Functional operation of the device at any

conditions beyond those indicated in the Recommended

Operating Conditions section is not implied.

TQFN-4×4-24L, θ^JA.................................................. 35℃/W

TQFN-4×4-24L, θ^{JB............................................................................}10℃/W

TQFN-4×4-24L, θJC............................................................................16℃/W

Output Sink Current

STAT.............................................................................6mA

nINT..............................................................................6mA

Junction Temperature.................................................+150℃

Storage Temperature Range........................-65℃ to +150℃

Lead Temperature (Soldering, 10s)............................+260℃

ESD Susceptibility

ESD SENSITIVITY CAUTION

This integrated circuit can be damaged if ESD protections are

not considered carefully. SGMICRO recommends that all

integrated circuits be handled with appropriate precautions.

Failureto observe proper handlingand installation procedures

can cause damage. ESD damage can range from subtle

performance degradation tocomplete device failure. Precision

integrated circuits may be more susceptible to damage

because even small parametric changes could cause the

device not to meet the published specifications.

HBM.............................................................................2000V

CDM ............................................................................1000V

NOTE:

1. Maximum 28V for 10 seconds.

DISCLAIMER

SG Micro Corp reserves the right to make any change in

circuit design, or specifications without prior notice.

SG Micro Corp

www.sg-micro.com

SEPTEMBER 2022

3

SGM41541

SGM41542

High Input Voltage, 3.78A Single-Cell Battery Charger

with NVDC Power Path Management

PIN CONFIGURATIONS

SGM41541 (TOP VIEW)

SGM41542 (TOP VIEW)

24 23 22 21 20 19

VAC

1

2

3

4

5

6

18 GND

17 GND

16 SYS

VBUS

D+

1

2

3

4

5

6

18 GND

17 GND

16 SYS

PSEL

D-

nPG

SGM41541

SGM41542

STAT

SYS

STAT

SYS

15

14 BAT

BAT

15

14 BAT

BAT

SCL

SDA

SCL

SDA

13

7

8

9

10 11 12

7

8

9

10 11 12

TQFN-4×4-24L

PIN DESCRIPTION

NAME

TYPE ⁽¹⁾

FUNCTION

SGM

41541

41542

Sense Input for DC Input Voltage (Typically from an AC/DC Adaptor). Must be connected

to VBUS pin. (SGM41541 only)

1

2

—

VAC

AI

DI

Power Source Selection Input. If PSEL is pulled high, the input current limit is set to 500mA

(USB 2.0) and if it is pulled low, the limit is set to 2.4A (adaptor). When the I²C link to the

host is established, the host can program a different input current limit value by writing to

the IINDPM[4:0] register. (SGM41541 only)

PSEL

Positive USB Data Line. D+/D- based USB device protocol detection and voltage of this pin

can be set by DP_VSET[1:0]. (SGM41542 only)

—

3

2

—

3

D+

nPG

D-

AIO

DO

Open-Drain Active Low Input Power Good Indicator. Use a 10kΩ pull-up to the logic high

rail. A low state indicates a good input (V_{VBUS_UVLOZ}< V_VBUS< V_{VBUS_OV}, V_VBUSis above sleep

mode threshold, and V_VBUS> V_VBUSMINwhen I_{BAD_SRC}= 30mA). (SGM41541 only)

Negative USB Data Line. D+/D- based USB device protocol detection and voltage of this

pin can be set by DM_VSET[1:0]. (SGM41542 only)

—

AIO

Open-Drain Charge Status Output. Use a 10kΩ pull-up to the logic high rail (or an LED + a

resistor). The STAT pin acts as follows:

During charge: low (LED ON).

4

STAT

DO

Charge completed or charger in sleep mode: high (LED OFF).

Charge suspended (in response to a fault): 1Hz, 50% duty cycle pulses (LED BLINKS).

The function can be disabled via EN_ICHG_MON[1:0] register.

5

6

5

6

SCL

SDA

DI

I²C Clock Signal. Use a 10kΩ pull-up to the logic high rail.

I²C Data Signal. Use a 10kΩ pull-up to the logic high rail.

DIO

Open-Drain Interrupt Output Pin. Use a 10kΩ pull-up to the logic high rail. The nINT pin is

active low and sends a negative 256µs pulse to inform host about a new charger status

update or a fault.

7

8

7

nINT

NC

DO

—

8, 24

Do Not Connect and Leave This Pin Floating.

SG Micro Corp

www.sg-micro.com

SEPTEMBER 2022

4

SGM41541

SGM41542

High Input Voltage, 3.78A Single-Cell Battery Charger

with NVDC Power Path Management

PIN DESCRIPTION (continued)

NAME

TYPE ⁽¹⁾

FUNCTION

SGM

41541

41542

Charge Enable Input Pin (Active Low). Battery charging is enabled when CHG_CONFIG bit

is 1 and nCE pin is pulled low.

9

nCE

DI

—

External Direct Charge Enable Pin. This pin can be set high to enable an external direct

charging device.

10

DCEN

Temperature Sense Input Pin. Connect to the battery NTC thermistor that is grounded on

the other side. To program operating temperature window, it can be biased by a resistor

divider between REGN and GND. Charge suspends if TS voltage goes out of the

programmed range. It is recommended to use a 103AT-2 type thermistor.

11

12

11

12

TS

AI

DI

If NTC or TS pin function is not needed, use a 10kΩ/10kΩ pair for the resistor divider.

BATFET On/Off Control Input. Use an internal pull-up to a small voltage for maintaining the

default high logic (whenever a source or battery is available). In the ship mode, the

BATFET is off. To exit ship mode and turn BATFET on, a logic low pulse with a duration of

t_SHIPMODE(1s TYP) can be applied to nQON. When VBUS source is not connected, a logic

low pulse with a duration of t_{QON_RST}(10s TYP) resets the system power (SYS) by turning

BATFET off for t_{BATFET_RST}(320ms TYP) and then back on to provide a full power reset for

system.

nQON

Battery Positive Terminal Pin. Use a 10µF capacitor between BAT and GND pins close to

the device. SYS and BAT pins are internally connected by BATFET with current sensing

capability.

13, 14

15, 16

13, 14

15, 16

BAT

SYS

P

Connection Point to Converter Output. SYS is connected to the converter LC filter output

that powers the system. BAT to SYS internal current (power from battery to system) is

sensed. Connect a 20μF capacitor between SYS pin and GND close to the device.

17, 18

19, 20

17, 18

19, 20

GND

SW

—

P

Ground Pin of the Device.

Switching Node Output. Connect SW pin to the output inductor. Connect a 47nF bootstrap

capacitor from SW pin to BTST pin.

High-side Driver Positive Supply. It is internally connected to the boost-strap diode

cathode. Use a 47nF ceramic capacitor from SW pin to BTST pin.

21

22

21

22

BTST

P

LDO Output that Powers LSFET Driver and Internal Circuits. Internally, the REGN pin is

connected to the anode of the bootstrap diode. Place a 4.7μF (10V rating) ceramic

capacitor between REGN pin and GND. It is recommended to place the capacitor close to

the REGN pin.

REGN

PMID Pin. PMID is the actual higher voltage port of converter (Buck or Boost) and is

connected to the drain of the reverse blocking MOSFET (RBFET) and the drain of HSFET.

Connect a 22μF ceramic capacitor from PMID pin to GND. It is the proper point for

decoupling of high frequency switching currents.

23

24

23

1

PMID

VBUS

—

P

Charger Input (V_IN). The internal N-channel reverse blocking MOSFET (RBFET) is

connected between VBUS and PMID pins. Place a 1μF ceramic capacitor from VBUS pin

to GND close to the device. For SGM41542, this pin senses the input voltage.

Thermal Pad and Ground Reference. It is the ground reference for the device and also the

thermal pad to conduct heat from the device (not suitable for high current return). Tie

externally to the PCB ground plane (GND). Thermal vias under the pad are needed to

conduct the heat to the PCB ground planes.

Exposed

Pad

Exposed

Pad

NOTE:

1. AI = Analog Input, AO = Analog Output, AIO = Analog Input and Output, DI = Digital Input, DO = Digital Output, DIO = Digital

Input and Output, P = Power.

SG Micro Corp

www.sg-micro.com

SEPTEMBER 2022

5

SGM41541

SGM41542

High Input Voltage, 3.78A Single-Cell Battery Charger

with NVDC Power Path Management

ELECTRICAL CHARACTERISTICS

(V_{VBUS_UVLOZ}< V_VBUS< V_{VBUS_OV}and V_VBUS> V_BAT+ V_SLEEP, T_J= -40℃ to +85℃, typical values are at T_J= +25℃, unless

otherwise noted.)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX UNITS

Quiescent Currents

Battery Discharge Current

(BAT, SW, SYS) in Buck Mode

V_BAT= 4.5V, V_VBUS< V_{VBUS_UVLOZ}

leakage between BAT and VBUS, BATFET off

,

I_{BQ_VBUS}

I_{BQ_HIZ_BOFF}

I_{BQ_HIZ_BON}

0.1

9

1

µA

Battery Discharge Current

(BAT) in Buck Mode

V_BAT= 4.5V, HIZ mode and BATFET_DIS = 1 or no

VBUS, I²C disabled, BATFET disabled

20

30

40

Battery Discharge Current

(BAT, SW, SYS)

V_BAT= 4.5V, HIZ mode and BATFET_DIS = 0 or no

VBUS, I²C disabled, BATFET enabled

15

25

V

_VBUS= 5V, HIZ mode and BATFET_DIS = 1,

no battery

I_{VBUS_HIZ}

µA

V_VBUS= 12V, HIZ mode and BATFET_DIS = 1,

no battery

55

2.5

4

80

3

Input Supply Current (VBUS)

in Buck Mode

V

_VBUS= 12V, V_VBUS> V_BAT, converter not switching

I_VBUS

mA

V_BAT= 3.8V, I_SYS= 0A, V_VBUS> V_BAT, V_VBUS> V_{VBUS_UVLOZ}

converter switching, BATFET off

,

Battery Discharge Current

in Boost Mode

I_BOOST

V_BAT= 4.2V, I_VBUS= 0A, converter switching

3

BAT Pin and VBUS Pin Power-Up

VBUS Operating Range

VBUS UVLO to Have Active I²C

(with No Battery)

V_{VBUS_OP}

V_VBUSrising

3.9

13.5

3.6

V

V_{VBUS_UVLOZ}

3.2

400

3.4

V_VBUSrising, T_J= +25℃

I²C Active Hysteresis

V_{VBUS_UVLOZ_HYS}V_VBUSfalling from above V_{VBUS_UVLOZ}

V_{VBUS_PRESENT}

V_{VBUS_PRESENT_HYS}V_VBUSfalling from above V_{VBUS_PRESENT}

mV

V

V_VBUSMinimum (as One of the

Conditions) to Turn on REGN

3.8

80

V_VBUSrising, T_J= +25℃

V_VBUSHysteresis (as One of the

Conditions) to Turn on REGN

400

50

mV

V

_VBUS- V_BAT, V_{VBUSMIN_FALL}≤ V_BAT≤ V_REG, V_VBUSfalling,

Sleep Mode Falling Threshold

Sleep Mode Rising Threshold

20

V_SLEEP

T_J= +25℃

V

_VBUS- V_BAT, V_{VBUSMIN_FALL}≤ V_BAT≤ V_REG, V_VBUSrising,

140

190

6.5

240

V_SLEEPZ

T_J= +25℃

6.5V Setting

VBUS

OVP[1:0] = 01

OVP[1:0] = 10

OVP[1:0] = 11

OVP[1:0] = 01

OVP[1:0] = 10

OVP[1:0] = 11

6.15

9.95

13.4

6.85

Over-Voltage

Rising Threshold

10.5V Setting

14V Setting

6.5V Setting

10.5V Setting

14V Setting

V_{VBUS_OV_RISE}

V_VBUSrising

10.5 11.05

V

14

14.6

110

260

300

VBUS

Over-Voltage

Hysteresis

V_{VBUS_OV_HYS}

mV

BAT Voltage to Have Active I²C

(No Source on VBUS)

V_{BAT_UVLOZ}

V_BATrising

2.65

V

V_{BAT_DPL_FALL}

V_{BAT_DPL_RISE}

V_{BAT_DPL_HYS}

V_BATfalling

V_BATrising

2

2.25

2.5

BAT Depletion Threshold

2.25

2.75

BAT Depletion Rising Hysteresis

250

mV

mA

Bad Adapter Detection Current

(Internal Current Sink)

I_{BAD_SRC}

Sink current from VBUS to GND

V_VBUSfalling

30

3.8

215

Bad Adapter Detection (VBUS

Voltage Drop) Falling Threshold

V_{VBUSMIN_FALL}

V_{VBUSMIN_HYS}

3.65

3.9

V

Bad Adapter Detection (VBUS

Voltage Drop) Hysteresis

mV

SG Micro Corp

www.sg-micro.com

SEPTEMBER 2022

6

SGM41541

SGM41542

High Input Voltage, 3.78A Single-Cell Battery Charger

with NVDC Power Path Management

ELECTRICAL CHARACTERISTICS (continued)

(V_{VBUS_UVLOZ}< V_VBUS< V_{VBUS_OV}and V_VBUS> V_BAT+ V_SLEEP, T_J= -40℃ to +85℃, typical values are at T_J= +25℃, unless

otherwise noted.)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX UNITS

Power Path Management

V_BAT= 4.4V, V_BAT> V_{SYS_MIN}

BATFET_DIS = 1

,

V_BAT+

50mV

System Regulation Voltage

V_SYS

V

V_BAT< SYS_MIN[2:0] = 101 (3.5V),

BATFET_DIS = 1

Minimum DC System Voltage Output

Maximum DC System Voltage Output

V_{SYS_MIN}

V_{SYS_MAX}

3.5

3.65

4.45

V_BAT≤ 4.4V, V_BAT> V_{SYS_MIN}= 3.5V,

BATFET_DIS = 1

4.38

4.52

V

Top Reverse Blocking MOSFET

On-Resistance between VBUS and PMID -

Q1

R_{ON_RBFET}

27

25

mΩ

Top Switching MOSFET On-Resistance

between PMID and SW - Q2

R_{ON_HSFET}

R_{ON_LSFET}

V_FWD

V_REGN= 5V

Bottom Switching MOSFET On-Resistance

between SW and GND - Q3

28

25

mΩ

BATFET Forward Voltage in Supplement Mode

Battery Charger

mV

Charge Voltage Program Range

Charge Voltage Step

V_{BAT_REG_RANGE}

V_{BAT_REG_STEP}

3.856

4.624

V

32

mV

4.192 4.208 4.224

4.184 4.208 4.232

4.333 4.35 4.367

4.324 4.35 4.376

4.380 4.397 4.414

4.371 4.397 4.423

T_J= +25℃

VREG[4:0] = 01011

(4.208V)

T_J= -40℃ to +85℃

T_J= +25℃

VREG[4:0] = 01111

(4.352V)

Charge Voltage Setting

V_{BAT_REG}

V

T_J= -40℃ to +85℃

T_J= +25℃

VREG[4:0] = 10001

(4.400V)

T_J= -40℃ to +85℃

T_J= +25℃

V_{BAT_REG}= 4.208V or

-0.4

-0.6

0

0.4

0.6

Charge Voltage Setting Accuracy

V_{BAT_REG_ACC}

V

_{BAT_REG}= 4.352V or

_{BAT_REG}= 4.400V

%

T_J= -40℃ to +85℃

Charge Current Regulation Range

Charge Current Regulation Step

I_{CHG_REG_RANGE}

I_{CHG_REG_STEP}

3780

mA

60

0.035 0.055 0.075

T_J= +25℃

I

_CHG= 60mA

I_CHG= 240mA

I_CHG= 720mA

I_CHG= 1.38A

I_CHG= 2.04A

I_CHG= 60mA

I_CHG= 240mA

I_CHG= 720mA

I_CHG= 1.38A

I_CHG= 2.04A

0.2

0.23 0.255

V_BAT= 3.8V,

T_J= +25℃

0.64

1.24

1.93

0.7

0.755

1.47

2.15

0.08

1.35

2.04

Charge Current Regulation Setting

I_{CHG_REG}

A

0.045 0.06

0.21

0.67

1.31

1.97

150

0.24 0.275

V_BAT= 3.1V,

T_J= +25℃

0.72

1.38

2.04

180

0.77

1.45

2.11

210

Pre-Charge Current Regulation Setting

Battery LOW Falling Threshold

Battery LOW Rising Threshold

I_PRECHG

mA

V

IPRECHG[3:0] = 0010 (180mA), T_J= +25℃

V_{BATLOW_FALL}I_CHG= 480mA

2.82

3.06

2.95

3.15

3.08

3.24

V_{BATLOW_RISE}Change from pre-charge to fast charging

ITERM[3:0] = 0010

V

I

_CHG> 1.26A,

135

145

167

172

200

V

_{BAT_REG}= 4.208V

(180mA), T_J= +25℃

ITERM[3:0] = 0010

(180mA), T_J= +25℃

Termination Current Regulation Setting

I_TERM

mA

I_CHG≤ 1.26A,

V

_{BAT_REG}= 4.208V

SG Micro Corp

www.sg-micro.com

SEPTEMBER 2022

7

SGM41541

SGM41542

High Input Voltage, 3.78A Single-Cell Battery Charger

with NVDC Power Path Management

ELECTRICAL CHARACTERISTICS (continued)

(V_{VBUS_UVLOZ}< V_VBUS< V_{VBUS_OV}and V_VBUS> V_BAT+ V_SLEEP, T_J= -40℃ to +85℃, typical values are at T_J= +25℃, unless

otherwise noted.)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX UNITS

Battery Charger

V_SHORT

V_SHORTZ

I_SHORT

1.93

2.13

2

2.07

V

V_BATfalling, T_J= +25℃

Battery Short Voltage

2.19

90

2.25

V_BATrising, T_J= +25℃

Battery Short Current

V_BAT< V_SHORTZ

mA

VRECHG = 0 (100mV)

VRECHG = 1 (200mV)

80

110

220

17

145

mV

260

Recharge Threshold below V_{BAT_REG}

V_RECHG

V_BATfalling

V_SYS= 4.2V

190

System Discharge Load Current

BATFET MOSFET On-Resistance

I_{SYS_LOAD}

mA

R_{ON_BATFET}

19

25

mΩ

V_BAT= 4.2V, measured from BAT pin to SYS pin, T_J= +25℃

Input Voltage and Current Regulation (DPM: Dynamic Power Management)

VINDPM_OS = 00 (4.4V)

4.31

6.29

7.84

4.4

4.49

6.49

8.12

VINDPM_OS = 01 (6.4V)

VINDPM_OS = 10 (8V)

VINDPM_OS = 11 (11V)

6.39

7.98

Input Voltage Regulation Limit

V_INDPM

VINDPM[3:0] = 0101

V

10.77 10.96 11.15

Input Voltage Regulation Accuracy

V_{INDPM_ACC}

V_{DPM_VBAT}

-2

2

%

V

Input Voltage Regulation Limit

Tracking VBAT

V_BAT= 4V, V_INDPM= 3.9V,

VDPM_BAT_TRACK[1:0] = 11 (300mV)

4.35

IINDPM[4:0] = 00100 (500mA)

IINDPM[4:0] = 01000 (900mA)

IINDPM[4:0] = 01110 (1.5A)

IINDPM[4:0] = 10011 (2A)

445

825

640

V

_VBUS= 5V, current

1000

1530

1980

pulled from SW,

USB Input Current Regulation Limit

I_INDPM

mA

%

1370

1820

T_J= +25℃

Input Current Limit during System

Start-Up Sequence

I_{IN_START}

270

BAT Pin Over-Voltage Protection

V_{BATOVP_RISE}

V_BATrising

V_BATfalling

102.8 103.8 104.8

100.8 101.8 102.8

As percentage of

Battery Over-Voltage Threshold

V_{BAT_REG}, T_J= +25℃

V_{BATOVP_FALL}

Thermal Regulation and Thermal Shutdown

120

80

TREG = 1 (120℃)

TREG = 0 (80℃)

Junction Temperature Regulation

Threshold

T_{JUNCTION_REG}Temperature increasing

℃

Thermal Shutdown Rising

Temperature

T_SHUT

Temperature increasing

150

30

℃

Thermal Shutdown Hysteresis

T_{SHUT_HYS}

JEITA Thermistor Comparator (Buck Mode)

Charge suspends if temperature T is below T1

(T < T1), as percentage of V_REGN

72.6

71.1

67.5

73.2

71.6

68.0

73.8

72.1

68.5

T1 (0℃) Threshold Voltage on TS Pin

V_T1

%

V_T1Falling

As percentage of V_REGN

Charge sets to I_CHG/2 and the lower of 4.1V and V_REG

if T1 < T < T2, as percentage of V_REGN

T2 (10℃) Threshold Voltage on TS

V_T2

V_T3

V_T4

V_T2Falling

As percentage of V_REGN

66.2

45.4

66.7

45.9

67.2

46.4

V_T3Rising

Charge sets to the lower of 4.1V and V_REG

if T3 < T < T4, as percentage of V_REGN

T3 (45℃) Threshold Voltage on TS

44

35

44.5

35.5

34.2

45

36

V_T4Rising

As percentage of V_REGN

T4 (60℃) Threshold Voltage on TS

Charge suspends if T > T4, as percentage of V_REGN

33.7

34.7

SG Micro Corp

www.sg-micro.com

SEPTEMBER 2022

8

SGM41541

SGM41542

High Input Voltage, 3.78A Single-Cell Battery Charger

with NVDC Power Path Management

ELECTRICAL CHARACTERISTICS (continued)

(V_{VBUS_UVLOZ}< V_VBUS< V_{VBUS_OV}and V_VBUS> V_BAT+ V_SLEEP, T_J= -40℃ to +85℃, typical values are at T_J= +25℃, unless

otherwise noted.)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX UNITS

Cold or Hot Thermistor Comparator (Boost Mode)

Cold Temperature Threshold

(TS Pin Voltage Rising Threshold)

79.3

78.5

30.7

33.9

80

79

80.7

%

79.5

As percentage of V_REGN(approx. -20℃ w/ 103AT)

As percentage of V_REGN

V_BCOLD

TS Voltage Falling (Exit Cold Range)

Hot Temperature Threshold

(TS Pin Voltage Falling Threshold)

31.2

34.5

31.7

%

35.1

As percentage of V_REGN(approx. 60℃ w/ 103AT)

As percentage of V_REGN

V_BHOT

TS Voltage Rising (Exit Hot Range)

Charge Over-Current Comparator (Cycle-by-Cycle)

HSFET Cycle-by-Cycle Over-Current

I_{HSFET_OCP}

6.6

9

9.2

A

T_J= +25℃

Threshold

System Overload Threshold

I_{BATFET_OCP}

T_J= +25℃

Charge Under-Current Comparator (Cycle-by-Cycle)

LSFET Under-Current Falling Threshold I_{LSFET_UCP}

PWM

Change rectifier from synchronous mode to

non-synchronous mode

180

mA

Buck mode

Oscillator frequency, T_J= +25℃

Boost mode

1380

1500

99

1620

PWM Switching Frequency

f_SW

kHz

%

Maximum PWM Duty Cycle ⁽¹⁾

Boost Mode Operation

D_MAX

Boost Mode Regulation Voltage

V_{OTG_REG}

V_BAT= 3.8V, I_PMID= 0A, BOOSTV[1:0] = 10 (5.15V)

4.99

-2.8

5.13

5.28

2.9

V

Boost Mode Regulation Voltage

Accuracy

V_{OTG_REG_ACC}V_BAT= 3.8V, I_PMID= 0A, BOOSTV[1:0] = 10 (5.15V)

V_BATfalling, MIN_BAT_SEL = 0

%

2.88

3.03

2.32

2.51

1.1

3.0

3.2

2.5

2.7

1.4

2.35

6

3.1

3.35

2.66

2.88

1.75

2.8

V_BATrising, MIN_BAT_SEL = 0

V_{BATLOW_OTG}

Exit Boost Mode Due to Low Battery

Voltage

V

A

V_BATfalling, MIN_BAT_SEL = 1

V_BATrising, MIN_BAT_SEL = 1

BOOST_LIM = 0 (1.2A), T_J= +25℃

I_OTG

OTG Mode Maximum Output Current

OTG Over-Voltage Threshold

1.9

BOOST_LIM = 1 (2A), T_J= +25℃

V_{OTG_OVP}

Rising threshold

5.8

6.2

V

HSFET Under-Current Falling

Threshold

Change rectifier from synchronous mode to

non-synchronous mode

I_{OTG_HSZCP}

430

mA

REGN LDO

V_VBUS= 9V, I_REGN= 40mA

V_VBUS= 5V, I_REGN= 20mA

4.35

4.75

4.85

5.15

4.95

REGN LDO Output Voltage

V_REGN

V

Logic I/O Pin Characteristics (nCE, DCEN, SCL, SDA, nQON)

Input Low Threshold

Input High Threshold

Input Low Threshold

Input High Threshold

V_IL

V_IH

V_IL

0.4

V

SCL, SDA,

nQON, nCE

1.3

0.1

REGN

0.1

V

DCEN

V_IH

I_BIAS

V

High-Level Leakage Current

Pull up rail 1.8V

1

µA

Logic I/O Pin Characteristics (nPG, STAT, nINT) – Open-Drain

Low-Level Output Voltage V_OL

0.2

V

NOTE: 1. Guaranteed by design. Not production tested.

SG Micro Corp

www.sg-micro.com

SEPTEMBER 2022

9

SGM41541

SGM41542

High Input Voltage, 3.78A Single-Cell Battery Charger

with NVDC Power Path Management

TIMING REQUIREMENTS

(V_{VBUS_UVLOZ}< V_VBUS< V_{VBUS_OV}and V_VBUS> V_BAT+ V_SLEEP, T_J= -40℃ to +85℃, typical values are at T_J= +25℃, unless

otherwise noted.)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

V_VBUS/V_BATPower-Up

V_VBUSrising above ACOV threshold to

turn off Q2

VBUS OVP Reaction Time

t_ACOV

0.1

30

µs

Wait Window for Bad Adapter Detection

Battery Charger

t_{BAD_SRC}

ms

Deglitch Time for Charge Termination

Deglitch Time for Recharge

t_{TERM_DGL}

t_{RECHG_DGL}

t_{SYSOVLD_DGL}

t_BATOVP

230

112

1

ms

µs

System Over-Current Deglitch Time to Turn off Q4

µs

Battery Over-Voltage Deglitch Time to Disable

Charge

t_{BATOVP_DCEN}DCEN active

2.8

14.5

31

3.5

16

4.4

17.9

39

ms

h

Typical Charge Safety Timer Range

Typical Top-Off Timer Range

t_SAFETY

CHG_TIMER = 1

t_{TOP_OFF}

TOPOFF_TIMER[1:0] = 10 (35min)

35

min

nQON Timing and Ship Mode Timing

nQON Negative Pulse Low Pulse Width to Turn on

BATFET and Exit Ship Mode

t_SHIPMODE

0.9

1

1.2

s

nQON Low Time to Reset BATFET

BATFET off Time during Full System Reset

Wait Delay for Entering Ship Mode

Digital Clock and Watchdog Timer

t_{QON_RST}

t_{BATFET_RST}

t_{SM_DLY}

9

10

11.5

355

s

ms

s

285

11

320

12.3

13.5

WATCHDOG[1:0] = 01,

REGN LDO disabled

Watchdog Reset Time

t_WDT

40.9

s

Digital Clock Frequency in Low Power

Digital Clock Frequency

I²C Interface

f_LPDIG

f_DIG

REGN LDO disabled

REGN LDO enabled

31

kHz

500

SCL Clock Frequency

f_SCL

400

kHz

SG Micro Corp

www.sg-micro.com

SEPTEMBER 2022

10

SGM41541

SGM41542

High Input Voltage, 3.78A Single-Cell Battery Charger

with NVDC Power Path Management

TYPICAL PERFORMANCE CHARACTERISTICS

Charge Efficiency vs. Charge Current

System Efficiency vs. System Load Current

96

94

92

90

88

86

84

82

80

78

76

97

92

87

82

77

72

67

62

57

V_VBUS= 5V

V_VBUS= 9V

V_VBUS= 12V

V_VBUS= 5V

V_VBUS= 9V

V_VBUS= 12V

V_{SYS MIN}= 3.5V, PFM Enable

V_BAT= 3.8V, I_SYS= 0A, DCR = 5.5mΩ

_

0.0 0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6 4.0

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0

Charge Current (A)

System Load Current (A)

Boost Mode Efficiency vs. Output Current

Charge Current Accuracy vs. Charge Current I²C Setting

6

96

91

86

81

76

71

66

61

56

4

V_BAT= 3.1V

V_BAT= 3.8V

V_BAT= 3.2V

2

0

-2

-4

-6

V_VBUS= 9V

3.0 3.5 4.0

PFM Enable

0.5

1.0

1.5

2.0

2.5

0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0

Charge Current (A)

Output Current (A)

Constant Charge Voltage vs. Temperature

Input Current Limit vs. Temperature

V_VBUS= 5V

4.35

1400

1200

1000

800

600

400

200

0

V_VBUS= 5V

V_VBUS= 12V

4.30

4.25

4.20

4.15

4.10

4.05

I_INDPM= 500mA

60 80 100 120

-40 -20

0

20

40

60

80 100 120

-40 -20

0

20

40

Temperature (℃)

SG Micro Corp

www.sg-micro.com

SEPTEMBER 2022

11

SGM41541

SGM41542

High Input Voltage, 3.78A Single-Cell Battery Charger

with NVDC Power Path Management

TYPICAL PERFORMANCE CHARACTERISTICS (continued)

System Voltage vs. System Load Current

3.80

3.75

3.70

3.65

3.60

4.30

4.25

4.20

4.15

4.10

V_VBUS= 5V, V_{SYS_MIN}= 3.5V

I_INDPM= 3.8A, V_BAT= 2.9V

V_VBUS= 5V, V_{SYS_MIN}= 3.5V

I_INDPM= 3.8A, V_BAT= 4.2V

0.0

0.5

1.0

1.5

2.0

2.5

3.0

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0

System Load Current (A)

PWM Switching Waveform

PFM Switching Waveform

AC Coupled

V_SYS

SW

I_L

V_VBUS= 9V, I_SYS= 10mA, Charge Disable, No Battery

V_VBUS= 12V, V_BAT= 3.8V, I_CHG= 3A

Time (500ns/div)

Time (20μs/div)

Boost Mode Switching Waveform

Boost Mode Load Transient

AC Coupled

V_VBUS

SW

I_VBUS

I_L

I_BAT

V_BAT= 3.8V, I_LOAD= 1A

V_BAT= 3.8V, I_LOAD= 0A-1A

Time (500ns/div)

Time (5ms/div)

SG Micro Corp

www.sg-micro.com

SEPTEMBER 2022

12

SGM41541

SGM41542

High Input Voltage, 3.78A Single-Cell Battery Charger

with NVDC Power Path Management

TYPICAL PERFORMANCE CHARACTERISTICS (continued)

Power-Up with Charge Disabled

Power-Up with Charge Enabled

V_VBUS

REGN

V_SYS

V_VBUS

REGN

V_SYS

SW

I_BAT

V_VBUS= 5V, V_BAT= 3.2V

Time (50ms/div)

Charge Enable

Time (100ms/div)

Charge Disable

STAT

nCE

STAT

nCE

SW

I_BAT

V_VBUS= 5V

Time (500μs/div)

Time (10μs/div)

Input Current DPM Response without Battery

Load Transient during Supplement Mode

AC Coupled

V_SYS+ 3V Offset

V_SYS

I_IN

I_BAT

I_SYS

V_VBUS= 5V, I_INDPM= 3A, I_SYS= 0A-2A-0A, Charge Disable

V_VBUS= 9V, I_INDPM= 1.5A, V_BAT= 3.8V, I_CHG= 2A, I_SYS= 0A-4A

Time (2ms/div)

SG Micro Corp

www.sg-micro.com

SEPTEMBER 2022

13

SGM41541

SGM41542

High Input Voltage, 3.78A Single-Cell Battery Charger

with NVDC Power Path Management

TYPICAL APPLICATION CIRCUITS

22µF

OTG

5V at 1.2A

Input

3.9V to 13.5V

VAC

PMID

LS/SC

DCEN

VBUS

1µF

1µH

VSYS

10µF × 2

SW

47nF

BTST

PSEL

PHY

20Ω

REGN

SYS

4.7µF

SGM41541

GND

2.2kΩ

SYS

BAT

nPG

I_CHG= 2A

10µF

V_REF

STAT

10kΩ

Host

51pF

REGN

SDA

SCL

nINT

47Ω

5.23kΩ

30.9kΩ

TS

nCE

nQON

10kΩ

Optional

Figure 1. SGM41541 Typical Application Circuit

22µF

OTG

5.15V at 2A

Input

3.9V to 13.5V

PMID

LS/SC

DCEN

VBUS

1µF

1µH

VSYS

10µF × 2

SW

47nF

BTST

20Ω

D+

D-

USB

REGN

4.7µF

SGM41542

SYS

GND

SYS

BAT

I_CHG= 2A

10µF

V_REF

2.2kΩ

10kΩ

STAT

10kΩ

Host

51pF

47Ω

REGN

5.23kΩ

SDA

SCL

nINT

TS

nCE

nQON

30.9kΩ

10kΩ

Optional

Figure 2. SGM41542 Typical Application Circuit

SG Micro Corp

www.sg-micro.com

SEPTEMBER 2022

14

SGM41541

SGM41542

High Input Voltage, 3.78A Single-Cell Battery Charger

with NVDC Power Path Management

FUNCTIONAL BLOCK DIAGRAM

VBUS

PMID

RBFET (Q1)

REGN

LDO

REGN

BTST

Q1

Control

Protections:

Voltage & Current

Sensing

OVP

UVP

OCP

UCP

OTP

&

DAC Reference

HSFET (Q2)

D+

SW

(SGM41542 Only)

Converter

Control

Input

Source

Detection

D-

REGN

(SGM41542 Only)

PSEL

(SGM41541 Only)

LSFET (Q3)

GND

SYS

REGN

DCEN

Digital

Control

I_CHG

nPG

(SGM41541 Only)

Q4 Gate

Control

BATFET (Q4)

nINT

BAT

V_PULL-UP

STAT

nQON

nCE

SDA

SCL

Battery

Temperature

Sensing

I²C

Interface

JEITA

Control

TS

SGM41541

SGM41542

Figure 3. Block Diagram

SG Micro Corp

www.sg-micro.com

SEPTEMBER 2022

15

SGM41541

SGM41542

High Input Voltage, 3.78A Single-Cell Battery Charger

with NVDC Power Path Management

DETAILED DESCRIPTION

The SGM41541/SGM41542 are power management and

charger devices for applications such as cell phones and

tablets that use high capacity single-cell Li-Ion or Li-polymer

batteries. The SGM41541/SGM41542 can accommodate a

wide range of input sources including USB, wall adapter and

car chargers. It is optimized for 5V input (USB voltage) but is

capable to operate with input voltages from 3.9V to 13.5V. It

also supports JEITA profile for battery charging safety at high

or low temperatures. Automatic power path selection to

power the system (SYS) from the input source (VBUS),

battery (BAT), or both, is another feature of the device.

Battery charge current is programmable and can reach to a

maximum of 3.78A (charge). In the Boost mode, the battery

voltage is boosted to power the VBUS pin (2A MAX) when it

is a power receiving node (USB OTG) that is typically

regulated to 5.15V.

Power-Up from Battery Only (No Input

Source)

When only the battery is presented as a source and its

voltage is above depletion threshold (V_{BAT_DPL_RISE}), the

BATFET turns on and connects the battery to the system.

The quiescent current is minimum because the REGN LDO

remains off. Conduction losses are also low due to small

R_DSONof BATFET. Low losses help to extend the battery run

time.

The discharge current through BATFET is continuously

monitored. In the supplement mode, if a system overload (or

short) occurs (I_BAT> I_{BATFET_OCP}), the BATFET is turned off

immediately and BATFET_DIS bit is set to 1. The BATFET

will not enable until the input source is applied or one of the

BATFET Enable Mode (Exit Ship Mode) methods (explained

later) is used to activate the BATFET.

The device may operate in several different modes:

Power-Up Process from the Input Power

Source

In HIZ mode, the reverse blocking FET (Q1), internal REGN

LDO, converter switches and some other parts of the internal

circuit remain off to save the battery while it is supplying DC

power to the system through BATFET.

Upon connection of an input source (VBUS), its voltage

sensed from VAC pin (for SGM41541) or VBUS pin (for

SGM41542) is checked to turn on the internal REGN LDO

regulator and the bias circuits (no matter whether the battery

is present or not). The input current limit is determined and

set before the Buck converter is started. The sequences of

actions when VBUS as input source is powered up are:

In the sleep mode, the switching is stopped. The charger

goes to the sleep mode when the input source voltage (V_VBUS

)

is not high enough for charging the battery. In other words,

V_VBUSis smaller than V_BAT+ V_SLEEP(where V_SLEEPis a small

threshold) and Buck converter is not able to charge, even at

its maximum duty cycle. The Boost may also go to the sleep

mode if similar issue happens in the reverse direction (when

1. REGN LDO power-up.

2. Poor power source detection (qualification).

3. Input power source type detection. (Based on D+/D- or

PSEL input. It is used to set the default input current limit

(IINDPM[4:0]).)

V_VBUSis almost equal to or smaller than V_BAT).

In supplement mode, the input source power is not enough to

supply system demanded power and the battery assists by

discharging to the system in parallel, and providing the deficit.

4. Setting of the input voltage limit threshold (VINDPM

threshold).

5. DC/DC converter power-up.

Power-On Reset (POR)

The internal circuit of the device is powered from the greater

Details of the power-up steps are explained in the following

sections.

voltage between V_VBUSand V_BAT. When the voltage of the

selected source goes above its UVLO level (V_VBUS

>

V_{VBUS_UVLOZ}or V_BAT> V_{BAT_UVLOZ}), a POR happens and

activates the sleep comparator, battery depletion comparator

and BATFET driver. Upon activation, the I²C interface will

also be ready for communication and all registers reset to

their default values.

SG Micro Corp

www.sg-micro.com

SEPTEMBER 2022

16

SGM41541

SGM41542

High Input Voltage, 3.78A Single-Cell Battery Charger

with NVDC Power Path Management

DETAILED DESCRIPTION (continued)

REGN LDO Power-Up

The REGN low dropout regulator powers the internal bias

circuits, HSFET and LSFET gate drivers and TS rail

(thermistor pin). The STAT pin can also be pulled up to REGN.

The REGN enables when the following 2 conditions are

satisfied and remain valid for a 220ms delay time, otherwise

the device stays in high impedance mode (HIZ) with REGN

LDO off.

Input Current Limit by PSEL (SGM41541)

PSEL pin interfaces with USB physical layer (PHY) for input

current limit setting. The USB PHY device output is used to

detect if the input is a USB host or a charging port. In the

host-control mode, the host must enable IINDET_EN bit for

reading the PSEL value and updating the IINDPM[4:0]. In the

default mode, IINDPM[4:0] is updated automatically by PSEL

value in real time as given in Table 1.

1. V_VBUS> V_{VBUS_PRESENT}

2. V_VBUS> V_BAT+ V_SLEEPZ(in Buck mode) or V_VBUS< V_BAT

_SLEEP(in Boost mode).

.

Table 1. Input Current Limit Setting from PSEL

+

PSEL

Input Current

V

Input Detection

VBUS_STAT[2:0]

Limit (I_INDPM

)

In HIZ state, the quiescent current drawn from VBUS is very

small (less than I_{VBUS_HIZ}). System is only powered by the

battery in HIZ mode.

USB Host SDP

Adapter

High

Low

500mA

001

010

2400mA

Input Current Limit by D+/D- Detection (SGM41542)

The SGM41542 integrates a D+/D- based input source

detection to set the input current limit when VBUS is plugged

in. When input source is plugged in, the device starts USB

BC1.2 detection and sets the SDP/CDP/DCP related input

current limit. And if the data contact detection timer expires,

the non-standard adapter detection starts and then sets the

input current limit. Please refer to Table 2 and Table 3.

Poor Power Source Detection (Qualification)

When REGN LDO is powered, the input source (adaptor) is

checked for its type and current capacity. To start the Buck

converter, the input (VBUS) must meet the following

conditions:

1. V_VBUS< V_{VBUS_OV}

.

2. V_VBUS> V_VBUSMINduring t_{BAD_SRC}test period (30ms TYP) in

which the I_{BAD_SRC}(30mA TYP) current is pulled from VBUS.

Table 2. Non-Standard Adapter Detection

Non-Standard

Adapter

Input Current

Limit (A)

If the test is failed, the conditions are repeatedly checked

every 2 seconds. As soon as the input source passes

qualification, the VBUS_GD bit in status register is set to 1

and a pulse is sent to the nINT pin to inform the host. Type

detection will start as next step.

D+ Threshold

D- Threshold

Divider 1

Divider 2

Divider 3

Divider 4

VD+ within V2P7 VD- within V2P0

VD+ within V1P2 VD- within V1P2

VD+ within V2P0 VD- within V2P7

VD+ within V2P7 VD- within V2P7

2.1

2

1

2.4

Input Power Source Type Detection

The input source detection will run through the D+/D- lines or

the PSEL pin while REGN LDO is powered and after the

VBUS_GD bit is set. The SGM41542 can detect the input

source types, which include SDP/CDP/DCP and non-standard

adapter through the D+/D- pins following USB BC1.2

Specification. The SGM41541 sets input current limit through

PSEL pins. A pulse is sent to nINT pin to inform the host

when the input source type detection is completed. Some

registers and pins are also updated as detailed below:

Table 3. Input Current Limit Setting from D+/D- Detection

D+/D- Detection

USB SDP (USB500)

USB CDP

Input Current Limit (I_INDPM)

500mA

1.5A

2.4A

2.1A

2A

USB DCP

Divider 1

Divider 2

Divider 3

1A

Divider 4

2.4A

500mA

Unknown 5V Adapter

1. Input current limit register (the value in the IINDPM[4:0]) is

changed to set current limit.

Force Detection of Input Current Limit

2. PG_STAT (power good) bit is set.

The host can set IINDET_EN bit to 1 in host mode to force the

device to run. And the IINDET_EN bit returns to 0 by itself and

input result is updated after the detection is completed.

3. VBUS_STAT[2:0] register is updated to indicate USB or

adaptor input source types.

The input current is always limited by the IINDPM[4:0] register

and the limit can be updated by the host if needed.

D+/D- Output Voltage Setting (SGM41542)

The host can set D+/D- output voltages by DP_VSET[1:0]

and DM_VSET[1:0] to HIZ, 0V, 0.6V or 3.3V. When BC1.2

detection runs, these bits are ignored.

SG Micro Corp

www.sg-micro.com

SEPTEMBER 2022

17

SGM41541

SGM41542

High Input Voltage, 3.78A Single-Cell Battery Charger

with NVDC Power Path Management

DETAILED DESCRIPTION (continued)

1. V_BAT> V_{BATLOW_OTG}

.

Setting of the Input Voltage Limit Threshold

(VINDPM Threshold)

A wide voltage range (3.9V to 5.4V, 5.9V to 9V, 10.5V to 12V)

is supported for the input voltage limit setting in VINDPM[3:0]

and VINDPM_OS[1:0], 4.5V is the default for USB.

2. V_VBUS< V_BAT+ V_SLEEP(in sleep mode).

3. Acceptable voltage range at TS pin (V_BHOT< V_TS< V_BCOLD).

The output voltage is set to V_VBUS= 5.15V and is maintained

as long as V_BATis above V_{BATLOW_OTG}. The output current can

reach up to the programmed value by BOOST_LIM bit (2A or

1.2A). The VBUS_STAT[2:0] status register bits are set to

111 in Boost mode (OTG).

The device supports dynamic tracking of the battery voltage

(VINDPM). VDPM_BAT_TRACK[1:0] bits can be used to

enable tracking (00 to disable tracking) and set the tracking

offset value. When the tracking is enabled, the input voltage

limit will be set to the larger value between the VINDPM[3:0] and

V_BAT+ VDPM_BAT_TRACK[1:0]. The VDPM_BAT_TRACK[1:0]

tracking offset can be set to 200mV, 250mV or 300mV. And

this function only takes effect when VINDPM_OS[1:0] = 00.

To minimize the output overshoot in Boost mode, the device

starts with PFM first and then switches to PWM. As stated

before, PFM can be avoided by using PFM_DIS bit in Buck

and Boost modes.

Host Mode and Default Mode Operation

with Watchdog Timer

DC/DC Converter Power-Up

The 1.5MHz switching converter composed of LSFET and

HSFET is enabled, which can start switching when the input

current limit is set. Converter is initiated with a soft-start when

the system voltage is ramped up. If SYS voltage is less than

2.19V, the input current is limited to 200mA or IINDPM[4:0],

whichever is smaller, otherwise the limit is set to IINDPM[4:0].

After a power-on reset, the device starts in default mode

(standalone) with all registers reset as if the watchdog timer is

expired. When the host is in sleep mode or there is no host,

the device stays in the default mode in which the

SGM41541/SGM41542 operates like an autonomous charger.

The battery is charged for 16 hours (default value for the fast

charging safety timer). Then the charge stops while Buck

converter continues to operate to power the system load. In

this mode, WATCHDOG_FAULT bit is high.

The BATFET remains on to charge the battery if the battery

charging function is enabled, otherwise BATFET turns off.

When converter operates for battery charging, it acts as an

efficient, fixed frequency synchronous Buck converter

regardless of the input/output voltages and currents. However,

it is capable to switch to PFM mode at light load when

charging is disabled or when the detected battery voltage is

less than minimum system voltage setting. PFM operation

can be enabled or prevented in either Buck or Boost mode

using the PFM_DIS bit.

Most of the flexibility features of the SGM41541/SGM41542

become available in the host mode when the device is

controlled by a host with I²C. By setting the WD_RST bit to 1,

the charger mode changes from default mode to host mode.

In this mode the WATCHDOG_FAULT bit is low and all

device parameters can be programmed by the host. To

prevent device watchdog from reset that results in going back

to default mode, the host must disable the watchdog timer by

setting WATCHDOG[1:0] = 00, or it must consistently reset the

watchdog timer before expiry by writing 1 to WD_RST to prevent

WATCHDOG_FAULT bit from being set. Every time a 1 is

written to the WD_RST, the watchdog timer will restart

counting. Therefore, it should be reset again before overflow

(expiry) to keep the device in the host mode. If the watchdog

timer expires (WATCHDOG_FAULT bit = 1), the device returns

to default mode and all registers are reset to their default

values except for EN_ICHG_MON[1:0], IINDPM[4:0], PFM_DIS,

SYS_MIN[2:0], MIN_BAT_SEL, Q1_FULLON, OVP[1:0],

Boost Mode

The SGM41541/SGM41542 supports USB On-The-Go.

When a load device is connected to the USB port, the

converter can operate as a step-up synchronous converter

(Boost mode) with 1.5MHz switching frequency to supply

power from the battery to that load. The 1.2A USB OTG

output current limit requirement is achieved by programming,

however the Boost converter can deliver 2A to the output

(default limit). Converter will be set to Boost mode if at least

30ms is passed from enabling this mode (OTG_CONFIG bit =

1) and the following conditions are satisfied:

BOOSTV[1:0],

BATFET_DIS,

VINDPM[3:0],

BATFET_DLY,

VDPM_BAT_TRACK[1:0],

VINDPM_INT_MASK,

IINDPM_INT_MASK, REG_RST and VINDPM_OS[1:0] bits

that keep their values unchanged.

SG Micro Corp

www.sg-micro.com

SEPTEMBER 2022

18

SGM41541

SGM41542

High Input Voltage, 3.78A Single-Cell Battery Charger

with NVDC Power Path Management

DETAILED DESCRIPTION (continued)

POR

Start a New Charging Cycle

If the converter can start switching and all the following

conditions are satisfied, a new charge cycle starts:

Watchdog Timer Expired

Start

Watchdog Timer

Reset Registers

I²C Interface Enabled

Y

• NTC temperature fault is not asserted (TS pin).

• Safety timer fault is not asserted.

I²C Write?

N

Host Mode

Host Programs Registers

• BATFET is not forced off. (BATFET_DIS bit = 0).

• Charging enabled (3 conditions: CHG_CONFIG bit = 1,

ICHG[5:0] register is not 0mA and nCE pin is low).

• Battery voltage is below the programmed full charge level

(V_REG).

Default Mode

Reset Watchdog Timer

Reset Selective Registers

Y

N

WD_RST Bit = 1?

N

Y

I²C Write?

A new charge cycle starts automatically if battery voltage falls

Y

Watchdog Timer

Expired?

below the recharge threshold level (V_REG- 100mV or V_REG

-

200mV configured by VRECHG bit). Also, if the charge cycle

is completed, a new charging cycle can be initiated by

toggling of the nCE pin or CHG_CONFIG bit.

Figure 4. Watchdog Timer Flow Chart

Battery Charging Management

Normally a charge cycle terminates when the charge voltage

is above the recharge threshold level and the charging

current falls below the termination threshold if the device is

not in thermal regulation or Dynamic Power Management

(DPM) mode.

The SGM41541/SGM41542 is designed for charging

single-cell Li-Ion or Li-poly batteries with a charge current up

to 3.78A (MAX). The battery connection switch (BATFET) is

in the charge or discharge current path features low

on-resistance (19mΩ) to allow high efficiency and low voltage

drop.

Charge Status Report

STAT is an open-drain output pin that reports the status of

charge and can drive an LED for indication: a low indicates

charging is in progress, a high shows charging is completed

or disabled and alternating low/high (blinking) show a

charging fault. The STAT may be disabled (keep the open

drain switch off) by setting EN_ICHG_MON[1:0] = 11.

Charging Cycle in Autonomous Mode

Charging is enabled if CHG_CONFIG = 1 and nCE pin is

pulled low. In default mode, the SGM41541/SGM41542 runs

a charge cycle with the default parameters itemized in Table

4. At any moment, the host can control the charging

operations by writing the registers.

The CHRG_STAT[1:0] status register reports the present

charging phase and status by two bits: 00 = charging disabled,

01 = in pre-charge, 10 = in fast charging (constant current mode

or constant voltage mode) and 11 = charging completed.

Table 4. Charging Parameter Default Setting

Default Mode

SGM41541/SGM41542

Charging Voltage (V_REG

)

4.208V

2.04A

180mA

JEITA

16h

Charging Current (I_CHG

Pre-Charge Current (I_PRECHG

)

A negative pulse is sent on nINT pin to inform the host when a

charging cycle is completed.

)

Termination Current (I_TERM

Temperature Profile

Safety Timer

)

In addition, the output status of STAT pin can be set by

STAT_SET[1:0] bits, 00 = LED off (HIZ), 01 = LED on (low),

10 = LED blinking at 1s on 1s off, 11 = LED blinking at 1s on

3s off. This two bits only take effect when

EN_ICHG_MON[1:0] = 01.

SG Micro Corp

www.sg-micro.com

SEPTEMBER 2022

19

SGM41541

SGM41542

High Input Voltage, 3.78A Single-Cell Battery Charger

with NVDC Power Path Management

DETAILED DESCRIPTION (continued)

Battery Charging Profile

The SGM41541/SGM41542 features a full battery charging

profile with five phases. In the beginning of the cycle, the

battery voltage (V_BAT) is tested and appropriate current and

voltage regulation levels are selected as shown in Table 5.

Depending on the detected status of the battery, the proper

phase is selected to start or for continuation of the charging

cycle. The phases are trickle charge (V_BAT< 2.19V),

pre-charge and fast-charge (constant current and constant

voltage).

CHRG_STAT[1:0] bits are set to 11 and a negative pulse is

sent to nINT pint after termination.

If the charger is regulating input current, input voltage or

junction temperature instead of charge current, termination

will be temporarily prevented. EN_TERM bit is termination

control bit and can be set to 0 to disable termination before it

happens.

At low termination currents (60mA TYP), the offset in the

internal comparator may give rise to a higher (+10mA to

+20mA) actual termination current. A delay in termination can

be added (optional) as a compensation for comparator offset

using a programmable top-off timer. During the delay,

constant voltage charge phase continues and gives the falling

charge current a chance to drop closer to the programmed

value. The top-off delay timer has the same restrictions of the

safety timer. As an example, if under some conditions the

safety timer is suspended, the top-off timer will also be

suspended or if the safety timer is slowed down, the

termination timer will also be slowed down. The

TOPOFF_ACTIVE bit reports the active/not active status of

Table 5. Charging Current Setting Based on V_BAT

Selected

Charging

Current

V_BAT

Voltage

Default Value

in the Register

CHRG_STAT[1:0]

< 2.19V

2.19V to 3.15V

> 3.15V

I_SHORT

I_PRECHG

I_CHG

90mA

180mA

2.048A

01

10

Note that in the DPM or thermal regulation modes, normal

charging functions are temporarily modified: The charge

current will be less than the value in the register; termination

is disabled, and the charging safety timer is slowed down by

counting at half clock rate.

the

top-off

timer.

The

CHRG_STAT[1:0]

and

TOPOFF_ACTIVE bits can be read to find status of the

termination.

Any of the following events resets the top-off timer:

Charge Termination

A charge cycle is terminated when the battery voltage is

higher than the recharge threshold and the charge current

falls below the programmed termination current. Unless there

is a high power demand for system and it needs to operate in

supplement mode, the BATFET turns off at the end of the

charge cycle. Even after termination, the Buck converter

operates continuously to supply the system.

1. Disable to enable transition of nCE (charge enable).

2. A low to high change in the status of termination.

3. Set REG_RST bit to 1.

The setting of the top-off timer is applied at the time of

termination detection and unless a new charge cycle is

started, modifying the top-off timer parameters after

termination has no effect. A negative pulse is sent to nINT

when top-off timer is started or ended.

Regulation Voltage

VREG[4:0]

Battery Voltage

Charge Current

ICHG[5:0]

Charge Current

V_BATLOW

(3.15V)

V_SHORTZ(2.19V)

IPRECHG[3:0]

ITERM[3:0]

I_SHORT

Trickle Charge Pre-charge

Fast Charge and Voltage Regulation

Top-Off Timer Safety Timer

(Optional)

Expiration

Figure 5. Battery Charging Profile

SG Micro Corp

www.sg-micro.com

SEPTEMBER 2022

20

SGM41541

SGM41542

High Input Voltage, 3.78A Single-Cell Battery Charger

with NVDC Power Path Management

DETAILED DESCRIPTION (continued)

Temperature Qualification

The charging current and voltage of the battery must be

limited when battery is cold or hot. A thermistor input for

battery temperature monitoring is included in the device that

can protect the battery based on JEITA guidelines.

warm threshold T3 can be changed through JEITA_VT2[1:0]

and JEITA_VT3[1:0], and the charge current can be disabled

by setting JEITA_ISET_L_EN = 0.

SGM41541

SGM41542

BAT

Compliance with JEITA Guideline

JEITA guideline (April 20, 2007 release) is implemented in the

device for safe charging of the Li-Ion battery. JEITA highlights

the considerations and limits that should to be considered for

charging at cold or hot battery temperatures. High charge

current and voltage must be avoided outside normal

operating temperatures (typically 0 ℃ and 60 ℃ ). This

functionality can be disabled if not needed. Four temperature

levels are defined by JEITA from T1 (minimum) to T4

(maximum). Outside this range, charging should be stopped.

The corresponding voltages sensed by NTC are named V_T1to

V_T4. Due to the sensor negative resistance, a higher

temperature results in a lower voltage on TS pin. The battery

cool range is between T1 and T2, and the warm range is

between T3 and T4. Charge must be limited in the cool and

warm ranges.

10µF

REGN

4.7µF

R_T1

TS

Li-Ion

Cell

NTC

10kΩ@25℃

R_T2

Figure 6. Battery Thermistor Connection and Bias Network

A 103AT-2 type thermistor is recommended to use for the

SGM41541/SGM41542. Other thermistors may be used and

bias network (see Figure 6) can be calculated based on the

following equations:

One of the conditions for starting a charge cycle is having the

TS voltage within V_T1to V_T4window limits. If during the

charge, battery gets too cold or too hot and TS voltage

exceeds the T1 - T4 limits, charging is suspended (zero

charge current) and the controller waits for the battery

temperature to come back within the T1 to T4 window.













1

R_THCOLD×R_THHOT

×

−

(1)

V_T1V_T4

R_T2

=

















1

R_THHOT

×

−1 −R

×

−1





THCOLD

V_T4

V_T1



JEITA recommends reducing charge current to 1/2 of fast

charging current or lower at cool temperatures (T1 - T2). For

warmer temperature (within T3 - T4 range), charge voltage is

recommended to be kept below 4.1V.









1

V_T1



−1



(2)



1

R_T1

=













1

+









R_T2

R_THCOLD

The SGM41541/SGM41542 exceeds the JEITA requirement

by its flexible charge parameter settings. At warm

temperature range (T3 - T4), the charge voltage is set to the

lower of V_REGand 4.1V when JEITA_VSET_H = 0, the charge

voltage is set to V_REGwhen JEITA_VSET_H = 1, and the

charge current can be reduced down to 0%, 20% or 50% of

fast charging current by the JEITA_ISET_H[1:0] bits. At cool

temperatures (T1 - T2), the current setting can be reduced

down to 50% or 20% of fast charging current selectable by

the JEITA_ISET_L bit when JEITA_ISET_L_EN = 1, and the

charge voltage is set to V_REGwhen JEITA_VSET_L = 0, the

charge voltage is set to the lower of V_REGand 4.1V when

JEITA_VSET_L = 1. Additional, the cool threshold T2 and

where V_T1and V_T4are T_COLDand T_HOTthreshold voltage on

TS pin as percentage to V_REGN, R_THCOLDand R_THHOTare

thermistor resistances (R_TH) at desired T1 (Cold) and T4 (Hot)

temperatures. Select T_COLD= 0℃ and T_HOT= 60℃ for Li-Ion

or Li-polymer batteries. For a 103AT-2 type thermistor

R_THCOLD= 27.28kΩ and R_THHOT= 3.02kΩ, the calculation

results are: R_T1= 5.29kΩ and R_T2= 30.72kΩ. The standard

value is 5.23kΩ for R_T1and 30.9kΩ for R_T2.

SG Micro Corp

www.sg-micro.com

SEPTEMBER 2022

21

SGM41541

SGM41542

High Input Voltage, 3.78A Single-Cell Battery Charger

with NVDC Power Path Management

DETAILED DESCRIPTION (continued)

Boost Mode Temperature Monitoring (Battery

Discharge)

The safety timer is paused if a fault occurs or charger is in

supplement mode, charging is suspended. It will resume once

the fault condition is removed. If charging cycle is stopped by

a restart or by toggling nCE pin or CHG_CONFIG bit, the

timer resets and restarts a new timing.

The device is capable to monitor the battery temperature for

safety during the Boost mode. The temperature must remain

within the V_BCOLDto V_BHOTthresholds, otherwise the Boost

mode will be suspended and VBUS_STAT[2:0] bits are set to

000. Moreover, NTC_FAULT[2:0] register is updated to report

Boost mode cold or hot condition. Once the temperature

returns within the right window, the Boost mode is resumed

and NTC_FAULT[2:0] register is cleared to 000 (normal).

Narrow Voltage DC (NVDC) Design in

SGM41541/SGM41542

The SGM41541/SGM41542 features an NVDC design using

the BATFET that connects the system and battery. By using

the linear region of the BATFET, the charger regulates the

system bus voltage (SYS pin) above the minimum setting

using Buck converter even if the battery voltage is very low.

MOSFET linear mode allows for the large voltage difference

between SYS and BAT pins to appear as V_DSacross the

switch while conducting and charging battery. SYS_MIN[2:0]

register sets the minimum system voltage (default 3.5V). If

the system is in minimum system voltage regulation,

VSYS_STAT bit is set.

V_REGN

Boost Disabled

V_BCOLD

(-20℃)

Boost Enabled

V_BHOT

(60℃)

The BATFET operates in linear region when the battery

voltage is lower than the minimum system voltage. The

system voltage is regulated to 180mV (TYP) above the

minimum system voltage setting. The battery gradually gets

charged and its voltage rises above the minimum system

voltage and lets BATFET to change from linear mode to fully

turned-on switch such that the voltage difference between the

system and battery is the small V_DSof fully on BATFET.

Boost Disabled

AGND

Figure 7. TS Pin Thermistor Temperature Window

Settings in Boost Mode

Safety Timer

Abnormal battery conditions may result in prolonged charge

cycles. An internal safety timer is considered to stop charging

in such conditions. If the safety time is expired,

CHRG_FAULT[1:0] bits are set to 11 and a negative pulse is

sent to nINT pin. By default, the charge time limit is 2 hours if

the battery voltage does not rise above V_BATLOWthreshold.

And it is 16 hours if it goes above V_BATLOW. This feature is

optional and can be disabled by clearing EN_TIMER bit. The

16 hours limit can also be reduced to 7 hours by clearing

CHG_TIMER bit.

The system voltage is always regulated to 50mV (TYP) above

the battery voltage if:

1. The charging is terminated.

2. Charging is disabled and the battery voltage is above the

minimum system voltage setting.

4.5

V_VBUS= 5V, V_BAT= 2.7V to 4.3V

V_REG= 4.624V, V_{SYS_MIN}= 3.5V

4.3

4.1

The safety timer counts at half clock rate when charger is

running under input voltage regulation, input current

regulation, JEITA cool or thermal regulation, because in these

conditions, the actual charge current is likely to be less than

the register setting. As an example, if the safety timer is set to

7 hours and the charger is regulating the input current

(IINDPM_STAT bit = 1) in the whole charging cycle, the

actual safety time will be 14 hours. Clearing the TMR2X_EN

bit will disable the half clock rate feature.

3.9

Charge Disable

3.7

Charge Enable

3.5

3.3

2.7 2.9 3.1 3.3 3.5 3.7 3.9 4.1 4.3

Battery Voltage (V)

Figure 8. System Voltage vs. Battery Voltage

SG Micro Corp

www.sg-micro.com

SEPTEMBER 2022

22

SGM41541

SGM41542

High Input Voltage, 3.78A Single-Cell Battery Charger

with NVDC Power Path Management

DETAILED DESCRIPTION (continued)

SGM41541/SGM41542 Dynamic Power Management

(DPM)

Battery Supplement Mode

If the system voltage drops below the battery voltage, the

BATFET gradually starts to turn on. The threshold margin is

180mV if V_{SYS_MIN}setting is less than V_BATand 45mV if

V_{SYS_MIN}setting is larger than V_BAT.At low discharge currents,

the BATFET gate voltage is regulated (R_DSmodulation) such

that the BATFET V_DSstays at 25mV. At higher currents, the

BATFET will turn fully on (reaching its lowest R_DSON). From

this point, increasing the discharge current will linearly

increase the BATFET V_DS(determined by R_DSON× I_D). Using

the MOSFET linear mode at lower currents prevents swinging

oscillation of entering and exiting the supplement mode.

The SGM41541/SGM41542 features

a dynamic power

management (DPM). To implement DPM, the device always

monitors the input current and voltage to regulate power

demand from the source and avoid input adapter overloading

or to meet the maximum current limits specified in the USB

specs. Overloading an input source may results in either

current trying to exceed the input current limit (I_INDPM) or the

voltage tending to fall below the input voltage limit (V_INDPM).

With DPM, the device keeps the VSYS regulated to its

minimum setting by reducing the battery charge current

adequately such that the input parameter (voltage or current)

does not exceed the limit. In other words, charge current is

reduced to satisfy I_IN≤ I_INDPMor V_IN≥ V_INDPMwhichever occurs

first. DPM can be either an I_INtype (IINDPM) or V_INtype

(VINDPM) depending on which limit is reached.

BATFET gate regulation V-I characteristics is shown in Figure

10. If the battery voltage falls below its minimum depletion,

the BATFET turns off and exits supplement mode.

4.5

4.0

3.5

3.0

2.5

2.0

1.5

Changing to the supplement mode may be required if the

charge current is decreased and reached to zero while the

input is still overloaded. In this case, the charger reduces the

system voltage below the battery voltage to allow operation in

the supplement mode and provide a portion of system power

demand from the battery through the BATFET.

The IINDPM_STAT or VINDPM_STAT status bits are set

during an IINDPM or VINDPM respectively. Figure 9

summarizes the DPM behavior (IINDPM type) for a design

example with a 9V/1.2A adapter, 3.2V battery, 2.8A charge

current setting and 3.4V minimum system voltage setting.

1.0

V_VBUS= 5V, V_{SYS_MIN}= 3.5V

I_INDPM= 500mA, V_BAT= 3.8V

0.5

Charge Enable

0.0

0

10 20 30 40 50 60 70 80 90 100

V_BAT-SYS(mV)

Voltage

9V

VBUS

Figure 10. BATFET Gate Regulation V-I Curve

VSYS

3.6V

BATFET Control for System Power Reset

and Ship Mode

3.4V

VBAT

3.2V

3.18V

Ship Mode (BATFET Disable)

Ship mode is usually used when the system is stored or in

idle state for a long time or is in shipping. In such conditions, it

is better to completely disconnect battery and make system

voltage zero to minimize the leakage and extend the battery

life. To enter ship mode, the BATFET has to be forced off by

setting BATFET_DIS bit. The BATFET turns off immediately if

BATFET_DLY bit is 0, or turns off after a t_{SM_DLY}delay (12.3

seconds) if BATFET_DLY is set.

Current

4A

ICHG

3.2A

2.8A

ISYS

IIN

1.2A

.0A

1

0.5A

-0.6A

DPM

Supplement

Figure 9. DPM Behavior Plot

SG Micro Corp

www.sg-micro.com

SEPTEMBER 2022

23

SGM41541

SGM41542

High Input Voltage, 3.78A Single-Cell Battery Charger

with NVDC Power Path Management

DETAILED DESCRIPTION (continued)

Exit Ship Mode (BATFET Enable)

To exit the ship mode and enable the BATFET one of the

following can be applied:

this function, a negative logic pulse with a minimum width of

t_{QON_RST}(10s TYP) must be applied to the nQON pin that

results in a temporary BATFET turn off for t_{BATFET_RST}(320ms

TYP) that automatically turns on afterward. Setting

BATFET_RST_EN to 0 can disable the function.

With the chip no powered by VBUS:

1. Connect the adapter to the input with a valid voltage to the

VBUS input.

In summary the nQON pin controls BATFET and system reset

in two different ways:

2. Pull nQON pin from logic high to low to enable BATFET, for

example, by shorting nQON to GND. The negative pulse

width should be at least a t_SHIPMODE(1s TYP) for deglitching.

1. Enable BATFET: Applying an nQON logic high to low

transition with longer than t_SHIPMODEdeglitch time (negative

pulse) turns on BATFET to exit ship mode (Figure 11 left). HIZ

is also enabled (EN_HIZ = 1) when exiting shipping mode.

After exiting shipping mode, the host can disable HIZ (EN_HIZ

= 0). OTG cannot be enabled (OTG_CONFIG = 1) until HIZ is

disabled.

With the chip already powered by VBUS:

3. Clear BATFET_DIS bit using host and I²C.

4. Set REG_RST to 1 to reset all registers.

5. Apply a negative pulse to nQON pin (same as 2).

Full System Reset with BATFET Using nQON

When the input source is not present, the BATFET can act as

a load on/off switch between the system and battery. This

feature can be used to apply a power-on reset to the system.

Host can toggle BATFET_DIS bit to cycle power off/on and

reset the system. A push-button connected to nQON pin or a

negative pulse can also be used to manually force a system

power cycle when BATFET is ON (BATFET_DIS bit = 0). For

2. Reset BATFET: By applying a logic low for a duration of at

least t_{QON_RST}to nQON pin while VBUS is not powered and

BATFET is allowed to turn on (BATFET_DIS bit = 0), the

BATFET turns off for t_{BATFET_RST}and then it is re-enabled

resulting in a system power-on reset (Figure 11 right). This

function can be disabled by clearing BATFET_RST_EN bit.

A typical push button circuit for nQON is given in Figure 12.

Press Push Button

nQON

t_{QON_RST}

t_SHIPMODE

t_{BATFET_RST}

BATFET

Status

BATFET off due to I²C

or system overload

BATFET on

BATFET off

Reset BATFET

Turn on BATFET

When BATFET_DIS = 1 or SLEEPZ = 1

When BATFET_DIS = 0 and SLEEPZ = 0

Figure 11. nQON Enable and Reset BATFET Timing

SYS

BATFET (Q4)

Control

BAT

V_PULL-UP

nQON

Figure 12. nQON Manual Operation Circuit

SG Micro Corp

www.sg-micro.com

SEPTEMBER 2022

24

SGM41541

SGM41542

High Input Voltage, 3.78A Single-Cell Battery Charger

with NVDC Power Path Management

DETAILED DESCRIPTION (continued)

Status Outputs Pins (STAT and nINT)

Power Good Indication (PG_STAT Bit)

4. Input source voltage entered the "input good" range:

a) V_VBUSexceeded V_BAT(not in sleep mode).

When a good input source is connected to VBUS and input

type is detected, the PG_STAT status bit goes high. A good

input source is detected if all following conditions on V_VBUS

are satisfied and input type detection is completed:

b) V_VBUScame below V_{VBUS_OV}

c) V_VBUSremained above V_VBUSMIN(3.8V TYP) when

_{BAD_SRC}(30mA TYP) load current is applied.

.

I

5. Input removed or out of the "input good" range.

6. A DPM event (VINDPM or IINDPM) occurred (a maskable

interrupt).

• V_VBUSis in the operating range: V_{VBUS_UVLOZ}< V_VBUS< V_{VBUS_OV}

.

• Device is not in sleep mode: V_VBUS> V_BAT+ V_SLEEP

.

• Input source is not poor: V_VBUS> V_VBUSMIN(3.8V TYP) when

I_{BAD_SRC}(30mA TYP) loading is applied. (Poor source

detection.)

Once a fault/flag happens, the INT pulse is asserted

immediately and the fault/flag bits are updated in REG09 and

REG0E. Fault/flag status is not reset in the register until the

host reads it. A new fault will not assert a new INT pulse until

the host reads REG09 and all the previous faults are cleared.

Therefore, in order to read the current time faults, the host

must read REG09 two times consecutively. The first read

returns the history of the fault register status (from the time of

the last read or reset) and the second one checks the current

active faults. As an exception, the NTC_FAULT bit reports the

actual real-time status of TS pin.

• Completed input source type detection.

Charge Status (STAT Pin)

Charging state is indicated with the open-drain STAT pin as

explained in Table 6. This pin is able to drive an LED (see

Figure 1 or Figure 2). The functionality of the STAT pin is

disabled if the EN_ICHG_MON[1:0] bits are set to 11.

Table 6. STAT Pin Function

Charging State

Charging battery (or recharge)

Charging completed

STAT Indicator

Low (LED ON)

High (LED OFF)

Current Pulse Control Protocol

The device provides the control to generate the VBUS current

pulse protocol to communicate with adjustable high voltage

adapter in order to signal adapter to increase/decrease output

voltage. To enable the interface, the EN_PUMPX bit must be

set. Then the host can select the increase/decrease voltage

pulse by setting one of the PUMPX_UP or PUMPX_DN bit

(but not both) to start the VBUS current pulse sequence.

During the current pulse sequence, the PUMPX_UP and

PUMPX_DN bits are set to indicate pulse sequence is in

progress and the device pulses the input current limit

between current limit set forth by IINDPM[4:0] register and the

100mA current limit. When the pulse sequence is completed,

the input current limit is returned to value set by IINDPM[4:0]

register and the PUMPX_UP or PUMPX_DN bit is cleared. In

addition, the EN_PUMPX can be cleared during the current

pulse sequence to terminate the sequence and force charger

to return to input current limit as set forth by the IINDPM[4:0]

register immediately. When EN_PUMPX bit is low, write to

PUMPX_UP and PUMPX_DN bits would be ignored and

have no effect on VBUS current limit.

Charging is disabled or in sleep mode

Charge is suspended due to input over-voltage,

TS fault, timer faults or system over-voltage or

Boost mode is suspended (TS fault)

1Hz Blinking

EN_ICHG_MON[1:0] = 01, controlled by register

only, no matter with charging state

STAT_SET[1:0]

nINT Interrupt Output Pin

When a new update occurs in the charger states, a 256μs

negative pulse is sent through the nINT pin to interrupt the

host. The host may not continuously monitor the charger

device and by receiving the interrupt, it can react and check

the charger situation on time.

The following events can generate an interrupt pulse:

1. Faults reflected in REG09 register (watchdog, Boost

overload, charge faults and battery over-voltage).

2. Charging completed.

3. PSEL or D+/D- detection identified a connected source

(USB or adapter).

SG Micro Corp

www.sg-micro.com

SEPTEMBER 2022

25

SGM41541

SGM41542

High Input Voltage, 3.78A Single-Cell Battery Charger

with NVDC Power Path Management

DETAILED DESCRIPTION (continued)

SGM41541/SGM41542 Protection Features

Monitoring of Voltage and Current

During the converter operation the input and system voltages

(VBUS and VSYS) and switch currents are constantly

monitored to assure safe operation of the device in both Buck

and Boost modes, as will be explained below.

(Hiccup). If short is not removed after retries, the OTG will be

disabled by clearing OTG_CONFIG bit. Also, an INT pulse is

sent and the BOOST_FAULT bit is set to 1 in REG09. When

the host activates the Boost mode again, the BOOST_FAULT

bit will be cleared.

3. Output Over-Voltage Protection for VBUS

In Boost mode, converter stops switching and exits Boost

mode (by clearing OTG_CONFIG bit) if VBUS voltage rises

above regulation and exceeds the V_{OTG_OVP}over-voltage limit

(6V TYP). An INT pulse is sent and the BOOST_FAULT bit is

set 1.

Buck Mode Voltage and Current Monitoring

1. Input Over-Voltage (ACOV)

Converter switching will stop as soon as VBUS voltage

exceeds V_{VBUS_OV}over-voltage limit that is programmable by

OVP[1:0] in REG06. It is selectable between 5.5V, 6.5V,

10.5V and 14V (default) for USB or 5V, 9V or 12V adaptors

respectively.

SGM41541/SGM41542 Thermal Regulation and

Shutdown

Each time VBUS exceeds the OVP limit, an INT pulse is

asserted. As long as the over-voltage persists, the

CHRG_FAULT[1:0] bits are set to 01 in REG09. Fault will be

cleared to 00 if the voltage comes back below limit (and a

hysteresis threshold) and host reads the fault register.

Charger resumes its normal operation when the voltage

comes back below OVP limit.

Buck Mode Thermal Protections

Internal junction temperature (T_J) is always monitored to

avoid overheating. A limit of +120 ℃ is considered for

maximum IC surface temperature in Buck mode and if T_J

intends to exceed this level, the device reduces the charge

current to keep maximum temperature limited to +120℃

(thermal regulation mode) and sets the THERM_STAT bit to 1.

As expected, the actual charging current is usually lower than

programmed value during thermal regulation. Therefore, the

safety timer runs at half clock rate and charge termination is

disabled during thermal regulation.

2. System Over-Voltage (SYSOVP)

During a system load transient, the device clamps the system

voltage to protect the system components from over-voltage.

The SYSOVP over-voltage limit threshold is 350mV + V_BAT, or

350mV + V_{SYS_MIN}when in SYSMIN condition (programmed

minimum system regulation voltage + 350mV). Once a

SYSOVP occurs, switching stops to clamp any overshoot and

a 17mA sink current is applied to SYS to pull the voltage

down.

If the junction temperature exceeds T_SHUT(+150℃), thermal

shutdown protection arises in which the converter is turned off,

CHRG_FAULT[1:0] bits are set to 10 in the fault register and

an INT pulse is sent. And VBUS_STAT[2:0] bits are set to 000,

PG_STAT and VBUS_GD are both set to 0. And nPG is

pulled high when thermal shutdown is triggered (SGM41541

only).

Boost Mode Voltage and Current Monitoring

In Boost mode the RBFET (reverse blocking) and LSFET

(low-side switch) FET currents and VBUS voltage are

monitored for protection.

When the device recovers and T_Jfalls below the hysteresis

band of T_{SHUT_HYS}(30℃ under T_SHUT), the converter resumes

automatically.

1. Soft-Start on VBUS

Boost mode begins with a soft-start to prevent large inrush

currents when it is enabled.

Boost Mode Thermal Protections

Similar to Buck mode, T_Jis monitored in Boost mode for

thermal shutdown protection. If junction temperature exceeds

T_SHUT(+150 ℃ ), the Boost mode will be disabled

(OTG_CONFIG bit clears). If T_Jfalls below the hysteresis band

of T_{SHUT_HYS}(30℃ under T_SHUT), the Boost can recover again by

re-enabling OTG_CONFIG bit by host.

2. Output Short Protection for VBUS

Short circuit protection is provided for VBUS output in Boost

mode. To accept different types of load connected to VBUS

and OTG adaptation, an accurate constant current regulation

control is implemented for Boost mode. In case of a short

circuit on VBUS pin, the Q1 turns off and retries 7 times

SG Micro Corp

www.sg-micro.com

SEPTEMBER 2022

26

SGM41541

SGM41542

High Input Voltage, 3.78A Single-Cell Battery Charger

with NVDC Power Path Management

DETAILED DESCRIPTION (continued)

Battery Protections

Battery Over-Voltage Protection (BATOVP)

I²C Data Communication

START and STOP Conditions

The over-voltage limit for the battery is 3.8% above the

battery regulation voltage setting. In case of a BATOVP,

charging or external direct charging stops right away, the

BAT_FAULT bit is set to 1 and an INT pulse is sent.

A transaction is started by taking control of the bus by master

if the bus is free. The transaction is terminated by releasing

the bus when the data transfer job is done as shown in Figure

13. All transactions begin by the master who applies a

START condition on the bus lines to take over the bus and

exchange data. At the end, the master terminates the

transaction by applying one (or more) STOP condition.

START condition is when SCL is high and a high to low

transition on the SDA is generated by master. Similarly, a

STOP is defined when SCL is high and SDA goes from low to

high. START and STOP are always generated by a master.

After a START and before a STOP the bus is considered

busy.

Battery Over-Discharge Protection

If battery discharges too much and V_BATfalls below the

depletion level (V_{BAT_DPL_FALL}), the device turns off BATFET to

protect battery. This protection is latched and is not recovered

until an input source is connected to the VBUS pin. In such

condition, the battery will start charging with the small I_SHORT

current (90mA TYP) first as long as V_BAT< V_SHORTZ. When

battery voltage is increased and V_SHORTZ< V_BAT< V_BATLOW

,

the charge current will increase to the pre-charge current

level programmed in the IPRECHG[3:0] register.

SDA

SCL

Battery Over-Current Protection for System

The BATFET will latch off, if its current limit is exceeded due to

a short or large overload on the system (I_BAT> I_{BATFET_OCP}). To

reset this latch off and enable BATFET, the "Exit Ship Mode"

procedure must be followed.

S

P

START

STOP

Figure 13. I²C Bus in START and STOP Conditions

I²C Serial Interface and Data Communication

Standard I²C interface is used to program SGM41541/

SGM41542 parameters and get status reports. I²C is well

known 2 wire serial communication interface that can connect

one (or more) master device(s) to some slave devices for

two-way communication. The bus lines are named serial data

(SDA) and serial clock (SCL). The device that initiates a data

transfer is a master. A master generates the SCL signal.

Slave devices have unique addresses to identify. A master is

typically a micro controller or a digital signal processor.

Data Bit Transmission and Validity

Data bit (high or low) must remain stable during clock HIGH

period. The state of SDA can only change when SCL is LOW.

For each data bit transmission, one clock pulse is generated

by the master. Bit transfer in I²C is shown in Figure 14.

SDA

The SGM41541/SGM41542 operates as a slave device that

address is 0x3B (3BH). It has sixteen 8-bit registers,

numbered from REG00 to REG0F. A register read beyond

REG0F (0x0F) returns 0xFF.

SCL

Data Line Stable Change of Data

and Data Valid

Allowed

Physical Layer

Figure 14. I²C Bus Bit Transfer

The standard I²C interface of SGM41541/SGM41542 support

standard mode and fast mode communication speeds. The

frequency of standard mode is up to 100kbits/s, while the fast

mode is up to 400kbits/s. Bus lines are pulled high by weak

current source or pull-up resistors and in logic high state with

no clocking when the bus is free. The SDA and SCL pins are

open-drain.

SG Micro Corp

www.sg-micro.com

SEPTEMBER 2022

27

SGM41541

SGM41542

High Input Voltage, 3.78A Single-Cell Battery Charger

with NVDC Power Path Management

DETAILED DESCRIPTION (continued)

Byte Format

Data is transmitted in 8-bit packets (one byte at a time). The

number of bytes in one transaction is not limited. In each

packet, the 8 bits are sent successively with the Most

Significant Bit (MSB) first. An acknowledge (or not-acknowledge)

bit must come after the 8 data bits. This bit informs the

transmitter whether the receiver is ready to proceed for the

next byte or not. Figure 15 shows the byte transfer process

with I²C interface.

Data Direction Bit and Addressing Slaves

The first byte sent by master after the START is always the

target slave address (7 bits) and an eighth data-direction bit

(R/W). R/W bit is 0 for a WRITE transaction and 1 for READ

(when master is asking for data). Data direction is the same

for all next bytes of the transaction. To reverse it, a new

START or repeated START condition must be sent by master

(STOP will end the transaction). Usually the second byte is a

WRITE sending the register address that is supposed to be

accesses in the next byte(s). The data transfer transaction is

shown in Figure 16.

Acknowledge (ACK) and Not Acknowledge (NCK)

After transmission of each byte by transmitter, an

acknowledge bit is replied by the receiver as ninth bit. With

the acknowledge bit, the receiver informs the transmitter that

the byte has been received, and another byte is expected or

can be sent (ACK) or it is not expected (NCK = not ACK).

Clock (SCL) is always generated by the master, including for

the acknowledge clock pulse, no matter who is acting as

transmitter or receiver. SDA line is released for receiver

control during the acknowledge clock pulse, and the receiver

can pull the SDA line low as ACK (reply a 0 bit) or let it be

high as NCK during the SCL high pulse. After that, the master

can either STOP (P) to end the transaction or send a new

START (S) condition to start a new transfer (called repeated

start). For example, when master wants to read a register in

slave, one start is needed to send the slave address and

register address, and then, without a stop condition, another

start is sent by master to initiate the receiving transaction

from slave. Master then sends the STOP condition and

releases the bus.

WRITE: If the master wants to write in the register, the third

byte can be written directly as shown in Figure 17 for a single

write data transfer. After receiving the ACK, master may issue

a STOP condition to end the transaction or send the next

register data, which will be written to the next address in a

slave as multi-write. A STOP is needed after sending the last

data.

READ: If the master wants to read a single register (Figure

18), it sends a new START condition along with device

address with R/W bit = 1. After ACK is received, master reads

the SDA line to receive the content of the register. Master

replies with NCK to inform slave that no more data is needed

(single read) or it can send an ACK to request for sending the

next register content (multi-read). This can continue until a

NCK is sent by master. A STOP must be sent by master in

any case to end the transaction.

1

9

1

9

SCL

SDA

MSB

Acknowledgement

signal from receiver

Acknowledgement

signal from receiver

S/Sr

P/Sr

START

or Repeated

START

ACK

STOP

or Repeated

START

Figure 15. Byte Transfer Process

1

9

1

9

1

9

SCL

SDA

R/W

P

S

I²C Slave Address

Data Byte

ACK

START

STOP

Figure 16. Data Transfer Transaction

SG Micro Corp

www.sg-micro.com

SEPTEMBER 2022

28

SGM41541

SGM41542

High Input Voltage, 3.78A Single-Cell Battery Charger

with NVDC Power Path Management

DETAILED DESCRIPTION (continued)

Frame 1

Frame 2

1

9

1

9

SCL

SDA

0

1

0

1

B7

B6

B5

B4

B3

B2

B1

B0

W

Byte#1 I²C Slave Address Byte

ACK by

Device

Byte#2 Register Address Byte

ACK by

Device

START by

Master

Frame 3

1

9

SCL

(Continued)

SDA

(Continued)

D7

D6

D5

D4

D3

D2

D1

D0

Byte#3 Data Byte 1 to

SGM41541/SGM41542 Register

ACK by

Device

STOP by

Master

Figure 17. A Single Write Transaction

Frame 1

Frame 2

1

0

9

1

9

SCL

SDA

1

0

1

B7

B6

B5

B4

B3

B2

B1

B0

W

Byte#1 I²C Slave Address Byte

ACK by

Device

START by

Master

Byte#2 Register Address Byte

ACK by

Device

Frame 3

Frame 4

1

0

9

1

9

SCL

(Continued)

SDA

(Continued)

1

0

1

D7

D6

D5

D4

D3

D2

D1

D0

R

START by

Master

Byte#3 I²C Slave Address Byte

Byte#4 Data Byte from Device

NCK by

Master

STOP by

Master

ACK by

Device

Figure 18. A Single Read Transaction

SG Micro Corp

www.sg-micro.com

SEPTEMBER 2022

29

SGM41541

SGM41542

High Input Voltage, 3.78A Single-Cell Battery Charger

with NVDC Power Path Management

DETAILED DESCRIPTION (continued)

Data Transactions with Multi-Read or Multi-Write

Multi-read and multi-write are supported by SGM41541/

SGM41542, as explained in Figure 19 and Figure 20. In the

multi-write, every new data byte sent by master is written to

the next register of the device. A STOP is sent whenever

master is done with writing into device registers.

In a multi-read transaction, after receiving the first register

data (its address is already written to the slave), the master

replies with an ACK to ask the slave for sending the next

register data. This can continue as much as it is needed by

master. Master sends back an NCK after the last received

byte and issues a STOP condition.

Frame 1

Frame 2

1

0

9

1

9

SCL

SDA

B7

B6

B5

B4

B3

B2

B1

B0

1

0

1

W

Byte#1 I²C Slave Address Byte

Byte#2 Register Address Byte

ACK by

Device

START by

Master

ACK by

Device

Frame 3

Frame 4

1

9

1

9

SCL

(Continued)

SDA

(Continued)

D7

D6

D5

D4

D3

D2

D1

D0

D7

D6

D5

D4

D3

D2

D1

D0

Byte#3 Data Byte 1 to

SGM41541/SGM41542 Register

ACK by

Device

Byte#4 Data Byte 2 to

SGM41541/SGM41542 Register

ACK by

Device

Frame N

1

9

SCL

(Continued)

SDA

(Continued)

D7

D6

D5

D4

D3

D2

D1

D0

Byte#N Data Byte n to

SGM41541/SGM41542 Register

ACK by

Device

STOP by

Master

Figure 19. A Multi-Write Transaction

SG Micro Corp

www.sg-micro.com

SEPTEMBER 2022

30

SGM41541

SGM41542

High Input Voltage, 3.78A Single-Cell Battery Charger

with NVDC Power Path Management

DETAILED DESCRIPTION (continued)

Frame 1

Frame 2

1

0

9

1

9

SCL

SDA

1

0

1

B7

B6

B5

B4

B3

B2

B1

B0

W

Byte#1 I²C Slave Address Byte

ACK by

Device

START by

Master

Byte#2 Register Address Byte

ACK by

Device

Frame 3

Frame 4

1

0

9

1

9

SCL

(Continued)

SDA

(Continued)

1

0

1

D7

D6

D5

D4

D3

D2

D1

D0

R

Byte#3 I²C Slave Address Byte

Byte#4 Data Byte 1 from Device

ACK by

Master

START by

Master

ACK by

Device

Frame 5

Frame N

1

9

1

9

SCL

(Continued)

SDA

(Continued)

D7

D6

D5

D4

D3

D2

D1

D0

D7

D6

D5

D3

D2

D1

D0

D4

Byte#5 Data Byte 2 from Device

ACK by

Master

Byte#N Data Byte n from Device

NCK by

Master

STOP by

Master

Figure 20. A Multi-Read Transaction

SG Micro Corp

www.sg-micro.com

SEPTEMBER 2022

31

SGM41541

SGM41542

High Input Voltage, 3.78A Single-Cell Battery Charger

with NVDC Power Path Management

REGISTER MAPS

All registers are 8-bit and individual bits are named from D[0] (LSB) to D[7] (MSB).

I²C Slave Address of SGM41541/SGM41542: 0x3B

R/W:

Read/Write bit(s)

R:

Read only bit(s)

PORV:

n:

Power-On Reset Value

Parameter code formed by the bits as an unsigned binary number.

REG00

Register address: 0x00; R/W

PORV = 00010111

Table 7. REG00 Register Details

BITS

BIT NAME

DESCRIPTION

Enable HIZ Mode

0 = Disable (default)

1 = Enable

COMMENT

PORV

TYPE

RESET BY

In HIZ mode, the VBUS pin is effectively

disconnected from internal circuit. Some

leakage current may exist.

REG_RST

or Watchdog

D[7]

EN_HIZ

0

R/W

Enable STAT Pin Function

00 = Enable following

charging state (default)

D[6:5] EN_ICHG_MON[1:0] 01 = Enable following

STAT_SET[1:0] bits

These bits turn on or off the function of the

STAT open-drain output pin (charge status

or customer customized indicator).

00

R/W

REG_RST

10 = Disable (float pin)

11 = Disable (float pin)

IINDPM[4]

1 = 1600mA

Input Current Limit Value (n: 5 bits):

= 100 + 100n (mA)

IINDPM[3]

1 = 800mA

Offset: 100mA

Range: 100mA (00000) - 3.1A (11110),

3.8A (11111)

IINDPM[2]

1 = 400mA

D[4:0]

IINDPM[4:0]

10111

R/W

REG_RST

Default: 2400mA (10111), not typical

IINDPM changes after an input source

detection.

IINDPM[1]

1 = 200mA

Host can overwrite IINDPM after input

source detection is completed.

IINDPM[0]

1 = 100mA

SG Micro Corp

www.sg-micro.com

SEPTEMBER 2022

32

SGM41541

SGM41542

High Input Voltage, 3.78A Single-Cell Battery Charger

with NVDC Power Path Management

REGISTER MAPS (continued)

REG01

Register address: 0x01; R/W

PORV = 00011010

Table 8. REG01 Register Details

BITS

BIT NAME

DESCRIPTION

COMMENT

PORV TYPE

RESET BY

Enable Pulse Frequency Modulation.

PFM is normally used to save power at light

load by reducing converter switching

frequency.

Enable PFM Mode

0 = Enable (default)

1 = Disable

D[7]

PFM_DIS

0

R/W REG_RST

Watchdog Timer Reset Control Bit.

Write 1 to this bit to avoid watchdog expiry.

WD_RST resets to 0 after watchdog timer

reset (expiry).

I²C Watchdog Timer Reset

0 = Normal (default)

1 = Reset

REG_RST

D[6]

WD_RST

R/W

or Watchdog

Enable OTG

0 = OTG disable (default)

1 = OTG enable

This bit has priority over charge enable in

the CHG_CONFIG.

REG_RST

or Watchdog

D[5]

D[4]

OTG_CONFIG

CHG_CONFIG

0

1

R/W

Enable Battery Charging

0 = Charge disable

1 = Charge enable (default)

Charge is enabled when CHG_CONFIG bit

is 1 and nCE pin is pulled low.

REG_RST

or Watchdog

Minimum System Voltage

000 = 2.6V

001 = 2.8V

Minimum System Voltage Value.

010 = 3V

D[3:1]

SYS_MIN[2:0]

MIN_BAT_SEL

011 = 3.2V

100 = 3.4V

101 = 3.5V (default)

110 = 3.6V

111 = 3.7V

Offset: 2.6V

Range: 2.6V (000) - 3.7V (111)

Default: 3.5V (101)

101

R/W REG_RST

Minimum Battery Voltage for

OTG Mode

0 = 3.0V V_BATfalling (default)

1 = 2.5V V_BATfalling

Default:

D[0]

V

_BATfalling, V_{BATLOW_OTG}= 3.0V.

_BATrising, V_{BATLOW_OTG}= 3.2V.

0

REG02

Register address: 0x02; R/W

PORV = 10100010

Table 9. REG02 Register Details

BITS

BIT NAME

DESCRIPTION

COMMENT

PORV TYPE

RESET BY

Boost Mode Current Limit

0 = 1.2A

1 = 2A (default)

The current limit options listed values are the

minimum specs. Actual value is typically

higher.

REG_RST

or Watchdog

D[7]

BOOST_LIM

1

R/W

Used to control the on-resistance of Q1

(VBUS switch) for better input current

measurement accuracy.

VBUS FET Switch (Q1)

0 = Use higher R_DSONif I_INDPM

< 700mA (for better accuracy)

1 = Use lower R_DSONalways

(fully ON for better efficiency)

D[6]

Q1_FULLON

0

R/W REG_RST

In Boost mode, full FET is always used, and

this bit has no effect.

ICHG[5]

1 = 1920mA

1

0

1

0

R/W

Fast Charge Current Value (n: 6 bits):

= 60n (mA) (n ≤ 50)

ICHG[4]

1 = 960mA

ICHG[3]

1 = 480mA

R/W

Offset: 0mA

Range: 0mA (000000) - 3780mA (111111)

Default: 2040mA (100010)

REG_RST

or Watchdog

D[5:0]

ICHG[5:0]

ICHG[2]

1 = 240mA

R/W

ICHG[1]

1 = 120mA

Notes:

R/W

Setting I_CHG= 0mA disables charge.

ICHG[0]

1 = 60mA

SG Micro Corp

www.sg-micro.com

SEPTEMBER 2022

33

SGM41541

SGM41542

High Input Voltage, 3.78A Single-Cell Battery Charger

with NVDC Power Path Management

REGISTER MAPS (continued)

REG03 (Pre-Charge and Termination Current Settings)

Register address: 0x03; R/W

PORV = 00100010

Table 10. REG03 Register Details

BITS

BIT NAME

DESCRIPTION

IPRECHG[3]

COMMENT

PORV TYPE

RESET BY

Pre-Charge Current Limit (n: 4 bits):

= 60 + 60n (mA) (n ≤ 12)

0

1

0

R/W

1 = 480mA

IPRECHG[2]

1 = 240mA

Offset: 60mA

Range: 60mA (0000) - 780mA (1100)

Default: 180mA (0010)

REG_RST

or Watchdog

D[7:4]

IPRECHG[3:0]

IPRECHG[1]

1 = 120mA

Note:

IPRECHG[0]

1 = 60mA

Values above 12D = 1100 (780mA) are

clamped to 12D = 1100 (780mA).

ITERM[3]

1 = 480mA

0

1

0

R/W

Termination Current Limit (n: 4 bits):

= 60 + 60n (mA)

ITERM[2]

1 = 240mA

REG_RST

or Watchdog

D[3:0]

ITERM[3:0]

Offset: 60mA

Range: 60mA (0000) - 960mA (1111)

Default: 180mA (0010)

ITERM[1]

1 = 120mA

ITERM[0]

1 = 60mA

REG04

Register address: 0x04; R/W

PORV = 01011000

Table 11. REG04 Register Details

BITS

BIT NAME

DESCRIPTION

VREG[4]

COMMENT

PORV TYPE

RESET BY

Charge Voltage Limit (n: 5 bits):

= 3856 + 32n (mV) if n ≤ 24, n≠15;

0

1

0

1

0

R/W

1 = 512mV

VREG[3]

1 = 256mV

= 4.352V

Offset: 3.856V

if n = 15

Range: 3.856V (00000) - 4.624V (11000)

Default: 4.208V (01011)

Special Value: 4.352V (01111)

VREG[2]

1 = 128mV

REG_RST

or Watchdog

D[7:3]

VREG[4:0]

VREG[1]

1 = 64mV

Note:

Values above 24D = 11000 (4.624V) are

clamped to 24D = 11000 (4.624V).

VREG[0]

1 = 32mV

Top-Off Timer

00 = Disabled (default)

The charge extension time added after the

termination condition is detected.

REG_RST

or Watchdog

D[2:1] TOPOFF_TIMER[1:0] 01 = 15 minutes

10 = 35 minutes

If disabled, charging terminates as soon as

termination conditions are met.

0

R/W

11 = 45 minutes

Battery Recharge Threshold

0 = 100mV below VREG[4:0]

(default)

A recharge cycle will start if a fully charged

battery voltage drops below VREG - VRECHG

settings.

REG_RST

or Watchdog

D[0]

VRECHG

1 = 200mV below VREG[4:0]

SG Micro Corp

www.sg-micro.com

SEPTEMBER 2022

34

SGM41541

SGM41542

High Input Voltage, 3.78A Single-Cell Battery Charger

with NVDC Power Path Management

REGISTER MAPS (continued)

REG05

Register address: 0x05; R/W

PORV = 10011111

Table 12. REG05 Register Details

BITS

BIT NAME

DESCRIPTION

COMMENT

PORV TYPE

RESET BY

REG_RST

Charging Termination Enable

0 = Disable

1 = Enable (default)

D[7]

EN_TERM

1

R/W

or Watchdog

DCEN Reset Enable or ITERM

Timer Setting

0 = Allow resetting DCEN or

set 200ms (default)

1 = Don′t allow resetting DCEN

or set 16ms

When DCEN = 1 and IBUS over-current

occurs, set this bit 0 or 1 to allow resetting

DCEN or not.

When DCEN = 0, set this bit 0 or 1 to set

ITERM detection timer to 200ms or 16ms.

REG_RST

or Watchdog

D[6]

ARDCEN_ITS

0

R/W

Watchdog Timer Setting

00 = Disable watchdog timer

D[5:4] WATCHDOG[1:0] 01 = 40s (default)

Expiry time of the watchdog timer if it is

not reset.

REG_RST

or Watchdog

01

R/W

10 = 80s

11 = 160s

Charge Safety Timer Enable

0 = Disable

1 = Enable (default)

Charge Safety Timer Setting

0 = 7h

1 = 16h (default)

Thermal Regulation Threshold

0 = 80℃

When enabled the pre-charge and fast

charge periods are included in the timing.

REG_RST

or Watchdog

D[3]

D[2]

D[1]

D[0]

EN_TIMER

CHG_TIMER

TREG

1

R/W

REG_RST

or Watchdog

REG_RST

or Watchdog

For Buck mode.

1 = 120℃ (default)

JEITA Charging Current

0 = 50% of I_CHG

JEITA_ISET_L

(0℃ - 10℃)

REG_RST

or Watchdog

When JEITA_ISET_L_EN = 1.

1 = 20% of I_CHG(default)

REG06

Register address: 0x06; R/W

PORV = 11100110

Table 13. REG06 Register Details

BITS

BIT NAME

DESCRIPTION

COMMENT

PORV TYPE

RESET BY

VBUS Pin OVP Threshold

00 = 5.5V

1

0

R/W

D[7:6]

OVP[1:0]

01 = 6.5V (5V input)

10 = 10.5V (9V input)

11 = 14V (12V input) (default)

Boost Mode Voltage Regulation

00 = 4.85V

01 = 5.00V

10 = 5.15V (default)

11 = 5.30V

OVP threshold for input supply.

REG_RST

D[5:4]

BOOSTV[1:0]

REG_RST

VINDPM Threshold (n: 4 bits):

= Offset + 0.1n (V)

VINDPM[3]

1 = 800mV

0

1

0

R/W

Offset: 3.9V (VINDPM_OS = 00, default)

Range: 3.9V (0000) - 5.4V (1111)

Default: 4.5V (0110)

VINDPM[2]

1 = 400mV

D[3:0]

VINDPM[3:0]

Offset: 5.9V (VINDPM_OS = 01)

Range: 5.9V (0000) - 7.4V (1111)

REG_RST

VINDPM[1]

1 =200mV

Offset: 7.5V (VINDPM_OS = 10)

Range: 7.5V (0000) - 9V (1111)

VINDPM[0]

1 =100mV

Offset: 10.5V (VINDPM_OS = 11)

Range: 10.5V (0000) - 12V (1111)

SG Micro Corp

www.sg-micro.com

SEPTEMBER 2022

35

SGM41541

SGM41542

High Input Voltage, 3.78A Single-Cell Battery Charger

with NVDC Power Path Management

REGISTER MAPS (continued)

REG07

Register address: 0x07; R/W

PORV = 01001100

Table 14. REG07 Register Details

BITS

BIT NAME

DESCRIPTION

COMMENT

PORV TYPE

RESET BY

Input Current Limit Detection

0 = Not in input current limit detection

(default)

1 = Force input current limit detection

when VBUS is present

Reloads with 0 when input detection

is completed.

REG_RST

or Watchdog

D[7]

IINDET_EN

0

1

R/W

Enable Half Clock Rate Safety Timer

0 = Disable

1 = Safety timer slow down during

DPM, JEITA cool, or thermal

regulation (default)

REG_RST

or Watchdog

D[6]

D[5]

TMR2X_EN

Slow down by a factor of 2.

Disable BATFET

0 = Allow BATFET (Q4) to turn on

(default)

1 = Turn off BATFET (Q4) after a

t_{SM_DLY}delay time (REG07 D[3])

BATFET_DIS

t_{SM_DLY}is typically 12.3 seconds.

0

R/W REG_RST

JEITA Charging Voltage

JEITA_VSET_H 0 = Set charge voltage to the lower of

REG_RST

R/W

D[4]

D[3]

4.1V and V_REG(default)

1 = Set charge voltage to V_REG

or Watchdog

(45℃ - 60℃)

BATFET Turn Off Delay Control

0 = Turn off BATFET immediately

1 = Turn off BATFET after t_{SM_DLY}

(default)

BATFET_DLY

BATFET_DIS bit is set.

1

R/W REG_RST

Enable BATFET Reset

D[2] BATFET_RST_EN 0 = Disable BATFET reset

1 = Enable BATFET reset (default)

REG_RST

R/W

or Watchdog

Dynamic VINDPM Tracking

00 = Disable (V_INDPMset by register)

01 = V_BAT+ 200mV

10 = V_BAT+ 250mV

11 = V_BAT+ 300mV

0

R/W

Set V_INDPMto track V_BATvoltage. Actual

VDPM_BAT_

TRACK[1:0]

D[1:0]

V_INDPMis the larger of VINDPM[3:0] and

REG_RST

R/W

this register value.

SG Micro Corp

www.sg-micro.com

SEPTEMBER 2022

36

SGM41541

SGM41542

High Input Voltage, 3.78A Single-Cell Battery Charger

with NVDC Power Path Management

REGISTER MAPS (continued)

REG08 (Status Bits, Read Only)

Register address: 0x08; R

PORV = xxxxxxxx

Table 15. REG08 Register Details

BITS

BIT NAME

DESCRIPTION

VBUS Status Register (SGM41542)

PORV TYPE

RESET BY

000 = No input

001 = USB host SDP

x

R

010 = USB CDP (1.5A)

011 = USB DCP (2.4A)

101 = Unknown adapter (500mA)

110 = Non-standard adapter (1A/2A/2.1A/2.4A)

111 = OTG

D[7:5]

VBUS_STAT[2:0]

NA

VBUS Status Register (SGM41541)

000 = No input

001 = USB host SDP (500mA) → PSEL HIGH

010 = Adapter 2.4A → PSEL LOW

111 = OTG

x

R

Other values are reserved.

Current limit value is reported in IINDPM[4:0] register.

Charging Status

00 = Charge disable

01 = Pre-charge (V_BAT< V_BATLOW

10 = Fast charging (constant current or voltage)

11 = Charging terminated

x

R

D[4:3]

CHRG_STAT[1:0]

)

NA

Input Power Status (VBUS in good voltage range and not poor)

0 = Input power source is not good

1 = Input power source is good

D[2]

D[1]

D[0]

PG_STAT

THERM_STAT

VSYS_STAT

x

R

NA

Thermal Regulation Status

0 = Not in thermal regulation

1 = In thermal regulation

System Voltage Regulation Status

0 = Not in VSYSMIN regulation (V_BAT> V_{SYS_MIN}

)

1 = In VSYSMIN regulation (V_BAT< V_{SYS_MIN}

)

SG Micro Corp

www.sg-micro.com

SEPTEMBER 2022

37

SGM41541

SGM41542

High Input Voltage, 3.78A Single-Cell Battery Charger

with NVDC Power Path Management

REGISTER MAPS (continued)

REG09 (Fault Bits, Read Only)

Register address: 0x09; R

PORV = xxxxxxxx

Table 16. REG09 Register Details

BITS

BIT NAME

DESCRIPTION

PORV

TYPE

RESET BY

NA

Watchdog Fault Status

D[7] WATCHDOG_FAULT 0 = Normal (no fault)

1 = Watchdog timer expired

x

R

Boost Mode Fault Status

0 = Normal

1 = VBUS overloaded in OTG, or VBUS OVP, or battery voltage too low

(any condition that prevents Boost starting)

D[6]

BOOST_FAULT

x

R

NA

Charging Fault Status

00 = Normal

D[5:4] CHRG_FAULT[1:0] 01 = Input fault (VBUS OVP or V_BAT< V_VBUS< 3.8V)

10 = Thermal shutdown

x

R

NA

11 = Charge safety timer expired

Battery Fault Status

0 = Normal

D[3]

BAT_FAULT

x

R

1 = Battery over-voltage (BATOVP)

JEITA Condition Based on Battery NTC Temperature Measurement

000 = Normal

010 = Warm (Buck mode only)

011 = Cool (Buck mode only)

101 = Cold

110 = Hot

x

R

D[2:0]

NTC_FAULT[2:0]

NA

NTC fault bits are updated in real time and do not need a read to reset.

SG Micro Corp

www.sg-micro.com

SEPTEMBER 2022

38

SGM41541

SGM41542

High Input Voltage, 3.78A Single-Cell Battery Charger

with NVDC Power Path Management

REGISTER MAPS (continued)

REG0A

Register address: 0x0A; R and R/W

PORV = xxxxxx00

Table 17. REG0A Register Details

BITS

BIT NAME

DESCRIPTION

Good Input Source Detected

PORV TYPE

RESET BY

D[7]

VBUS_GD

0 = A good VBUS is not attached

1 = A good VBUS attached

x

R

NA

Input Voltage Regulation (Dynamic Power Management)

0 = Not in VINDPM

D[6]

VINDPM_STAT

1 = In VINDPM

Input Current Regulation (Dynamic Power Management)

0 = Not in IINDPM

1 = In IINDPM

D[5]

D[4]

D[3]

IINDPM_STAT

CV_STAT

x

R

NA

CV Mode Status Indicator when DCEN = 1

0 = VBAT lower than VREG

1 = VBAT approach to VREG

Active Top-Off Timer Counting Status

TOPOFF_ACTIVE 0 = Top-off timer not counting

1 = Top-off timer counting

Input Over-Voltage Status (AC adaptor is the input source)

0 = No over-voltage (no ACOV)

1 = Over-voltage detected (ACOV)

D[2]

ACOV_STAT

x

0

R

NA

VINDPM Event Detection Interrupt Mask

D[1] VINDPM_INT_MASK 0 = Allow VINDPM INT pulse

1 = Mask VINDPM INT pulse

R/W REG_RST

IINDPM Event Detection Mask

D[0] IINDPM_INT_MASK 0 = Allow IINDPM to send INT pulse

1 = Mask IINDPM INT pulse

REG0B

Register address: 0x0B; R and R/W

PORV = 0110x1xx

Table 18. REG0B Register Description

BITS

BIT NAME

DESCRIPTION

PORV TYPE

RESET BY

Register Reset

0 = No effect (keep current register settings)

1 = Reset R/W bits of all registers to the default and reset safety timer

(It also resets itself to 0 after register reset is completed.)

D[7]

REG_RST

0

R/W REG_RST

1

0

x

1

x

R

Part ID

1100 = SGM41541

1101 = SGM41542

D[6:3]

PN[3:0]

NA

D[2]

SGMPART

NA

D[1:0]

DEV_REV[1:0]

Revision

SG Micro Corp

www.sg-micro.com

SEPTEMBER 2022

39

SGM41541

SGM41542

High Input Voltage, 3.78A Single-Cell Battery Charger

with NVDC Power Path Management

REGISTER MAPS (continued)

REG0C

Register address: 0x0C; R/W

PORV = 01110101

Table 19. REG0C Register Details

BITS

BIT NAME

DESCRIPTION

COMMENT

PORV TYPE

RESET BY

REG_RST

JEITA Charging Voltage

0 = Set charge voltage to V_REG(default)

1 = Set charge voltage to the lower of

4.1V and V_REG

Charge Enable during Cool

Temperature

JEITA_VSET_L

D[7]

0

1

R/W

or Watchdog

(0℃ - 10℃)

JEITA_ISET_L_EN

REG_RST

or Watchdog

D[6]

0 = Disable

(0℃ - 10℃)

1 = Enable (default)

Charge Current Setting during Warm

Temperature

JEITA_ISET_H[1:0]

00 = 0% of I_CHG

01 = 20% of I_CHG

10 = 50% of I_CHG

In warm condition, the safety

timer does not become 2X.

REG_RST

or Watchdog

D[5:4]

11

R/W

(45℃ - 60℃)

11 = 100% of I_CHG(default)

JEITA Cool Threshold Setting

00 = V_T2= 70.75% (5.5℃)

01 = V_T2= 68% (10℃) (default)

10 = V_T2= 65.25% (15℃)

REG_RST

or Watchdog

D[3:2]

JEITA_VT2 [1:0]

JEITA_VT3 [1:0]

01

R/W

11 = V_T2= 62.25% (20℃)

JEITA Warm Threshold Setting

00 = V_T3= 48.25% (40℃)

01 = V_T3= 44.5% (45℃) (default)

10 = V_T3= 40.75% (50.5℃)

11 = V_T3= 37.75% (54.5℃)

REG_RST

or Watchdog

D[1:0]

REG0D

Register address: 0x0D; R/W

PORV = 00000001

Table 20. REG0D Register Details

BITS

BIT NAME

DESCRIPTION

COMMENT

PORV TYPE

RESET BY

Current Pulse Control Enable

0 = Disable (default)

1 = Enable (PUMPX_UP and

PUMPX_DN)

Current Pulse Control Voltage up

Enable

0 = Disable (default)

1 = Enable

Current Pulse Control Voltage

down Enable

0 = Disable (default)

1 = Enable

REG_RST

or Watchdog

D[7]

EN_PUMPX

0

R/W

This bit can only be set when

EN_PUMPX bit is set and returns to 0

after current pulse control sequence is

completed.

REG_RST

or Watchdog

D[6]

D[5]

PUMPX_UP

PUMPX_DN

This bit can only be set when

EN_PUMPX bit is set and returns to 0

after current pulse control sequence is

completed.

REG_RST

or Watchdog

D+ Output Voltage Setting

00 = HIZ (default)

01 = 0V

10 = 0.6V

11 = 3.3V

Register bits are reset to default value

when input source is plugged-in and can

be changed after D+/D- detection is

completed.

REG_RST

or Watchdog

D[4:3]

DP_VSET[1:0]

00

R/W

D- Output Voltage Setting

00 = HIZ (default)

01 = 0V

10 = 0.6V

11 = 3.3V

Register bits are reset to default value

when input source is plugged-in and can

be changed after D+/D- detection is

completed.

REG_RST

or Watchdog

D[2:1]

D[0]

DM_VSET[1:0]

JEITA_EN

00

1

R/W

JEITA Enable

0 = Disable

1 = Enable (default)

REG_RST

or Watchdog

SG Micro Corp

www.sg-micro.com

SEPTEMBER 2022

40

SGM41541

SGM41542

High Input Voltage, 3.78A Single-Cell Battery Charger

with NVDC Power Path Management

REGISTER MAPS (continued)

REG0E

Register address: 0x0E; R or R/W

PORV = xxxxxxxx

Table 21. REG0E Register Details

BITS

BIT NAME

DESCRIPTION

COMMENT

PORV TYPE

RESET BY

VBUS Input Detection Done Flag

INPUT_DET_DONE 0 = Normal

1 = Detection done

PSEL or DPDM detection done flag

after VBUS plug in.

D[7]

X

R

NA

D[6:0]

Reserved

Reserved.

REG0F

Register address: 0x0F; R or R/W

PORV = 00000000

Table 22. REG0F Register Details

BITS

BIT NAME

DESCRIPTION

VREG Fine Tuning

COMMENT

PORV TYPE

RESET BY

00 = Disable (default)

01 = V_REG+ 8mV

10 = V_REG- 8mV

REG_RST

or Watchdog

D[7:6]

VREG_FT

00

R/W

11 = V_REG- 16mV

REG_RST

or Watchdog

D[5]

D[4]

Reserved

DCEN

Reserved

Reserved.

0

R/W

DCEN Pin Output Control

0 = Low (default)

1 = High

When BATOVP time reaches

REG_RST

or Watchdog

t

_{BATOVP_DCEN}, the bit resets to default.

STAT Pin Output Setting

00 = LED off (HIZ) (default)

01 = LED on (low)

10 = LED blinking 1s on 1s off

11 = LED blinking 1s on 3s off

VINDPM Offset

This bits only takes effect when

EN_ICHG_MON[1:0] = 01.

REG_RST

or Watchdog

D[3:2]

STAT_SET[1:0]

00

R/W

00 = 3.9V (default)

D[1:0] VINDPM_OS[1:0] 01 = 5.9V

R/W REG_RST

10 = 7.5V

11 = 10.5V

SG Micro Corp

www.sg-micro.com

SEPTEMBER 2022

41

SGM41541

SGM41542

High Input Voltage, 3.78A Single-Cell Battery Charger

with NVDC Power Path Management

APPLICATION INFORMATION

The SGM41541/SGM41542 is typically used as a charger

with power path management in smart phones, tablets and

other portable devices. In the design, it comes along with a

host controller (a processor with I²C interface) and a

single-cell Li-Ion or Li-polymer battery.

the converter does not operate at D ≈ 50%, the worst case

capacitor RMS current can be estimated from (5) in which D

is the closest operating duty cycle to 0.5.

(5)

I_CIN= I_CHG× D× 1−D

(

)

For SGM41541/SGM41542, place C_INacross PMID and GND

pins close to the chip. Voltage rating of the capacitor must be

at least 25% higher than the normal input voltage to minimize

voltage derating. For a 13.5V input voltage, the preferred

rating is 25V or higher.

Detailed Design Procedure

Inductor Design

Small energy storage elements (inductor and capacitor) can

be used due to the high frequency (1.5MHz) switching

converter used in the SGM41541/SGM41542. Inductor

should tolerate currents higher than the maximum charge

current (I_CHG) plus half the inductor peak to peak ripple

current (∆I) without saturation:

A C_IN= 22μF is suggested.

Output Capacitor Design

The output capacitance (on the system) must have enough

RMS (ripple) current rating to carry the inductor switching

ripple and provide enough energy for system transient current

demands. I_COUT(C_OUTRMS current) can be calculated by:

∆I

2

(3)

I_SAT> I_CHG

+

The inductor ripple current is determined by the input voltage

(V_VBUS), duty cycle (D = V_BAT/V_VBUS), switching frequency (f_S=

1.5MHz) and the inductance (L). In CCM:

I_RIPPLE

I_COUT

=

≈ 0.29×I_RIPPLE

2× 3

(6)

(7)

V_VBUS×D× 1−D

(

)

And the output voltage ripple can be calculated by:

(4)

∆I =

f_S×L



₂









V_OUT

∆V_O

=

1−

8LC_OUTf_S

V_VBUS

Inductor ripple current is maximum when D ≈ 0.5. In the

practical designs, inductor peak to peak current ripple is

selected in a range between 20% to 40% of the maximum DC

current ∆I = (0.2 ~ 0.4) × I_CHGfor a good trade-off between

inductor size and efficiency. Selecting higher ripple allows

choosing of smaller inductance.

Increasing L or C_OUT(the LC filter) can reduce the ripple.

The internal loop compensation of the device is optimized for >

22μF ceramic output capacitor. 10V, X7R (or X5R) ceramic

capacitors are recommended for the output.

For each application, V_VBUSand I_CHGare known, so L can be

calculated from (4) and current rating of the inductor can be

selected from (3). Choose an inductor that has small DCR

and core losses at 1.5MHz to have high efficiency and cool

operation at full load.

Input Power Supply Considerations

To power the system from the SGM41541/SGM41542, either

an input power source with a voltage between 3.9V to 13.5V

and at least 100mA current rating should power VBUS, or a

single-cell Li-Ion battery with voltage higher than V_{BAT_UVLOZ}

should be connected to BAT pin of the device. The input

source must have enough current rating to allow maximum

power delivery through charger (Buck converter) to the

system.

Input Capacitor Design

Select low ESR ceramic input capacitor (X7R or X5R) with

sufficient voltage and RMS ripple current rating for decoupling

of the input switching ripple current (I_CIN). The RMS ripple

current in the worst case is around the I_CHG/2 when D ≈ 0.5. If

SG Micro Corp

www.sg-micro.com

SEPTEMBER 2022

42

SGM41541

SGM41542

High Input Voltage, 3.78A Single-Cell Battery Charger

with NVDC Power Path Management

APPLICATION INFORMATION (continued)

Layout Guidelines

It is better to avoid using vias for these connections and keep

The switching node (SW) creates very high frequency noises,

which are several times higher than f_SW(1.5MHz) due to

sharp rise and fall of the voltage and current in the switches.

To reduce the ringing issues and noise generation, it is

important to design a proper layout for minimizing the current

path impedance and loop area. A graphical guideline for the

current loops and their frequency content is provided in

Figure 21. The following considerations can help to make a

better layout.

the high frequency current paths short enough and on the

same layer. A GND copper layer under the component layer

helps to reduce noise emissions. Pay attention to the DC

current and AC current paths in the layout and keep them

short and decoupled as much as possible.

4. For analog signals, it is better to use a separate analog

ground (AGND) branched only at one point from GND pin. To

avoid high current flow through the AGND path, it should be

connected to GND only at one point (preferably the GND pin).

1. Place the input capacitor between PMID and GND pins as

close as possible to the chip with shortest copper connections

(avoid vias). Choose the smallest capacitor size.

5. Place decoupling capacitors close to the IC pins with the

shortest copper connections.

6. Solder the exposed thermal pad of the package to the PCB

ground planes. Ensure that there are enough thermal vias

directly under the IC, connecting to the ground plane on the

other layers for better heat dissipation and cooling of the

device.

2. Connect one pin of the inductor as close as possible to the

SW pin of the device and minimize the copper area

connected to the SW node to reduce capacitive coupling from

SW area to nearby signal traces. This decreases the noise

induced through parasitic stray capacitances and

displacement currents to other conductors. SW connection

should be wide enough to carry the charging current. Keep

other signals and traces away from SW if possible.

7. Select proper sizes for the vias and ensure enough copper

is available to carry the current for a given current path. Vias

usually have some considerable parasitic inductance and

resistance.

3. Place output capacitor GND end as close as possible to the

GND pin of the device and the GND end of input capacitor C_IN.

DC Current

DC Current Path

(I_AC≈ 0)

SYS

SW

(Boost Mode

Direction)

Switching Frequency

and Its Low Order

Very High

Frequency

(Current Path)

SYS

Harmonics

(Current Path)

Load

Transient

Current Path

C_IN

C_OUT

Figure 21. The Paths and Loops Carrying High Frequency, DC Currents and Very High Frequency

(for Layout Design Consideration)

SG Micro Corp

www.sg-micro.com

SEPTEMBER 2022

43

SGM41541

SGM41542

High Input Voltage, 3.78A Single-Cell Battery Charger

with NVDC Power Path Management

REVISION HISTORY

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

SEPTEMBER 2022 ‒ REV.B.1 to REV.B.2

Page

Update Electrical Characteristics section.............................................................................................................................................................7

AUGUST 2022 ‒ REV.B to REV.B.1

Page

Added part number SGM41541.........................................................................................................................................................................All

JULY 2022 ‒ REV.A.4 to REV.B

Page

Update Electrical Characteristics section.............................................................................................................................................................7

JUNE 2022 ‒ REV.A.3 to REV.A.4

Page

Update Compliance with JEITA Guideline section .............................................................................................................................................21

APRIL 2022 ‒ REV.A.2 to REV.A.3

Page

Update Register Maps REG0E section..............................................................................................................................................................42

MARCH 2022 ‒ REV.A.1 to REV.A.2

Page

Added Package Thermal Resistance section.......................................................................................................................................................3

MARCH 2022 ‒ REV.A to REV.A.1

Page

Update Recommended Operating Conditions section..........................................................................................................................................3

Update Pin Description section............................................................................................................................................................................5

Changes from Original (FEBRUARY 2022) to REV.A

Page

Changed from product preview to production data.............................................................................................................................................All

SG Micro Corp

www.sg-micro.com

SEPTEMBER 2022

44

PACKAGE INFORMATION

PACKAGE OUTLINE DIMENSIONS

TQFN-4×4-24L

D

e

L

D1

E

E1

N24

k

PIN 1#

N1

b

DETAIL A

TOP VIEW

BOTTOM VIEW

3.8

2.7

C

SEATING PLANE

A

A1

A2

eee

C

2.7 3.8

SIDE VIEW

0.7

ALTERNATE A-1

ALTERNATE A-2

0.5

DETAIL A

ALTERNATE TERMINAL

CONSTRUCTION

0.24

RECOMMENDED LAND PATTERN (Unit: mm)

Dimensions In Millimeters

Symbol

MIN

0.700

0.000

MOD

MAX

0.800

0.050

A

A1

A2

b

-

0.203 REF

0.180

3.900

2.600

-

0.300

4.100

2.800

D

-

E

-

D1

E1

e

-

0.500 BSC

0.200 MIN

-

k

L

0.300

0.500

eee

0.080

NOTE: This drawing is subject to change without notice.

SG Micro Corp

TX00086.001

www.sg-micro.com

PACKAGE INFORMATION

TAPE AND REEL INFORMATION

REEL DIMENSIONS

TAPE DIMENSIONS

P2

P0

W

Q2

Q4

Q2

Q4

Q2

Q4

Q1

Q3

Q1

Q3

Q1

Q3

B0

Reel Diameter

P1

A0

K0

Reel Width (W1)

DIRECTION OF FEED

NOTE: The picture is only for reference. Please make the object as the standard.

KEY PARAMETER LIST OF TAPE AND REEL

Reel Width

Reel

Diameter

A0

B0

K0

P0

P1

P2

W

Pin1

Package Type

W1

(mm)

(mm) (mm) (mm) (mm) (mm) (mm) (mm) Quadrant

TQFN-4×4-24L

13″

12.4

4.30

1.10

4.0

8.0

2.0

12.0

Q2

SG Micro Corp

TX10000.000

www.sg-micro.com

PACKAGE INFORMATION

CARTON BOX DIMENSIONS

NOTE: The picture is only for reference. Please make the object as the standard.

KEY PARAMETER LIST OF CARTON BOX

Length

(mm)

Width

(mm)

Height

(mm)

Reel Type

Pizza/Carton

13″

386

280

370

5

SG Micro Corp

www.sg-micro.com

TX20000.000


型号：	SGM41542
厂家：	Shengbang Microelectronics Co, Ltd
描述：	High Input Voltage, 3.78A Single-Cell Battery Charger with NVDC Power Path Management 电池
文件：	总47页 (文件大小：1451K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

SGM41542 [SGMICRO]

相关型号：

SI9130DB

SI9135LG-T1

SI9135LG-T1-E3

SI9135_11

SI9136_11

SI9130CG-T1-E3

SI9130LG-T1-E3

SI9130_11

SI9137

SI9137DB

SI9137LG

SI9122E