SGM41600_技术文档

SGM41600

I²C Controlled 6A Single-Cell Switched-Capacitor

Fast Charger with Bypass Mode and ADC

GENERAL DESCRIPTION

FEATURES

The SGM41600 is an efficient 6A switched-capacitor battery

charging device with I²C control that can operate either in

charge-pump voltage divider mode or in bypass mode. It can

charge single-cell Li-Ion or Li-polymer battery in a wide 3.3V

to 11.5V input voltage range (VBUS) from smart wall adapters

or power banks. The switched-capacitor architecture is

optimized for 50% duty cycle to cut the input current to

one-half of the battery current and reduce the wiring drops,

losses and temperature rise in the application.

● Efficiency Optimized Switched-Capacitor Architecture

 Up to 6A Output Current

 3.3V to 11.5V Input Voltage Range

 200kHz to 1.5MHz Switching Frequency Setting

 Up to 97% Voltage Divider Mode Efficiency

(when V_BAT= 4V, I_BAT= 3A)

● Comprehensive Integrated Protection Features

 External OVP Control and Regulation

 Input Over-Voltage Protection (BUS_OVP)

 Input Short-Circuit Protection (BUS_SC)

 Input Over-Current Protection (IBUS_OCP)

 Input Under-Current Protection (IBUS_UCP)

 Battery Over-Voltage Protection (BAT_OVP)

 Output Short-Circuit Protection (VOUT_SC)

 Battery Over-Current Protection (IBAT_OCP)

 CFLY Short-Circuit Protection (CFLY_SC)

 Converter Over-Current Protection (CONV_OCP)

 Die Over-Temperature Protection (TDIE_OTP)

● 5-Channel 12-Bit (Effective) ADC Converter

 VBUS, IBUS, VBAT, IBAT, TDIE Monitoring

A two-phase switched-capacitor topology is used to reduce

the required input capacitors, improve efficiency and minimize

the output ripple. Necessary protection features for safe

charging performance including input over-voltage protection

by external OVPFET (Q_OVP) and input reverse blocking (using

an internal NFET) are provided.

A fast analog-to-digital converter (ADC) with 12-bit effective

resolution is also included to measure die temperature, bus

voltage, bus current, battery voltage and battery current (5

channels) for battery management of the charge process.

The SGM41600 is available in a Green WLCSP- 2.6×2.6-36B

package and can operate in the -40℃ to +85℃ ambient

temperature range.

APPLICATIONS

Smart Phone, Tablet PC

TYPICAL APPLICATION

C_BST1C_FLY1

OVPGATE VAC BST1 CFH1 CFL1

Q_OVP

VBUS

VOUT

Adapter

C_VBUS

C_VOUT

PGND

Battery

Pack

DP

DM

SGM41600

BATP

SDA

BATN/SRP

Host

SCL

R_SEN

nINT

SRN

REGN

AGND PMID BST2 CFH2 CFL2

C_REGN

C_PMID

C_BST2C_FLY2

Figure 1. Typical Application Circuit

SG Micro Corp

MARCH 2023 – REV. A. 1

www.sg-micro.com

I²C Controlled Single-Cell 6A Switched-Capacitor

Fast Charger with Bypass Mode and ADC

SGM41600

PACKAGE/ORDERING INFORMATION

SPECIFIED

TEMPERATURE

RANGE

PACKAGE

DESCRIPTION

ORDERING

NUMBER

PACKAGE

MARKING

PACKING

OPTION

MODEL

SGM

41600

XXXXX

XX#XX

SGM41600 WLCSP-2.6×2.6-36B

SGM41600YG/TR

Tape and Reel, 5000

-40℃ to +85℃

MARKING INFORMATION

NOTE: XXXXX = Date Code, Trace Code and Vendor Code. XX#XX = Coordinate Information and Wafer ID Number.

Date Code - Year

Trace Code

Vendor Code

X X X X X

XX＃XX

Coordinate Information

Wafer ID Number ("A" = 01, "B" = 02, …"Y" = 25)

Coordinate Information

Green (RoHS & HSF): SG Micro Corp defines "Green" to mean Pb-Free (RoHS compatible) and free of halogen substances. If

you have additional comments or questions, please contact your SGMICRO representative directly.

ABSOLUTE MAXIMUM RATINGS

RECOMMENDED OPERATING CONDITIONS

VAC.....................................................................3.3V to 18V

OVPGATE..............................................................8V to 23V

VBUS (Bypass Mode) ........................................3.3V to 5.5V

VBUS (Voltage Divider Mode)..........................5.5V to 11.5V

VOUT, BATP............................................................3V to 5V

I_VOUT(Bypass Mode).................................................0A to 4A

I_VOUT(Voltage Divider Mode)....................................0A to 6A

(CFH1 - VOUT), CFL1...........................................0V to 5.5V

(CFH2 - VOUT), CFL2...........................................0V to 5.5V

BATN/SRP, SRN...................................................0V to 1.5V

(SRP - SRN)..................................................-0.05V to 0.05V

SDA, SCL, nINT .......................................................0V to 5V

Junction Temperature Range...................... -40℃ to +125℃

VAC (Converter Not Switching) ......................... -0.3V to 30V

OVPGATE ......................................................... -0.3V to 30V

OVPGATE to VBUS............................................. -0.3V to 6V

VBUS, PMID (Converter Not Switching)............ -0.3V to 22V

BST1, BST2.......................................-0.3V to (PMID + 5.5V)

VOUT................................................................... -0.3V to 6V

CFH1, CFH2 to VOUT......................................... -0.3V to 6V

CFL1, CFL2......................................................... -0.3V to 6V

DP, DM, REGN, BATP, SDA, SDL, nINT............. -0.3V to 6V

BATN/SRP, SRN .............................................. -0.3V to 1.8V

SRP to SRN...................................................... -0.5V to 0.5V

Package Thermal Resistance

WLCSP-2.6×2.6-36B, θ_JA.......................................... 58℃/W

Junction Temperature.................................................+150℃

Storage Temperature Range.......................-65℃ to +150℃

Lead Temperature (Soldering, 10s)............................+260℃

ESD Susceptibility

OVERSTRESS CAUTION

Stresses beyond those listed in Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to

absolute maximum rating conditions for extended periods

may affect reliability. Functional operation of the device at any

conditions beyond those indicated in the Recommended

Operating Conditions section is not implied.

HBM.............................................................................2000V

CDM ............................................................................1000V

ESD SENSITIVITY CAUTION

This integrated circuit can be damaged if ESD protections are

not considered carefully. SGMICRO recommends that all

integrated circuits be handled with appropriate precautions.

Failureto observe proper handlingand installation procedures

can cause damage. ESD damage can range from subtle

performance degradation tocomplete device failure. Precision

integrated circuits may be more susceptible to damage

because even small parametric changes could cause the

device not to meet the published specifications.

DISCLAIMER

SG Micro Corp reserves the right to make any change in

circuit design, or specifications without prior notice.

SG Micro Corp

www.sg-micro.com

MARCH 2023

2

I²C Controlled Single-Cell 6A Switched-Capacitor

Fast Charger with Bypass Mode and ADC

SGM41600

PIN CONFIGURATION

(TOP VIEW)

1

2

3

4

5

6

OVP

GATE

A

B

C

D

E

F

VAC

VBUS

BST1

CFH1

VOUT

CFL1

PGND

PMID

CFH1

VOUT

CFL1

PGND

DP

DM

SCL

PMID

CFH2

VOUT

CFL2

PGND

BST2

CFH2

VOUT

CFL2

PGND

SDA

BATN

/SRP

SRN

nINT

REGN

BATP

AGND

WLCSP-2.6×2.6-36B

SG Micro Corp

www.sg-micro.com

MARCH 2023

3

I²C Controlled Single-Cell 6A Switched-Capacitor

Fast Charger with Bypass Mode and ADC

SGM41600

PIN DESCRIPTION

NAME

VAC

TYPE ⁽¹⁾

FUNCTION

A1

AI

P

Adapter DC Voltage Sense Input Pin. Connect it to the drain of the external OVPFET (Q_OVP).

Device Power Input Pins. Connect a 10µF or larger ceramic capacitor between VBUS and PGND

pins as close to the device as possible.

A2, A3, A4, A5

VBUS

OVPGATE

BST1

PMID

DP

A6

AO

P

External N-FET Gate Control Pin. Connect to the gate of the external OVPFET (Q_OVP).

Phase 1 Bootstrap Pin. It is the BST pin to supply Q_CH1gate driver. Use a 0.1μF or larger MLCC

B1

capacitor from this pin to CFH1 pin.

B2, B5

P

Power Stage Supply Input Pins. Bypass them with at least 10µF ceramic capacitor to PGND.

USB Communication Interface Positive Line. Connect to the USB D+ data line.

USB Communication Interface Negative Line. Connect to the USB D- data line.

B3

AIO

P

B4

DM

Phase 2 Bootstrap Pin. It is the BST pin to supply Q_CH2gate driver. Use a 0.1μF or larger MLCC

B6

BST2

CFH1

SDA

capacitor from this pin to CFH2 pin.

Phase 1 Flying Capacitor Positive Pins. Connect two 22µF or larger parallel capacitors between

CFH1 and CFL1 pins as close as possible to the device.

C1, C2

P

C3

DIO

DI

P

I²C Interface Data Line.

C4

SCL

I²C Interface Clock Input Line.

Phase 2 Flying Capacitor Positive Pins. Connect two 22µF or larger parallel capacitors between

CFH2 and CFL2 pins as close as possible to the device.

Output Pins. Connect to the battery pack positive terminal. Two 10µF capacitors between VOUT

and PGND pins are recommended.

C5, C6

CFH2

VOUT

BATN/SRP

SRN

D1, D2, D5, D6

P

D3

AI

P

Battery Voltage Sensing Negative Input or Battery Current Sensing Positive Input.

Battery Current Sensing Negative Input. Place a 5mΩ (R_SEN) shunt resistor between SRN and

D4

BATN/SRP pins.

Phase 1 Flying Capacitor Negative Pins. Connect two 22µF or larger parallel capacitors between

CFH1 and CFL1 pins as close as possible to the device.

Battery Voltage Sensing Positive Input. Connect a 100Ω resistor between BATP and positive

E1, E2

CFL1

BATP

nINT

E3

AI

DO

P

terminal of the battery pack.

Open-Drain Interrupt Output Pin. Connect a pull-up 10kΩ to the logic high rail. It is normally high

but generates a low 256µs pulse when a charge fault occurs to inform the host.

Phase 2 Flying Capacitor Negative Pins. Connect two 22µF or larger parallel capacitors between

CFH2 and CFL2 pins as close as possible to the device.

E4

E5, E6

F1, F2, F5, F6

F3

CFL2

PGND

AGND

REGN

P

Power Ground Pin.

P

Analog Ground Pin (reference for low current signals).

Internal 3.3V LDO Output. Connect a 4.7μF MLCC capacitor between this pin and AGND.

F4

AO

NOTE:

1. P = power, AI = analog input, AO = analog output, AIO = analog input/output, DI = digital input, DO = digital output, DIO =

digital input/output.

SG Micro Corp

www.sg-micro.com

MARCH 2023

4

I²C Controlled Single-Cell 6A Switched-Capacitor

Fast Charger with Bypass Mode and ADC

SGM41600

ELECTRICAL CHARACTERISTICS

(T_J= -40℃ to +125℃, typical values are at T_J= +25℃, unless otherwise noted.)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

Supply Currents

ADC disabled, charge disabled, Q_OVPused,

VAC OVP activated, V_VAC= 12V, V_VBUS= 0V,

V_VOUT= 0V

ADC disabled, charge disabled, Q_OVPused,

V_VBUS= 8V

ADC enabled, charge enabled, Q_OVPused,

V_VBUS= 8V > 2 × V_VOUT, f_SW= 500kHz

ADC disabled, charge disabled,

VBUS not present, V_VAC= 0V, V_VOUT= 4.5V

ADC enabled, charge disabled, (after 1-shot ADC

conversion complete), VBUS not present,

V_VAC= 0V, V_VOUT= 4.5V

VAC Input Quiescent Current

(No VBUS or BAT sources)

I_{Q_VAC}

200

280

70

µA

50

10

µA

mA

µA

VBUS Power Input Quiescent

Current ⁽¹⁾

I_{Q_VBUS}

30

3.3

Battery-Only Quiescent Current

I_{Q_VOUT}

10

µA

VBUS Present Rising Threshold V_{BUS_PRESENT_R}V_VBUSrising

3

V

VBUS Present Hysteresis

External OVP Control

V_{BUS_PRESENT_HYS}

240

mV

VAC Present Rising Threshold

VAC Present Hysteresis

V_{VAC_PRESENT_R}V_VACrising

V_{VAC_PRESENT_HYS}

3

3.35

V

160

mV

VAC Present Rising Threshold

Deglitch Time ⁽¹⁾

V_BAT= 4V, deglitch between V_VACrising above

V_{VAC_PRESENT_R}and starting external OVPFET turn-on

I²C programmable, 1V per step, 12V by default

t_{VAC_IN_DEG}

20

ms

VAC OVP Rising Threshold

V_{VAC_OVP}

4

19

V

VAC OVP Threshold Accuracy

V_{VAC_OVP_ACC}

V_{VAC_OVP}= 5V or 12V

-2.7

3.7

%

VAC OVP Rising

Deglitch Time ⁽¹⁾

Deglitch between V_VACrising above V_{VAC_OVP}

and triggering the protection action

t_{VAC_OVP_DEG}

100

ns

VBUS Pull-Down Resistor

VAC Pull-Down Resistor

VAC Pull-Down Timeout ⁽¹⁾

R_{PD_VBUS}

R_{PD_VAC}

t_{VAC_PD}

V_VBUS= 2V

1

kΩ

Ω

60

70

AC_PDN_EN = 1

400

ms

V_{BAT_OVP}

- 200mV

V_{BAT_OVP}

- 50mV

VBAT Regulation Range

V_{BAT_REG}

V_{BAT_REG_ACC}

t_{VBAT_IN_DEG}

I²C programmable, 50mV per step

-0.4

-0.8

0.4

0.8

V

_{BAT_REG}= 4.3V, T_J= +25℃

VBAT Regulation Accuracy

%

V_{BAT_REG}= 4.3V, T_J= -40℃ to +125℃

Deglitch between V_BATrising above V_{BAT_REG}

(entering regulation mode), and flag bit set to 1

I²C programmable, 100mA per step

VBAT Regulation Entry

Deglitch Time ⁽¹⁾

500

µs

I_{BAT_OCP}

- 500mA

I_{BAT_OCP}

- 200mA

IBAT Regulation Range

I_{BAT_REG}

I_{BAT_REG_ACC}

t_{IBAT_IN_DEG}

IBAT Regulation Accuracy

-5.5

5

%

I_BAT= 4A, R_SEN= 5mΩ, T_J= +25℃

Deglitch between I_BATrising above I_{BAT_REG}

(entering regulation mode ) and flag bit set to 1

IBAT Regulation Entry

Deglitch Time ⁽¹⁾

µs

Switched Capacitor Chargers

VBUS to VOUT Resistance

R_DSONof Reverse Blocking FET

R_DSONof Q_CH1/2

R_DROPOUT

R_{DS_QRB}

R_{DS_QCH}

R_{DS_QDH}

R_{DS_QCL}

R_{DS_QDL}

Bypass mode

30

10

26

14

45

18

mΩ

V_VBUS= 10V, V_VOUT= 5V, I_BAT= 1A

R_DSONof Q_DH1/2

R_DSONof Q_CL1/2

R_DSONof Q_DL1/2

SG Micro Corp

www.sg-micro.com

MARCH 2023

5

I²C Controlled Single-Cell 6A Switched-Capacitor

Fast Charger with Bypass Mode and ADC

SGM41600

ELECTRICAL CHARACTERISTICS (continued)

(T_J= -40℃ to +125℃, typical values are at T_J= +25℃, unless otherwise noted.)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

Protection

nINT Low Pulse Duration when a

Protection Occurs

VBUS OVP Rising Threshold

Programming Range

t_INT

256

µs

I²C programmable, 100mV per step, 11.5V by

default

V_{BUS_OVP}

4

14

2

V

%

ns

VBUS OVP Threshold Accuracy

VBUS OVP Rising Deglitch Time ⁽¹⁾

V_{BUS_OVP_ACC}V_{BUS_OVP}= 5V or 11.5V

Deglitch between V_VBUSrising above V_{BUS_OVP}

-3.5

t_{VBUS_OVP_DEG}

100

and triggering protection action

Voltage divider I²C programmable,

0.5

3.6

mode

100mA per step, 3A by default

IBUS OCP Threshold Programming

Range

I_{BUS_OCP}

A

I²C programmable,

Bypass mode

2.5

-6

5.6

6

100mA per step, 5A by default

IBUS OCP Threshold Initial Accuracy

IBUS OCP Deglitch Time

I_{BUS_OCP_ACC}

t_{IBUS_OCP_DEG}

%

I_BUS= 2.5A, T_J= +25℃

Deglitch between I_BUSrising above I_{BUS_OCP}

and triggering protection action

50

µs

Rising, set by REG0x07[6] = 0

Rising, set by REG0x07[6] = 1

200

400

300

500

400

600

IBUS UCP Rising Threshold

IBUS UCP Rising Deglitch Time

IBUS UCP Falling Threshold

IBUS UCP Falling Deglitch Time

I_{BUS_UCP_R}

t_{IBUS_UCPR_DEG}

I_{BUS_UCP_F}

mA

µs

Deglitch between I_BUSrising above I_{BUS_UCP_R}

and triggering protection action

10

Falling, set by REG0x07[6] = 0

Falling, set by REG0x07[6] = 1

50

150

250

350

mA

µs

150

Deglitch between I_BUSfalling below I_{BUS_UCP_F}

and triggering protection action

I²C programmable, 25mV per step,

4.35V by default

t_{IBUS_UCPF_DEG}

V_{BAT_OVP}

10

VBAT OVP Rising Threshold

Programming Range

4

5

V

%

µs

A

VBAT OVP Threshold Accuracy

V_{BAT_OVP_ACC}V_{BAT_OVP}= 4.35V

Deglitch between V_BATrising above V_{BAT_OVP}

-0.5

0.5

8

and triggering protection action

VBAT OVP Rising Deglitch Time

t_{VBAT_OVP_DEG}

During VBAT_REG

I²C programmable, 100mA per step,

7.2A by default

500

IBAT OCP Threshold Programming

Range

I_{BAT_OCP}

2

7.2

5.5

4.1

A

I

_BAT= 4A, R_SEN= 5mΩ, T_J= +25℃

IBAT OCP Threshold Accuracy

I_{BAT_OCP_ACC}

-5.5

%

I_BAT= 4A, R_SEN= 5mΩ, T_J= +25℃

Deglitch between I_BATrising above I_{BAT_OCP}

and triggering protection action

50

µs

mV

℃

s

IBAT OCP Deglitch Time

t_{IBAT_OCP_DEG}

During IBAT_REG

I²C programmable, 50mV per step,

300mV by default, V_DRP= V_VAC- V_VBUS

500

VDRP OVP Threshold Programming

Range

V_{DRP_OVP}

T_{DIE_OTP}

t_WDT

50

400

80

TDIE OTP Rising Threshold

150

Watchdog Timeout Programming

Range ⁽¹⁾

I²C programmable, 0.5s by default

0.5

ADC Specification

ADC Resolution

ADC Conversion Time ⁽¹⁾

ADC_RES

12

3

bits

ms

V

t_{ADC_CONV}

Report data for each channel

3.5

Range

0

16.38

ADC BUS Voltage Readable in

REG0x12 and REG0x13

V_{BUS_ADC}

V_{BUS_ADC_ACC}

I_{BUS_ADC}

LSB

4

mV

%

ADC BUS Voltage Accuracy

-2.5

0

2

V_VBUS= 3.3V to 11.5V, T_J= 0℃ to +85℃

Range

8.19

A

ADC BUS Current Readable in

REG0x14 and REG0x15

LSB

2

mA

%

ADC BUS Current Accuracy

I_{BUS_ADC_ACC}

I_BUS= 2A, T_J= 0℃ to +85℃

SG Micro Corp

www.sg-micro.com

MARCH 2023

6

I²C Controlled Single-Cell 6A Switched-Capacitor

Fast Charger with Bypass Mode and ADC

SGM41600

ELECTRICAL CHARACTERISTICS (continued)

(T_J= -40℃ to +125℃, typical values are at T_J= +25℃, unless otherwise noted.)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

V

Range

LSB

0

5.5

ADC BAT Voltage Readable in

REG0x16 and REG0x17

V_{BAT_ADC}

2

mV

%

ADC BAT Voltage Initial Accuracy

V_{BAT_ADC_ACC}

-0.85

0

0.75

8.19

V_BAT= 3V to 4.8V, T_J=+25℃

Range

A

ADC BAT Current Readable in

REG0x18 and REG0x19

I_{BAT_ADC}

I_{BAT_ADC_ACC}

T_{DIE_ADC}

LSB

2

mA

%

ADC BAT Current Initial Accuracy

-7.5

-40

7.5

I_BAT= 4A, R_SEN= 5mΩ, T_J=+25℃

Range

LSB

150

℃

ADC TDIE Temperature Readable in

REG0x1A

1

℃

ADC TDIE Temperature Accuracy

T_{DIE_ADC_ACC}

±4

℃

Logic I/O Threshold (SCL, SDA and nINT Pins)

High Level Input Voltage

Low Level Input Voltage

Low Level Output Voltage

I²C Characteristics

V_{IH_I2C}

V_{IL_I2C}

V_{OL_I2C}

SCL and SDA pins

1.3

V

SCL and SDA pins

0.4

Sink 5mA, SDA and nINT pins

Fast-mode

400

SCL Clock Frequency

f_CLK

kHz

Fast-mode plus

1000

DP/DM Detection

V_{DP_SRC}

V_{DAT_REF}

t_{DCD_DBNC}

DP Force Detection Voltage

DM Pull-Down Detection Threshold

DM Pull-Down Detection Debounce Time ⁽¹⁾

0.55

0.6

60

0.65

0.4

V

ms

NOTE:

1. Guaranteed by design.

SG Micro Corp

www.sg-micro.com

MARCH 2023

7

I²C Controlled Single-Cell 6A Switched-Capacitor

Fast Charger with Bypass Mode and ADC

SGM41600

TYPICAL PERFORMANCE CHARACTERISTICS

Typical performance characteristics are taken with test equipment and the demo board for non-switching and switching tests,

respectively.

Efficiency vs. Charge Current

— 200kHz

V_BAT= 4V, 3 × 22μF per Phase

99

98

97

96

95

94

99

98

97

96

95

94

— 200kHz

V_BAT= 4V, 2 × 22μF per Phase

— 375kHz

— 500kHz

— 750kHz

— 1000kHz

— 1250kHz

— 1500kHz

— 375kHz

— 500kHz

— 750kHz

— 1000kHz

— 1250kHz

— 1500kHz

0

1

2

3

4

5

6

7

0

1

2

3

4

5

6

7

Charge Current (A)

Device Loss vs. Charge Current

V_BAT= 4V, 2 × 22μF per Phase

Charge Current (A)

Device Loss vs. Charge Current

V_BAT= 4V, 3 × 22μF per Phase

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0.0

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0.0

— 200kHz

— 375kHz

— 500kHz

— 750kHz

— 1000kHz

— 1250kHz

— 1500kHz

— 200kHz

— 375kHz

— 500kHz

— 750kHz

— 1000kHz

— 1250kHz

— 1500kHz

0

1

2

3

4

5

6

7

0

1

2

3

4

5

6

7

Charge Current (A)

VOUT Ripple at 500kHz

V_BAT= 4V, f = 500kHz

Charge Current (A)

VBAT_OVP Accuracy vs. VBAT_OVP Setting Voltage

160

140

120

100

80

0.5

I_BAT= 1A, f = 500kHz

0.4

0.3

0.2

0.1

0.0

-0.1

-0.2

-0.3

-0.4

-0.5

60

— 2 × 22μF per Phase

— 3 × 22μF per Phase

40

1

2

3

4

5

6

4.0 4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9 5.0

V_{BAT_OVP}(V)

Charge Current (A)

SG Micro Corp

www.sg-micro.com

MARCH 2023

8

I²C Controlled Single-Cell 6A Switched-Capacitor

Fast Charger with Bypass Mode and ADC

SGM41600

TYPICAL PERFORMANCE CHARACTERISTICS (continued)

Typical performance characteristics are taken with test equipment and the demo board for non-switching and switching tests,

respectively.

IBUS_ADC Accuracy vs. BUS Current

V_BAT= 4V, f = 500kHz

IBUS_ADC Error vs. BUS Current

V_BAT= 4V, f = 500kHz

5

4

0.100

0.075

0.050

0.025

0.000

-0.025

-0.050

-0.075

-0.100

3

2

1

0

-1

-2

-3

-4

-5

0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0

I_BUS(A)

0.0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0

I_BUS(A)

IBAT_ADC Accuracy vs. BAT Current

V_BAT= 4V, f = 500kHz

IBAT_ADC Error vs. BAT Current

V_BAT= 4V, f = 500kHz

5

4

0.20

0.15

0.10

0.05

0.00

-0.05

-0.10

3

2

1

0

-1

0.5

1.5

2.5

3.5

4.5

5.5

6.5

0.5

1.5

2.5

3.5

4.5

5.5

6.5

I_BAT(A)

VBAT_ADC Accuracy vs. BAT Voltage

I_BAT= 4A, f = 500kHz

VBAT_ADC Error vs. BAT Voltage

1.00

0.75

0.50

0.25

0.00

-0.25

-0.50

-0.75

-1.00

0.100

0.075

0.050

0.025

0.000

-0.025

-0.050

-0.075

-0.100

3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6

V_BAT(V)

0

1

2

3

4

5

6

V_BAT(V)

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9

I²C Controlled Single-Cell 6A Switched-Capacitor

Fast Charger with Bypass Mode and ADC

SGM41600

TYPICAL APPLICATION CIRCUIT

C_FLY1

C_BST1

22μF × 2

100nF

OVPGATE VAC BST1 CFH1 CFL1

Q_OVP

VBUS

VOUT

C_VOUT

10μF × 2

C_VBUS

10μF

C_VAC

1μF

Adapter

PGND

DP

DM

R_BATP

100Ω

3V3

Battery

Pack

SGM41600

BATP

10kΩ × 3

SDA

BATN/SRP

SRN

R_SEN

5mΩ

Host

SCL

nINT

REGN

AGND PMID BST2 CFH2 CFL2

C_PMID

C_REGN

4.7μF

10μF

C_FLY2

22μF × 2

C_BST2

100nF

Figure 2. Typical Application Circuit

FUNCTIONAL BLOCK DIAGRAM

CFL1

PMID

BST1

CFH1

VBUS

REGN

PGND

VOUT

Q_RB

Q_CH1

Q_DL1

Bias Power

Select

& LDO

Driver

Control

Q_DH1Q_CL1

Driver

Control

Driver

Control

VAC

External

OVPFET

Control

SCL

SDA

nINT

DP

IBUS_OCP

VBUS

Switched

Capacitor

Control

OVPGATE

IBUS

VBAT

IBAT

TDIE

IBUS_UCP

VBUS

12-Bit

ADC

Digital

Control

VBUS_OVP

IBAT

DM

VAC

VBAT

VAC_OVP

AGND

VBAT

BATP

BATN/SRP

SRN

Protection

VBAT_OVP

IBAT_OCP

VOUT

IBAT

CFLY_SC

CFHx

CFLx

Driver

Control

Driver

Control

ICONV

CONV_OCP

TDIE

Q_DH2Q_CL2

TDIE_OTP

VAC

Q_CH2

Q_DL2

VBUS

VDRP_OVP

PGND

PMID

BST2

CFH2

CFL2

Figure 3. Functional Block Diagram

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I²C Controlled Single-Cell 6A Switched-Capacitor

Fast Charger with Bypass Mode and ADC

SGM41600

DETAILED DESCRIPTION

The SGM41600 is an efficient 6A battery charger that

operates in voltage divider mode (switched-capacitor charge

pump) or in bypass mode. A two-phase switched-capacitor

core is integrated in the device to minimize the ripples and

improve efficiency in the voltage divider mode. A FET control

output for protection, a reverse blocking NFET and all other

necessary protection features for safe charging are included.

A high speed 12-bit ADC converter is also included to provide

bus voltage, bus current, battery voltage, battery current, and

die temperature information for the charge management host

via I²C serial interface.

half of the input voltage under no load conditions as explained

before. The SGM41600 has two phases of such architecture

operating at f_SWfrequency with 180° phase difference. Each

phase provides I_VOUT/2 at the VOUT node, so:

V_VOUT= ½V_PMID- ½R_EFF× I_VOUT

(6)

At low switching frequencies the capacitor charge sharing

losses are dominant and R_EFF≈ 1/(4f_SWC_FLY). As frequency

increases, R_EFFfinally approaches (R_{DS_QCH}+ R_{DS_QDH}

R_{DS_QCL}+ R_{DS_QDL})/2.

+

2:1

R_EFF

+

V_VOUT

-

V_PMID

-

Charge-Pump Voltage Divider Mode

The charge-pump voltage divider mode operates with a fixed

50% duty cycle. The basic principle of operation is shown in

Figure 4. In period 1, Q1 and Q3 are tuned on and V_PMID

charges the C_FLYand the battery (in series) such that:

Figure 5. Model of Voltage Divider

The two-phase interleaved operation ensures a smooth input

current and simplifies the noise filtering. The VOUT ripple can

be estimated by first order approximation of C_FLYvoltage drop

due to the discharge in the half period, plus the discharge

drop during the short dead time (15ns, TYP).

V_CFLY= V_PMID- V_BAT

(1)

In period 2, Q2 and Q4 are turned on and C_FLYappears in

parallel with the battery:

V_CFLY= V_BAT

(2)

Selecting high quality C_FLYcapacitors and proper switching

frequency are the key factors for a well performing capacitor

voltage divider. Switching frequency selection is a trade-off

between efficiency and capacitor size. Lower frequency

increases efficiency by reducing switching losses but requires

larger capacitance to maintain low output ripple and low

output impedance (R_EFF). An optimum switching frequency

can be found for any selected C_FLYcapacitor to minimize

losses.

Ignoring the small fluctuation of the capacitor and battery

voltages in period 1 and 2 in steady state operation, Equation

1 and 2 can be combined to calculate capacitor voltage:

V_CFLY= V_BAT= V_PMID/2

(3)

Ignoring small energy loss in each switching period, the input

and output cycle-average powers are equal. Therefore,

V_PMID× I_BUS= V_BAT× I_BAT

(4)

Bypass Mode

or

The SGM41600 is designed to operate in bypass mode when

I_BUS= I_BAT/2

(5)

V_BUSis close to the V_VOUT. When such valid voltage is present

I_BUS

I_BAT

C_FLY

V_PMID

on VBUS, the device enters bypass mode and all switches

between VBUS and VOUT are fully turned on while the other

switches are kept off. When V_BUSis near V_VOUT, the bypass

mode offers the best efficiency and the device is capable of

sourcing up to 5.6A (Maximum 4A continuous current is

recommended in this mode).

Q1

Q2

Q3

Q4

V_PMID

V_BAT

V_CFLY

Period 1

C_FLY

C_VOUT

V_BAT

I_BUS

I_BAT

C_FLY

V_PMID

V_BAT

V_CFLY

Period 2

The output voltage is close to the V_BUSminus a voltage drop

caused by the on-resistances of the RBFET plus the two

high-side switches of the two phases in parallel. So the REFF

in bypass mode is:

Figure 4. Voltage Divider Charger Operating Principle

Assuming no charge leakage path and considering R_EFFas

the effective input to output resistance (due to the switch

on-resistances and C_FLYlosses), the divider can be modeled

as shown in Figure 5. Using this model, the output voltage is

R_EFF(Bypass mode) ≈ (R_{DS _ QCH1}+ R_{DS _ QDH1})||(R_{DS _ QCH2}+ R_{DS _ QDH2}

)

(7)

where R_{DS_QXX}is the on-resistance of the switch xx.

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I²C Controlled Single-Cell 6A Switched-Capacitor

Fast Charger with Bypass Mode and ADC

SGM41600

DETAILED DESCRIPTION (continued)

Charge System

reaches the V_{BAT_REG}point, the SGM41600 provides feedback

to the adapter to reduce the current. This will eventually

The SGM41600 is a slave charger device and needs a host.

The host must set up all protection functions and disable the

main charger before enabling the SGM41600. The host must

monitor the nINT interrupts especially during high current

charging. It must also communicate with the wall adapter to

control the charge current.

reduce and ramp down the bus current below I_{BUS_UCP_F}

.

Startup Sequence

The SGM41600 is powered from the greater of VAC or VOUT

(VAC is used as sense input for adapter voltage as well). The

internal watchdog timer is enabled by default and if no I²C

read or write occurs before its expiry, the ADC_EN and

CHG_MODE bits are reset to their default values and after an

initial 8ms power-up time, an INT pulse is triggered to show

watchdog timeout. The host should not attempt to read or

write before this initial nINT signal.

Figure 6 shows the block diagram of a charge system using

the SGM41600 along with a PD controller and other devices.

In this system, the SGM41600 can allow each of the D+/D

lines to be controlled independently to output one of the

preset voltage levels (0V, 0.6V, 1.2V, 2.0V, 2.7V, 3.3V, and

Hi-Z). Each line can be set to one of these presets via I²C in

REG0x36. This allows the implementation of a handshaking

protocol between the charger and an adapter with an

interface that allows adjusting the voltage. Since the adapter

voltage is controllable, the operating point of the charger can

The device does not start charging after powered up,

because by default the charger is disabled. The ADC can be

enabled and the host can read the system parameters before

enabling charge. The charge can be enabled only if V_VBUS

>

V

_{BUS_PRESENT_R}and V_BATP> 2.8V.

be fine-tuned to ensure high efficiency during charging. When

the smart wall adapter is detected, the AP unit controls the

switching charger (SGM41516) that powers the load system

and the switched capacitor charger (SGM41600) that

provides high current charging. The communication between

those devices is via I²C serial interface.

Device Power-Up from Battery without

Input Source

To reduce the quiescent current and maximize the battery run

time when it is the only available source, the REGN LDO and

most of the sensing circuits are turned off, except

AC_PRESENT, BUS_INSERT and BAT_INSERT functions.

When the BUS_PDN_EN bit is set, the external OVPFET is

turned off, and VBUS pull-down R_{PD_VBUS}is activated to help

discharging VBUS after a hot-plug event. This will keep the

device in low quiescent current mode even after an input

source is plugged.

A typical charge profile for a high-capacity battery using

switching charger and switched capacitor charger together is

shown in Figure 7. During the trickle charge and pre-charge,

the charging is controlled by the switching charger. Once the

battery voltage reaches 3V, the adapter can negotiate for a

higher bus voltage and enable the SGM41600 for charging

(bypass or voltage divider mode). Once the battery voltage

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I²C Controlled Single-Cell 6A Switched-Capacitor

Fast Charger with Bypass Mode and ADC

SGM41600

DETAILED DESCRIPTION (continued)

CFH1

CFL1

OVPGATE VAC

Phase 1

VBUS

VOUT

PGND

DP

SGM41600

DM

SDA/

SCL

Phase 2

CFH2

CFL2

SGM41516

VBUS

SW

System

Battery

SDA/

SCL

SYS

BAT

Type C

Connector

GND

VBUS

+

Type C

Connector

VBUS

-

D+

D-

D+

D-

CC1

CC2

CC1

CC2

PD Controller

CC1

CC2

I²C BUS

AP

Smart Wall

Adaptor

Portable Device

Figure 6. Simplified Charge System

I_BUS(A)

V_BAT(V)

VBAT_REG

≥ 3V

IBUS_UCP_FALL

Pre-Charge Level

Time

Fast Charge

by SGM41516

Pre-charge by

SGM41516

Fast Charge

by SGM41600

Constant Voltage

by SGM41600

Constant Voltage

by SGM41516

Figure 7. SGM41600 System Charging Profile

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I²C Controlled Single-Cell 6A Switched-Capacitor

Fast Charger with Bypass Mode and ADC

SGM41600

DETAILED DESCRIPTION (continued)

Device Power-Up from Input Source

When an input source is plugged-in and the V_VBUS

ADC_CTRL register. Setting the ADC_EN bit to 1 enables the

ADC. This bit can be used to turn off the ADC and save power

when it is not needed. The ADC_RATE bit allows choosing

continuous conversion or 1-shot conversion mode. The ADC

operates independent of the faults, unless the host sets the

ADC_EN bit to 0.

>

V_{BUS_PRESENT_R}condition is valid, the host must initialize all

protections to the desired thresholds before enabling charge.

The protection thresholds that need to be set are AC_OVP,

VBUS_LO, VBUS_HI, BUS_OVP, IBUS_OCP, IBUS_UCP,

BAT_OVP, IBAT_OCP, VBAT_REG, IBAT_REG, and

VDRP_OVP. If one of the protection trigger conditions is met,

the charger stops switching. It will also turn off the external

OVPFET when AC_OVP or BUS_SC event occurs.

The ADC can operate if V_VBUS> V_{BUS_PRESENT_R}or V_BATP

>

2.8V condition is valid. Otherwise the ADC conversion is

postponed until one of them is satisfied. The ADC readings

are valid only for DC values and not for transients.

After setting protections, the VBUS voltage is checked to be

between 2 × V_{BUS_LO}× V_VOUTand 2 × V_{BUS_HI}× V_VOUTto allow

voltage divider mode operation, or between V_{BUS_LO}× V_VOUT

and V_{BUS_HI}× V_VOUTfor bypass mode operation. Charging is

enabled and current flows into the battery when the host sets

bypass or voltage divider mode by writing 001 or 010 in the

CHG_MODE[2:0] bits respectively. Then raising the VBUS

voltage will increase the battery charge current. When the

converter is on, any command to change the charge mode is

ignored. To do so, the charging must be disabled first, and

then the charge mode can be changed by I²C serial interface.

By default, all ADC channels are converted in continuous

conversion mode except the channels disabled by the

ADC_CTRL register. If the 1-shot conversion mode is

selected, the ADC_DONE_FLAG bit is set to 1 when all

channels are converted, then the ADC_EN bit is reset to 0. In

the continuous conversion mode, the ADC_DONE_FLAG bit

is set to 0.

nINT Pin, Flag and Mask Bits

The nINT pin is an open-drain output and must be pulled up

to a logic high rail. It is pulled low with a duration of t_INTto

notify the host when it is triggered by an event. See the

register map for all event flag and control bits.

REGN Management

The SGM41600 internal digital core is powered by the REGN

LDO. This LDO is enabled and powered by PMID. A 4.7µF or

lager capacitor is required on the REGN pin.

When an event occurs, a nINT signal is sent to the host and

the corresponding flag bit is set to 1. The flag bit can be reset

by read only after the fault is cleared. The nINT signal is not

re-sent if an event is still present after the flag bit is read,

unless another kind of event occurs. If an event mask bit is

set, that event will not send nINT signal, but the flag bit is still

updated independent of the mask bit.

ADC

The SGM41600 integrates a fast 5-channel, 12-bit ADC

converter to monitor input/output currents and voltages and

the temperature of the device. The ADC is controlled by the

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I²C Controlled Single-Cell 6A Switched-Capacitor

Fast Charger with Bypass Mode and ADC

SGM41600

DETAILED DESCRIPTION (continued)

Fault Event and Protection Status

Table 1 shows the protection features and corresponding

conditions of the device.

is sent to the OVPGATE output to turn on the external

OVPFET. If the V_VACreaches the V_{VAC_OVP}threshold for

t_{VAC_OVP_DEG}deglitch time, the gate voltage starts to drop.

Figure 8 shows the AC_OVP and OVPGATE operation

timings. The V_{VAC_OVP}threshold can be set by I²C serial

interface. The adapter voltage must never exceed the

absolute maximum rating of the VAC pin and the external

OVPFET.

VAC Over-Voltage Protection (AC_OVP)

The SGM41600 monitors the adapter voltage on the VAC pin

to control the external OVPFET using OVPGATE output. The

VAC over-voltage protection circuit is powered by VAC and is

enabled if V_VACrises above V_{VAC_PRESENT_R}. If V_VACis above

V_{VAC_PRESENT_R}for at least t_{VAC_IN_DEG}time, a 5V gate voltage

Table 1. Fault Event List

FAULT EVENT

CONDITIONS

PROTECTION ACTION

Turn off OVPFET and Q_RB, enable R_{PD_VBUS}, and reset

CHG_MODE[2:0] to 000

AC_OVP

V_VAC> V_{VAC_OVP}for t_{VAC_OVP_DEG}during AC_PRESENT interval

V_BUS< 2V during BUS_INSERT interval

or during OVPFET turn-on interval

or reverse I_QRB> 4A during switching

or V_VBUS< 1.9 × V_VOUTin divider mode

or V_VBUS< 0.95 × V_VOUTin bypass mode

CHG_MODE[2:0] ≠ 000 (Off Mode)

(disabled after switching for 100s)

CHG_MODE[2:0] ≠000 (Off Mode)

(disabled after switching for 100s)

Turn off OVPFET and Q_RB, and reset CHG_MODE[2:0] to

000

BUS_SC

VBUS_LO

VBUS_HI

Charging initiation suspended

BUS_OVP

IBUS_OCP

IBUS_UCP

V_VBUS> V_{BUS_OVP}for t_{VBUS_OVP_DEG}during BUS_INSERT interval Turn off Q_RBand reset CHG_MODE[2:0] to 000

CHG_MODE[2:0] ≠ 000 (Off Mode)

Turn off Q_RBand reset CHG_MODE[2:0] to 000

IBUS_UCP_TIMEOUT I_BUS< I_{BUS_UCP_R}after 100s timeout

BAT_OVP

IBAT_OCP

VOUT_SC

V_BAT> V_{BAT_OVP}for t_{VBAT_OVP_DEG}during BAT_INSERT interval Turn off Q_RBand reset CHG_MODE[2:0] to 000

CHG_MODE[2:0] ≠ 000 (Off Mode)

Turn off Q_RBand reset CHG_MODE[2:0] to 000

CHG_MODE[2:0] ≠ 000 (Off Mode)

CFLY_SC

CHG_MODE[2:0] = 010 (Voltage Divider Mode)

CHG_MODE[2:0] ≠ 000 (Off Mode)

CONV_OCP

VDRP_OVP

REG_TIMEOUT

TDIE_OTP

CHG_MODE[2:0] ≠ 000 (Off Mode)

CHG_MODE[2:0] ≠ 000 (Off Mode) or ADC_EN = 1

V(t)

V_{VAC_OVP}

V_OVPGATE

5V

V_VAC

V_{VAC_PRESENT_R}

V_{VAC_PRESENT_HYS}

t

t_{VAC_IN_DEG}

t_{VAC_OVP_DEG}

t_{VAC_IN_DEG}

Figure 8. AC_OVP and OVPGATE Operation Timings

SG Micro Corp

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15

I²C Controlled Single-Cell 6A Switched-Capacitor

Fast Charger with Bypass Mode and ADC

SGM41600

DETAILED DESCRIPTION (continued)

Input Short-Circuit Protection (BUS_SC)

The BUS_SC function monitors the VBUS pin for short-circuit.

This function is enabled if the external OVPFET is turned on

or if V_VBUSrises above V_{BUS_PRESENT_R}. If the V_VBUSfalls below

2V (BUS_SC event), the OVPFET is turned off, and charging

is stopped. CHG_MODE[2:0] bits are reset to 000 (disable).

Also, BUS_ABSENT_FLAG bit is set to 1, and an INT pulse is

asserted. The device will wait for 650ms before automatically

re-enabling and initiating startup sequence.

turned on and the IBUS_OCP function starts detecting the

input current. If the I_BUSreaches I_{BUS_OCP}threshold, the device

stops charging and resets CHG_MODE[2:0] bits to 000

(disable). The battery current is monitored by the voltage

across an external 5mΩ series shunt resistor. This differential

voltage is measured between BATN/SRP and SRN pins. If

I_{BAT_OCP}threshold is reached, the device stops charging and

resets CHG_MODE[2:0] bits to 000 (disable). The IBUS_OCP

and IBAT_OCP thresholds can be set by I²C serial interface.

Input Under-Current Protection (IBUS_UCP)

During charging, if V_VBUSis less than 1.9 × V_VOUTin divider

mode or 0.95 × V_VOUTin bypass mode, or if the Q_RBreverse

current rises above 4A, the Q_RBand OVPFET are turned off,

and charging is stopped. CHG_MODE[2:0] bits are reset to

000 (disable). Also, BUS_ABSENT_FLAG bit is set to 1, and

an INT pulse is asserted.

The IBUS_UCP function detects the input current via Q_RB

.

After charging is started, a 100s timer is enabled and I_BUS

current is compared with I_{BUS_UCP_R}(selected by the

IBUS_UCP bit). If I_BUScannot exceed I_{BUS_UCP_R}within the

100s period, the charging will be stopped and

CHG_MODE[2:0] bits are reset to 000 (disable). If I_BUS

exceeds I_{BUS_UCP_R}within the 100s period, the timer is

stopped and from then, if I_BUSfalls below the I_{BUS_UCP_F}

threshold, the charging will be stopped and CHG_MODE[2:0]

bits are reset to 000 (disable).

VBUS Charge Voltage Range (VBUS_LO and

VBUS_HI)

The VBUS_LO and VBUS_HI functions are included to avoid

problems due to wrong V_BUSsetting for charging. Under no

charge condition if V_VBUSis less than (V_VOUT× V_{BUS_LO}× 2) or

above (V_VOUT× V_{BUS_HI}× 2), the device remains in charge

initiation operation if the voltage divider mode is selected. If

VOUT Short-Circuit Protection (VOUT_SC)

The VOUT_SC function monitors the VOUT pin for

short-circuit. This function is enabled during charging. If V_VOUT

falls below V_VBUS/2.28 threshold when the voltage divider

mode is selected, the charger is turned off and

CHG_MODE[2:0] bits are reset to 000 (disable). Also, the

PIN_DIAG_FLAG bit is set to 1, and an INT pulse is

generated. When the bypass mode is selected, the threshold

is V_VBUS/1.14.

the bypass mode is selected, the range is from (V_VOUT

×

V_{BUS_LO}) to (V_VOUT× V_{BUS_HI}). Charging will start once V_BUSis

within the charge range. VBUS_LO and VBUS_HI functions

are enabled for maximum 100s at startup and are disabled if

I_BUSis above I_{BUS_UCP_R}during a period of 100s. The

VBUS_LO and VBUS_HI thresholds can be set by I²C serial

interface.

Input and Battery Over-Voltage Protections

(BUS_OVP and BAT_OVP)

CFLY Short-Circuit Protection (CFLY_SC)

The CFLY_SC function identifies the health of flying

capacitors before and during voltage divider switching

(charging). The device initialization process is started after

CHG_MODE[2:0] bits are set to 010. When V_BUSis in the

charge range, the flying capacitors (C_FLY) in both phases are

pre-charged. A CFLY short-circuit is detected if they cannot

be charged, and the voltage between V_CFHxand V_CFLx

remains below 2V. If so, the initialization process is stopped

and CHG_MODE[2:0] bits are reset to 000 (disable). Even if

C_FLYcapacitors pass the short-circuit test in the initialization

process, the CFLY_SC function remains active and whenever

a V_CFLYvoltage falls below 2V, the charger is turned off and

CHG_MODE[2:0] bits are reset to 000 (disable). The

PIN_DIAG_FLAG bit is set to 1 and an INT pulse is generated

as well. During a CFLY_SC event, other protection events

such as IBUS_OCP, BAT_OVP or CONV_OCP may occur.

The BUS_OVP and BAT_OVP functions detect input and

output charge voltage conditions. If either input or output

voltage is higher than the protection threshold, the charger is

turned off and CHG_MODE[2:0] bits are reset to 000 (disable).

The BUS_OVP function monitors VBUS pin voltage. The

BAT_OVP uses BATP and BATN/SRP remote sense pins to

monitor differential voltage between the battery terminals. To

minimize the risk of battery terminal short in the

manufacturing process, a series 100Ω resistor on the BATP

pin is required. The BUS_OVP and BAT_OVP thresholds can

be set by I²C serial interface.

Input and Battery Over-Current Protections

(IBUS_OCP and IBAT_OCP)

The IBUS_OCP function monitors the input current via Q_RB. If

CHG_MODE[2:0] bits are set to enable charge, the Q_RBis

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I²C Controlled Single-Cell 6A Switched-Capacitor

Fast Charger with Bypass Mode and ADC

SGM41600

DETAILED DESCRIPTION (continued)

A CFLY discharge circuit is activated before the internal

RBFET (Q_RB) is turned on if V_VBUS> V_{BUS_PRESENT_R}to prevent

over-current stress at the start of charging.

current and if the I_{BAT_REG}threshold is exceeded, the

OVPGATE voltage is controlled (reduced) to regulate the

charge current.

Converter Over-Current Protection (CONV_OCP)

The CONV_OCP function monitors the converter switch

operating currents. If the Q_CHxand Q_DLxcurrents reach switch

OCP threshold during voltage divider mode, the

CONV_OCP_FLAG bit is set to 1, an INT pulse is generated,

the charging is stopped, and CHG_MODE[2:0] bits are reset

to 000 (disable).

If one of the regulation functions is triggered and persist for

650ms when REG_TIMEOUT_DIS bit is set to 0, the charging

will be stopped and CHG_MODE[2:0] bits are reset to 000

(disable). The system should adjust the charging conditions

to prevent the battery voltage and current regulation for more

than 650ms (or prevent triggering of the VDRP_OVP).

Dropout Over-Voltage Protection (VDRP_OVP)

When VBAT_REG or IBAT_REG is active, a large voltage

drop may appear on the external OVPFET and cause

excessive power loss and heat. To avoid that, the

VDRP_OVP function monitors the voltage drop between VAC

and VBUS pins. If it is higher than V_{DRP_OVP}threshold for

t_{DRP_OVP_DEG}deglitch time (set by VDRP_OVP_DEG bit in

REG0x05), the charging will be stopped and CHG_MODE[2:0]

bits are reset to 000 (disable). The V_{DRP_OVP}threshold and

t_{DRP_OVP_DEG}deglitch time can be programmed by I²C serial

interface.

Battery Voltage and Current Regulation

(VBAT_REG and IBAT_REG)

The SGM41600 has VBAT_REG and IBAT_REG regulation

functions to regulate the battery voltage and current for a

short period before the system can re-adjust the conditions

such that these functions can be disabled. The regulation

thresholds can be set by I²C serial interface.

The VBAT_REG function monitors the differential voltage

between BATP and BATN/SRP pins and if the battery voltage

is above the V_{BAT_REG}threshold, the OVPGATE voltage is

controlled to regulate the battery voltage.

Die Over-Temperature Protection (TDIE_OTP)

The

TDIE_OTP

function

prevents

charging

in

The VBAT_REG_FLAG bit is also set to 1, and an INT pulse

is generated. Then the host can negotiate with the adapter to

reduce the current. This will gradually reduce the current until

the bus current falls to the I_{BUS_UCP_F}and charging will end.

over-temperature condition. The die temperature is monitored

and if the +150℃ threshold is reached, the charging is

stopped and CHG_MODE[2:0] bits are reset to 000 (disable).

An automatic startup sequence can initiate if the die

temperature falls below +130℃.

Similarly, the IBAT_REG function monitors the differential

voltage between BATN/SRP and SRN pins to find the battery

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MARCH 2023

17

I²C Controlled Single-Cell 6A Switched-Capacitor

Fast Charger with Bypass Mode and ADC

SGM41600

REGISTER MAP

All registers are 8-bit and individual bits are named from D[0] (LSB) to D[7] (MSB).

I²C Slave Address of SGM41600 is: 0x6F (0b1101111 + W/R)

THRESHOLD

SETTING

FUNCTION

FLAG

MASK

ENABLE

DEGLITCH

REG_RST

CHG_MODE

WD_TIMEOUT

FSW_SET

—

0x00[7]

—

0x00[6:4]

0x00[2:0]

0x01[7:5]

0x01[4:3]

0x0F[5]

—

0x10[5]

—

0x00[3]

—

FSW_SHIFT

—

PIN_DIAG

(CFLY_SC and VOUT_SC)

0x0F[0]

0x10[0]

--

0x02[7]

—

VBUS_LO

VBUS_HI

0x0D[2]

0x0D[1]

0x0F[3]

—

0x0E[2]

0x0E[1]

0x10[3]

—

0x02[3:2]

0x02[5]

0x02[4]

—

0x02[1:0]

BUS_SC and BUS_ABSENT

DEVICE_REV

DEVICE_ID

0x01[0]

—

0x03[7:4]

—

0x03[3:0]

—

AC_OVP

0x0B[7]

0x0B[6]

0x0B[5]

0x0B[4]

0x0B[3]

0x0B[2]

0x0B[1]

0x0B[0]

0x0F[2]

0x0D[7]

0x0D[6]

0x0D[5]

0x0D[4]

—

0x0C[7]

0x0C[6]

0x0C[5]

0x0C[4]

0x0C[3]

0x0C[2]

0x0C[1]

0x0C[0]

0x10[2]

0x0E[7]

0x0E[6]

0x0E[5]

0x0E[4]

—

0x04[3:0]

0x04[4]

0x05[7]

0x05[6]

0x05[5]

0x06[7]

0x07[5]

0x07[7]

—

AC_PDN

—

BUS_PDN

—

VDRP_OVP

BUS_OVP

0x05[2:0]

0x05[4]

—

0x06[6:0]

IBUS_OCP

0x07[4:0]

—

IBUS_UCP_RISE

IBUS_UCP_FALL

IBUS_UCP_TIMEOUT

BAT_OVP

0x07[6]

—

0x07[6]

—

0x08[5:0]

0x08[7]

0x09[7]

0x0A[2]

0x0A[5]

0x0A[6]

—

IBAT_OCP

0x09[5:0]

—

VBAT_REG

IBAT_REG

0x0A[1:0]

—

0x0A[4:3]

—

REG_TIMEOUT

TDIE_OTP

—

0x0D[3]

0x0D[0]

0x0F[7]

0x0F[6]

0x0F[4]

0x0F[1]

—

0x0E[3]

0x0E[0]

0x10[7]

0x10[6]

0x10[4]

0x10[1]

—

CONV_OCP

BUS_INSERT

BAT_INSERT

AC_ABSENT

ADC_DONE

ADC_EN

0x01[1]

—

0x11[7]

—

ADC_RATE

VBUS_ADC

IBUS_ADC

—

0x11[6]

—

0x12[3:0] + 0x13[7:0]

0x14[3:0] + 0x15[7:0]

0x16[3:0] + 0x17[7:0]

0x18[3:0] + 0x19[7:0]

0x1A[7:0]

0x11[5]

0x11[4]

0x11[3]

0x11[2]

0x11[1]

—

VBAT_ADC

IBAT_ADC

—

TDIE_ADC

—

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MARCH 2023

18

I²C Controlled Single-Cell 6A Switched-Capacitor

Fast Charger with Bypass Mode and ADC

SGM41600

REGISTER MAP (continued)

Bit Types:

R:

Read only

R/W:

RC:

Read/Write

Read clears the bit

R/WC: Read/Write. Writing a ‘1’ clears the bit. Writing a ‘0’ has no effect.

REG0x00: CONTROL1 Register Address [reset = 0x00]

BITS

BIT NAME

DEFAULT

TYPE

DESCRIPTION

RESET BY

Register Reset

D[7]

REG_RST

0

R/W

0 = No register reset (default)

1 = Reset all registers to their default values

Charge Mode Control

000 = Off mode (default)

001 = Forward bypass mode

010 = Forward charge-pump voltage divider mode

011 ~ 111 = Off mode

Note: These bits are not allowed to change during charging.

Watchdog Enable

0 = Watchdog enabled (default)

1 = Watchdog disabled

Watchdog Timer Setting

000 = 0.5s (default)

REG_RST

REG_RST,

Watchdog or

many other

events

D[6:4]

D[3]

CHG_MODE[2:0]

WDT_DIS

000

0

R/W

REG_RST

001 = 1s

010 = 2s

D[2:0]

WDT_TIMER[2:0]

000

R/W

011 = 5s

REG_RST

100 = 10s

101 = 20s

110 = 40s

111 = 80s

REG0x01: CONTROL2 Register Address [reset = 0x42]

BITS

BIT NAME

DEFAULT

TYPE

DESCRIPTION

RESET BY

Voltage Divider Switching Frequency Setting

000 = 200kHz

001 = 375kHz

010 = 500kHz (default)

011 = 750kHz

D[7:5]

FSW_SET[2:0]

010

R/W

NA

100 = 1000kHz

101 = 1250kHz

110 ~ 111 = 1500kHz

Trimming Bits for Switching Frequency

(for EMI frequency spectrum shifting)

00/11 = Nominal frequency (default)

01 = Nominal frequency + 10%

10 = Nominal frequency - 10%

D[4:3]

FSW_SHIFT[1:0]

00

R/W

REG_RST

D[2]

D[1]

Reserved

0

1

R

Reserved

NA

CONV OCP Threshold Setting Bit

0 = 7.3A

CONV_OCP

R/W

1 = 5.6A (default)

Setting Bit of VBUS Short-Circuit Trigger Mode during Switching

0 = Triggered by Q_RB4A reverse current (default)

1 = Triggered by V_VBUS/V_OUTscale factor, 1.9 in voltage divider

mode while 0.95 in bypass mode

D[0]

BUS_SC_TRG

0

R/W

NA

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MARCH 2023

19

I²C Controlled Single-Cell 6A Switched-Capacitor

Fast Charger with Bypass Mode and ADC

SGM41600

REGISTER MAP (continued)

REG0x02: CONTROL3 Register Address [reset = 0xBC]

BITS

D[7]

D[6]

D[5]

BIT NAME

PIN_DIAG_EN

Reserved

DEFAULT

TYPE

R/W

R

DESCRIPTION

RESET BY

REG_RST

NA

Pin Diagnosis Enable

0 = Disabled

1 = Enabled (default)

1

0

1

Reserved

Low VBUS Error Detection Enable

0 = Disabled

VBUS_LO_EN

R/W

REG_RST

1 = Enabled (default)

High VBUS Error Detection Enable

0 = Disabled

1 = Enabled (default)

Low VBUS Error Range Scale Setting

00 = 1.01

D[4]

VBUS_HI_EN

VBUS_LO[1:0]

1

R/W

REG_RST

NA

D[3:2]

11

01 = 1.02

10 = 1.03

11 = 1.04 (default)

High VBUS Error Range Scale Setting

00 = 1.10 (default)

01 = 1.15

D[1:0]

VBUS_HI[1:0]

00

R/W

NA

10 = 1.20

11 = 1.25

REG0x03: DEVICE_INFO Register Address [reset = 0x08]

BITS

BIT NAME

DEFAULT

TYPE

DESCRIPTION

RESET BY

D[7:4]

DEVICE_REV[3:0]

0000

R

Device Revision

NA

Device ID

1000 = SGM41600

D[3:0]

DEVICE_ID[3:0]

1000

R

NA

REG0x04: AC_OVP Register Address [reset = 0x18]

BITS

BIT NAME

DEFAULT

TYPE

DESCRIPTION

RESET BY

D[7:5]

Reserved

000

R

Reserved

NA

VAC OVP Enable

0 = Disabled

1 = Enabled (default)

D[4]

AC_OVP_EN

AC_OVP[3:0]

1

R/W

REG_RST

VAC OVP Rising Threshold Setting

VAC OVP Rising Threshold Value: = 4V + AC_OVP[3:0] × 1V

Offset: 4V

D[3:0]

1000

Range: 4V (0000) - 19V (1111)

Default: 12V (1000)

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MARCH 2023

20

I²C Controlled Single-Cell 6A Switched-Capacitor

Fast Charger with Bypass Mode and ADC

SGM41600

REGISTER MAP (continued)

REG0x05: Pull-Down & VDRP_OVP Register Address [reset = 0x25]

BITS

BIT NAME

DEFAULT

TYPE

DESCRIPTION

VAC Pull-Down Resistor Enable

RESET BY

0 = Disabled (default)

D[7]

AC_PDN_EN

0

R/W

1 = Enabled

NA

When enabled, the VAC is pulled down for 400ms and then this

bit is automatically reset to 0.

VBUS Pull-Down Resistor Enable

0 = Disabled (default)

1 = Enabled

D[6]

D[5]

BUS_PDN_EN

0

1

R/W

REG_RST

Enabling this bit will turn off the external OVPFET and discharge

VBUS with R_{PD_VBUS}. This action is important during a hot-plug

event to prevent transient over-voltages.

VDRP OVP Enable (V_DRP= V_VAC- V_VBUS

0 = Disabled

)

VDRP_OVP_EN

1 = Enabled (default)

VDRP OVP Deglitch Time Setting

0 = 10µs (default)

D[4]

D[3]

VDRP_OVP_DEG

Reserved

0

R/W

R

1 = 5ms

REG_RST

NA

This is deglitch time (t_{DRP_OVP_DEG}) between the moment V_DRP

exceeds V_{DRP_OVP}threshold and triggering of the protection action.

Reserved

VDRP OVP Threshold Setting

VDRP OVP Threshold Value: = 50mV + VDRP_OVP[2:0] × 50mV

Offset: 50mV

D[2:0]

VDRP_OVP[2:0]

101

R/W

NA

Range: 50mV (000) - 400mV (111)

Default: 300mV (101)

REG0x06: BUS_OVP Register Address [reset = 0xCB]

BITS

BIT NAME

DEFAULT

TYPE

DESCRIPTION

RESET BY

VBUS OVP Enable

0 = Disabled

D[7]

BUS_OVP_EN

1

R/W

REG_RST

1 = Enabled (default)

VBUS OVP Rising Threshold Setting

VBUS OVP Rising Threshold Value: = 4V + BUS_OVP[6:0] × 100mV

Offset: 4V

D[6:0]

BUS_OVP[6:0]

1001011

R/W

REG_RST

Range: 4V (0000000) - 14V (1100100)

Default: 11.5V (1001011)

If BUS_OVP[6:0] ≥ 1100100, V_{BUS_OVP}= 14V

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MARCH 2023

21

I²C Controlled Single-Cell 6A Switched-Capacitor

Fast Charger with Bypass Mode and ADC

SGM41600

REGISTER MAP (continued)

REG0x07: IBUS_OCP and IBUS_UCP Register Address [reset = 0xB9]

BITS

BIT NAME

DEFAULT

TYPE

DESCRIPTION

RESET BY

IBUS UCP Enable

0 = Disabled

D[7]

IBUS_UCP_EN

1

R/W

REG_RST

1 = Enabled (default)

IBUS UCP Threshold Setting

0 = I_{BUS_UCP_R}= 300mA rising, I_{BUS_UCP_F}= 150mA falling (default)

1 = I_{BUS_UCP_R}= 500mA rising, I_{BUS_UCP_F}= 250mA falling

The system should control the I_BUScurrent to rise to I_{BUS_UCP_R}

within 100s.

This bit can only be changed before enabling switching.

IBUS OCP Enable

D[6]

D[5]

IBUS_UCP

0

1

R/W

NA

IBUS_OCP_EN

0 = Disabled

REG_RST

1 = Enabled (default)

IBUS OCP Threshold Setting

Voltage Divider Mode:

I

_{BUS_OCP}= 0.5A + IBUS_OCP[4:0] × 100mA

Offset: 0.5A

Range: 0.5A (00000) - 3.6A (11111)

Default: 3A (11001)

D[4:0]

IBUS_OCP[4:0]

11001

R/W

REG_RST

Bypass Mode:

I

_{BUS_OCP}= 2.5A + IBUS_OCP[4:0] × 100mA

Offset: 2.5A

Range: 2.5A (00000) - 5.6A (11111)

Default: 5A (11001)

REG0x08: BAT_OVP Register Address [reset = 0x8E]

BITS

D[7]

D[6]

BIT NAME

BAT_OVP_EN

Reserved

DEFAULT

TYPE

R/W

R

DESCRIPTION

RESET BY

REG_RST

NA

VBAT OVP Enable

0 = Disabled

1 = Enabled (default)

1

0

Reserved

VBAT OVP Rising Threshold Setting

VBAT OVP Rising Threshold Value: = 4V + BAT_OVP[5:0] × 25mV

Offset: 4V

D[5:0]

BAT_OVP[5:0]

001110

R/W

REG_RST

Range: 4V (000000) - 5V (101000)

Default: 4.35V (001110)

When BAT_OVP[5:0] ≥ 101000, V_{BAT_OVP}= 5V

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MARCH 2023

22

I²C Controlled Single-Cell 6A Switched-Capacitor

Fast Charger with Bypass Mode and ADC

SGM41600

REGISTER MAP (continued)

REG0x09: IBAT_OCP Register Address [reset = 0xB4]

BITS

D[7]

D[6]

BIT NAME

IBAT_OCP_EN

Reserved

DEFAULT

TYPE

R/W

R

DESCRIPTION

RESET BY

REG_RST

NA

IBAT OCP Enable

0 = Disabled

1 = Enabled (default)

1

0

Reserved

IBAT OCP Threshold Setting

IBAT OCP Threshold Value: = 2A + IBAT_OCP[5:0] × 100mA

Offset: 2A

D[5:0]

IBAT_OCP[5:0]

110100

R/W

REG_RST

Range: 2A (000000) to 7.2A (110100)

Default: 7.2A (110100)

When IBAT_OCP[5:0] ≥ 110100, I_{BAT_OCP}= 7.2A

REG0x0A: Regulation Register Address [reset = 0x24]

BITS

BIT NAME

DEFAULT

TYPE

DESCRIPTION

RESET BY

D[7]

Reserved

0

R

Reserved

NA

Regulation Timeout Disable

0 = Enabled (default)

1 = Disabled.

If the regulation lasts longer than 650ms, charging will be disabled.

IBAT Regulation Enable

0 = Disabled

1 = Enabled (default)

D[6]

D[5]

REG_TIMEOUT_DIS

IBAT_REG_EN

0

1

R/W

NA

During regulation, t_{IBAT_OCP_DEG}is increased to 500µs to avoid

unwanted triggering of IBAT_OCP

IBAT Regulation Threshold Setting

00 = 200mA below IBAT_OCP[5:0] threshold setting (default)

01 = 300mA below IBAT_OCP[5:0] threshold setting

10 = 400mA below IBAT_OCP[5:0] threshold setting

11 = 500mA below IBAT_OCP[5:0] threshold setting

The margin below IBAT_OCP[5:0] threshold at which IBAT

regulation starts.

VBAT Regulation Enable

0 = Disabled

1 = Enabled (default)

During regulation, t_{VBAT_OVP_DEG}is increased to 500µs to avoid

unwanted triggering of VBAT OVP

VBAT Regulation Threshold Setting

00 = 50mV below BAT_OVP[5:0] threshold setting (default)

01 = 100mV below BAT_OVP[5:0] threshold setting

10 = 150mV below BAT_OVP[5:0] threshold setting

11 = 200mV below BAT_OVP[5:0] threshold setting

The margin below BAT_OVP[5:0] threshold at which VBAT

regulation starts.

D[4:3]

D[2]

IBAT_REG[1:0]

VBAT_REG_EN

VBAT_REG[1:0]

00

1

R/W

NA

D[1:0]

00

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MARCH 2023

23

I²C Controlled Single-Cell 6A Switched-Capacitor

Fast Charger with Bypass Mode and ADC

SGM41600

REGISTER MAP (continued)

REG0x0B: FLT_FLAG1 Register Address [reset = 0x00]

BITS

BIT NAME

DEFAULT

TYPE

DESCRIPTION

RESET BY

VAC OVP Fault Flag

0 = No VAC OVP fault

D[7]

AC_OVP_FLAG

0

RC

1 = VAC OVP fault has occurred

NA

It generates an interrupt on nINT pin if unmasked. After the VAC

OVP fault is cleared, a read on this bit will reset it to 0.

VAC Pull-Down Event Flag

0 = No VAC pull-down event

D[6]

D[5]

D[4]

D[3]

D[2]

D[1]

D[0]

AC_PDN_FLAG

BUS_PDN_FLAG

VDRP_OVP_FLAG

BUS_OVP_FLAG

IBUS_OCP_FLAG

0

RC

1 = VAC pull-down event has occurred

It generates an interrupt on nINT pin if unmasked. After the VAC

pull-down event is cleared, a read on this bit will reset it to 0.

VBUS Pull-Down Event Flag

NA

0 = No VBUS pull-down event

1 = VBUS pull-down event has occurred

It generates an interrupt on nINT pin if unmasked. After the VBUS

pull-down event is cleared, a read on this bit will reset it to 0.

VDRP OVP Fault Flag

0 = No VDRP OVP fault

1 = VDRP OVP fault has occurred

It generates an interrupt on nINT pin if unmasked. Read this bit

to reset it to 0.

VBUS OVP Fault Flag

0 = No VBUS OVP fault

1 = VBUS OVP fault has occurred

It generates an interrupt on nINT pin if unmasked. After the VBUS

OVP fault is cleared, a read on this bit will reset it to 0.

IBUS OCP Fault Flag

0 = No IBUS OCP fault

1 = IBUS OCP fault has occurred

It generates an interrupt on nINT pin if unmasked. Read this bit

to reset it to 0.

IBUS_UCP_RISE Event Flag

REG_RST

NA

0 = No IBUS_UCP_RISE event

IBUS_UCP_RISE_

FLAG

1 = IBUS_UCP_RISE event has occurred

It generates an interrupt on nINT pin if unmasked. Read this bit

to reset it to 0.

IBUS_UCP_FALL Event Flag

0 = No IBUS_UCP_FALL event

1 = IBUS_UCP_FALL event has occurred

It generates an interrupt on nINT pin if unmasked. Read this bit

to reset it to 0.

REG_RST

IBUS_UCP_FALL_

FLAG

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24

I²C Controlled Single-Cell 6A Switched-Capacitor

Fast Charger with Bypass Mode and ADC

SGM41600

REGISTER MAP (continued)

REG0x0C: FLT_INT_MASK1 Register Address [reset = 0x00]

BITS

BIT NAME

DEFAULT

TYPE

DESCRIPTION

Mask VAC OVP Fault Interrupt

RESET BY

0 = VAC OVP fault interrupt can work (default)

1 = Mask VAC OVP fault interrupt

D[7]

AC_OVP_MASK

0

R/W

REG_RST

AC_OVP_FLAG bit is set after the event, but the interrupt signal

is not generated.

Mask VAC Pull-Down Event Interrupt

0 = VAC pull-down event interrupt can work (default)

1 = Mask VAC pull-down event interrupt

AC_PDN_FLAG bit is set after the event, but the interrupt signal

is not generated.

Mask VBUS Pull-Down Event Interrupt

0 = VBUS pull-down event interrupt can work (default)

1 = Mask VBUS pull-down event interrupt

BUS_PDN_FLAG bit is set after the event, but the interrupt

signal is not generated.

Mask VDRP OVP Fault Interrupt

0 = VDRP OVP fault interrupt can work (default)

1 = Mask VDRP OVP fault interrupt

VDRP_OVP_FLAG bit is set after the event, but the interrupt

signal is not generated.

Mask BUS OVP Fault Interrupt

0 = BUS OVP fault interrupt can work (default)

1 = Mask BUS OVP fault interrupt

BUS_OVP_FLAG bit is set after the event, but the interrupt

signal is not generated.

Mask IBUS OCP Fault Interrupt

0 = IBUS OCP fault interrupt can work (default)

1 = Mask IBUS OCP fault interrupt

D[6]

D[5]

D[4]

D[3]

D[2]

D[1]

D[0]

AC_PDN_MASK

BUS_PDN_MASK

VDRP_OVP_MASK

BUS_OVP_MASK

IBUS_OCP_MASK

0

R/W

REG_RST

IBUS_OCP_FLAG bit is set after the event, but the interrupt

signal is not generated.

Mask IBUS_UCP_RISE Event Interrupt

0 = IBUS_UCP_RISE event interrupt can work (default)

1 = Mask IBUS_UCP_RISE event interrupt

IBUS_UCP_RISE_FLAG bit is set after the event, but the

interrupt signal is not generated.

Mask IBUS_UCP_FALL Event Interrupt

0 = IBUS_UCP_FALL event interrupt can work (default)

1 = Mask IBUS_UCP_FALL event interrupt

IBUS_UCP_FALL_FLAG bit is set after the event, but the

interrupt signal is not generated.

IBUS_UCP_RISE_

MASK

IBUS_UCP_FALL_

MASK

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MARCH 2023

25

I²C Controlled Single-Cell 6A Switched-Capacitor

Fast Charger with Bypass Mode and ADC

SGM41600

REGISTER MAP (continued)

REG0x0D: FLT_FLAG2 Register Address [reset = 0x00]

BITS

BIT NAME

DEFAULT

TYPE

DESCRIPTION

RESET BY

VBAT OVP Fault Flag

0 = No VBAT OVP fault

D[7]

BAT_OVP_FLAG

0

RC

1 = VBAT OVP fault has occurred

NA

It generates an interrupt on nINT pin if unmasked. After the

VBAT OVP fault is cleared, reading this bit will reset it to 0.

IBAT OCP Fault Flag

0 = No IBAT OCP fault

D[6]

D[5]

D[4]

D[3]

IBAT_OCP_FLAG

VBAT_REG_FLAG

IBAT_REG_FLAG

TDIE_OTP_FLAG

0

RC

1 = IBAT OCP fault has occurred

It generates an interrupt on nINT pin if unmasked. Read this bit

to reset it to 0.

VBAT Regulation Event Flag

0 = No VBAT regulation event

1 = VBAT regulation event has occurred

It generates an interrupt on nINT pin if unmasked. After the

VBAT regulation event is cleared, reading this bit will reset it to 0.

IBAT Regulation Event Flag

NA

0 = No IBAT regulation event

1 = IBAT regulation event has occurred

It generates an interrupt on nINT pin if unmasked. After the IBAT

regulation event is cleared, reading this bit will reset it to 0.

TDIE OTP Fault Flag (Die Over-Temperature)

0 = No TDIE OTP fault

1 = TDIE OTP fault has occurred

It generates an interrupt on nINT pin if unmasked. After the TDIE

OTP fault is cleared, reading this bit will reset it to 0.

VBUS_LO Fault Flag Bit (VBUS under-voltage)

It is set to 1 if V_VBUS/V_VOUT< 2 × V_{BUS_LO}in voltage divider mode,

or V_VBUS/V_VOUT< V_{BUS_LO}in bypass mode.

0 = No VBUS_LO fault

D[2]

D[1]

VBUS_LO_FLAG

VBUS_HI_FLAG

0

RC

NA

1 = VBUS_LO fault has occurred

It generates an interrupt on nINT pin if unmasked. After the

VBUS_LO fault is cleared, reading this bit will reset it to 0.

VBUS_HI Fault Flag Bit (VBUS over-voltage)

It is set to 1 if V_VBUS/V_VOUT> 2 × V_{BUS_HI}in voltage divider mode,

or V_VBUS/V_VOUT> V_{BUS_HI}in bypass mode.

0 = No VBUS_HI fault

1 = VBUS_HI fault has occurred

It generates an interrupt on nINT pin if unmasked. After the

VBUS_HI fault is cleared, reading this bit will reset it to 0.

CONV OCP Fault Flag

(Converter over-current during voltage divider mode)

It is set to 1 if the internal switching FETs, Q_CHxand Q_DLxreach

switch OCP threshold successively.

D[0]

CONV_OCP_FLAG

0

RC

NA

0 = No CONV OCP fault

1 = CONV OCP fault has occurred

It generates an interrupt on nINT pin if unmasked. Read this bit

to reset it to 0.

SG Micro Corp

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MARCH 2023

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I²C Controlled Single-Cell 6A Switched-Capacitor

Fast Charger with Bypass Mode and ADC

SGM41600

REGISTER MAP (continued)

REG0x0E: FLT_INT_MASK2 Register Address [reset = 0x00]

BITS

BIT NAME

DEFAULT

TYPE

DESCRIPTION

Mask VBAT OVP Fault Interrupt

RESET BY

0 = VBAT OVP fault interrupt can work (default)

1 = Mask VBAT OVP fault interrupt

D[7]

BAT_OVP_MASK

0

R/W

REG_RST

BAT_OVP_FLAG bit is set after the event, but the interrupt

signal is not generated.

Mask IBAT OCP Fault Interrupt

0 = IBAT OCP fault interrupt can work (default)

1 = Mask IBAT OCP fault interrupt

IBAT_OCP_FLAG bit is set after the event, but the interrupt

signal is not generated.

D[6]

D[5]

D[4]

D[3]

D[2]

D[1]

D[0]

IBAT_OCP_MASK

VBAT_REG_MASK

IBAT_REG_MASK

TDIE_OTP_MASK

VBUS_LO_MASK

VBUS_HI_MASK

CONV_OCP_MASK

0

R/W

REG_RST

Mask VBAT Regulation Event Interrupt

0 = VBAT regulation event interrupt can work (default)

1 = Mask VBAT regulation event interrupt.

VBAT_REG_FLAG bit is set after the event, but the interrupt

signal is not generated.

Mask IBAT Regulation Event Interrupt

0 = IBAT regulation event interrupt can work (default)

1 = Mask IBAT regulation event interrupt

IBAT_REG_FLAG bit is set after the event, but the interrupt

signal is not generated.

Mask TDIE OTP Fault Interrupt

0 = TDIE OTP fault interrupt can work (default)

1 = Mask TDIE OTP fault interrupt

TDIE_OTP_FLAG bit is set after the event, but the interrupt

signal is not generated.

Mask VBUS_LO Fault Interrupt

0 = VBUS_LO fault interrupt can work (default)

1 = Mask VBUS_LO fault interrupt

VBUS_LO_FLAG bit is set after the event, but the interrupt

signal is not generated.

Mask VBUS_HI Fault Interrupt

0 = VBUS_HI fault interrupt can work (default)

1 = Mask VBUS_HI fault interrupt

VBUS_HI_FLAG bit is set after the event, but the interrupt signal

is not generated.

Mask CONV OCP Fault Interrupt

0 = CONV OCP fault interrupt can work (default)

1 = Mask CONV OCP fault interrupt

CONV_OCP_FLAG bit is set after the event, but the interrupt

signal is not generated.

SG Micro Corp

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MARCH 2023

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I²C Controlled Single-Cell 6A Switched-Capacitor

Fast Charger with Bypass Mode and ADC

SGM41600

REGISTER MAP (continued)

REG0x0F: FLT_FLAG3 Register Address [reset = 0x00]

BITS

BIT NAME

DEFAULT

TYPE

DESCRIPTION

VBUS Insert Event Flag

RESET BY

This bit is set to 1 if V_VBUS> V_{BUS_PRESENT_R}

.

0 = No VBUS insert event

1 = VBUS insert event has occurred

D[7]

BUS_INSERT_FLAG

0

RC

NA

It generates an interrupt on nINT pin if unmasked. Read this

bit to reset it to 0.

VBAT Insert Event Flag

If ADC_EN bit = 1 or V_VAC> V_{VAC_PRESENT_R}or V_VBUS

V_{BUS_PRESENT_R}, this bit will set to 1 when V_BATP> 2.8V.

0 = No VBAT insert event

>

D[6]

BAT_INSERT_FLAG

0

RC

NA

1 = VBAT insert event has occurred

It generates an interrupt on nINT pin if unmasked. Read this

bit to reset it to 0.

Watchdog Timeout Fault Flag

0 = No watchdog timeout fault

D[5]

D[4]

WD_TIMEOUT_FLAG

AC_ABSENT_FLAG

0

RC

1 = Watchdog timeout fault has occurred

It generates an interrupt on nINT pin if unmasked. Read this

bit to reset it to 0.

REG_RST

VAC Absent Fault Flag

This bit is set to 1 if V_VAC< V_{VAC_PRESENT_R}- V_{VAC_PRESENT_HYS}

.

0 = No VAC absent fault

1 = VAC absent fault has occurred

NA

It generates an interrupt on nINT pin if unmasked. Read this

bit to reset it to 0.

VBUS Absent Fault Flag

It is set to 1 if V_VBUS< V_{BUS_PRESENT_R}- V_{BUS_PRESENT_HYS}

.

0 = No VBUS absent fault

1 = VBUS absent fault has occurred.

It generates an interrupt on nINT pin if unmasked. Read this

bit to reset it to 0.

IBUS UCP Timeout Fault Flag

D[3]

D[2]

BUS_ABSENT_FLAG

0

RC

NA

0 = No IBUS UCP timeout fault

IBUS_UCP_TIMEOUT_

FLAG

1 = IBUS UCP timeout fault has occurred

It generates an interrupt on nINT pin if unmasked. Read this

bit to reset it to 0.

ADC Conversion Complete Flag

In 1-shot conversion mode, this bit is set to 1 after ADC

conversion of all enabled channels is complete.

0 = Normal

1 = ADC conversion complete.

It generates an interrupt on nINT pin if unmasked. Read this

bit to reset it to 0.

D[1]

D[0]

ADC_DONE_FLAG

PIN_DIAG_FLAG

0

RC

NA

Pin Diagnosis Fail Flag

When charging is enabled, some conditions are checked on

the C_FLYand VOUT to assure proper operation.

0 = Normal

REG_RST

1 = C_FLYor VOUT short fault has occurred

It generates an interrupt on nINT pin if unmasked. Read this

bit to reset it to 0.

SG Micro Corp

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I²C Controlled Single-Cell 6A Switched-Capacitor

Fast Charger with Bypass Mode and ADC

SGM41600

REGISTER MAP (continued)

REG0x10: FLT_INT_MASK3 Register Address [reset = 0x00]

BITS

BIT NAME

DEFAULT

TYPE

DESCRIPTION

Mask VBUS Insert Event Interrupt

RESET BY

0 = VBUS insert event interrupt can work (default)

1 = Mask VBUS insert event interrupt

D[7]

BUS_INSERT_MASK

0

R/W

REG_RST

BUS_INSERT_FLAG bit is set after the event, but the interrupt

signal is not generated.

Mask VBAT Insert Event Interrupt

0 = VBAT insert event interrupt can work (default)

1 = Mask VBAT insert event interrupt

BAT_INSERT_FLAG bit is set after the event, but the interrupt

signal is not generated.

D[6]

D[5]

D[4]

D[3]

D[2]

D[1]

D[0]

BAT_INSERT_MASK

WD_TIMEOUT_MASK

AC_ABSENT_MASK

BUS_ABSENT_MASK

0

R/W

REG_RST

Mask Watchdog Timeout Fault Interrupt

0 = watchdog timeout fault interrupt can work (default)

1 = Mask watchdog timeout fault interrupt

WD_TIMEOUT_FLAG bit is set after the event, but the

interrupt signal is not generated.

Mask VAC Absent Fault Interrupt

0 = VAC absent fault interrupt can work (default)

1 = Mask VAC absent fault interrupt

AC_ABSENT_FLAG bit is set after the event, but the interrupt

signal is not generated.

Mask VBUS Absent Fault Interrupt

0 = VBUS absent fault interrupt can work (default)

1 = Mask VBUS absent fault interrupt

BUS_ABSENT_FLAG bit is set after the event, but the

interrupt signal is not generated.

Mask IBUS UCP Timeout Fault Interrupt

0 = IBUS UCP timeout fault interrupt can work (default)

1 = Mask IBUS UCP timeout fault interrupt

IBUS_UCP_TIMEOUT_FLAG bit is set after the event, but the

interrupt signal is not generated.

Mask ADC Conversion Complete Event Interrupt

0 = ADC conversion complete event interrupt can work (default)

1 = Mask ADC conversion complete event interrupt

ADC_DONE_FLAG bit is set after the event, but the interrupt

signal is not generated.

IBUS_UCP_TIMEOUT_

MASK

ADC_DONE_MASK

PIN_DIAG_MASK

Mask Pin Diagnosis Fail Interrupt

0 = Pin diagnosis fail interrupt can work (default)

1 = Mask pin diagnosis fail interrupt

PIN_DIAG_FLAG bit is set after the event, but the interrupt

signal is not generated.

SG Micro Corp

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MARCH 2023

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I²C Controlled Single-Cell 6A Switched-Capacitor

Fast Charger with Bypass Mode and ADC

SGM41600

REGISTER MAP (continued)

REG0x11: ADC_CTRL Register Address [reset = 0x00]

BITS

BIT NAME

DEFAULT

TYPE

DESCRIPTION

RESET BY

ADC Conversion Enable

0 = Disabled (default)

1 = Enabled

Note: In 1-shot mode when the selected channel conversions

are complete, the ADC_EN bit is automatically reset to 0.

ADC Conversion Mode Control

0 = Continuous conversion (default)

1 = 1-shot conversion

VBUS ADC Control

0 = Enable conversion (default)

1 = Disable conversion

IBUS ADC Control

0 = Enable conversion (default)

1 = Disable conversion

VBAT ADC Control

0 = Enable conversion (default)

1 = Disable conversion

IBAT ADC Control

0 = Enable conversion (default)

1 = Disable conversion

REG_RST

or Watchdog

D[7]

ADC_EN

0

R/W

D[6]

D[5]

D[4]

D[3]

D[2]

ADC_RATE

0

R/W

REG_RST

VBUS_ADC_DIS

IBUS_ADC_DIS

VBAT_ADC_DIS

IBAT_ADC_DIS

TDIE ADC Control

D[1]

D[0]

TDIE_ADC_DIS

Reserved

0

R/W

R

0 = Enable conversion (default)

1 = Disable conversion

REG_RST

NA

Reserved

REG0x12: VBUS_ADC1 Register Address [reset = 0x00]

BITS

BIT NAME

DEFAULT

TYPE

DESCRIPTION

RESET BY

D[7:4]

Reserved

0000

R

Reserved

NA

Higher 4 bits of the 12-bit ADC VBUS Data (4mV resolution)

MSB<3:0>: 8192mV, 4096mV, 2048mV, 1024mV

D[3:0]

VBUS_ADC[11:8]

0000

R

REG_RST

REG0x13: VBUS_ADC0 Register Address [reset = 0x00]

BITS

BIT NAME

DEFAULT

TYPE

DESCRIPTION

RESET BY

Low Byte of the ADC VBUS Data (4mV resolution)

D[7:0]

VBUS_ADC[7:0]

00000000

R

LSB<7:0>: 512mV, 256mV, 128mV, 64mV, 32mV, 16mV, 8mV, REG_RST

4mV

REG0x14: IBUS_ADC1 Register Address [reset = 0x00]

BITS

BIT NAME

DEFAULT

TYPE

DESCRIPTION

RESET BY

NA

D[7:4]

Reserved

0000

R

Reserved

Higher 4 bits of the 12-bit ADC IBUS Data (2mA resolution)

MSB<3:0>: 4096mA, 2048mA, 1024mA, 512mA

D[3:0]

IBUS_ADC[11:8]

0000

R

REG_RST

REG0x15: IBUS_ADC0 Register Address [reset = 0x00]

BITS

BIT NAME

DEFAULT

TYPE

DESCRIPTION

RESET BY

Low Byte of the ADC IBUS Data (2mA resolution)

LSB<7:0>: 256mA, 128mA, 64mA, 32mA, 16mA, 8mA, 4mA,

2mA

D[7:0]

IBUS_ADC[7:0]

00000000

R

REG_RST

SG Micro Corp

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MARCH 2023

30

I²C Controlled Single-Cell 6A Switched-Capacitor

Fast Charger with Bypass Mode and ADC

SGM41600

REGISTER MAP (continued)

REG0x16: VBAT_ADC1 Register Address [reset = 0x00]

BITS

BIT NAME

DEFAULT

TYPE

DESCRIPTION

RESET BY

NA

D[7:4]

Reserved

0000

R

Reserved

Higher 4 bits of the 12-bit ADC VBAT Data (2mV resolution)

MSB<3:0>: 4096mV, 2048mV, 1024mV, 512mV

D[3:0]

VBAT_ADC[11:8]

0000

R

REG_RST

REG0x17: VBAT_ADC0 Register Address [reset = 0x00]

BITS

BIT NAME

DEFAULT

TYPE

DESCRIPTION

RESET BY

Low Byte of the ADC VBAT Data (2mV resolution)

LSB<7:0>: 256mV, 128mV, 64mV, 32mV, 16mV, 8mV, 4mV,

2mV

D[7:0]

VBAT_ADC[7:0]

00000000

R

REG_RST

REG0x18: IBAT_ADC1 Register Address [reset = 0x00]

BITS

BIT NAME

DEFAULT

TYPE

DESCRIPTION

RESET BY

D[7:4]

Reserved

0000

R

Reserved

NA

Higher 4 bits of the 12-bit IBAT Data (2mA resolution)

MSB<3:0>: 4096mA, 2048mA, 1024mA, 512mA

D[3:0]

IBAT_ADC[11:8]

0000

R

REG_RST

REG0x19: IBAT_ADC0 Register Address [reset = 0x00]

BITS

BIT NAME

DEFAULT

TYPE

DESCRIPTION

RESET BY

Low Byte of ADC IBAT Data (2mA resolution)

LSB<7:0>: 256mA, 128mA, 64mA, 32mA, 16mA, 8mA, 4mA,

2mA

D[7:0]

IBAT_ADC[7:0]

00000000

R

REG_RST

REG0x1A: TDIE_ADC Register Address [reset = 0x00]

BITS

BIT NAME

DEFAULT

TYPE

DESCRIPTION

RESET BY

ADC TDIE Data (8-bit)

LSB<7:0>: 128℃, 64℃, 32℃, 16℃, 8℃, 4℃, 2℃, 1℃

D[7:0]

TDIE_ADC[7:0]

00000000

R

REG_RST

ADC TDIE Temperature Value: = TDIE_ADC[7:0] × 1℃ - 40℃

SG Micro Corp

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MARCH 2023

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I²C Controlled Single-Cell 6A Switched-Capacitor

Fast Charger with Bypass Mode and ADC

SGM41600

REGISTER MAP (continued)

REG0x36: DPDM_DAC Register Address [reset = 0x00]

BITS

BIT NAME

DEFAULT

TYPE

DESCRIPTION

RESET BY

DP Pin Output Driver Voltage Setting

000 = Hi-Z mode (default)

001 = 0V (V_{0P0_VSRC}

)

010 = 0.6V (V_{0P6_VSRC}

011 = 1.2V (V_{1P2_VSRC}

100 = 2.0V (V_{2P0_VSRC}

101 = 2.7V (V_{2P7_VSRC}

110 = 3.3V (V_{3P3_VSRC}

111 = Reserved

)

REG_RST or

Watchdog

D[7:5]

DP_DAC[2:0]

000

R/W

Register bits are reset to default value when input source is

plugged-in and can be changed after DP/DM detection is

complete.

DM Pin Output Driver Voltage Setting

000 = Hi-Z mode (default)

001 = 0V (V_{0P0_VSRC}

)

010 = 0.6V (V_{0P6_VSRC}

011 = 1.2V (V_{1P2_VSRC}

100 = 2.0V (V_{2P0_VSRC}

101 = 2.7V (V_{2P7_VSRC}

110 = 3.3V (V_{3P3_VSRC}

111 = Reserved

)

REG_RST or

Watchdog

D[4:2]

DM_DAC[2:0]

000

R/W

Register bits are reset to default value when input source is

plugged-in and can be changed after DP/DM detection is

complete.

Enable Bit of DP/DM DAC for HVDCP

0 = Disabled (default)

1 = Enabled

REG_RST or

Watchdog

D[1]

D[0]

EN_HVDCP

Reserved

0

R/W

R

Reserved

NA

SG Micro Corp

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MARCH 2023

32

I²C Controlled Single-Cell 6A Switched-Capacitor

Fast Charger with Bypass Mode and ADC

SGM41600

APPLICATION INFORMATION

Input Capacitors (C_VAC, C_VBUSand C_PMID

Input capacitors are selected by considering two main factors:

)

switching frequency improves the efficiency, but the voltage

and current ripples are increased.

Output Capacitor (C_VOUT

)

1. Adequate voltage margin above maximum surge voltage

2. Not too large voltage margin in order to limit the peak

currents drawn from the source and reduce the input noise

C_VOUTselection criteria are similar to the C_FLYcapacitor.

Larger C_VOUTvalue results in less output voltage ripple, but

due to the dual-phase operation, the C_VOUTRMS current is

much smaller than C_FLY, so smaller capacitance value can be

chosen for C_VOUTas given in equation 9:

For C_VAC,use at least a 1µF low ESR bypass ceramic

capacitor placed close to the VAC and PGND pins. The C_VBUS

and C_PMIDare determined by the minimum capacitance

needed for stable operation and the required ESR to minimize

the voltage ripple and load step transients. Typically, 10μF or

larger X5R ceramic capacitors are sufficient for C_VBUSand

I_BAT× t_DEAD

C_VOUT

=

(9)

0.5 × V_{VOUT_RPP}

where t_DEADis the dead time between the two phases and

V_{VOUT_RPP}is the peak-to-peak output voltage ripple and is

C_PMID. Consider the DC bias derating of the ceramic

typically set to the 2% of V_VOUT

.

capacitors. The X5R and X7R capacitors are relatively stable

against DC bias and high temperature. Note that the bias

effect is more severe with smaller package sizes, so choose

the largest affordable package size. Also consider a large

margin for the voltage rating for the worst-case transient input

voltages.

C_VOUTis biased to the battery voltage and its nominal value

should be derated for battery voltage DC bias. Typically two

10µF, X5R or better grade ceramic capacitors placed close to

the VOUT and PGND pins provide stable performance.

External Bootstrap Capacitor (C_BST

)

External OVPFET (Q_OVP

)

The bootstrap capacitors provide the gate driver supply

voltage for the internal high-side switches (Q_CH1and Q_CH2).

Place a 100nF low ESR ceramic capacitor between BST1

and CFH1 pins and another one between BST2 and CFH2

pins.

The maximum recommended V_VBUSinput range is 11.5V. If

the supplied VAC voltage is above 11.5V, or if regulation

functions are needed during load or wall adapter transients,

an external OVPFET is recommended between the USB

connector and the SGM41600. Choose a low R_DSONMOSFET

for the OVPFET to minimize power losses.

PCB Layout Guidelines

A good PCB layout is critical for stable operation of the

Flying Capacitors (C_FLY

)

SGM41600. Follow these guidelines for the best results:

For selection of the C_FLYcapacitors, the current rating, ESR

and the bias voltage derating are critical parameters. The

C_FLYcapacitors are biased to half of the input voltage. To

trade-off between efficiency and power density, set the C_FLY

voltage ripple to the 2% of the V_VOUTas a good starting point.

The C_FLYfor each phase can be calculated by equation 8:

1. Use short and wide traces for VBUS as it carries high

current.

2. Minimize connectors wherever possible. Connector losses

are significant especially at high currents.

3. Use solid thermal vias for better thermal relief.

4. Bypass VBUS, PMID and VOUT pins to PGND with

ceramic capacitors as close to the device pins as

possible.

I_BAT

C_FLY

=

(8)

4f_SWV_{CFLY_RPP}

8%f_SWV_OUT

where I_BATis the charging current and V_{CFLY_RPP}is the

peak-to-peak voltage ripple of the C_FLY

5. Place C_FLYcapacitors as close as possible to the device

with small pad areas to reduce switching noise and EMI.

6. Connect or reference all quiet signals to the AGND pin.

7. Connect and reference all power signals to the PGND pins

(preferably the nearest ones).

.

Choosing a too small capacitor for C_FLYresults in lower

efficiency and high output voltage/current ripples. However

choosing a too large C_FLYonly provides minor efficiency and

output ripple improvements.

8. Try not to interrupt or break the power planes by signal

traces.

The default switching frequency is f_SW= 500kHz. It can be

adjusted by FSW_SET[2:0] bits in REG0x01. Selecting a low

SG Micro Corp

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MARCH 2023

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I²C Controlled Single-Cell 6A Switched-Capacitor

Fast Charger with Bypass Mode and ADC

SGM41600

REVISION HISTORY

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

MARCH 2023 ‒ REV.A to REV.A.1

Page

Changed Detailed Description section ...............................................................................................................................................................12

Changes from Original (JULY 2022) to REV.A

Page

Changed from product preview to production data.............................................................................................................................................All

SG Micro Corp

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MARCH 2023

34

PACKAGE INFORMATION

PACKAGE OUTLINE DIMENSIONS

WLCSP-2.6×2.6-36B

D

0.22

0.20

0.4

36 × Φ

PIN1 #

E

0.4

TOP VIEW

RECOMMENDED LAND PATTERN (Unit: mm)

36 × Φd

6

5

3

2

1

4

A

B

C

D

E

F

A

e

A1

e

SIDE VIEW

BOTTOM VIEW

Dimensions In Millimeters

Symbol

MIN

MOD

0.575

MAX

0.625

0.220

2.630

0.290

A

A1

D

E

0.525

0.180

2.570

0.230

0.200

2.600

d

0.260

e

0.400 BSC

NOTE: This drawing is subject to change without notice.

SG Micro Corp

TX00222.000

www.sg-micro.com

PACKAGE INFORMATION

TAPE AND REEL INFORMATION

REEL DIMENSIONS

TAPE DIMENSIONS

P2

P0

W

Q2

Q4

Q2

Q4

Q2

Q4

Q1

Q3

Q1

Q3

Q1

Q3

B0

Reel Diameter

P1

A0

K0

Reel Width (W1)

DIRECTION OF FEED

NOTE: The picture is only for reference. Please make the object as the standard.

KEY PARAMETER LIST OF TAPE AND REEL

Reel Width

Reel

Diameter

A0

B0

K0

P0

P1

P2

W

Pin1

Package Type

W1

(mm)

(mm) (mm) (mm) (mm) (mm) (mm) (mm) Quadrant

WLCSP-2.6×2.6-36B

13″

12.4

2.75

0.77

4.0

8.0

2.0

12.0

Q1

SG Micro Corp

TX10000.000

www.sg-micro.com

PACKAGE INFORMATION

CARTON BOX DIMENSIONS

NOTE: The picture is only for reference. Please make the object as the standard.

KEY PARAMETER LIST OF CARTON BOX

Length

(mm)

Width

(mm)

Height

(mm)

Reel Type

Pizza/Carton

13″

386

280

370

5

SG Micro Corp

www.sg-micro.com

TX20000.000


型号：	SGM41600
厂家：	Shengbang Microelectronics Co, Ltd
描述：	I2C Controlled 6A Single-Cell Switched-Capacitor Fast Charger with Bypass Mode and ADC
文件：	总37页 (文件大小：1184K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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