SGM4703_技术文档

SGM4703

High-Power Stereo Class-D Audio Power Amplifier

with Adjustable Power Limit and Automatic Level Control

GENERAL DESCRIPTION

FEATURES

The SGM4703 is a high-power, high efficiency, stereo

Class-D audio power amplifier with adjustable power limit

(APL) and automatic level control (ALC). It operates with a

wide range of supply voltages from 5V to 26V. With 24V

supply voltage, it can deliver 2 × 40W peak output power for a

pair of 8Ω speakers with 10% THD+N.

● Wide Range of Supply Voltages from 5V to 26V

● Adjustable Power Limit to Safeguard Audio Speakers

● Automatic Level Control to Eliminate Output Clipping

● 4 Selectable Gain Settings: 20/26/30/34dB

● 3 Selectable ALC Dynamic Characteristics

● 2 Selectable PWM Frequencies with Optional

Spread-Spectrum: 360kHz and 500kHz

The high efficiency of SGM4703 extends battery life in playing

music and allows it to deliver an output power of 2 × 20W

without the need for a bulky heat sink on a two-layer system

board. Its high PSRR and low EMI emission reduce system

design and manufacturing complexities, as well as lower

system cost.

● 2 Selectable Modulation Schemes: SSM and DSM

● Optional PBTL Configuration for Mono Applications

● Maximum Output Power in Non-ALC

 2 × 40W (V_DD= 24V, 8Ω + 33μH, BTL, THD+N = 10%)

 2 × 32W (V_DD= 24V, 8Ω + 33μH, BTL, THD+N = 1%)

 80W (V_DD= 24V, 4Ω + 33μH, PBTL, THD+N = 10%)

 64W (V_DD= 24V, 4Ω + 33μH, PBTL, THD+N = 1%)

● ALC Output Power (THD+N < 0.5%) in ALC

 2 × 30W (V_DD= 24V, 8Ω + 33μH, BTL)

The SGM4703 features APL and ALC. The APL limits peak

audio outputs to a user-defined value to protect audio

speakers from excessive power dissipation or over-load. The

APL and ALC adjust the voltage gain of the audio amplifiers in

response to over-limit audio inputs, eliminating output clipping

distortion while maintaining a maximally allowed dynamic

range of audio outputs. The limiting voltage of APL and ALC

can be either a user-defined value or the supply voltage.

 2 × 21W (V_DD= 15V, 4Ω + 33μH, BTL)

 60W (V_DD= 24V, 4Ω + 33μH, PBTL)

● Wide ALC Dynamic Range: 12dB (V_DD= 12V)

● Low THD+N: 0.02% (V_DD= 12V, 4Ω + 33μH, P_O= 10W/CH)

● High PSRR: 80dB at 1kHz with SSM

● Protection Modes against Various Operating Faults

Including Under-Voltage, Over-Voltage, Over-Current,

Over-Temperature and DC-Detect

The SGM4703 can be configured into driving either a pair of

speakers in Bridge-Tied-Load (BTL) configuration for stereo

applications or a single speaker in Parallel BTL (PBTL)

configuration for mono applications.

● Available in a Green TSSOP-28 (Exposed Pad)

Package

The SGM4703 features two PWM modulation schemes for

Class-D audio amplifiers: Dual-Side-Modulation (DSM) and

Single-Side-Modulation (SSM).

APPLICATIONS

Bluetooth/Wireless Speakers

Consumer Audio Speakers

Soundbars

In SGM4703, comprehensive protection modes against

various operating faults ensure its safe and reliable operation.

SG Micro Corp

DECEMBER 2022 – REV. A

www.sg-micro.com

High-Power Stereo Class-D Audio Power Amplifier

SGM4703

with Adjustable Power Limit and Automatic Level Control

PACKAGE/ORDERING INFORMATION

SPECIFIED

TEMPERATURE

RANGE

PACKAGE

DESCRIPTION

ORDERING

NUMBER

PACKAGE

MARKING

PACKING

OPTION

MODEL

SGM4703

YPTS28

XXXXX

TSSOP-28

(Exposed Pad)

SGM4703

SGM4703YPTS28G/TR

Tape and Reel, 4000

-40℃ to +85℃

MARKING INFORMATION

NOTE: XXXXX = Date Code, Trace Code and Vendor Code.

X X X X X

Vendor Code

Trace Code

Date Code - Year

Green (RoHS & HSF): SG Micro Corp defines "Green" to mean Pb-Free (RoHS compatible) and free of halogen substances. If

you have additional comments or questions, please contact your SGMICRO representative directly.

OVERSTRESS CAUTION

ABSOLUTE MAXIMUM RATINGS

Supply Voltage Pins

Stresses beyond those listed in Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to

absolute maximum rating conditions for extended periods

may affect reliability. Functional operation of the device at any

conditions beyond those indicated in the Recommended

Operating Conditions section is not implied.

AVDD, PVDD.................................................. -0.3V to 30V

Digital I/O Pins

EN, FAULTB ..................................... -0.3V to V_AVDD+ 0.3V

MODS ............................................... -0.3V to V_GVDD+ 0.3V

Analog Output Pins

GVDD ............................................................ -0.3V to 6.5V

ALC, GAIN, FREQ ............................ -0.3V to V_GVDD+ 0.3V

Analog Input Pins

ESD SENSITIVITY CAUTION

This integrated circuit can be damaged if ESD protections are

not considered carefully. SGMICRO recommends that all

integrated circuits be handled with appropriate precautions.

Failureto observe proper handlingand installation procedures

can cause damage. ESD damage can range from subtle

performance degradation tocomplete device failure. Precision

integrated circuits may be more susceptible to damage

because even small parametric changes could cause the

device not to meet the published specifications.

INPL/R, INNL/R, PLIMIT................... -0.3V to V_GVDD+ 0.3V

Package Thermal Resistance

TSSOP-28 (Exposed Pad), θ_JA.................................. 28℃/W

Junction Temperature.................................................+150℃

Storage Temperature Range.......................-65℃ to +150℃

Lead Temperature (Soldering, 10s)............................+260℃

ESD Susceptibility

HBM.............................................................................1500V

CDM ............................................................................1000V

DISCLAIMER

SG Micro Corp reserves the right to make any change in

circuit design, or specifications without prior notice.

SG Micro Corp

www.sg-micro.com

DECEMBER 2022

2

High-Power Stereo Class-D Audio Power Amplifier

SGM4703

with Adjustable Power Limit and Automatic Level Control

RECOMMENDED OPERATING CONDITIONS

PARAMETER

Supply Voltage Range ^{(1, 2)}

SYMBOL

V_DD

CONDITIONS

MIN

5

TYP

MAX

26

UNITS

PVDD, AVDD

V

Operating Ambient Temperature

T_A

-40

+85

℃

BTL Configuration (Stereo)

PBTL Configuration (Mono)

At INPL/R, INNL/R

4

3

1

Minimum Load Impedance ⁽³⁾

R_L

Ω

Audio Input Capacitor

C_IN

µF

V_RMS

V

Maximum Audio Input Voltage Level

PLIMIT Voltage Range

V_{IN, MAX}At INNL/R, INPL/R

2.0

V_GVDD

5

V_PLIMIT

I_LOAD

PLIMIT

0

Maximum Load Current at GVDD

mA

Ceramic

Electrolytic or Tantalum ⁽⁴⁾

1

220

1

C_PVDD

Supply Decoupling Capacitor

C_AVDD

C_GVDD

C_PLIMIT

C_B

Ceramic

µF

Ceramic

1

Ceramic

0.1

Bootstrap Holding Capacitor

Mono Mode Select

At BSTPL/R, BSTNL/R

INNR

INPR

PBTL Configuration

Both Pins Shorted to GND

Single-Side-Modulation (SSM)

High or Open

Low

Modulation Scheme Select

MODS

GAIN

Double-Side-Modulation (DSM)

26dB

Open

30dB

Shorted to GND

68kΩ to GND

300kΩ to GND

Open

Voltage Gain Select

34dB

20dB

Non-ALC

ALC-1

Shorted to GND

68kΩ to GND

300kΩ to GND

Open

ALC Mode Select

ALC

ALC-2

ALC-3

Constant Frequency at 360kHz

360kHz with Spread-Spectrum

Constant Frequency at 500kHz

500kHz with Spread-Spectrum

Shorted to GND

68kΩ to GND

300kΩ to GND

PWM Frequency Select

NOTES:

FREQ

1. The peak supply voltage including its tolerance over various operating conditions must not exceed its absolute-maximum-rated value (26V).

Exposure to absolute-maximum-rated supply voltage may damage the device or affect device reliability permantly.

2. For high power applications, the maximum power supply V_DDthat can be applied to the SGM4703 is largely limited by the thermal dissipation

capability of the package and the system board layout.

3. The SGM4703 is specfied with an 8Ω resistive load in series with 33µH inductive load or with a 4Ω resistive load in series with 33µH inductive

load or with a 2Ω or 3Ω resistive load in series with 15µH inductive load (in PBTL configuration). Without inductive loads, the maximum continous

output power will severely suffer from efficiency and thermal degradation.

4. If the input supply is located more than a few centimeters from SGM4703, additional bulk capacitor may be required in addition to the ceramic

capacitors.

SG Micro Corp

www.sg-micro.com

DECEMBER 2022

3

High-Power Stereo Class-D Audio Power Amplifier

SGM4703

with Adjustable Power Limit and Automatic Level Control

PIN CONFIGURATION

(TOP VIEW)

1

2

28

27

26

25

24

23

22

21

20

19

18

17

16

15

EN

PVDD

BSTPL

VOPL

FAULTB

INPL

3

4

INNL

5

GAIN

PGND

VONL

BSTNL

BSTNR

VONR

PGND

VOPR

BSTPR

PVDD

6

FREQ

AVDD

AGND

GVDD

PLIMIT

INNR

7

Exposed

Pad

8

9

10

11

12

13

14

INPR

ALC

MODS

TSSOP-28 (Exposed Pad)

PIN DESCRIPTION

NAME

TYPE

DESCRIPTION

Chip enable (active high) with an on-chip 250kΩ pull-down resistor to ground. A TTL logic

input in compliance with AVDD.

1

EN

DI

Open-drain output indicating operational faults of OCP or DCP. Both faults can be set for

auto-recovery by externally connecting FAULTB to EN. Otherwise, both OCP and DCP faults

must be reset by cycling EN.

2

FAULTB

DO

3

4

INPL

INNL

AI

Left-channel non-inverting audio input biased at one half of GVDD.

Left-channel inverting audio input biased at one half of GVDD.

Voltage gain select with an on-chip 250kΩ pull-down resistor to ground. Connect to a resistor

to ground to set the voltage gain of the audio amplifiers.

5

GAIN

FREQ

AVDD

AGND

GVDD

PLIMIT

INNR

INPR

ALC

AO

P

PWM frequency select with an on-chip 250kΩ pull-down resistor to ground. Connect to a

resistor to ground to set the PWM frequency with optional spread-spectrum.

6

Analog supply. Connect to a 1µF capacitor for decoupling. Also, add a decoupling resistor of

10Ω between this pin and the system power supply for high-frequency filtering.

7

8

G

Analog ground. Connect to the system power ground GND.

9

AO

AI

Internally generated reference voltage at 5.6V. Connect to a 1µF capacitor for decoupling.

Adjustable power limit. Connect to a resistor divider from GVDD to AGND to set the output

voltage limit. Add a 0.1μF capacitor for decoupling.

10

11

12

13

Right-channel inverting audio input biased at one half of GVDD. Connect to ground (without

decoupling capacitor) for mono mode in PBTL configuration.

AI

Right-channel non-inverting audio input biased at one half of GVDD. Connect to ground

(without decoupling capacitor) for mono mode in PBTL configuration.

AI

ALC mode select with an on-chip 250kΩ pull-down resistor to ground. Connect to a resistor to

ground or leave open to set ALC dynamic characteristic.

AO

SG Micro Corp

www.sg-micro.com

DECEMBER 2022

4

High-Power Stereo Class-D Audio Power Amplifier

SGM4703

with Adjustable Power Limit and Automatic Level Control

PIN DESCRIPTION (continued)

NAME

TYPE

DESCRIPTION

PWM modulation select with an on-chip 250kΩ pull-up resistor to GVDD. A TTL logic input in

compliance with GVDD.

14

MODS

DI

Power supply inputs for the right-channel H-bridge. The power supplies for right-channel and

left-channel H-bridges are internally.

15, 16

17

PVDD

BSTPR

VOPR

PGND

VONR

BSTNR

BSTNL

VONL

PGND

VOPL

BSTPL

PVDD

GND

P

Connect to bootstrap holding capacitor for the right-channel non-inverting output, VOPR. A

0.1µF capacitor must be placed between this pin and VOPR for proper operation.

AO

G

18

Right-channel non-inverting audio output terminal.

Power ground for the right-channel H-bridge. Connect to the system ground GND. The power

ground for right-channel and left-channel H-bridges are internally shorted.

19

20

AO

G

Right-channel inverting audio output terminal.

Connect to a bootstrap holding capacitor for the right-channel inverting output, VONR. A

0.1µF capacitor must be placed between this pin and VONR for proper operation.

21

Connect to a bootstrap holding capacitor for the left-channel inverting output, VONL. A 0.1µF

capacitor must be placed between this pin and VONL for proper operation.

22

23

Left-channel inverting audio output terminal.

Power ground for the left-channel H-bridge. Connect to the system ground GND. The power

ground for right-channel and left-channel H-bridges are internally shorted.

24

25

AO

P

Left-channel non-inverting audio output terminal.

Connect to a bootstrap holding capacitor for the left-channel non-inverting output, VOPL. A

0.1µF capacitor must be placed between this pin and VOPL for proper operation.

26

Power supply inputs for the left-channel H-bridge. The power supplies for right-channel and

left-channel H-bridges are internally shorted.

27, 28

Exposed

Pad

G

Exposed pad. Connect to the system ground GND.

TYPICAL APPLICATION

V_DD

C_{PV DD}

10nF

C_{PV DD}

1μF

C_{PV DD}

+

220μF

R_EN

28

27

26

25

24

1

2

3

4

EN

PV DD

BSTPL

VOPL

EN

10kΩ

FAULTB

INPL

C_IN

1μF

R_INE

C_B

INPL

INNL

0Ω

0. 1μF

LSL

R_INE

INNL

GAIN

FREQ

0Ω

5

6

7

8

PG ND

VO NL

V_DD

23

22

21

20

19

18

17

16

SPEAKER

LSR

R_{AV DD}

C_B

AV DD

AG ND

BS TNL

BS TNR

VO NR

PG ND

VOPR

BSTPR

PV DD

0. 1μF

10Ω C_{AV DD}

1μF

SGM4703

C_B

0. 1μF

9

10

11

12

13

GV DD

PLIMIT

INNR

INPR

C_{GV DD}

1μF

C_IN

1μF

R_INE

INNR

INPR

SPEAKER

0Ω

R_INE

C_B

0Ω

0. 1μF

V_DD

ALC

15

14

MODS

C_{PV DD}

10nF

C_{PV DD}

1μF

C_{PV DD}

+

220μF

Figure 1. Typical Application Circuit

SG Micro Corp

www.sg-micro.com

DECEMBER 2022

5

High-Power Stereo Class-D Audio Power Amplifier

SGM4703

with Adjustable Power Limit and Automatic Level Control

IMPORTANT APPLICATION NOTES

8. A ferrite bead filter constructed from a ferrite bead

and a ceramic capacitor can be used to suppress EMI.

Choose a ferrite bead with a rated current no less than

4A for 8Ω loads, 7A for 4Ω loads, and 9A for 3Ω or less

loads (in PBTL configuration). Place the filter tightly

together and as close as possible to the audio

amplifier’s output pins. A ferrite bead filter can also

reduce high-frequency interference.

Output Power Considerations

1. The maximum output power of SGM4703 is

determined primarily by the power supply (its output

voltage and current) and speaker impedance. As a high

power audio amplifier, the maximum output power of

SGM4703 can be severely limited by the thermal

dissipation capability of the system board layout.

2. The SGM4703 is packaged with an exposed thermal

pad on the underside of the device. Solder the thermal

pad directly onto a large grounded metal island (GND)

underneath the package, as a thermal sink for proper

thermal dissipation. On the grounded metal island,

place several rows of solid, equally-spaced vias

connecting to the bottom layer of the system board.

Failure to do so can severely limit its thermal

dissipation capability. It might even cause the device

going into over-temperature mute occasionally.

9. For applications where EMC requirements are

extremely stringent or speaker wires are long, use a

second-order LC low-pass filter. Place the filter tightly

together and as close as possible to the audio amplifier’s

output pins. The LC output filter must be designed

specifically for the speaker load since the load impedance

affects the quality factor of the filter.

General Considerations

10. The SGM4703 requires adequate power supply

decoupling to ensure its peak output power, high

efficiency, low distortion, and low EMI emissions. Place

each supply decoupling capacitor as individually close

as possible to AVDD and PVDD pins.

3. Use wide open areas around the SGM4703 on the

top and bottom layers of the system board as the

ground plane GND. Place lots of solid vias connecting

the top and bottom layers of GND. Furthermore, for

proper thermal dissipation, reserve wide and

uninterrupted GND areas along the thermal flow on the

top layer, i.e., no wires cutting through the GND layer

and obstructing the thermal flow in the proximity of the

device.

11. Place a small decoupling resistor (10Ω) between

the system power supply and AVDD to prevent high

frequency Class-D transient spikes from interfering with

the on-chip linear amplifiers.

12. For best noise performance, use differential inputs

from the audio source for SGM4703. In single-ended

input applications, the unused inputs of SGM4703 must

be AC-grounded at the audio source. Also, take care to

match the impedances seen at two differential inputs

closely.

4. All the power ground pins PGND are directly shorted

to the ground plane GND as a central “star” ground for

the SGM4703. Use a single point of connection

between the analog ground AGND and the ground

plane GND to minimize the coupling of high-current

switching noise onto audio signals.

13. The maximum input signal dictates the required

voltage gain to achieve the desired maximum output

power. For best noise performance, consider a voltage

gain as low as possible.

5. The power supply pins, PVDD, for the audio

amplifiers’ output stages are directly connected

together with short and wide metal traces.

6. Use direct and low-impedance traces from the audio

outputs (VOPL/R and VONL/R) to their individual

output filters and speakers.

14. Do not alter the logic state of the MODS pin while

the device is in operation. To change the setting of the

pin, the device must be first brought into shutdown

mode by pulling the EN pin low for at least 10ms before

it can be restored to its normal operation.

Output Filter Considerations

7. For most applications, the SGM4703 does not

require an LC output filter when speaker wires are less

than 10cm.

SG Micro Corp

www.sg-micro.com

DECEMBER 2022

6

High-Power Stereo Class-D Audio Power Amplifier

SGM4703

with Adjustable Power Limit and Automatic Level Control

TEST SETUP FOR ELECTRICAL AND PERFORMANCE CHARACTERISTICS

C_IN

R_INE

INN

VOP

AUX-0025

Switching Amplifier

Measurement Filter

Measurement

Output

Measurement

Input

SGM4703

Load

R_INE

C_IN

INP

VON

VDD

GND

C_S

+

Supply

-

Figure 2. Test Setup Diagram

All parameters specified in Electrical and Typical Performance Characteristics sections are measured according to

the conditions:

1. The two differential inputs are shorted for common-mode input voltage measurement. All other parameters are

taken with input resistors R_INE= 0kΩ and input capacitors C_IN= 1μF, unless otherwise specified.

2. The supply decoupling capacitors C_S= 2 × (10nF + 1μF + 220μF) are placed close to the device.

3. A 33μH inductor was placed in series with the load resistor to emulate a speaker load for all AC and dynamic

parameters.

SG Micro Corp

www.sg-micro.com

DECEMBER 2022

7

High-Power Stereo Class-D Audio Power Amplifier

SGM4703

with Adjustable Power Limit and Automatic Level Control

ELECTRICAL CHARACTERISTICS

(Minimum and Maximum values are at T_A= -40℃ to +85℃, V_DD= 12V, f = 1kHz, Load = 4Ω + 33µH, C_IN= 4 × 1µF, R_INE= 4 × 0Ω,

GAIN = NC (A_V= 26dB), FREQ = NC (f_PWM= 360kHz), MODS = NC (SSM), ALC shorted to GND (ALC-1), V_PLIMIT= V_GVDD, C_PVDD

=

2 × (10nF + 1μF + 220μF), C_AVDD= 1µF, C_GVDD= 1µF, C_B= 4 × 0.1µF, both channels driven, typical values are measured at T_A=

+25℃, unless otherwise specified.)

PARAMETER

Supply Voltage

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

V_DD

PVDD, AVDD

5

26

V

V_PVDD= 12V, Inputs AC-grounded, No Load

V_PVDD= 26V, Inputs AC-grounded, No Load

PLIMIT = GND, No Load

15

22

Supply Quiescent Current

Mute Current

I_VDD

I_MUTE

I_SD

mA

µA

37

12

8

SSM, MODS = NC

V_PVDD= 26V, V_EN= 0V

55

100

120

4.85

Shutdown Current

DSM, MODS = GND

70

Supply Voltage UVLO Detection

Supply Voltage UVLO Release

Supply Voltage OVP Detection

Supply Voltage OVP Release

Voltage Regulator Output

V_UVLOUP

V_UVLODN

V_OVPUP

V_OVPDN

V_GVDD

V_COMM

V_IL

V_DDRising

4.60

4.30

28.0

26.5

5.6

2.8

V

V_DDFalling

4.00

25.0

V_DDRising

30.5

V_DDFalling

No Load

Input Common-Mode Bias

Digital Low Input Voltage

INPL/R, INNL/R

EN, MODS

0.8

EN

2

V_AVDD

V_GVDD

0.25

Digital High Input Voltage

V_IH

V

MODS

Digital Low Output Voltage

Pull-Down Resistor to Ground

Pull-Up Resistor to GVDD

Output Resistance in Shutdown

V_OL

R_DOWN

R_UP

FAULTB, R_PULLUP= 100kΩ, V_DD= 18V

EN, MODS, ALC, GAIN, FREQ

MODS

V

250

5

kΩ

R_OUT-SD

At VOPL/R, VONL/R, EN = Low

Open

2.5

0

V_GAIN

V_FREQ

V_ALC

,

Shorted to GND

68kΩ to GND

300kΩ to GND

Open

Voltage Level at

GAIN, FREQ, ALC Pins

V

0.55

1.4

30

R_GAIN= 0kΩ

20

Internal Input Resistance at

INPL/R, INNL/R Pins

R_INI

kΩ

R_GAIN= 68kΩ

12

R_GAIN= 300kΩ

Open

60

26

R_GAIN= 0kΩ

30

Voltage Gain

A_V

dB

R_GAIN= 68kΩ

34

R_GAIN= 300kΩ

Open or R_FREQ= 0kΩ

R_FREQ= 68kΩ or R_FREQ= 300kΩ

Dual BTL Configuration

PBTL Configuration

20

360

500

8.8

13

PWM Frequency

f_SW

kHz

A/CH

A

Over-Current Limit

I_LIMIT

Over-Temperature Threshold

Over-Temperature Hysteresis

T_OTSD

T_HYS

160

20

℃

SG Micro Corp

www.sg-micro.com

DECEMBER 2022

8

High-Power Stereo Class-D Audio Power Amplifier

SGM4703

with Adjustable Power Limit and Automatic Level Control

ELECTRICAL CHARACTERISTICS (continued)

(Minimum and Maximum values are at T_A= -40℃ to +85℃, V_DD= 12V, f = 1kHz, Load = 4Ω + 33µH, C_IN= 4 × 1µF, R_INE= 4 × 0Ω,

GAIN = NC (A_V= 26dB), FREQ = NC (f_PWM= 360kHz), MODS = NC (SSM), ALC shorted to GND (ALC-1), V_PLIMIT= V_GVDD, C_PVDD

=

2 × (10nF + 1μF + 220μF), C_AVDD= 1µF, C_GVDD= 1µF, C_B= 4 × 0.1µF, both channels driven, typical values are measured at T_A=

+25℃, unless otherwise specified.)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

Class-D Amplifier (V_DD= 12V, R_L= 4Ω + 33µH, Both Channels Driven)

Maximum Output Power

ALC Output Power

P_O,MAX

P_O,ALC

THD+N = 1%

15

13

W/CH

V_IN= 0.50V_RMS

SSM

DSM

SSM

DSM

SSM

DSM

0.04

0.02

0.3

86

P_O= 1W/CH, Non-ALC Mode

P_O= 10W/CH, Non-ALC Mode

V_IN= 0.50V_RMS, ALC Mode

Total Harmonic Distortion + Noise

THD+N

%

P_O= 10W/CH, Non-ALC Mode

V_IN= 0.50V_RMS, ALC Mode

No Load

Power Efficiency

η

%

87

Output Offset Voltage

Idle-Channel Noise

Signal-to-Noise Ratio

V_OS

V_N

±20

145

94

mV

µV_RMS

dB

Inputs AC-Grounded, A-weighted

SNR

Maximum Output (7V_RMS), A-weighted

SSM

f = 1kHz

80

Power Supply Rejection Ratio

PSRR

CMRR

dB

DSM

60

Common Mode Rejection Ratio

Channel Separation

f = 1kHz, V_IN= 0.2V_RMS

60

dB

Crosstalk P_O= 10W, f = 1kHz

_DD= 12V

85

V

12

Maximum ALC Attenuation

A_MAX

V_DD= 15V

10

dB

V_DD= 18V

8.5

45

Startup Time

t_STARTUP

t_SD

Including Fade-In Time

ms

Shutdown Settling Time

DC Current Protection (DCP)

10

Including Fade-Out Time, T_A= +25℃

V

_DD= 12V, Load = 4Ω + 33µH

2.4

3.0

3.6

DC-Detect Threshold

V_DCP

V_DD= 15V, Load = 4Ω + 33µH

V_DD= 18V, Load = 4Ω + 33µH

V

Fade-In and Fade-Out

Fade-In Time

t_FADEIN

8

5

ms

Fade-Out Time

t_FADEOUT

SG Micro Corp

www.sg-micro.com

DECEMBER 2022

9

High-Power Stereo Class-D Audio Power Amplifier

SGM4703

with Adjustable Power Limit and Automatic Level Control

ELECTRICAL CHARACTERISTICS (continued)

(V_DD= 15V, f = 1kHz, Load = 4Ω + 33μH, SSM, both channels driven, T_A= +25℃, unless otherwise specified.)

PARAMETER

Maximum Output Power ⁽¹⁾

ALC Output Power

SYMBOL

P_O,PEAK

P_O,ALC

CONDITIONS

THD+N = 10%, Non-ALC Mode

THD+N = 1%, Non-ALC Mode

V_DD= 15V, V_IN= 0.60V_RMS

MIN

TYP

27

MAX

UNITS

W/CH

%

23

21

P_O= 15W/CH, Non-ALC Mode

V_IN= 0.60V_RMS, ALC Mode

P_O= 15W/CH, Non-ALC Mode

V_IN= 0.60V_RMS, ALC Mode

P_O= 20W/CH, A-weighted

0.02

0.3

85

Total Harmonic Distortion + Noise

THD+N

Power Efficiency ⁽²⁾

η

%

86

Signal-to-Noise Ratio

SNR

95

dB

(V_DD= 18V, f = 1kHz, Load = 8Ω + 33μH, SSM, both channels driven, T_A= +25℃, unless otherwise specified.)

PARAMETER

Maximum Output Power ⁽¹⁾

ALC Output Power

SYMBOL

P_O,PEAK

P_O,ALC

CONDITIONS

THD+N = 10%, Non-ALC Mode

THD+N = 1%, Non-ALC Mode

V_IN= 0.70V_RMS

MIN

TYP

22

MAX

UNITS

W/CH

%

18

16

P_O= 10W/CH, Non-ALC Mode

V_IN= 0.70V_RMS, ALC Mode

P_O= 10W/CH, Non-ALC Mode

V_IN= 0.70V_RMS, ALC Mode

P_O= 15W/CH, A-weighted

0.02

0.3

90

Total Harmonic Distortion + Noise

THD+N

Power Efficiency ⁽²⁾

η

%

91

Signal-to-Noise Ratio

SNR

97

dB

(V_DD= 24V, f = 1kHz, Load = 8Ω + 33μH, SSM, both channels driven, T_A= +25℃, unless otherwise specified.)

PARAMETER

Maximum Output Power ⁽¹⁾

ALC Output Power

SYMBOL

P_O,PEAK

P_O,ALC

CONDITIONS

THD+N = 10%, Non-ALC Mode

THD+N = 1%, Non-ALC Mode

V_IN= 1.0V_RMS

MIN

TYP

40

MAX

UNITS

W/CH

%

32

30

P_O= 20W/CH, Non-ALC Mode

V_IN= 1.0V_RMS, ALC Mode

P_O= 20W/CH, Non-ALC Mode

V_IN=1.0V_RMS, ALC Mode

P_O= 25W/CH, A-weighted

0.02

0.3

90

Total Harmonic Distortion + Noise

THD+N

Power Efficiency ⁽²⁾

η

%

91

Signal-to-Noise Ratio

SNR

98

dB

SG Micro Corp

DECEMBER 2022

www.sg-micro.com

10

High-Power Stereo Class-D Audio Power Amplifier

SGM4703

with Adjustable Power Limit and Automatic Level Control

ELECTRICAL CHARACTERISTICS (continued)

(V_DD= 24V, f = 1kHz, Load = 4Ω + 33μH, SSM, PBTL configuration, T_A= +25℃, unless otherwise specified.)

PARAMETER

Maximum Output Power ⁽¹⁾

ALC Output Power

SYMBOL

P_O,PEAK

P_O,ALC

CONDITIONS

THD+N = 10%, Non-ALC Mode

THD+N = 1%, Non-ALC Mode

V_IN= 1.0V_RMS

MIN

TYP

80

MAX

UNITS

W

64

60

W

P_O= 40W, Non-ALC Mode

V_IN= 1.0V_RMS, ALC Mode

P_O= 40W, Non-ALC Mode

V_IN= 1.0V_RMS, ALC Mode

P_O= 50W, A-weighted

0.1

0.3

90

Total Harmonic Distortion + Noise

THD+N

%

Power Efficiency ⁽²⁾

η

%

91

Signal-to-Noise Ratio

SNR

98

dB

(V_DD= 15V, f = 1kHz, Load = 3Ω + 15μH, SSM, PBTL configuration, T_A= +25℃, unless otherwise specified.)

PARAMETER

Maximum Output Power ⁽¹⁾

ALC Output Power

SYMBOL

P_O,PEAK

P_O,ALC

CONDITIONS

THD+N = 10%, Non-ALC Mode

THD+N = 1%, Non-ALC Mode

V_IN= 0.60V_RMS

MIN

TYP

40

UNITS

W

33

30

W

P_O= 20W, Non-ALC Mode

V_IN= 0.60V_RMS, ALC Mode

P_O= 20W, Non-ALC Mode

V_IN= 0.60V_RMS, ALC Mode

P_O= 30W, A-weighted

0.1

0.3

89

Total Harmonic Distortion + Noise

THD+N

%

Power Efficiency ⁽²⁾

η

%

90

Signal-to-Noise Ratio

SNR

96

dB

(V_DD= 12V, f = 1kHz, Load = 2Ω + 15μH, SSM, PBTL configuration, T_A= +25℃, unless otherwise specified.)

PARAMETER

Maximum Output Power ⁽¹⁾

ALC Output Power

SYMBOL

P_O,PEAK

P_O,ALC

CONDITIONS

THD+N = 10%, Non-ALC Mode

THD+N = 1%, Non-ALC Mode

V_IN= 0.50V_RMS

MIN

TYP

37

UNITS

W

30

27

W

P_O= 20W, Non-ALC Mode

V_IN= 0.50V_RMS, ALC Mode

P_O= 20W, Non-ALC Mode

V_IN= 0.50V_RMS, ALC Mode

P_O= 25W, A-weighted

0.1

0.3

87

Total Harmonic Distortion + Noise

THD+N

%

Power Efficiency ⁽²⁾

η

%

88

Signal-to-Noise Ratio

SNR

94

dB

NOTES:

1. The peak output power is defined as an instantaneous maximum output power with no consideration of the thermal dissipation capability of the

system board. The maximum continuous output power will be less than the peak output power and largely depend upon the thermal dissipation

capability of the system board.

2. All the power efficiency data are given for a two-side, two-layer printed circuit board and shall be used for reference only. The power efficiency

will be strongly affected by the thermal dissipation capability of the system board, such as the number of layers and the application of a heat sink.

SG Micro Corp

DECEMBER 2022

www.sg-micro.com

11

High-Power Stereo Class-D Audio Power Amplifier

SGM4703

with Adjustable Power Limit and Automatic Level Control

TYPICAL PERFORMANCE CHARACTERISTICS

T_A= +25℃, f = 1kHz, C_IN= 4 × 1µF, A_V= 26dB, f_PWM= 360kHz, SSM Mode, V_PLIMIT= V_GVDD, both channels driven (BTL Mode),

unless otherwise specified.

Maximum Output Power vs. Supply Voltage

44

40

36

32

28

24

20

16

12

8

40

32

24

16

8

R_L= 8Ω + 33μH, Non-ALC Mode

R_L= 4Ω + 33μH, Non-ALC Mode

THD+N = 10%

THD+N = 1%

Dashed lines indicate

thermally-limited regions

Dashed lines indicate

thermally-limited regions

4

0

6

8

10 12 14 16 18 20 22 24

6

8

10

12

14

16

18

Supply Voltage (V)

Maximum Output Power vs. Supply Voltage

ALC Output Power vs. Supply Voltage

80

72

64

56

48

40

32

24

16

8

60

50

40

30

20

10

0

R_L= 4Ω + 33μH, Non-ALC Mode,

PBTL Mode

R_L= 3Ω + 15μH, Non-ALC Mode,

PBTL Mode

THD+N = 10%

THD+N = 1%

THD+N = 10%

THD+N = 1%

Dashed lines indicate

thermally-limited regions

Dashed lines indicate

thermally-limited regions

0

6

8

10 12 14 16 18 20 22 24

6

8

10

12

14

16

18

Supply Voltage (V)

ALC Output Power vs. Supply Voltage

Output Power vs. Input Voltage

60

50

40

30

20

10

0

100

10

ALC-1 Mode, V_IN= 1.0V_RMS

A_V= 20dB

A_V= 26dB

A_V= 30dB

A_V= 34dB

1

R_L= 4Ω + 33μH

0.1

R_L= 8Ω + 33μH

0.01

Dashed lines indicate

thermally-limited regions

V_DD= 24V, R_L= 8Ω + 33μH, Non-ALC Mode

0.001

0.01

0.1

1

10

6

8

10 12 14 16 18 20 22 24

Input Voltage (V_RMS

)

Supply Voltage (V)

SG Micro Corp

DECEMBER 2022

www.sg-micro.com

12

High-Power Stereo Class-D Audio Power Amplifier

SGM4703

with Adjustable Power Limit and Automatic Level Control

TYPICAL PERFORMANCE CHARACTERISTICS (continued)

T_A= +25℃, f = 1kHz, C_IN= 4 × 1µF, A_V= 26dB, f_PWM= 360kHz, SSM Mode, V_PLIMIT= V_GVDD, both channels driven (BTL Mode),

unless otherwise specified.

Output Power vs. Input Voltage

Gain vs. Frequency

100

10

30

26

22

18

14

10

V_DD= 15V, R_L= 3Ω + 15μH

ALC-2 Mode, PBTL Mode

1

Non-ALC Mode, PBTL Mode

V_DD= 12V,

R_L= 4Ω + 33μH,

Gain = 26dB,

0.1

V

_IN= 0.1V_RMS

0.01

0.1

1

10

0.6

100

1000

Frequency (Hz)

10000

100000

Input Voltage (V_RMS

)

Output Voltage Limit vs. V_PLIMIT

24

20

16

12

8

16

12

8

No Load

R_L= 4Ω + 33μH

R_L= 8Ω + 33μH

4

V_DD= 24V, V_IN= 1.0V_RMS, APL Mode

V_DD= 12V, V_IN= 0.50V_RMS, APL Mode

0

0.6 1.0 1.4 1.8 2.2 2.6 3.0 3.4 3.8

1.0

1.4

1.8

2.2

2.6

3.0

V_PLIMIT(V)

Output Power vs. V_PLIMIT

32

28

24

20

16

12

8

16

12

8

4

V_DD= 12V, R_L= 4Ω + 33μH,

_IN= 0.50V_RMS, APL Mode

V_DD= 24V, R_L= 8Ω + 33μH,

_IN= 1.0V_RMS, APL Mode

4

V

0

0.6 1.0 1.4 1.8 2.2 2.6 3.0 3.4 3.8

1.0

1.4

1.8

2.2

2.6

3.0

V_PLIMIT(V)

SG Micro Corp

DECEMBER 2022

www.sg-micro.com

13

High-Power Stereo Class-D Audio Power Amplifier

SGM4703

with Adjustable Power Limit and Automatic Level Control

TYPICAL PERFORMANCE CHARACTERISTICS (continued)

T_A= +25℃, f = 1kHz, C_IN= 4 × 1µF, A_V= 26dB, f_PWM= 360kHz, SSM Mode, V_PLIMIT= V_GVDD, both channels driven (BTL Mode),

unless otherwise specified.

THD+N vs. Output Power

100

10

100

10

V_DD= 24V, R_L= 8Ω + 33μH, Non-ALC Mode

V_DD= 12V, R_L= 4Ω + 33μH, Non-ALC Mode

1

0.1

SSM Mode

DSM Mode

0.01

DSM Mode

0.001

0.01

0.1

1

10

100

1

0.01

0.1

1

10

100

Output Power (W/CH)

THD+N vs. Output Power

THD+N vs. Input Voltage

Non-ALC Mode

100

10

100

10

V_DD= 15V, R_L= 3Ω + 15μH, Non-ALC Mode

1

SSM Mode, PBTL Mode

DSM Mode, PBTL Mode

0.1

0.01

V_DD= 24V, R_L= 8Ω + 33μH

_DD= 12V, R_L= 4Ω + 33μH

V_DD= 15V, R_L= 3Ω + 15μH, PBTL Mode

V

0.001

0.01

0.1

1

10

0.01

0.1

1

Output Power (W)

Input Voltage (V_RMS)

THD+N vs. Input Voltage

THD+N vs. Input Frequency

100

10

1

V_DD= 12V, R_L= 4Ω + 33μH, Non-ALC Mode

V_DD= 18V, R_L= 8Ω + 33μH, P_O= 5W/CH

V

_DD= 12V, R_L= 4Ω + 33μH, P_O= 5W/CH

_DD= 15V, R_L= 3Ω + 15μH, P_O= 20W,

PBTL Mode

1

0.1

SSM Mode

DSM Mode

0.1

0.01

0.001

0.01

0.001

0.01

0.1

10

100

1000

10000

100000

Input Voltage (V_RMS

)

Input Frequency (Hz)

SG Micro Corp

www.sg-micro.com

DECEMBER 2022

14

High-Power Stereo Class-D Audio Power Amplifier

SGM4703

with Adjustable Power Limit and Automatic Level Control

TYPICAL PERFORMANCE CHARACTERISTICS (continued)

T_A= +25℃, f = 1kHz, C_IN= 4 × 1µF, A_V= 26dB, f_PWM= 360kHz, SSM Mode, V_PLIMIT= V_GVDD, both channels driven (BTL Mode),

unless otherwise specified.

THD+N vs. Input Frequency

Efficiency vs. Output Power

10

1

100

80

60

40

20

0

V_DD= 12V, R_L= 4Ω + 33μH, P_O= 5W/CH

Non-ALC Mode

0.1

SSM Mode

DSM Mode

V_DD= 6V, R_L= 8Ω + 33μH

0.01

0.001

V

_DD= 12V, R_L= 8Ω + 33μH

_DD= 18V, R_L= 8Ω + 33μH

_DD= 24V, R_L= 8Ω + 33μH

10

100

1000

10000

100000

0

5

10

15

20

25

30

35

40

Input Frequency (Hz)

Output Power (W/CH)

Efficiency vs. Output Power

100

80

60

40

20

0

100

80

60

40

20

0

Non-ALC Mode, PBTL Mode

Non-ALC Mode

V_DD= 6V, R_L= 4Ω + 33μH

V_DD= 12V, R_L= 3Ω + 15μH

_DD= 18V, R_L= 3Ω + 15μH

V

_DD= 12V, R_L= 4Ω + 33μH

_DD= 18V, R_L= 4Ω + 33μH

V

0

10

20

30

40

0

10

20

30

40

50

60

Output Power (W/CH)

Output Power (W)

PSRR vs. Input Frequency

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

V_DD= 12V, R_L= 3Ω + 15μH, Inputs AC-Grounded

V_DD= 12V, R_L= 4Ω + 33μH, Inputs AC-Grounded

DSM Mode, PBTL Mode

DSM Mode

SSM Mode, PBTL Mode

SSM Mode

10

100

1000

10000

100000

10

100

1000

10000

100000

Frequency (Hz)

SG Micro Corp

DECEMBER 2022

www.sg-micro.com

15

High-Power Stereo Class-D Audio Power Amplifier

SGM4703

with Adjustable Power Limit and Automatic Level Control

TYPICAL PERFORMANCE CHARACTERISTICS (continued)

T_A= +25℃, f = 1kHz, C_IN= 4 × 1µF, A_V= 26dB, f_PWM= 360kHz, SSM Mode, V_PLIMIT= V_GVDD, both channels driven (BTL Mode),

unless otherwise specified.

Crosstalk vs. Input Frequency

Quiescent Current vs. Supply Voltage

Inputs AC-Grounded, No Load

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

24

20

16

12

8

V_DD= 12V, R_L= 4Ω + 33μH, P_O= 10W

DSM Mode

SSM Mode

Left-to-Right

4

Right-to-Left

0

4

6

8

10 12 14 16 18 20 22 24 26

10

100

1000

Frequency (Hz)

10000

100000

Supply Voltage (V)

Audio Outputs during ALC Attack

Audio Outputs during ALC Release

V_DD= 12V, V_IN= 0.34V_RMSto 1.0V_RMS, R_L= 4Ω + 33µH,

ALC-1 Mode

V_DD= 12V, V_IN= 1.0V_RMSto 0.34V_RMS, R_L= 4Ω + 33µH,

ALC-1 Mode

V_IN

V_OP- V_ON

Time (2ms/div)

Time (500ms/div)

Audio Outputs during Startup

Audio Outputs during Shutdown

V_OP

V_ON

V_EN

V_ON

V_EN

V_OP- V_ON

V_DD= 12V, V_IN= 0.1V_RMS, R_L= 4Ω + 33µH, f = 500Hz

V_DD= 12V, V_IN= 0.1V_RMS, R_L= 4Ω + 33µH, f = 5kHz

Time (10ms/div)

Time (1ms/div)

SG Micro Corp

www.sg-micro.com

DECEMBER 2022

16

High-Power Stereo Class-D Audio Power Amplifier

SGM4703

with Adjustable Power Limit and Automatic Level Control

FUNCTIONAL BLOCK DIAGRAM

GVDD

AVDD

PVDD

LDO

MODS

BSTPL

VOPL

VONL

BSTNL

INPL

INNL

Input

Buffer

Class-D

Modulator

Output

Stage

Shutdown

EN

GAIN

Control

OCP

DCP

Gain

Control

FAULTB

Oscillator

PWM Freq.

Control

OTP

FREQ

PLIMIT

ALC

UVLO

OVP

PLIMIT

Control

ALC

Control

BSTPR

INPR

INNR

VOPR

VONR

BSTNR

Input

Buffer

Class-D

Modulator

Output

Stage

PBTL

Control

SGM4703

AGND

PGND

Figure 3. Block Diagram

SG Micro Corp

www.sg-micro.com

DECEMBER 2022

17

High-Power Stereo Class-D Audio Power Amplifier

SGM4703

with Adjustable Power Limit and Automatic Level Control

APPLICATION INFORMATION

The SGM4703 is a high-power, high efficiency, stereo

Class-D audio power amplifier with adjustable power

limit (APL) and automatic level control (ALC). It

operates with a wide range of supply voltages from 5V

to 26V. With 24V supply voltage, it can deliver 2 × 40W

peak output power for a pair of 8Ω speakers with 10%

THD+N.

The SGM4703 includes comprehensive protection

modes against various operating faults including

under-voltage, over-voltage, over-current, over-

temperature, and DC-detect for safe and reliable

operation.

Operating Mode Control

The SGM4703 features APL and ALC modes of

operation. In APL mode, peak audio outputs are

clamped (hard-limited) to a voltage level defined by the

PLIMIT pin, protecting audio speakers from excessive

power dissipation and over-load.

The high efficiency of SGM4703 extends battery life in

playing music and allows it to deliver an output power

of 2 × 20W without the need for a bulky heat sink on a

two-layer system board. Its high PSRR and low EMI

emission reduce system design and manufacturing

complexities, as well as thus lower system cost.

As described in Table 1, depending upon the pin

voltage at PLIMIT and the pin configuration at ALC, the

SGM4703 can be configured into one of four operating

modes: Mute, APL, ALC, and Traditional. In SGM4703,

the pin voltage at PLIMIT, V_PLIMIT, defines the limiting

voltage of audio outputs for both APL and ALC modes.

The SGM4703 features APL and ALC. The APL limits

peak audio outputs to a user-defined value to protect

audio speakers from excessive power dissipation and

over-load. The APL and ALC adjust the voltage gain of

the audio amplifiers in response to over-limit audio

inputs, eliminating output clipping distortion while

maintaining a maximally allowed dynamic range of

audio outputs. The limiting voltage of APL and ALC can

be either the supply voltage or a user-defined value.

If V_PLIMITis set less than 0.3V, the device operates in

mute mode regardless of the pin configuration at ALC.

If V_PLIMITis set higher than 4.5V with the ALC pin

unconnected, the device operates in a traditional

Class-D mode without APL or ALC. In this mode, the

output clipping distortion will occur as peak output

voltages reach to the supply voltage PVDD.

The SGM4703 can be configured into driving either a

pair of speakers in Bridge-Tied-Load (BTL)

configuration for stereo applications or a single speaker

in Parallel BTL (PBTL) configuration for mono

applications. In PBTL configuration, with 15V supply

voltage, it can deliver into a 3Ω speaker an output

power of 33W with 1% THD+N, or an ALC output power

of 30W with THD+N less than 0.5%.

If V_PLIMITis set in the range from 0.7V to 3.5V with the

ALC pin connected to ground through an external

resistor of 0kΩ, 68kΩ or 300kΩ, the device operates in

APL mode. The audio outputs in APL mode are limited

to a value approximately equal to (6 × V_PLIMIT).

If V_PLIMITis set higher than 4.5V with the ALC pin

connected to ground through an external resistor of

0kΩ, 68kΩ, or 300kΩ, the device operates in ALC mode

and the limiting voltage of audio outputs is internally set

at the supply voltage. Thus, the peak voltage of audio

outputs is limited to a value that is substantially close to

PVDD.

The SGM4703 features two PWM modulation schemes

for use in Class-D audio amplifiers: Dual-Side-

Modulation (DSM) and Single-Side-Modulation (SSM),

allowing for system optimization for higher efficiency or

lower THD.

Table 1. Operating Mode Control

V_PLIMIT

V_PLIMIT< 0.3V

V_PLIMIT< 4.5V

V_PLIMIT> 4.5V

0.7V < V_PLIMIT< 3.5V

V_PLIMIT> 4.5V

R_ALC

Mode

Mute

X

Description

Audio outputs shorted to PGND.

Not applicable.

X

Open

Traditional No APL and No ALC.

APL

ALC

Audio outputs limited to a value defined by V_PLIMIT

.

0kΩ, 68kΩ or 300kΩ

to GND

Audio outputs limited to the supply voltage PVDD.

SG Micro Corp

www.sg-micro.com

DECEMBER 2022

18

High-Power Stereo Class-D Audio Power Amplifier

SGM4703

with Adjustable Power Limit and Automatic Level Control

APPLICATION INFORMATION (continued)

Figure 4 depicts large audio outputs in different

operating modes when excessive inputs are applied to

cause peak outputs higher than either the supply

voltage or a user-defined voltage limit lower than the

supply voltage.

Automatic Level Control (ALC)

The automatic level control is to maintain the audio

outputs for a maximum voltage swing without clip

distortion when excessive inputs that may cause output

clipping are applied. With ALC, the SGM4703 lowers

the voltage gain of both audio amplifiers to an

appropriate value such that output clipping is

substantially eliminated.

Traditional (No APL No ALC)

ALC with VDD Limiting

APL Output Limiting Voltage

APL with Adjustable Limiting

In Figure 6, “Attack” is the duration where the voltage

gain of the audio amplifiers decreases until output

clipping is substantially eliminated. “Release” is the

duration where the voltage gain of the audio amplifiers

recovers (increases) until it reaches to a value that is

maximally allowed without output clipping.

Figure 4. Large Audio Outputs in Different Operating

Modes

Output Signal when Supply Voltage is Sufficiently Large

GVDD Supply

The GVDD is an internally generated supply voltage for

internal circuitry. It is also used as the supply voltage for

the resistor divider to set the voltage at the PLIMIT pin.

It is highly suggested to decouple the GVDD pin with a

1μF ceramic capacitor to ground for stable operation.

Note that the current drawn from the GVDD pin by

external circuitry, including all the resistor dividers at

ALC, GAIN, FREQ, and PLIMIT pins, must be kept less

than 5mA.

Output Signal in ALC Off Mode

Output Signal in ALC On Mode

Attack

Release

MUTE Control

The SGM4703 can be configured into mute mode when

the PLIMIT pin is pulled low by an inverting transistor,

as shown in Figure 5. In mute mode, the output stages

of both audio amplifiers are in Hi-Z and the differential

audio outputs (VOPL/R and VONL/R) are pulled to

ground through on-chip resistors respectively. To

restore to its normal operation, the output of the

inverting transistor is reverted to Hi-Z state, allowing

the resistor divider (from GVDD to ground) tapped at

the PLIMIT pin to set the voltage limit for APL.

Figure 6. Automatic Level Control Diagram

ALC Mode Select

The SGM4703 can be configured into ALC or Non-ALC

mode via the ALC pin, as described in Table 2. When

the ALC pin is left unconnected, the SGM4703

operates in Non-ALC mode. The Non-ALC mode is

typically chosen for applications where maximum audio

loudness is desired and the amount of output clipping

distortions can be measurably controlled at the audio

source. In other pin configurations, the SGM4703

operates in ALC mode with three specific audio

dynamic characteristics. For most applications, the ALC

mode is preferred for its capability to substantially

eliminate output clipping distortion, excessive power

dissipation and speaker over-load.

GVDD

C_GVDD

R₂

1μF

PLIMIT

C_PLIMIT

10kΩ

Mute

NPN

0.1μF

R₁

Figure 5. Example Circuit Diagram of Mute Control

SG Micro Corp

DECEMBER 2022

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19

High-Power Stereo Class-D Audio Power Amplifier

SGM4703

with Adjustable Power Limit and Automatic Level Control

APPLICATION INFORMATION (continued)

Three sets of ALC dynamic characteristics can be

selected for specific sound effects, as described in

Table 2. The ALC-1 mode (the ALC pin shorted to GND)

plays music in a most mellow manner with negligible

amount of clipping distortion and lower average output

power. On the other hand, the ALC-3 mode (the ALC

pin shorted to GND via a 300kΩ resistor) plays music in

a most dynamic manner with some extent of clipping

distortion and higher average output power (loudness).

The voltage gain of the audio amplifiers can be slightly

adjusted by inserting small external input resistors R_INE

in series with the input capacitors C_IN, as depicted in

Figure 7 and Figure 8 for differential and single-ended

inputs respectively. In the figures, it is required that C_IN

,

= C_INL1/2= C_INR1/2and R_INE= R_INL1/2= R_INR1/2

.

As depicted in Figure 8, the unused inputs of SGM4703

in single-ended inputs applications must be

AC-grounded at the audio source. Also, take care to

match the impedances of two differential inputs.

Table 2. ALC Mode Select

Sound Effects

C_INL1

R_INL1

ALC Pin

Configuration

ALC

Mode

Output

Clipping

INNL

INPL

INNL

INPL

Loudness

C_INL2

R_INL2

Distortion

Potentially highest

loudness

No control on

output clipping

Open

Non-ALC

Most mellow sound

(Lowest loudness

under ALC)

C_INR1

C_INR2

Negligible

output clipping

R_INR1

R_INR2

Shorted to GND ALC-1

INNR

INPR

INNR

INPR

Slight output

clipping

68kΩ to GND

300kΩ to GND

ALC-2

ALC-3

Medium loudness

Most dynamic sound

(Highest loudness

under ALC)

Acceptable

output clipping

Figure 7. Gain Setting (Differential Inputs)

Note: The resistor tolerance of R_ALCshould be 5% or better.

C_INL1

R_INL1

INL

INNL

INPL

Voltage Gain Setting

C_INL2

R_INL2

To accommodate various application requirements, the

SGM4703 features 4 selectable voltage gains for audio

amplifiers. An external resistor R_GAINfrom the GAIN pin

to ground sets the voltage gain, as shown in Table 3.

C_INR1

C_INR2

R_INR1

R_INR2

INR

INNR

INPR

Although the voltage gains as described in Table 3 vary

a little (less than 2%) from parts to parts, the input

impedances at the same voltage gain may vary by ±20%

over parts, due to process variations in the actual

resistance of the input resistors. For design purposes,

the input impedance should be assumed to be 10kΩ,

which is the absolute minimum input impedance of the

audio amplifiers in SGM4703. At lower gain settings,

the input impedance could be as high as 60kΩ.

Figure 8. Gain Setting (Single-Ended Inputs)

The value of R_INE(in kΩ) for a given voltage gain can be

calculated by Equation 1, where A_Vis the voltage gain

of the audio amplifier.

600

(1)

A_V=

R_INE+R_INI

Table 3. Voltage Gain Select

The choice of the voltage gain will strongly influence

the loudness and quality of audio sounds. In general,

the higher the voltage gain is, the louder the sound is

perceived. However an excessive voltage gain may

cause audio outputs to be severely clipped (Non-ALC

mode) or compressed (ALC mode) for high-level (loud)

audio sounds. On the other hand, an unusually low gain

may cause relatively low-level (quite) sounds soft or

inaudible. Thus it is crucial to choose a proper voltage

gain for well balanced audio quality.

GAIN Pin

Configuration

R_INI

(kΩ)

A_V

(V/V)

A_V

(dB)

Open

30

20

12

60

20

30

50

10

26

30

34

20

Shorted to GND

68kΩ to GND

300kΩ to GND

Note: The resistor tolerance of R_GAINshould be 5% or better.

SG Micro Corp

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DECEMBER 2022

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High-Power Stereo Class-D Audio Power Amplifier

SGM4703

with Adjustable Power Limit and Automatic Level Control

APPLICATION INFORMATION (continued)

Table 5. PWM Frequency Select with Optional

Spread-Spectrum

The voltage gain is chosen based upon various

system-level considerations including the supply

voltage, the dynamic range of audio sources and

speaker loads, and the desired sound effects. As a

general guideline, the voltage gain can be simply

expressed in Equation 2. In the equation, V_IN,MAX(in

FREQ

Pin Configuration

PWM Frequency

(kHz)

Spread-Spectrum

Open

360

500

No

Yes

No

Shorted to GND

68kΩ to GND

300kΩ to GND

V_RMS) is the maximum input level from the audio source,

Yes

PVDD (in volts) is the supply voltage, and α is the

design parameter, which ranges from 0.66 to 1.0. The

higher α is, the higher the average output power (louder)

is, with some degree of compression for high-level

audio sounds.

Note: The resistor tolerance of R_FREQshould be 5% or better.

PWM Modulation Schemes

To accommodate various application requirements, the

SGM4703 features two PWM modulation schemes, i.e.,

Single-Side-Modulation (SSM) and Double-Side-

Modulation (DSM). In typical applications, the SSM

scheme is preferred for its lower EMI and higher PSRR

and efficiency. The modulation scheme is selected via

the MODS pin, as described in Table 6. The PWM

modulation scheme is latched during power-up and

cannot be changed while the device is in operation.

α×PVDD

(2)

A_V=

V

IN,MAX

As an example, Table 4 shows the voltage gain for

various input levels with PVDD at 12V, 18V and 24V

and α at about 0.80. In this table, R_INEis the external

input resistor in series with the input capacitor and R_INI

is the internal input resistor.

Table 4. Typical Voltage Gain Settings for Various V_DD

Audio Input Levels

&

Table 6. Modulation Scheme Select

MODS

High or Open

Low

Modulation Schemes

Single-Side-Modulation (SSM)

Double-Side- Modulation (DSM)

V_{IN, MAX}

(V_RMS

A_V

(V/V)

A_V

(dB)

R_GAINto GND

R_INI

(kΩ)

R_INE

(kΩ)

)

(kΩ)

V_DD= 12V

0.5

20

13.3

10

26

22.5

20

Open

300

30

60

0

15

0

Double-Side-Modulation (DSM)

0.7

With DSM scheme, during an idle condition (no audio

signal applied), both VOPL/R and VONL/R outputs are

at 50% duty cycle and in phase with each other,

resulting in little or no current flowing through the

speaker. When a positive audio input is applied, the

duty cycle of VOPL/R is greater than 50% and VONL/R

is less than 50%, resulting in a positive current flowing

through the speaker. When a negative audio input is

applied, the duty cycle of VOPL/R is less than 50% and

VONL/R is greater than 50%, resulting in a negative

current flowing through the speaker. Compared with the

traditional modulation scheme, the DSM scheme

reduces the switching current, which minimizes any I²R

losses in the speaker load and eliminates the need for

an LC output filter for most applications.

1.0

V_DD= 18V

0.5

30

20

15

29.5

26

0

20

30

0

0.7

Open

1.0

23.5

10

V_DD= 24V

0.5

40

28.5

20

32

29

26

68

0

12

20

30

3.0

1.0

0

0.7

1.0

Open

PWM Frequency Setting

To accommodate various application requirements, the

SGM4703 features two selectable PWM frequencies

with optional spread-spectrum for the Class-D audio

amplifiers. An external resistor R_FREQfrom the FREQ

pin to ground sets the PWM frequency and optional

spread-spectrum, as shown in Table 5.

SG Micro Corp

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21

High-Power Stereo Class-D Audio Power Amplifier

SGM4703

with Adjustable Power Limit and Automatic Level Control

APPLICATION INFORMATION (continued)

Single-Side-Modulation (SSM)

The SSM scheme alters the DSM scheme in order to

achieve higher efficiency with a slight penalty in THD

degradation and more attention required for the

selection of the output filter. With SSM scheme, the

audio outputs operate with less than 10% modulation

during an idle condition. When an audio signal is

applied, one output will decrease and another one will

increase. The decreasing output signal will quickly rail

to ground at which point all the audio modulation takes

place through the rising output. The result is that only

one output is switching during a majority of the audio

cycle. Efficiency is improved with SSM scheme due to

the reduction of switching losses. The THD penalty with

SSM scheme is minimized by the on-chip linear

feedback loop.

BTL configuration. To operate the SGM4703 in mono

mode, connect the INNR and INPR pins (pin 11 and 12)

directly to ground (no decoupling capacitors). In mono

mode, as shown in Figure 11, an audio input signal

applied to the left channel (pin 3 and 4) is routed to the

H-bridge of both channels. Note that the mono mode is

intended to be configured strictly by the hardware

connection. Leaving either INNR or INPR pin

unconnected while the audio outputs VOPL/R and

VONL/R are wired together in PBTL configuration can

trigger an over-current or thermal overload protection or

both. The mono mode is configured by the following

arrangement:

● Connect INPR and INNR pins directly to ground (no

decoupling capacitors).

● Connect VOPL to VONL together as one terminal of

the speaker and connect VOPR to VONR together

as the other terminal of the speaker. Use heavy

PCB traces as close as possible to the device.

Volume Fade-In and Fade-Out

The SGM4703 features volume fade-in and fade-out to

reduce intermittent sound and eliminate uncomfortable

hearing experience during the transitions when the

device enters or exits the normal operation. Figure 9

and Figure 10 show the audio output waveforms during

fade-in and fade-out respectively.

● Place the speaker between the left and

right-channel outputs.

● Apply an audio signal to the left-channel inputs

(INPL and INNL pins).

C_IN

R_INE

IN

INNL

INPL

VOPL

VONL

LS

C_IN

SPEAKER

INNR

INPR

VOPR

VONR

Fade-In

Time

Figure 9. Fade-In Waveform

Figure 11. PBTL Configuration for Mono Applications

Click-and-Pop Suppression

The SGM4703 features comprehensive click-and-pop

suppression. During startup, the click-and-pop

suppression circuitry reduces any audible transients

internal to the device. When entering into shutdown,

the differential audio outputs VOPL/R and VONL/R

ramp down to ground simultaneously.

Fade-Out

Time

PSRR Enhancement

Figure 10. Fade-Out Waveform

Without a dedicated pin for the common-mode voltage

bias and an external holding capacitor onto the pin, the

SGM4703 achieves a PSRR, 80dB at 1kHz with SSM

scheme.

PBTL Configuration (Mono Mode)

The SGM4703 features an optional mono mode that

allows the left and right channels to operate in parallel

SG Micro Corp

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High-Power Stereo Class-D Audio Power Amplifier

SGM4703

with Adjustable Power Limit and Automatic Level Control

APPLICATION INFORMATION (continued)

An on-chip pull-down resistor of 250kΩ is included onto

Startup and Shutdown

the EN pin. Thus, shutdown mode is the state when the

power supply is first applied to the device. Whenever

possible, please hold the EN pin low until the device is

properly powered up and the audio signals at the inputs

are stable. Also, for best power-off pop performance,

place the device in shutdown mode prior to removing

the power supply voltage.

The SGM4703 requires a power-up sequence (see

Figure 12). Please hold EN low at least 10ms after

PVDD and AVDD supply voltages are turned on.

The SGM4703 employs the EN pin to minimize power

consumption when not in use. When the EN pin is

pulled low, the SGM4703 is forced into shutdown mode.

At this time, all the analog circuitry is de-biased and the

supply current is reduced to the minimum level, and the

differential outputs are shorted to ground through an

on-chip resistor (5kΩ) individually. Once in shutdown

mode, the EN pin must remain low for at least 10ms (t_SD)

for the shutdown settling time before it can be pulled

high again. When the EN pin is asserted high, the

device exits out of shutdown mode and enters into

normal operation after the startup time (t_STARTUP) of

45ms.

Note that the setting at the MODS pin is latched during

startup and cannot be changed while the device is in

operation. To change the setting of the MODS pin, the

device must be first brought into shutdown mode by

pulling the EN pin low for at least 10ms before it can be

restored to its normal operation.

PVDD

AVDD

t_SD

GVDD

t_{EN_DELA Y}> 10ms

> t_SD

EN

t_{ST ARTUP}

t_Fade-In

t_Fade-Out

VOP/N

Figure 12. Startup Timming

SG Micro Corp

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DECEMBER 2022

23

High-Power Stereo Class-D Audio Power Amplifier

SGM4703

with Adjustable Power Limit and Automatic Level Control

APPLICATION INFORMATION (continued)

DC-Detect Protection (DCP)

Protection Modes

The SGM4703 features DCP circuit to protect the

speakers from large DC current. A DC-detect fault is

issued when the duty cycle of differential outputs of

either channel exceeds 20% for more than 720ms at

the same polarity. The device enters into mute mode,

where the differential audio outputs VOPL/R and

VONL/R are pulled to ground through on-chip resistors

(5kΩ) individually. Note that the DCP threshold is a

function of the supply voltage, as shown in Table 8. To

avoid nuisance faults due to the DCP circuit, it is

recommended to hold the EN pin low during startup

until the audio signals at the inputs are stable. Also,

take care to closely match the impedance seen at two

differential inputs.

For safe operation, the SGM4703 incorporates

comprehensive protection circuits against various

operating faults including Under-Voltage, Over-Voltage,

Over-Current, Over-Temperature, and DC-Detect, as

described in Table 7. In the shutdown mode, all the

analog circuitry is de-biased with differential outputs to

be shorted to ground. In the mute mode, all the analog

circuitry is enabled with differential outputs to be

shorted to ground.

Under-Voltage Lockout (UVLO)

The SGM4703 incorporates circuitry to detect a low

supply voltage for safe and reliable operation. When

the supply voltage is first applied, the SGM4703 will

remain inactive until the supply voltage exceeds 4.6V

(V_UVLOUP). When the supply voltage is removed and

drops below 4.3V (V_UVLODN), the SGM4703 enters into

mute mode, where the differential audio outputs

VOPL/R and VONL/R are pulled to ground through

on-chip resistors (5kΩ) individually.

A DC-detect fault is latched and reported on the

FAULTB pin as a low state. Also, the SGM4703 enters

into mute mode and remains in mute mode. The latch

can be cleared by cycling the EN pin through the low

state.

Over-Current Protection (OCP)

In operation, the outputs of Class-D amplifiers are

constantly monitors for any over-current and/or

short-circuit conditions. When a short-circuit condition

between two differential outputs, differential outputs to

PVDD or ground is detected, the device enters into

mute mode, where the differential audio outputs

VOPL/R and VONL/R are pulled to ground through

on-chip resistors (5kΩ) individually. If the fault persists

over a prescribed period, the fault condition is latched

and reported on the FAULTB pin as a low state. Also,

the SGM4703 enters into mute mode and remains in

mute mode. The latch can be cleared by cycling the EN

pin through the low state.

Over-Voltage Protection (OVP)

The SGM4703 features over-voltage protection. When

the supply voltage exceeds 28V (V_OVPUP), the device

enters into mute mode, where the differential audio

outputs VOPL/R and VONL/R are pulled to ground

through on-chip resistors (5kΩ) individually. The device

will resume normal operation once the supply voltage

returns to a value lower than 26.5V (V_OVPDN).

Over-Temperature Shutdown (OTSD)

When the die temperature exceeds +160℃, the device

enters into mute mode, where the differential audio

outputs VOPL/R and VONL/R are pulled to ground

through on-chip resistors (5kΩ) individually. The device

will resume normal operation once the die temperature

returns to a lower temperature, which is about 20℃

lower than the threshold.

If automatic recovery from the OCP fault is desired,

connect the FAULTZ pin directly to the EN pin, as shown

in Figure 13. It allows the FAULTZ pin to automatically

drive the EN pin low, which clears the OCP latch.

Table 7. Protection Modes of Various Operating faults

Latched or

Self-Recovery

Fault

Detection Condition

FAULTB

Audio Outputs

Mode

Audio outputs shorted to PVDD or

GND or each other

Over-Current

Low

5kΩ to GND

Mute

Latched

DC-Detect

Over-Temperature

Under-Voltage

Over-Voltage

See Table 8

T_J> 160℃

Low

5kΩ to GND

Mute

Latched

-

Self-Recovery

PVDD < 4.3V

PVDD > 28V

SG Micro Corp

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DECEMBER 2022

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High-Power Stereo Class-D Audio Power Amplifier

SGM4703

with Adjustable Power Limit and Automatic Level Control

APPLICATION INFORMATION (continued)

Table 8. DC-Detect Threshold Voltages

smaller, less costly, and more efficient solution can be

accomplished.

PVDD (V)

Output Offset Voltage V_OS(V)

6.5

12

15

18

1.3

2.4

3.0

3.6

Because the frequency of the audio outputs is well

beyond the bandwidth of most speakers, voice coil

movement due to the square-wave frequency is very

small. Although this movement is small, a speaker not

designed to handle the additional power can be

damaged. For optimum performance, use speakers

with series inductances greater than 10μH. Typical 4Ω

speakers exhibit series inductances from 10μH to

47μH.

If automatic recovery from the DCP fault is desired,

connect the FAULTB pin directly to the EN pin, as

shown in Figure 13. It allows the FAULTB pin to

automatically drive the EN pin low, which clears the

DCP latch.

Ferrite Bead Output Filter

With an edge-rate control circuitry in SGM4703, it is

possible to design a low EMI, highly efficient Class-D

audio amplifier without the need for classic LC

reconstruction filters when the amplifier drives speaker

loads with short speaker wires (less than 10cm).

However, EMI suppression can be further reduced by

use of a low-cost ferrite bead filter comprising a ferrite

bead and a capacitor, as shown in Figure 14. The

ferrite bead filter is applied to block radiation in the

range of 30MHz and above from appearing on the

speaker wires and the power supply lines. The

impedance of the ferrite bead is used with a small

capacitor in the range of 1nF to reduce the frequency

spectrum of the signal to an acceptable level. For best

performance, the resonant frequency of the ferrite bead

filter should be less than 10MHz.

10kΩ

GPIO

EN

FAULTB

MCU

Figure 13. Automatic Recovery from OCP or DCP Fault

Latch

Class-D Audio Amplifier

The audio power amplifiers in SGM4703 operate in

much the same way as traditional Class-D amplifiers

and similarly offer much higher power efficiency.

Fully Differential Amplifier

The SGM4703 includes a pair of fully differential

amplifiers with differential inputs and outputs. The fully

differential amplifiers ensure that the differential output

voltages are equal to the differential input voltages

times the amplifier gain. Although the SGM4703

supports for a single-ended input, differential inputs are

much preferred for applications where the environment

can be noisy in order to ensure maximum SNR.

FB₁

VOP

SPEAKER

Ferrite Chip Bead

C₁

FB₂

VON

Low-EMI Filterless Output Stage

Ferrite Chip Bead

C₂

Traditional Class-D audio amplifiers require for the use

of external LC filters, or shielding, to meet EN55022B

electromagnetic-interference (EMI) regulation standards.

The SGM4703 applies an edge-rate control circuitry to

reduce EMI emissions, while maintaining high power

efficiency.

Figure 14. Ferrite Bead Filter for EMI Reduction

Choose a ferrite bead with low DC resistance (DCR)

and high impedance (100Ω ~ 330Ω) at high frequencies

(>100MHz). The current flowing through the ferrite

bead must be also taken into consideration. The

effectiveness of ferrites can be greatly aggravated at

much lower than their rated current values. Choose a

ferrite bead with a rated current no less than 4A for 8Ω

loads, 7A for 4Ω loads, and 9A for 3Ω loads (in PBTL

configuration).

Filterless Design

The SGM4703 does not require an output filter. The

device relies on the inherent inductance of the speaker

coil and the natural filtering of both the speaker and the

human ear to recover the audio component of the

square-wave output. By eliminating the output filter, a

SG Micro Corp

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High-Power Stereo Class-D Audio Power Amplifier

SGM4703

with Adjustable Power Limit and Automatic Level Control

APPLICATION INFORMATION (continued)

A high quality ceramic capacitor is needed for the ferrite

bead filter. A low ESR ceramic capacitor with good

temperature and voltage characteristics will be the best

choice. The capacitor value varies based on the ferrite

bead chosen and the actual speaker lead length. It is

crucial to place each ferrite bead filter tightly together

and individually close to VOPL/R and VONL/R pins

respectively.

In Figure 15, the corner frequency of the LC low-pass

filter, as given by Equation 3, must be designed to be

sufficiently high to allow for high-frequency components

of audio signals, yet be low enough to sufficiently

attenuate high-frequency components of the audio

outputs from VOPL/R and VONL/R. The corner

frequency of the filter is typically set about 50kHz. In

Equation 3, it is assumed that L = L₁= L₂, C_G= C₂= C₃,

and C = 2 × C₁+ C_G.

Additional EMI improvements may be obtained by

adding snubber networks from each of the Class-D

outputs to ground. Suggested values for a simple RC

series snubber network are 10Ω in series with a 680pF

capacitor. Note that design of the RC snubber circuit is

specific to every application and must take into account

the parasitic reactance of the system board to reach

proper values of R and C. Evaluate and ensure that the

voltage spikes (overshoots and undershoots) at

VOPL/R and VONL/R on the actual system board are

within their absolute maximum ratings. Pay close

attention to the layout of the RC snubber circuit to be

tight and individually close to VOPL/R and VONL/R

pins, respectively.

1

(3)

f_{C, LPF}

=

2π LC

The quality factor Q of the output filter is important.

Lower Q increases output noise and higher Q results in

passband peaking at frequencies near the corner

frequency. The quality factor of the filter is typically set

between 0.5 and 0.8. As shown in Equation 4, the

speak load, R_LOAD, affects the quality factor of the filter.

R_LOAD

2

C

L

(4)

Q =

×

Table 9 lists suggested component values of L₁, L₂, C₁,

C₂, and C₃for the second-order Butterworth low-pass

filter with the speaker load at 2Ω, 3Ω, 4Ω, or 8Ω.

LC Output Filter

Table 9. Suggested Component Values of LC Output

For applications with nearby highly noise sensitive

circuits or long speaker wires, it may become

necessary to add an LC reconstruction filter for best

EMI reduction. A classic second-order low-pass filter,

as shown in Figure 15, can be used for the output filter.

Filter

Speaker

Load

(Ω)

Modulation L₁, L₂

C₁

(µF)

C₂, C₃

(µF)

f_{C, LPF}

(kHz)

Q

Schemes

(µH)

SSM

DSM

SSM

DSM

SSM

DSM

SSM

DSM

15

0.22

0.1

0.56

0.15

1.0

56

55

48

50

52

51

54

55

0.76

0.77

0.68

0.63

0.56

0.57

0.53

0.52

8

4

3

2

L₁

-

VOP

10

0.47

C₂

LSL

C₁

10

-

0.47

-

8.2

5.6

0.22

1.2

SPEAKER

L₂

VON

C₃

0.68

-

0.22

1.5

Figure 15. LC Output Filter for EMI Reduction

SG Micro Corp

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High-Power Stereo Class-D Audio Power Amplifier

SGM4703

with Adjustable Power Limit and Automatic Level Control

APPLICATION INFORMATION (continued)

Audio Input Capacitors (C_INL1, C_INL2, C_INR1

and C_INR2

Supply Coupling Capacitors (C_PVDD, C_AVDD

,

)

C_GVDDand C_PLIMIT

)

The input DC decoupling capacitors are recommended

to bias the incoming audio inputs to a proper DC level.

The input capacitor C_IN, in conjunction with the amplifier

input resistance (including both internal resistor R_INI

and external resistor R_INE, if any) forms a high-pass

filter that removes the DC bias of the audio inputs. The

corner frequency f_C,HPFof the high-pass filter is given by

Decouple each pair of PVDD pins respectively with a

1μF low-ESR ceramic capacitor (X7R or X5R) to GND.

It is highly suggested to add an additional 0.01μF

ceramic capacitor, in tandem with each 1μF capacitor,

for high-frequency decoupling. The rated voltage of the

supply coupling capacitors must be higher than the

power supply voltage with sufficient tolerance to limit

the effects of DC bias. Place the decoupling capacitors

as individually close as possible to each pair of PVDD

pins.

Equation 5. In the equation, it is assumed that R_INE

R_INL1= R_INL2= R_INR1= R_INR2and C_IN= C_INL1= C_INL2

=

C

_INR1= C_INR2.

1

If the power supply input is located more than a few

inches from SGM4703, additional bulk supply

decoupling capacitors (electrolytic or tantalum type)

may be required. Add a large (220μF or greater) bulk

capacitor on the PVDD power bus in close proximity to

the SGM4703.

(5)

f_{C, HPF}

=

2π× R_INE+R_INI×C

(

)

IN

R_INEis the external input resistance for a specific

voltage gain. Note that the variation of the actual input

resistance will affect the voltage gain proportionally.

Choose R_INEwith a tolerance of 2% or better.

Decouple the AVDD pin with a 1μF low-ESR ceramic

capacitor to AGND. Place the decoupling capacitor as

close as possible to the AVDD pin. Furthermore, add a

small decoupling resistor (R_AVDD) of 10Ω between the

system power supply and the AVDD pin, preventing

high-frequency transients of PVDD from interfering with

on-chip linear amplifiers.

Choose C_INsuch that f_C,HPFis well below the lowest

frequency of interest. Setting it too high affects the

amplifiers’ low-frequency response. Consider an

example where the specification calls for A_V= 26dB

and f_C,HPF= 5Hz. In this example, R_INE= 0Ω and R_INI

=

30kΩ and C_INis calculated to be about 1.06μF; thus

1μF, as a common choice of capacitance, can be

chosen for C_IN.

Decouple the GVDD pin with a 1μF low-ESR ceramic

capacitor to AGND. Place the decoupling capacitor

close to the GVDD pin.

Any mismatch in capacitance between two audio inputs

will cause a mismatch in the corner frequencies.

Severe mismatch may also cause turn-on pop noise,

PSRR, CMRR performance. Choose C_INwith a

tolerance of ±2% or better.

Decouple the PLIMIT pin with a 0.1μF low-ESR

ceramic capacitor to AGND for high-frequency filtering.

Place the decoupling capacitor close to the PLIMIT pin.

Furthermore, the type of the input capacitor is crucial to

audio quality. For best audio quality, use capacitors

whose dielectrics have low-voltage coefficients, such

as tantalum or aluminum electrolytic. Capacitors with

high-voltage coefficients, such as ceramics, may result

in increased distortion at low frequencies.

SG Micro Corp

www.sg-micro.com

DECEMBER 2022

27

High-Power Stereo Class-D Audio Power Amplifier

SGM4703

with Adjustable Power Limit and Automatic Level Control

PCB LAYOUT

As a high power, high efficiency, Class-D stereo audio

power amplifier, the SGM4703 requires proper PCB

layout and grounding to ensure high efficiency, low

distortion, and low EMI emission. Use wide traces for

the power supply inputs (PVDD) and audio outputs

(VOPL/R and VONL/R) to minimize losses due to

parasitic trace resistances. Route all traces that carry

switching transients away from the traces or

components in the audio signal path.

current loop from each of the audio outputs through the

output filters and back to the PGND pins as short and

tight as possible.

Power Dissipation – The maximum output power of

SGM4703 can be severely limited by its thermal

dissipation capability. To ensure the device operating

properly and reliably at maximum output power without

incurring over-temperature shutdown, the following

guidelines are given for best thermal dissipation

capability:

Ground Plane – It is required to use a solid metal

plane with sufficiently wide area as a central ground

GND for SGM4703. All the power ground pins PGND

are directly shorted to the large ground plane GND,

which serves as a central “star” ground for the

SGM4703. Use a single point of connection between

the analog ground AGND and the ground plane GND to

minimize the coupling of high-current switching noise

onto audio signals.

● Fill both top and bottom layers of the system board

with solid GND metal traces.

● Solder the thermal pad directly onto a grounded

metal plane.

● Place lots of equally-spaced vias underneath the

thermal pad connecting the top and bottom layers of

GND. The vias are connected to a solid metal plane

on the bottom layer of the board.

Supply Decoupling Capacitors

–

The supply

● Reserve wide and uninterrupted areas along the

thermal flow on the top layer, i.e., no wires cutting

through the GND layer and obstructing the thermal

flow.

decoupling capacitors (C_PVDDand C_AVDD) should be

placed as individually close as possible to PVDD and

AVDD pins.

Output Filters – Place each audio output filter (ferrite

bead or LC filter) individually close to their respective

output pins, VOPL/R and VONL/R, for best EMI

performance and operational robustness. Keep the

● Avoid using vias for traces carrying high current.

SG Micro Corp

www.sg-micro.com

DECEMBER 2022

28

High-Power Stereo Class-D Audio Power Amplifier

SGM4703

with Adjustable Power Limit and Automatic Level Control

TYPICAL APPLICATION CIRCUITS

V_DD

C_{PV DD}

+

220μF

C_{PV DD}

10nF

C_{PV DD}

1μF

R_EN

28

27

26

25

24

1

EN

PV DD

BSTPL

VOPL

EN

10kΩ

2

FAULTB

C_IN

1μF

C_B1

L_F1

3

4

INPL

INNL

INPL

INNL

0. 1μF

LSL

Ferrite Bead

C_F1

1nF

PG ND

VO NL

5

GAIN

FREQ

AV DD

AG ND

GV DD

PLIMIT

INNR

INPR

C_F2

1nF

V_DD

L_F2

23

22

21

20

19

18

17

16

6

7

SPEAKER

LSR

R_{AV DD}

C_B2

Ferrite Bead

L_F3

BS TNL

BS TNR

VO NR

PG ND

VOPR

BSTPR

PV DD

0. 1μF

C_{AV DD}

1μF

10Ω

SGM4703

C_B3

8

9

C_{GV DD}

0. 1μF

1μF

Ferrite Bead

C_F3

1nF

10

11

C_F4

1nF

C_IN

1μF

L_F4

INNR

INPR

SPEAKER

C_B4

12

Ferrite Bead

0. 1μF

V_DD

13

14

ALC

15

MODS

C_{PV DD}

220μF

+

C_{PV DD}

10nF

C_{PV DD}

1μF

Figure 16. Differential Inputs in Non-ALC Mode with DSM

V_DD

C_{PV DD}

+

220μF

C_{PV DD}

R_EN

28

27

26

25

24

1

2

3

4

EN

PV DD

BSTPL

VOPL

EN

10nF

1μF

10kΩ

FAULTB

INPL

C_IN

1μF

C_B1

L_F1

INL

0. 1μF

LSL

Ferrite Bead

C_F1

1nF

C_F2

1nF

INNL

GAIN

FREQ

5

6

PG ND

VO NL

V_DD

L_F2

23

22

21

20

19

18

17

16

SPEAKER

LSR

R_{AV DD}

C_B2

7

8

Ferrite Bead

L_F3

AV DD

AG ND

BS TNL

BS TNR

VO NR

PG ND

VOPR

BSTPR

PV DD

0. 1μF

10Ω C_{AV DD}

1μF

SGM4703

C_B3

C_{GV DD}

0. 1μF

1μF

C_F3

1nF

C_F4

1nF

Ferrite Bead

9

GV DD

10

11

PLIMIT

INNR

C_IN

1μF

L_F4

SPEAKER

C_B4

12

13

14

Ferrite Bead

INR

INPR

0. 1μF

V_DD

ALC

15

MODS

C_{PV DD}

220μF

+

C_{PV DD}

10nF

1μF

Figure 17. Single-Ended Inputs in ALC-1 Mode with SSM

SG Micro Corp

www.sg-micro.com

DECEMBER 2022

29

High-Power Stereo Class-D Audio Power Amplifier

SGM4703

with Adjustable Power Limit and Automatic Level Control

TYPICAL APPLICATION CIRCUITS (continued)

V_DD

C_{PV DD}

+

220μF

C_{PV DD}

R_EN

28

27

26

25

24

1

2

3

4

EN

PV DD

BSTPL

VOPL

EN

10nF

1μF

10kΩ

FAULTB

INPL

C_IN

1μF

C_B1

L_F1

0. 1μF

LSL

Ferrite Bead

INL

C_F1

1nF

INNL

GAIN

FREQ

AV DD

5

6

PG ND

VO NL

C_F2

1nF

V_DD

L_F2

23

22

21

20

19

18

17

16

SPEAKER

LSR

R_{AV DD}

C_B2

7

Ferrite Bead

L_F3

BS TNL

BS TNR

VO NR

PG ND

VOPR

BSTPR

PV DD

0. 1μF

10Ω C_{AV DD}

1μF

SGM4703

C_B3

8

AG ND

GV DD

C_{GV DD}

0. 1μF

1μF

Ferrite Bead

9

C_F3

1nF

10

11

PLIMIT

INNR

C_F4

1nF

C_IN

1μF

L_F4

INR

SPEAKER

C_B4

12

Ferrite Bead

INPR

0. 1μF

V_DD

13

14

ALC

R₂

R₁

15

MODS

MUTE

C_{PV DD}

220μF

+

C_{PV DD}

R₃

10kΩ

10nF

1μF

C_PLIMIT

0. 1μF

Q₁

NPN

Figure 18. Single-Ended Inputs in APL Mode with Mute Control

V_DD

C_{PV DD}

+

220μF

C_{PV DD}

R_EN

28

27

26

25

24

1

2

3

4

EN

PV DD

BSTPL

VOPL

EN

10nF

1μF

10kΩ

FAULTB

INPL

C_IN

1μF

C_B1

INP

INN

0. 1μF

INNL

GAIN

5

6

7

8

PG ND

VO NL

V_DD

23

22

21

20

19

18

17

16

FREQ

AV DD

AG ND

L_F110μH

R_{AV DD}

C_B2

LS

C_F1

BS TNL

BS TNR

VO NR

PG ND

VOPR

BSTPR

PV DD

0. 1μF

10Ω

SGM4703

C_{AV DD}

1μF

C_B3

1μF

C_F2

C_{GV DD}

0. 1μF

1μF

9

L_F210μH

GV DD

1μF

SPEAKER

4Ω

10

11

PLIMIT

INNR

C_B4

12

13

14

INPR

ALC

0. 1μF

V_DD

15

R_ALC

68kΩ

MODS

C_{PV DD}

220μF

+

C_{PV DD}

10nF

1μF

Figure 19. Differential Inputs in ALC-2 Mode with DSM in PBTL Configuration

SG Micro Corp

www.sg-micro.com

DECEMBER 2022

30

High-Power Stereo Class-D Audio Power Amplifier

SGM4703

with Adjustable Power Limit and Automatic Level Control

REVISION HISTORY

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Original (DECEMBER 2022) to REV.A

Page

Changed from product preview to production data.............................................................................................................................................All

SG Micro Corp

DECEMBER 2022

www.sg-micro.com

31

PACKAGE INFORMATION

PACKAGE OUTLINE DIMENSIONS

TSSOP-28 (Exposed Pad)

D

D1

3.66

E1

E2

E

2.60

5.94

1.78

b

e

0.42

0.65

RECOMMENDED LAND PATTERN (Unit: mm)

L1

A

A1

θ

L

c

A2

Dimensions

In Millimeters

Dimensions

In Inches

Symbol

MIN

MAX

MIN

MAX

0.047

0.006

0.041

0.012

0.008

0.386

0.152

0.177

0.110

0.260

A

A1

A2

b

1.200

0.150

1.050

0.300

0.200

9.800

3.860

4.500

2.800

6.600

0.050

0.800

0.190

0.090

9.600

3.460

4.300

2.400

6.200

0.002

0.031

0.007

0.004

0.378

0.136

0.169

0.094

0.244

c

D

D1

E

E1

E2

e

0.650 BSC

1.000 BSC

0.026 BSC

0.039 BSC

L

L1

θ

0.450

0°

0.750

8°

0.018

0°

0.030

8°

NOTES:

1. Body dimensions do not include mode flash or protrusion.

2. This drawing is subject to change without notice.

3. Reference JEDEC MO-153.

SG Micro Corp

TX00153.002

www.sg-micro.com

PACKAGE INFORMATION

TAPE AND REEL INFORMATION

REEL DIMENSIONS

TAPE DIMENSIONS

P2

P0

W

Q2

Q4

Q2

Q4

Q2

Q4

Q1

Q3

Q1

Q3

Q1

Q3

B0

Reel Diameter

P1

A0

K0

Reel Width (W1)

DIRECTION OF FEED

NOTE: The picture is only for reference. Please make the object as the standard.

KEY PARAMETER LIST OF TAPE AND REEL

Reel Width

Reel

Diameter

A0

B0

K0

P0

P1

P2

W

Pin1

Package Type

W1

(mm)

(mm) (mm) (mm) (mm) (mm) (mm) (mm) Quadrant

TSSOP-28

(Exposed Pad)

13″

17.6

6.80

10.20

1.60

4.0

8.0

2.0

16.0

Q1

SG Micro Corp

TX10000.000

www.sg-micro.com

PACKAGE INFORMATION

CARTON BOX DIMENSIONS

NOTE: The picture is only for reference. Please make the object as the standard.

KEY PARAMETER LIST OF CARTON BOX

Length

(mm)

Width

(mm)

Height

(mm)

Reel Type

Pizza/Carton

13″

386

280

370

5

SG Micro Corp

www.sg-micro.com

TX20000.000


型号：	SGM4703
厂家：	Shengbang Microelectronics Co, Ltd
描述：	High-Power Stereo Class-D Audio Power Amplifier with Adjustable Power Limit and Automatic Level Control
文件：	总34页 (文件大小：1043K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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